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Tue, 23 Jun 2026 08:35:39 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:20f1:5c9:8a6d:48a1]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-4923fe7b9e5sm370653045e9.10.2026.06.23.08.35.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jun 2026 08:35:38 -0700 (PDT) From: Jerome Brunet To: Enzo Adriano via B4 Relay Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Ulf Hansson , enzo.adriano.code@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Subject: Re: [PATCH 3/4] arm64: dts: allwinner: add Allwinner A733 SoC In-Reply-To: <20260613-a733-dts-v1-public-ready-v1-3-7787c94681db@gmail.com> (Enzo Adriano via's message of "Sat, 13 Jun 2026 05:42:15 -0400") References: <20260613-a733-dts-v1-public-ready-v1-0-7787c94681db@gmail.com> <20260613-a733-dts-v1-public-ready-v1-3-7787c94681db@gmail.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Tue, 23 Jun 2026 17:35:36 +0200 Message-ID: <1j33ydb77b.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260623_083541_371402_ACA1097C X-CRM114-Status: GOOD ( 17.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On sam. 13 juin 2026 at 05:42, Enzo Adriano via B4 Relay wrote: > From: Enzo Adriano > > Add the initial A733 SoC description with CPUs, timers, interrupt > controller, clocks, pinctrl, UART0, and MMC0. > > Keep peripherals disabled by default. Board DTS files can enable only the > devices that are proven on their hardware. > > Signed-off-by: Enzo Adriano > --- > arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi | 198 +++++++++++++++++++++++++ > 1 file changed, 198 insertions(+) > > diff --git a/arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi b/arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi > new file mode 100644 > index 000000000000..3721aa9e8573 > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi > @@ -0,0 +1,198 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) > + > +#include > +#include > +#include > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a55"; > + device_type = "cpu"; > + reg = <0x000>; > + enable-method = "psci"; > + capacity-dmips-mhz = <530>; > + }; > + > + cpu1: cpu@100 { > + compatible = "arm,cortex-a55"; > + device_type = "cpu"; > + reg = <0x100>; > + enable-method = "psci"; > + capacity-dmips-mhz = <530>; > + }; > + > + cpu2: cpu@200 { > + compatible = "arm,cortex-a55"; > + device_type = "cpu"; > + reg = <0x200>; > + enable-method = "psci"; > + capacity-dmips-mhz = <530>; > + }; > + > + cpu3: cpu@300 { > + compatible = "arm,cortex-a55"; > + device_type = "cpu"; > + reg = <0x300>; > + enable-method = "psci"; > + capacity-dmips-mhz = <530>; > + }; > + > + cpu4: cpu@400 { > + compatible = "arm,cortex-a55"; > + device_type = "cpu"; > + reg = <0x400>; > + enable-method = "psci"; > + capacity-dmips-mhz = <530>; > + }; > + > + cpu5: cpu@500 { > + compatible = "arm,cortex-a55"; > + device_type = "cpu"; > + reg = <0x500>; > + enable-method = "psci"; > + capacity-dmips-mhz = <530>; > + }; > + > + cpu6: cpu@600 { > + compatible = "arm,cortex-a76"; > + device_type = "cpu"; > + reg = <0x600>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + }; > + > + cpu7: cpu@700 { > + compatible = "arm,cortex-a76"; > + device_type = "cpu"; > + reg = <0x700>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + }; > + }; > + > + osc24M: osc24M-clk { Note A733 supports 19.2MHz, 24MHz and 26MHz xtals apparently. The A7S and A7A do have a 26MHz xtal according to the schematics. While this might be fine in the SoC dtsi, your are missing something in your board dts to change the xtal rate, at least. Also the node and clock name are a bit misleading now. > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + }; > + > + osc32k: osc32k-clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "osc32k"; I think this is the ext32k supposed to feed the rtc ccu ... > + }; > + > + iosc: internal-osc-clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <16000000>; > + clock-output-names = "iosc"; > + }; > + > + psci { > + compatible = "arm,psci-1.0", "arm,psci-0.2"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + arm,no-tick-in-suspend; > + interrupts = , > + , > + , > + ; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0x0 0x40000000>; > + > + pio: pinctrl@2000000 { > + compatible = "allwinner,sun60i-a733-pinctrl"; > + reg = <0x02000000 0x600>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>; > + clock-names = "apb", "hosc", "losc"; > + gpio-controller; > + #gpio-cells = <3>; > + interrupt-controller; > + #interrupt-cells = <3>; > + > + mmc0_pins: mmc0-pins { > + pins = "PF0", "PF1", "PF2", > + "PF3", "PF4", "PF5"; > + function = "mmc0"; > + drive-strength = <30>; > + bias-pull-up; > + }; > + }; > + > + ccu: clock-controller@2002000 { > + compatible = "allwinner,sun60i-a733-ccu"; > + reg = <0x02002000 0x2000>; > + clocks = <&osc24M>, <&osc32k>, <&iosc>; ^ ... not directly the main CCU. > + clock-names = "hosc", "losc", "iosc"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + uart0: serial@2500000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x02500000 0x400>; > + interrupts = ; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART0>; > + resets = <&ccu RST_BUS_UART0>; > + status = "disabled"; > + }; > + > + gic: interrupt-controller@3400000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0x03400000 0x10000>, > + <0x03460000 0x100000>; > + }; > + > + mmc0: mmc@4020000 { > + compatible = "allwinner,sun60i-a733-mmc", > + "allwinner,sun20i-d1-mmc"; > + reg = <0x04020000 0x1000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; > + clock-names = "ahb", "mmc"; > + resets = <&ccu RST_BUS_MMC0>; > + reset-names = "ahb"; > + pinctrl-names = "default"; > + pinctrl-0 = <&mmc0_pins>; > + max-frequency = <200000000>; > + cap-sd-highspeed; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > +}; -- Jerome