From: Jerome Brunet <jbrunet@baylibre.com>
To: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Cc: neil.armstrong@linaro.org, mturquette@baylibre.com,
sboyd@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, khilman@baylibre.com,
martin.blumenstingl@googlemail.com, jian.hu@amlogic.com,
kernel@sberdevices.ru, rockosov@gmail.com,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v9 2/5] clk: meson: a1: add Amlogic A1 PLL clock controller driver
Date: Mon, 13 Mar 2023 10:18:02 +0100 [thread overview]
Message-ID: <1j5yb50zxz.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <20230309182857.a2fzotcejueio23w@CAB-WSD-L081021>
On Thu 09 Mar 2023 at 21:28, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
>> >>
>> >> This last poke should not bits otherwise handled by parms.
>> >> This is a rate init in disguise.
>> >>
>> >
>> > I believe, you are talking about hifi_pll clk_regmap conflicts with
>> > hifi_init_regs. The above init sequence shouldn't affect pll regmap setup,
>> > it doesn't touch them (we assume that default bit values are all zero):
>> >
>> > .en = {
>> > .reg_off = ANACTRL_HIFIPLL_CTRL0,
>> > .shift = 28,
>> > .width = 1,
>> > },
>> > // init_value = 0x01f18440
>> > // en_mask = 0x10000000
>> >
>> > .m = {
>> > .reg_off = ANACTRL_HIFIPLL_CTRL0,
>> > .shift = 0,
>> > .width = 8,
>> > },
>> > // init_value = 0x01f18440
>> > // m_mask = 0x0000000f
>>
>> mask is 0xff with width 8
>>
>
> Ah, you're right. Anyway, I think this is just init value and it's okay
> to set it during initialization and rewrite after in parameter
> propagation stage.
>
... But the magic pokes are there only to initialize the unmanaged part
of the clock regs. I'd like it to be clear and stay that way.
So please, clear the managed fields from the initial poke table.
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next prev parent reply other threads:[~2023-03-13 9:22 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-01 18:37 [PATCH v9 0/5] add Amlogic A1 clock controller drivers Dmitry Rokosov
2023-03-01 18:37 ` [PATCH v9 1/5] clk: meson: add support for A1 PLL clock ops Dmitry Rokosov
2023-03-06 11:09 ` Jerome Brunet
2023-03-06 20:12 ` Dmitry Rokosov
2023-03-01 18:37 ` [PATCH v9 2/5] clk: meson: a1: add Amlogic A1 PLL clock controller driver Dmitry Rokosov
2023-03-02 10:02 ` kernel test robot
2023-03-06 11:17 ` Jerome Brunet
2023-03-06 20:05 ` Dmitry Rokosov
2023-03-09 14:20 ` Jerome Brunet
2023-03-09 18:28 ` Dmitry Rokosov
2023-03-13 9:18 ` Jerome Brunet [this message]
2023-03-13 10:25 ` Dmitry Rokosov
2023-03-01 18:37 ` [PATCH v9 3/5] dt-bindings: clock: meson: add A1 PLL clock controller bindings Dmitry Rokosov
2023-03-01 19:47 ` Rob Herring
2023-03-03 8:28 ` Krzysztof Kozlowski
2023-03-03 9:11 ` Dmitry Rokosov
2023-03-06 11:33 ` Jerome Brunet
2023-03-06 19:07 ` Dmitry Rokosov
2023-03-01 18:37 ` [PATCH v9 4/5] clk: meson: a1: add Amlogic A1 Peripherals clock controller driver Dmitry Rokosov
2023-03-06 11:38 ` Jerome Brunet
2023-03-06 19:05 ` Dmitry Rokosov
2023-03-09 14:22 ` Jerome Brunet
2023-03-09 18:58 ` Dmitry Rokosov
2023-03-01 18:37 ` [PATCH v9 5/5] dt-bindings: clock: meson: add A1 Peripherals clock controller bindings Dmitry Rokosov
2023-03-01 19:47 ` Rob Herring
2023-03-03 8:29 ` Krzysztof Kozlowski
2023-03-03 9:14 ` Dmitry Rokosov
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