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[82.67.6.57]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4887a34a638sm5295892f8f.9.2026.09.25.02.14.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 02:14:16 -0700 (PDT) From: Jerome Brunet To: =?utf-8?B?WXUtQ2h1biBMaW4gW+ael+elkOWQm10=?= Cc: "sboyd@kernel.org" , "bmasney+clk@redhat.com" , "jbrunet+clk@baylibre.com" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "p.zabel@pengutronix.de" , =?utf-8?B?RWRnYXIgTGVlIFvmnY7mib/oq61d?= , "afaerber@suse.com" , =?utf-8?B?SnlhbiBDaG91IFvlkajoirflrold?= , "devicetree@vger.kernel.org" , "linux-clk@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-realtek-soc@lists.infradead.org" , =?utf-8?B?SmFtZXMgVGFpIFvmiLQ=?= =?utf-8?B?5b+X5bOwXQ==?= , =?utf-8?B?Q1lfSHVhbmdb6buD6Ymm5pmPXQ==?= , =?utf-8?Q?Stanley_Chang=5B=E6=98=8C=E8=82=B2?= =?utf-8?Q?=E5=BE=B7=5D?= , Brian Masney Subject: RE: [PATCH v14 09/11] clk: realtek: Add RTD1625-CRT clock controller driver In-Reply-To: References: <20260901072446.2563145-1-eleanor.lin@realtek.com> <20260901072446.2563145-10-eleanor.lin@realtek.com> <178947735404.448573.10061486937030065064.b4-reply@b4> Date: Fri, 25 Sep 2026 11:14:15 +0200 Message-ID: <1jjyo98zh4.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260925_021419_064264_7EEE98D3 X-CRM114-Status: GOOD ( 14.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On mer. 23 sept. 2026 at 05:43, Yu-Chun Lin [=E6=9E=97=E7=A5=90=E5=90=9B] <= eleanor.lin@realtek.com> wrote: > Hi Jerome, > >> > + >> > +static const char * const clk_gpu_parents[] =3D {"pll_gpu", "clk_sys"= }; >> > +static RTK_CLK_REGMAP_MUX(clk_gpu, clk_gpu_parents, >> CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, >> > + 0x28, 12, 0x1); static const char * const >> > +clk_ve_parents[] =3D {"pll_vo", "clk_sysh", "pll_ve1", "pll_ve2"}; >> > +static RTK_CLK_REGMAP_MUX(clk_ve1, clk_ve_parents, >> CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, >> > + 0x4c, 0, 0x3); static >> > +RTK_CLK_REGMAP_MUX(clk_ve2, clk_ve_parents, CLK_SET_RATE_PARENT | >> CLK_SET_RATE_NO_REPARENT, >> > + 0x4c, 3, 0x3); static >> > +RTK_CLK_REGMAP_MUX(clk_ve4, clk_ve_parents, CLK_SET_RATE_PARENT | >> CLK_SET_RATE_NO_REPARENT, >> > + 0x4c, 6, 0x3); static >> > +RTK_CLK_REGMAP_GATE_NO_PARENT(clk_en_misc, CLK_IS_CRITICAL, 0x50, >> 0, >> > +1); clk_en_pcie0, 0, 0x50, 2, >> > +1); clk_en_gspi, 0, 0x50, 6, 1); >> > +clk_en_iso_misc, 0, 0x50, 10, >> > +1); clk_en_sds, 0, 0x50, 12, 1); >> > +clk_en_hdmi, 0, 0x50, 14, 1); >>=20 >> This is a lot of clock with no parents which is a bit suspicious especia= lly for >> gates. >> What is really feeding those ? >>=20 > > In v15, we will do our best to reduce the number of gate clocks without a= parent. > > However, after discussing with our colleague, we confirmed that for some = of > these NO_PARENT gate clocks, their actual upstream clocks (like PLLs and > Muxes) are located in separate, independent hardware subsystems. The regi= sters > controlling those upstream clocks are physically inaccessible from the Li= nux > CPU domain. Control and input are different things. It feels like your DT (binding) description is not complete as it stands which will eventually be a problem. A clock with no input is something that does generate the clock by itself, like an osciallator. Pretending it has no parent because you don't know how describe it yet is wrong. > > Best Regards, > Yu-Chun --=20 Jerome