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Tue, 26 May 2026 00:33:16 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:4a0c:b15a:3467:f4ed]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-490454ea134sm338481635e9.8.2026.05.26.00.33.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 May 2026 00:33:15 -0700 (PDT) From: Jerome Brunet To: Jian Hu via B4 Relay Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl , jian.hu@amlogic.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 00/10] Add support for A9 family clock controller In-Reply-To: <20260511-b4-a9_clk-v1-0-41cb4071b7c9@amlogic.com> (Jian Hu via's message of "Mon, 11 May 2026 20:47:22 +0800") References: <20260511-b4-a9_clk-v1-0-41cb4071b7c9@amlogic.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Tue, 26 May 2026 09:33:14 +0200 Message-ID: <1jldd662x1.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260526_003318_390759_79105E9A X-CRM114-Status: GOOD ( 20.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On lun. 11 mai 2026 at 20:47, Jian Hu via B4 Relay wrote: > There are 4 clock controllers in A9 SoC: > - SCMI clock controller: these clocks are managed by the > Trusted Firmware-A(TF-A) and handled through SCMI. > - PLL clock controller. > - peripheral clock controller. > - AO clock controller. > > There are reserved register regions placed between individual PLLs, so a > separate driver is implemented for each PLL, similar to T7. > > Compared to previous SoCs PLLs, the A9 PLL controller introduces 4 new features: > 1.PLL l_detect signal supports active-high configuration. > Previous A7 and T7 l_detect signals are active-low. > 2.PLL reset signal supports active-low configuration. > Previous reset signals are active-high. > 3.Support POWER_OF_TWO for the PLL pre-divider N; > the N pre-divider follows the same calculation rule as OD. > 4.The PLL input path includes an inherent divide-by-2 divider. > > Implement the first three features in clk-pll.c (verified on A9 and T7), > with no impact to PLL logic on existing SoCs. Add a fixed divide-by-2 to > A9 PLL driver for the fourth feature. > > A9 PLL is composed as follows: > > PLL > +---------------------------------+ > | | > | +--+ | > in/2 >>---[ /2^N ]-->| | +-----+ | > | | |------| DCO |----->> out > | +--------->| | +--v--+ | > | | +--+ | | > | | | | > | +--[ *(M + (F/Fmax) ]<--+ | > | | > +---------------------------------+ > > out = in / 2 * (m + frac / frac_max) / 2^n > > Signed-off-by: Jian Hu > --- > Jian Hu (10): > dt-bindings: clock: Add Amlogic A9 SCMI clock controller > dt-bindings: clock: Add Amlogic A9 PLL clock controller > dt-bindings: clock: Add Amlogic A9 peripherals clock controller > dt-bindings: clock: Add Amlogic A9 AO clock controller > clk: amlogic: PLL l_detect signal supports active-high configuration > clk: amlogic: PLL reset signal supports active-low configuration > clk: amlogic: Support POWER_OF_TWO for PLL pre-divider > clk: amlogic: Add A9 PLL clock controller driver > clk: amlogic: Add A9 peripherals clock controller driver > clk: amlogic: Add A9 AO clock controller driver > > .../bindings/clock/amlogic,a9-aoclkc.yaml | 76 + > .../clock/amlogic,a9-peripherals-clkc.yaml | 150 ++ > .../bindings/clock/amlogic,a9-pll-clkc.yaml | 110 + > drivers/clk/meson/Kconfig | 28 + > drivers/clk/meson/Makefile | 2 + > drivers/clk/meson/a9-aoclk.c | 494 +++++ > drivers/clk/meson/a9-peripherals.c | 2317 ++++++++++++++++++++ > drivers/clk/meson/a9-pll.c | 831 +++++++ > drivers/clk/meson/clk-pll.c | 79 +- > drivers/clk/meson/clk-pll.h | 6 + > include/dt-bindings/clock/amlogic,a9-aoclkc.h | 76 + > .../clock/amlogic,a9-peripherals-clkc.h | 352 +++ > include/dt-bindings/clock/amlogic,a9-pll-clkc.h | 55 + > include/dt-bindings/clock/amlogic,a9-scmi-clkc.h | 51 + > 14 files changed, 4609 insertions(+), 18 deletions(-) For the next version, please split things up. There is no hard dependency between the different controllers. This will ease the review. The PLL controllers are bringing a new contraints in. The global/static nature of the controllers is something that has been bothering me for a while but there was no real reason to address it so far. Please give me some time to think about. Feel free to re-post the other controllers in the meantime. > --- > base-commit: ca89c88bcf69daca829044c638a8163d5ce47af0 > change-id: 20260511-b4-a9_clk-67652c1ae56e > > Best regards, -- Jerome