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Thu, 14 May 2026 08:16:38 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:8f63:bf1e:b5:28d8]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-48fd7290007sm31793235e9.5.2026.05.14.08.16.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 May 2026 08:16:38 -0700 (PDT) From: Jerome Brunet To: Jian Hu via B4 Relay Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl , jian.hu@amlogic.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 06/10] clk: amlogic: PLL reset signal supports active-low configuration In-Reply-To: <20260511-b4-a9_clk-v1-6-41cb4071b7c9@amlogic.com> (Jian Hu via's message of "Mon, 11 May 2026 20:47:28 +0800") References: <20260511-b4-a9_clk-v1-0-41cb4071b7c9@amlogic.com> <20260511-b4-a9_clk-v1-6-41cb4071b7c9@amlogic.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Thu, 14 May 2026 17:16:36 +0200 Message-ID: <1jmry26my3.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260514_081640_743586_BB816225 X-CRM114-Status: GOOD ( 23.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On lun. 11 mai 2026 at 20:47, Jian Hu via B4 Relay wrote: > From: Jian Hu > > In the A9 design, the PLL reset signal is configured as active-low. > > Add the flag 'CLK_MESON_PLL_RST_N' to indicate that the PLL reset signal > is active-low. > > Signed-off-by: Jian Hu > --- > drivers/clk/meson/clk-pll.c | 42 +++++++++++++++++++++++++++++++----------- > drivers/clk/meson/clk-pll.h | 2 ++ > 2 files changed, 33 insertions(+), 11 deletions(-) > > diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c > index 5a0bd75f85a9..8568ad6ba7b6 100644 > --- a/drivers/clk/meson/clk-pll.c > +++ b/drivers/clk/meson/clk-pll.c > @@ -295,10 +295,14 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw) > { > struct clk_regmap *clk = to_clk_regmap(hw); > struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); > + unsigned int rst; > > - if (MESON_PARM_APPLICABLE(&pll->rst) && > - meson_parm_read(clk->map, &pll->rst)) > - return 0; > + if (MESON_PARM_APPLICABLE(&pll->rst)) { > + rst = meson_parm_read(clk->map, &pll->rst); > + if ((rst && !(pll->flags & CLK_MESON_PLL_RST_ACTIVE_LOW)) || > + (!rst && (pll->flags & CLK_MESON_PLL_RST_ACTIVE_LOW))) Again not a great usage of binary ops. What you've written above is the verbose version of a XOR. The code duplication remarks applies to the rest of the patch too > + return 0; > + } > > if (!meson_parm_read(clk->map, &pll->en) || > !meson_parm_read(clk->map, &pll->l)) > @@ -326,14 +330,22 @@ static int meson_clk_pll_init(struct clk_hw *hw) > return 0; > > if (pll->init_count) { > - if (MESON_PARM_APPLICABLE(&pll->rst)) > - meson_parm_write(clk->map, &pll->rst, 1); > + if (MESON_PARM_APPLICABLE(&pll->rst)) { > + if (pll->flags & CLK_MESON_PLL_RST_ACTIVE_LOW) > + meson_parm_write(clk->map, &pll->rst, 0); > + else > + meson_parm_write(clk->map, &pll->rst, 1); > + } > > regmap_multi_reg_write(clk->map, pll->init_regs, > pll->init_count); > > - if (MESON_PARM_APPLICABLE(&pll->rst)) > - meson_parm_write(clk->map, &pll->rst, 0); > + if (MESON_PARM_APPLICABLE(&pll->rst)) { > + if (pll->flags & CLK_MESON_PLL_RST_ACTIVE_LOW) > + meson_parm_write(clk->map, &pll->rst, 1); > + else > + meson_parm_write(clk->map, &pll->rst, 0); > + } > } > > return 0; > @@ -363,15 +375,23 @@ static int meson_clk_pll_enable(struct clk_hw *hw) > return 0; > > /* Make sure the pll is in reset */ > - if (MESON_PARM_APPLICABLE(&pll->rst)) > - meson_parm_write(clk->map, &pll->rst, 1); > + if (MESON_PARM_APPLICABLE(&pll->rst)) { > + if (pll->flags & CLK_MESON_PLL_RST_ACTIVE_LOW) > + meson_parm_write(clk->map, &pll->rst, 0); > + else > + meson_parm_write(clk->map, &pll->rst, 1); > + } > > /* Enable the pll */ > meson_parm_write(clk->map, &pll->en, 1); > > /* Take the pll out reset */ > - if (MESON_PARM_APPLICABLE(&pll->rst)) > - meson_parm_write(clk->map, &pll->rst, 0); > + if (MESON_PARM_APPLICABLE(&pll->rst)) { > + if (pll->flags & CLK_MESON_PLL_RST_ACTIVE_LOW) > + meson_parm_write(clk->map, &pll->rst, 1); > + else > + meson_parm_write(clk->map, &pll->rst, 0); > + } > > /* > * Compared with the previous SoCs, self-adaption current module > diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h > index 97b7c70376a3..1be7e6e77631 100644 > --- a/drivers/clk/meson/clk-pll.h > +++ b/drivers/clk/meson/clk-pll.h > @@ -31,6 +31,8 @@ struct pll_mult_range { > #define CLK_MESON_PLL_NOINIT_ENABLED BIT(1) > /* l_detect signal is active-high */ > #define CLK_MESON_PLL_L_DETECT_ACTIVE_HIGH BIT(2) > +/* rst signal is active-low (Power-on reset) */ > +#define CLK_MESON_PLL_RST_ACTIVE_LOW BIT(3) > > struct meson_clk_pll_data { > struct parm en; -- Jerome