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Mon, 15 Jun 2026 10:56:32 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:5176:ebe3:853b:8fb0]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-4606f2e6a8fsm36837329f8f.37.2026.06.15.10.56.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 10:56:31 -0700 (PDT) From: Jerome Brunet To: Chen-Yu Tsai Cc: Junhui Liu , Michael Turquette , Stephen Boyd , Jernej Skrabec , Samuel Holland , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?Q?Andr?= =?utf-8?Q?=C3=A9?= Przywara Subject: Re: [PATCH 7/7] clk: sunxi-ng: Add Allwinner A733 RTC CCU support In-Reply-To: (Chen-Yu Tsai's message of "Sat, 28 Mar 2026 22:41:20 +0800") References: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> <20260121-a733-rtc-v1-7-d359437f23a7@pigmoral.tech> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Mon, 15 Jun 2026 19:56:29 +0200 Message-ID: <1jv7bjd6wi.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260615_105633_952262_37E07610 X-CRM114-Status: GOOD ( 29.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On sam. 28 mars 2026 at 22:41, Chen-Yu Tsai wrote: > On Wed, Jan 21, 2026 at 7:04=E2=80=AFPM Junhui Liu wrote: >> >> Add support for the internal CCU found in the RTC module of the Allwinner >> A733 SoC. While the basic 16MHz (IOSC) and 32kHz logic remains compatible >> with older SoCs like the sun6i, the A733 introduces several new features. >> >> The A733 RTC CCU supports choosing one of three external crystal >> frequencies: 19.2MHz, 24MHz, and 26MHz. It features hardware detection >> logic to automatically identify the frequency used on the board and >> exports this DCXO signal as the "hosc" clock. >> >> Furthermore, the driver implements logic to derive a 32kHz reference >> from the HOSC. This is achieved through a muxed clock path using fixed >> pre-dividers to normalize the different crystal frequencies to ~32kHz. > > Have you tested whether the actually normalizes the frequency, i.e. > selects a different divider based on the DCXO frequency? Otherwise > we're just lying about the frequency. > >> This path reuses the same hardware mux registers as the HOSC clock. >> >> Additionally, this CCU provides several gate clocks for specific >> peripherals, including SerDes, HDMI, and UFS. The driver is implemented >> as an auxiliary driver to be bound to the sun6i-rtc driver. >> >> Signed-off-by: Junhui Liu >> --- [...] >> +}; >> + >> +static const struct clk_parent_data hosc_parents[] =3D { >> + { .fw_name =3D "osc24M" }, >> + { .fw_name =3D "osc19M" }, >> + { .fw_name =3D "osc26M" }, >> + { .fw_name =3D "osc24M" }, >> +}; > > As mentioned in my reply to the binding, this is wrong. There is only > one input. > > The most you can do is check the rate of the parent clock against the > detected one, and _scream_ that the DT is wrong. And maybe override > the reported frequency. > > If you want to do the latter, you could add a new fixed rate gated > clock type to our library. You would fill in the rate before the > clocks get registered. I probably wouldn't go that far. We want people > to have correct hardware descriptions. > > Funnily enough Allwinner's BSP actually implements a fixed rate gate > for the next 24M-to-32k divider clock. What about implementing the register bellow as a read-only (and non-cached) divider using the factors provided by Junhui ? That would be an accurate description of the HW I think. The oscillator gets set in DT and if the output reported past the divider is not 32728Hz, you know you've got a problem (bad DT or HW gone bad) With a fixed-rate gate, you may actually end up lying about what actually happen, if the HW does not behave as expected. Do you prefer a fixed-rate gate still or should I try the RO divider approach ? > >> + >> +struct ccu_mux hosc_clk =3D { >> + .enable =3D DCXO_CTRL_DCXO_EN, >> + .mux =3D _SUNXI_CCU_MUX(14, 2), >> + .common =3D { >> + .reg =3D DCXO_CTRL_REG, >> + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("hosc", >> + hosc_parents, >> + &ccu_mux_ro_o= ps, >> + 0), >> + }, >> +}; > > So this is wrong. > >> + >> +static const struct ccu_mux_fixed_prediv hosc_32k_predivs[] =3D { >> + { .index =3D 0, .div =3D 732 }, > > Why is it 732 instead of 750? > >> + { .index =3D 1, .div =3D 586 }, >> + { .index =3D 2, .div =3D 793 }, >> + { .index =3D 3, .div =3D 732 }, >> +}; >> + >> +static struct ccu_mux hosc_32k_mux_clk =3D { >> + .enable =3D DCXO_CTRL_DCXO_EN, >