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Tue, 26 Aug 2025 02:11:33 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:46d7:73a6:7b7:2201]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3cad431ea49sm4204236f8f.42.2025.08.26.02.11.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Aug 2025 02:11:32 -0700 (PDT) From: Jerome Brunet To: Chuan Liu Cc: Da Xue , Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Jian Hu , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] clk: meson-g12a: fix bit range for fixed sys and hifi pll In-Reply-To: (Chuan Liu's message of "Tue, 26 Aug 2025 15:59:32 +0800") References: <20250822002203.1979235-1-da@libre.computer> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Tue, 26 Aug 2025 11:11:32 +0200 Message-ID: <1jy0r64fcr.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250826_021135_816115_26CE1660 X-CRM114-Status: GOOD ( 26.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue 26 Aug 2025 at 15:59, Chuan Liu wrote: > Hi Da: > > =C2=A0 =C2=A0=C2=A0Thanks for your feedback.=C2=A0but this patch is wrong. > > > On 8/22/2025 8:22 AM, Da Xue wrote: >> [ EXTERNAL EMAIL ] >> >> The bit range 17:0 does not match the datasheet for A311D / S905D3. >> Change the bit range to 18:0 for FIX and HIFI PLLs to match datasheet. > > > The upper 2 bits (bit18, bit17) of the frac were deprecated long ago. deprecated ? that is really confusing That seems to imply that it does have an effect but you are choosing not to use it. Please clarify. > The actual effective bit field for frac is bit[16:0]. However, the > corresponding datasheet has not been updated. I will provide feedback > and update the datasheet accordingly. > What about bit 17 and 18 then ? does it have any effect at all ? > >> >> The frac field is missing for sys pll so add that as well. > > > PLLs with frac support are used in scenarios requiring a wide range > of output frequencies (e.g., audio/video applications). > > Since sys_pll is dedicated to clocking the CPU and does not require > such frequency versatility, it does not support fractional frequency > multiplication. You are mixing "HW support" and "usage choice" here. What I read is : * Da says the SYS PLL does have HW support for the frac parameter * Amlogic does not see the point of using it since the CPU does not require fine tuning of the rate. Is that correct ? or is the HW just no present ? > > >> >> Patched: >> >> + sudo cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq \ >> /sys/devices/system/cpu/cpufreq/policy2/cpuinfo_cur_freq >> 996999 >> 500000 >> + sudo cat /sys/kernel/debug/meson-clk-msr/measure_summary >> + grep -i '\(sys_\|hifi_\|fixed_\)pll' >> hifi_pll 0 +/-1562Hz >> sys_pll_div16 0 +/-1562Hz >> sys_pll_cpub_div16 0 +/-1562Hz >> + sudo cat /sys/kernel/debug/clk/clk_summary >> + grep -i '\(sys_\|hifi_\|fixed_\)pll' >> hifi_pll_dco 0 0 0 0 >> hifi_pll 0 0 0 0 >> sys_pll_dco 1 1 0 39999999= 85 >> sys_pll 0 0 0 499999999 >> sys_pll_div16_en 0 0 0 499999999 >> sys_pll_div16 0 0 0 31249999 >> fixed_pll_dco 1 1 1 39879999= 85 >> fixed_pll 3 3 1 19939999= 93 >> >> Unpatch: >> >> + sudo cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq \ >> /sys/devices/system/cpu/cpufreq/policy2/cpuinfo_cur_freq >> 1000000 >> 500000 >> + sudo cat /sys/kernel/debug/meson-clk-msr/measure_summary >> + grep -i '\(sys_\|hifi_\|fixed_\)pll' >> hifi_pll 0 +/-1562Hz >> sys_pll_div16 0 +/-1562Hz >> sys_pll_cpub_div16 0 +/-1562Hz >> + sudo cat /sys/kernel/debug/clk/clk_summary >> + grep -i '\(sys_\|hifi_\|fixed_\)pll' >> hifi_pll_dco 0 0 0 0 >> hifi_pll 0 0 0 0 >> sys_pll_dco 1 1 0 48000000= 00 >> sys_pll 0 0 0 12000000= 00 >> sys_pll_div16_en 0 0 0 12000000= 00 >> sys_pll_div16 0 0 0 75000000 >> fixed_pll_dco 1 1 1 39999999= 39 >> fixed_pll 3 3 1 19999999= 70 >> >> Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") >> Signed-off-by: Da Xue >> --- >> drivers/clk/meson/g12a.c | 9 +++++++-- >> 1 file changed, 7 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c >> index 66f0e817e416..f78cca619ca5 100644 >> --- a/drivers/clk/meson/g12a.c >> +++ b/drivers/clk/meson/g12a.c >> @@ -157,7 +157,7 @@ static struct clk_regmap g12a_fixed_pll_dco =3D { >> .frac =3D { >> .reg_off =3D HHI_FIX_PLL_CNTL1, >> .shift =3D 0, >> - .width =3D 17, >> + .width =3D 19, >> }, >> .l =3D { >> .reg_off =3D HHI_FIX_PLL_CNTL0, >> @@ -223,6 +223,11 @@ static struct clk_regmap g12a_sys_pll_dco =3D { >> .shift =3D 10, >> .width =3D 5, >> }, >> + .frac =3D { >> + .reg_off =3D HHI_SYS_PLL_CNTL1, >> + .shift =3D 0, >> + .width =3D 19, >> + }, >> .l =3D { >> .reg_off =3D HHI_SYS_PLL_CNTL0, >> .shift =3D 31, >> @@ -1901,7 +1906,7 @@ static struct clk_regmap g12a_hifi_pll_dco =3D { >> .frac =3D { >> .reg_off =3D HHI_HIFI_PLL_CNTL1, >> .shift =3D 0, >> - .width =3D 17, >> + .width =3D 19, >> }, >> .l =3D { >> .reg_off =3D HHI_HIFI_PLL_CNTL0, >> -- >> 2.47.2 >> >> >> _______________________________________________ >> linux-amlogic mailing list >> linux-amlogic@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-amlogic --=20 Jerome