Kernel related (?) user space crash at ARM11 MPCore

[linux@arm.linux.org.uk (Russell King - ARM Linux)]

On Mon, Sep 21, 2009 at 11:12:29PM +0100, Jamie Lokier wrote:
> Btw, regarding "non-aliasing", it's pretty clear that it does alias
> the I-cache ;-), in much the same way as different addresses alias in
> the D-cache with an "aliasing" cache.  That may well be a clue as to
> clean, systematic and sane way of ensuring all the cache ops are in
> all the right places.

If you want your kernel to flush the I and D caches on every page fault,
process creation and exit, be my guest.  I'd rather have a system with
some reasonable performance left in it rather than being relegated back
to the days of VIVT caches.

The key thing is to work out the _minimum_ amount of cache flushing,
not just throw cache flushing blindly in.

MPCore, btw, is PIPT write allocate harvard.  In other words, it is
fully coherent with virtual mappings - the only things it isn't
coherent with is the instruction cache and DMA.  It'd be absolutely
stupid to have to throw the heavy weights of flushing large amounts
of cache for what is basically a small localized problem.