* [PATCH v3 0/8] [ARM] ST-Ericsson's U8500 SMP platform, a new patch set
@ 2009-10-11 22:26 srinidhi kasagar
2009-10-11 22:27 ` [PATCH v3 1/7] [ARM]: U8500 register definitions srinidhi kasagar
2009-10-14 22:17 ` [PATCH v3 0/8] [ARM] ST-Ericsson's U8500 SMP platform, a new patch set srinidhi kasagar
0 siblings, 2 replies; 4+ messages in thread
From: srinidhi kasagar @ 2009-10-11 22:26 UTC (permalink / raw)
To: linux-arm-kernel
From: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
This adds a new machine support for ST-Ericsson's U8500 platform. This is
an entry level patch which has bindings to existing modules like GIC, SCU,
TWD, PL011 UART. This also adds a new SPI device AB4500 (odler name STW4500)
which uses ARM pl022 bus driver.
There are similarly numbered platforms will appear in the near future bearing
ux500 naming scheme, and hence this patch set has this name for the first
U8500 platform. This is v3 patch re-based to linux-2.6.32-rc3, and fixed most
of the review comments. For the patch 7/7 to work on hardware, get the
patch 5741 from Russell's patch tracking system.
srinidhi kasagar (7):
[ARM]: U8500 register definitions
[ARM]: U8500 clock framework
[ARM]: U8500 core machine support
[ARM]: U8500 Makefile.boot
[ARM]: U8500 integrate to ARM architecture
[ARM]: adds AB4500 as pl022 device
mfd: add AB4500 SPI used in U8500
arch/arm/Kconfig | 19 ++-
arch/arm/Makefile | 1 +
arch/arm/mach-ux500/Kconfig | 15 ++
arch/arm/mach-ux500/Makefile | 8 +
.../{mach-footbridge => mach-ux500}/Makefile.boot | 0
arch/arm/mach-ux500/board-mop500.c | 146 +++++++++++
arch/arm/mach-ux500/clock.c | 95 +++++++
arch/arm/mach-ux500/cpu-u8500.c | 78 ++++++
arch/arm/mach-ux500/headsmp.S | 38 +++
.../include/mach/clkdev.h | 0
arch/arm/mach-ux500/include/mach/debug-macro.S | 19 ++
arch/arm/mach-ux500/include/mach/entry-macro.S | 89 +++++++
arch/arm/mach-ux500/include/mach/hardware.h | 129 ++++++++++
arch/arm/mach-ux500/include/mach/io.h | 22 ++
arch/arm/mach-ux500/include/mach/irqs.h | 71 ++++++
arch/arm/mach-ux500/include/mach/memory.h | 18 ++
arch/arm/mach-ux500/include/mach/mtu.h | 53 ++++
arch/arm/mach-ux500/include/mach/setup.h | 22 ++
arch/arm/mach-ux500/include/mach/smp.h | 32 +++
arch/arm/mach-ux500/include/mach/system.h | 25 ++
arch/arm/mach-ux500/include/mach/timex.h | 6 +
arch/arm/mach-ux500/include/mach/uncompress.h | 58 +++++
arch/arm/mach-ux500/include/mach/vmalloc.h | 18 ++
arch/arm/mach-ux500/localtimer.c | 28 ++
arch/arm/mach-ux500/platsmp.c | 186 ++++++++++++++
arch/arm/mach-ux500/timer.c | 163 ++++++++++++
drivers/mfd/Kconfig | 10 +
drivers/mfd/Makefile | 1 +
drivers/mfd/ab4500-core.c | 207 +++++++++++++++
include/linux/mfd/ab4500.h | 262 ++++++++++++++++++++
30 files changed, 1815 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mach-ux500/Kconfig
create mode 100644 arch/arm/mach-ux500/Makefile
copy arch/arm/{mach-footbridge => mach-ux500}/Makefile.boot (100%)
create mode 100644 arch/arm/mach-ux500/board-mop500.c
create mode 100644 arch/arm/mach-ux500/clock.c
create mode 100644 arch/arm/mach-ux500/cpu-u8500.c
create mode 100644 arch/arm/mach-ux500/headsmp.S
copy arch/arm/{mach-bcmring => mach-ux500}/include/mach/clkdev.h (100%)
create mode 100644 arch/arm/mach-ux500/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-ux500/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-ux500/include/mach/hardware.h
create mode 100644 arch/arm/mach-ux500/include/mach/io.h
create mode 100644 arch/arm/mach-ux500/include/mach/irqs.h
create mode 100644 arch/arm/mach-ux500/include/mach/memory.h
create mode 100644 arch/arm/mach-ux500/include/mach/mtu.h
create mode 100644 arch/arm/mach-ux500/include/mach/setup.h
create mode 100644 arch/arm/mach-ux500/include/mach/smp.h
create mode 100644 arch/arm/mach-ux500/include/mach/system.h
create mode 100644 arch/arm/mach-ux500/include/mach/timex.h
create mode 100644 arch/arm/mach-ux500/include/mach/uncompress.h
create mode 100644 arch/arm/mach-ux500/include/mach/vmalloc.h
create mode 100644 arch/arm/mach-ux500/localtimer.c
create mode 100644 arch/arm/mach-ux500/platsmp.c
create mode 100644 arch/arm/mach-ux500/timer.c
create mode 100755 drivers/mfd/ab4500-core.c
create mode 100644 include/linux/mfd/ab4500.h
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v3 1/7] [ARM]: U8500 register definitions
@ 2009-10-11 22:27 ` srinidhi kasagar
2009-10-17 14:31 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 4+ messages in thread
From: srinidhi kasagar @ 2009-10-11 22:27 UTC (permalink / raw)
To: linux-arm-kernel
From: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
This adds registers, shared peripheral interrupt numbers
and IO mappings for the U8500 platform core support.
Shared peripheral interrupts (SPI) are assigned to
[160:32], wherein first 32 interrupts are reserved.
Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
Reviewed-by: Alessandro Rubini <rubini@unipv.it>
---
arch/arm/mach-ux500/include/mach/hardware.h | 129 +++++++++++++++++++++++++++
arch/arm/mach-ux500/include/mach/io.h | 22 +++++
arch/arm/mach-ux500/include/mach/irqs.h | 71 +++++++++++++++
3 files changed, 222 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-ux500/include/mach/hardware.h
create mode 100644 arch/arm/mach-ux500/include/mach/io.h
create mode 100644 arch/arm/mach-ux500/include/mach/irqs.h
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
new file mode 100644
index 0000000..23fec82
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * U8500 hardware definitions
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/* macros to get at IO space when running virtually
+ * We dont map all the peripherals, let ioremap do
+ * this for us. We map only very basic peripherals here.
+ */
+#define U8500_IO_VIRTUAL 0xf0000000
+#define U8500_IO_PHYSICAL 0xa0000000
+
+/* this macro is used in assembly, so no cast */
+#define IO_ADDRESS(x) ((x) - U8500_IO_PHYSICAL + U8500_IO_VIRTUAL)
+
+/* typesafe io address */
+#define __io_address(n) __io(IO_ADDRESS(n))
+
+/*
+ * Base address definitions for U8500 Onchip IPs. All the
+ * peripherals are contained in a single 1 Mbyte region, with
+ * AHB peripherals at the bottom and APB peripherals at the
+ * top of the region. PER stands for PERIPHERAL region which
+ * itself divided into sub regions.
+ */
+#define U8500_PER3_BASE 0x80000000
+#define U8500_PER2_BASE 0x80110000
+#define U8500_PER1_BASE 0x80120000
+#define U8500_PER4_BASE 0x80150000
+
+#define U8500_PER6_BASE 0xa03c0000
+#define U8500_PER5_BASE 0xa03e0000
+#define U8500_PER7_BASE 0xa03d0000
+
+#define U8500_SVA_BASE 0xa0100000
+#define U8500_SIA_BASE 0xa0200000
+
+#define U8500_SGA_BASE 0xa0300000
+#define U8500_MCDE_BASE 0xa0350000
+#define U8500_DMA_BASE 0xa0362000
+
+#define U8500_SCU_BASE 0xa0410000
+#define U8500_GIC_CPU_BASE 0xa0410100
+#define U8500_TWD_BASE 0xa0410600
+#define U8500_GIC_DIST_BASE 0xa0411000
+#define U8500_L2CC_BASE 0xa0412000
+
+#define U8500_TWD_SIZE 0x100
+
+/* per7 base addressess */
+#define U8500_CR_BASE (U8500_PER7_BASE + 0x8000)
+#define U8500_MTU0_BASE (U8500_PER7_BASE + 0xa000)
+#define U8500_MTU1_BASE (U8500_PER7_BASE + 0xb000)
+#define U8500_TZPC0_BASE (U8500_PER7_BASE + 0xc000)
+#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
+
+/* per6 base addressess */
+#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
+#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
+#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
+#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
+#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
+#define U8500_CLKRST6_BASE (U8500_PER7_BASE + 0xf000)
+
+/* per5 base addressess */
+#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
+#define U8500_GPIO5_BASE (U8500_PER5_BASE + 0x1e000)
+#define U8500_CLKRST5_BASE (U8500_PER7_BASE + 0x1f000)
+
+/* per4 base addressess */
+#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x0000)
+#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x1000)
+#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x2000)
+#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x3000)
+#define U8500_RTC_BASE (U8500_PER4_BASE + 0x4000)
+#define U8500_SCR_BASE (U8500_PER4_BASE + 0x5000)
+#define U8500_DMC_BASE (U8500_PER4_BASE + 0x6000)
+#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x7000)
+
+/* per3 base addressess */
+#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
+#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
+#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
+#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
+#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
+#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
+#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
+#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
+#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xe000)
+#define U8500_CLKRST3_BASE (U8500_PER7_BASE + 0xf000)
+
+/* per2 base addressess */
+#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
+#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
+#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
+#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
+#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
+#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
+#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
+#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
+#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
+#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
+#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
+#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xe000)
+#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
+
+/* per1 base addresses */
+#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
+#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
+#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
+#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
+#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
+#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
+#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
+#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
+#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xa000)
+#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xe000)
+#define U8500_CLKRST1_BASE (U8500_PER2_BASE + 0xf000)
+
+#define U8500_BACKUPRAM0_VA_BASE 0xf0413000
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-ux500/include/mach/io.h b/arch/arm/mach-ux500/include/mach/io.h
new file mode 100644
index 0000000..1cf3f44
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/io.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-u8500/include/mach/io.h
+ *
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Modifications:
+ * 06-12-1997 RMK Created.
+ * 07-04-1999 RMK Major cleanup
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a) __typesafe_io(a)
+#define __mem_pci(a) (a)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
new file mode 100644
index 0000000..69d6dde
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2008 STMicroelectronics
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef ASM_ARCH_IRQS_H
+#define ASM_ARCH_IRQS_H
+
+#include <mach/hardware.h>
+
+#define IRQ_LOCALTIMER 29
+#define IRQ_LOCALWDOG 30
+
+/* Shared Peripheral Interrupt */
+#define IRQ_SPI_START 32
+
+/* Interrupt numbers generic for shared peripheral */
+#define IRQ_MTU0 (IRQ_SPI_START + 4)
+#define IRQ_SPI2 (IRQ_SPI_START + 6)
+#define IRQ_SPI0 (IRQ_SPI_START + 8)
+#define IRQ_UART0 (IRQ_SPI_START + 11)
+#define IRQ_I2C3 (IRQ_SPI_START + 12)
+#define IRQ_SSP0 (IRQ_SPI_START + 14)
+#define IRQ_MTU1 (IRQ_SPI_START + 17)
+#define IRQ_RTC_RTT (IRQ_SPI_START + 18)
+#define IRQ_UART1 (IRQ_SPI_START + 19)
+#define IRQ_I2C0 (IRQ_SPI_START + 21)
+#define IRQ_I2C1 (IRQ_SPI_START + 22)
+#define IRQ_USBOTG (IRQ_SPI_START + 23)
+#define IRQ_DMA (IRQ_SPI_START + 25)
+#define IRQ_UART2 (IRQ_SPI_START + 26)
+#define IRQ_HSIR_EXCEP (IRQ_SPI_START + 29)
+#define IRQ_MSP0 (IRQ_SPI_START + 31)
+#define IRQ_HSIR_CH0_OVRRUN (IRQ_SPI_START + 32)
+#define IRQ_HSIR_CH1_OVRRUN (IRQ_SPI_START + 33)
+#define IRQ_HSIR_CH2_OVRRUN (IRQ_SPI_START + 34)
+#define IRQ_HSIR_CH3_OVRRUN (IRQ_SPI_START + 35)
+#define AB4500_IRQ (IRQ_SPI_START + 40)
+#define IRQ_DISP (IRQ_SPI_START + 48)
+#define IRQ_SPI3 (IRQ_SPI_START + 49)
+#define IRQ_SSP1 (IRQ_SPI_START + 52)
+#define IRQ_I2C2 (IRQ_SPI_START + 55)
+#define IRQ_SDMMC0 (IRQ_SPI_START + 60)
+#define IRQ_MSP1 (IRQ_SPI_START + 62)
+#define IRQ_SPI1 (IRQ_SPI_START + 96)
+#define IRQ_MSP2 (IRQ_SPI_START + 98)
+#define IRQ_SDMMC4 (IRQ_SPI_START + 99)
+#define IRQ_HSIRD0 (IRQ_SPI_START + 104)
+#define IRQ_HSIRD1 (IRQ_SPI_START + 105)
+#define IRQ_HSITD0 (IRQ_SPI_START + 106)
+#define IRQ_HSITD1 (IRQ_SPI_START + 107)
+#define IRQ_GPIO0 (IRQ_SPI_START + 119)
+#define IRQ_GPIO1 (IRQ_SPI_START + 120)
+#define IRQ_GPIO2 (IRQ_SPI_START + 121)
+#define IRQ_GPIO3 (IRQ_SPI_START + 122)
+#define IRQ_GPIO4 (IRQ_SPI_START + 123)
+#define IRQ_GPIO5 (IRQ_SPI_START + 124)
+#define IRQ_GPIO6 (IRQ_SPI_START + 125)
+#define IRQ_GPIO7 (IRQ_SPI_START + 126)
+#define IRQ_GPIO8 (IRQ_SPI_START + 127)
+
+/* There are 128 shared peripheral interrupts assigned to
+ * INTID[160:32]. The first 32 interrupts are reserved.
+ */
+#define NR_IRQS 161
+
+#endif /*ASM_ARCH_IRQS_H*/
--
1.6.3.GIT
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v3 1/7] [ARM]: U8500 register definitions
2009-10-11 22:27 ` [PATCH v3 1/7] [ARM]: U8500 register definitions srinidhi kasagar
@ 2009-10-17 14:31 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 4+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2009-10-17 14:31 UTC (permalink / raw)
To: linux-arm-kernel
> +
> +/* this macro is used in assembly, so no cast */
> +#define IO_ADDRESS(x) ((x) - U8500_IO_PHYSICAL + U8500_IO_VIRTUAL)
> +
> +/* typesafe io address */
> +#define __io_address(n) __io(IO_ADDRESS(n))
please check your pathes as there is some whitesape in it
> +
> +/*
> + * Base address definitions for U8500 Onchip IPs. All the
> + * peripherals are contained in a single 1 Mbyte region, with
> + * AHB peripherals at the bottom and APB peripherals at the
> + * top of the region. PER stands for PERIPHERAL region which
> + * itself divided into sub regions.
> + */
> +#define U8500_PER3_BASE 0x80000000
> +#define U8500_PER2_BASE 0x80110000
> +#define U8500_PER1_BASE 0x80120000
> +#define U8500_PER4_BASE 0x80150000
> +
> +#define U8500_PER6_BASE 0xa03c0000
> +#define U8500_PER5_BASE 0xa03e0000
> +#define U8500_PER7_BASE 0xa03d0000
It will be nice to keep this named ordered
> +
> +#define U8500_SVA_BASE 0xa0100000
> +#define U8500_SIA_BASE 0xa0200000
> +
> +#define U8500_SGA_BASE 0xa0300000
> +#define U8500_MCDE_BASE 0xa0350000
> +#define U8500_DMA_BASE 0xa0362000
> +
> +#define U8500_SCU_BASE 0xa0410000
> +#define U8500_GIC_CPU_BASE 0xa0410100
> +#define U8500_TWD_BASE 0xa0410600
> +#define U8500_GIC_DIST_BASE 0xa0411000
> +#define U8500_L2CC_BASE 0xa0412000
> +
> +#define U8500_TWD_SIZE 0x100
it will be better to regroup base address by funtionnality intead of PERx_BASE
and keep them ordered
> +
> +/* per7 base addressess */
> +#define U8500_CR_BASE (U8500_PER7_BASE + 0x8000)
> +#define U8500_MTU0_BASE (U8500_PER7_BASE + 0xa000)
> +#define U8500_MTU1_BASE (U8500_PER7_BASE + 0xb000)
> +#define U8500_TZPC0_BASE (U8500_PER7_BASE + 0xc000)
> +#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
> +
<snip>
> diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
> new file mode 100644
> index 0000000..69d6dde
> --- /dev/null
> +++ b/arch/arm/mach-ux500/include/mach/irqs.h
> @@ -0,0 +1,71 @@
> +/*
> + * Copyright (C) 2008 STMicroelectronics
> + * Copyright (C) 2009 ST-Ericsson.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +#ifndef ASM_ARCH_IRQS_H
> +#define ASM_ARCH_IRQS_H
> +
> +#include <mach/hardware.h>
> +
> +#define IRQ_LOCALTIMER 29
> +#define IRQ_LOCALWDOG 30
> +
> +/* Shared Peripheral Interrupt */
> +#define IRQ_SPI_START 32
SPI is a few confusing maybe you can replace it by IRQ_SHPI_START or something
else
Best Regards,
J.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v3 0/8] [ARM] ST-Ericsson's U8500 SMP platform, a new patch set
2009-10-11 22:26 [PATCH v3 0/8] [ARM] ST-Ericsson's U8500 SMP platform, a new patch set srinidhi kasagar
2009-10-11 22:27 ` [PATCH v3 1/7] [ARM]: U8500 register definitions srinidhi kasagar
@ 2009-10-14 22:17 ` srinidhi kasagar
1 sibling, 0 replies; 4+ messages in thread
From: srinidhi kasagar @ 2009-10-14 22:17 UTC (permalink / raw)
To: linux-arm-kernel
The v3 patch is same as v2 which I have sent on 24th September, with some fixes
and re-ordering of patches are done in this version.
regards,
Srinidhi
On Mon, 2009-10-12 at 03:56 +0530, srinidhi kasagar wrote:
> From: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
>
> This adds a new machine support for ST-Ericsson's U8500 platform. This is
> an entry level patch which has bindings to existing modules like GIC, SCU,
> TWD, PL011 UART. This also adds a new SPI device AB4500 (odler name STW4500)
> which uses ARM pl022 bus driver.
>
> There are similarly numbered platforms will appear in the near future bearing
> ux500 naming scheme, and hence this patch set has this name for the first
> U8500 platform. This is v3 patch re-based to linux-2.6.32-rc3, and fixed most
> of the review comments. For the patch 7/7 to work on hardware, get the
> patch 5741 from Russell's patch tracking system.
>
> srinidhi kasagar (7):
> [ARM]: U8500 register definitions
> [ARM]: U8500 clock framework
> [ARM]: U8500 core machine support
> [ARM]: U8500 Makefile.boot
> [ARM]: U8500 integrate to ARM architecture
> [ARM]: adds AB4500 as pl022 device
> mfd: add AB4500 SPI used in U8500
>
> arch/arm/Kconfig | 19 ++-
> arch/arm/Makefile | 1 +
> arch/arm/mach-ux500/Kconfig | 15 ++
> arch/arm/mach-ux500/Makefile | 8 +
> .../{mach-footbridge => mach-ux500}/Makefile.boot | 0
> arch/arm/mach-ux500/board-mop500.c | 146 +++++++++++
> arch/arm/mach-ux500/clock.c | 95 +++++++
> arch/arm/mach-ux500/cpu-u8500.c | 78 ++++++
> arch/arm/mach-ux500/headsmp.S | 38 +++
> .../include/mach/clkdev.h | 0
> arch/arm/mach-ux500/include/mach/debug-macro.S | 19 ++
> arch/arm/mach-ux500/include/mach/entry-macro.S | 89 +++++++
> arch/arm/mach-ux500/include/mach/hardware.h | 129 ++++++++++
> arch/arm/mach-ux500/include/mach/io.h | 22 ++
> arch/arm/mach-ux500/include/mach/irqs.h | 71 ++++++
> arch/arm/mach-ux500/include/mach/memory.h | 18 ++
> arch/arm/mach-ux500/include/mach/mtu.h | 53 ++++
> arch/arm/mach-ux500/include/mach/setup.h | 22 ++
> arch/arm/mach-ux500/include/mach/smp.h | 32 +++
> arch/arm/mach-ux500/include/mach/system.h | 25 ++
> arch/arm/mach-ux500/include/mach/timex.h | 6 +
> arch/arm/mach-ux500/include/mach/uncompress.h | 58 +++++
> arch/arm/mach-ux500/include/mach/vmalloc.h | 18 ++
> arch/arm/mach-ux500/localtimer.c | 28 ++
> arch/arm/mach-ux500/platsmp.c | 186 ++++++++++++++
> arch/arm/mach-ux500/timer.c | 163 ++++++++++++
> drivers/mfd/Kconfig | 10 +
> drivers/mfd/Makefile | 1 +
> drivers/mfd/ab4500-core.c | 207 +++++++++++++++
> include/linux/mfd/ab4500.h | 262 ++++++++++++++++++++
> 30 files changed, 1815 insertions(+), 4 deletions(-)
> create mode 100644 arch/arm/mach-ux500/Kconfig
> create mode 100644 arch/arm/mach-ux500/Makefile
> copy arch/arm/{mach-footbridge => mach-ux500}/Makefile.boot (100%)
> create mode 100644 arch/arm/mach-ux500/board-mop500.c
> create mode 100644 arch/arm/mach-ux500/clock.c
> create mode 100644 arch/arm/mach-ux500/cpu-u8500.c
> create mode 100644 arch/arm/mach-ux500/headsmp.S
> copy arch/arm/{mach-bcmring => mach-ux500}/include/mach/clkdev.h (100%)
> create mode 100644 arch/arm/mach-ux500/include/mach/debug-macro.S
> create mode 100644 arch/arm/mach-ux500/include/mach/entry-macro.S
> create mode 100644 arch/arm/mach-ux500/include/mach/hardware.h
> create mode 100644 arch/arm/mach-ux500/include/mach/io.h
> create mode 100644 arch/arm/mach-ux500/include/mach/irqs.h
> create mode 100644 arch/arm/mach-ux500/include/mach/memory.h
> create mode 100644 arch/arm/mach-ux500/include/mach/mtu.h
> create mode 100644 arch/arm/mach-ux500/include/mach/setup.h
> create mode 100644 arch/arm/mach-ux500/include/mach/smp.h
> create mode 100644 arch/arm/mach-ux500/include/mach/system.h
> create mode 100644 arch/arm/mach-ux500/include/mach/timex.h
> create mode 100644 arch/arm/mach-ux500/include/mach/uncompress.h
> create mode 100644 arch/arm/mach-ux500/include/mach/vmalloc.h
> create mode 100644 arch/arm/mach-ux500/localtimer.c
> create mode 100644 arch/arm/mach-ux500/platsmp.c
> create mode 100644 arch/arm/mach-ux500/timer.c
> create mode 100755 drivers/mfd/ab4500-core.c
> create mode 100644 include/linux/mfd/ab4500.h
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2009-10-17 14:31 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2009-10-11 22:26 [PATCH v3 0/8] [ARM] ST-Ericsson's U8500 SMP platform, a new patch set srinidhi kasagar
2009-10-11 22:27 ` [PATCH v3 1/7] [ARM]: U8500 register definitions srinidhi kasagar
2009-10-17 14:31 ` Jean-Christophe PLAGNIOL-VILLARD
2009-10-14 22:17 ` [PATCH v3 0/8] [ARM] ST-Ericsson's U8500 SMP platform, a new patch set srinidhi kasagar
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).