* [PATCH 00/25] imx cleanups
@ 2009-11-16 20:34 Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 01/25] imx: reorder mx2x.h Uwe Kleine-König
2009-11-18 9:46 ` [PATCH 00/25] imx cleanups Sascha Hauer
0 siblings, 2 replies; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
this series is the start of a big cleanup of the imx support. The
overall goal is to support all SoCs with a single image. Therefor a few
things need to/should be done:
- clean up headers not to define the same constants (i.e. prefix
everything with the SoC's name)
- generalise device creation
- generalise static mappings
- probably much more
Here I start with the first two items.
On the way I plan to change all occurences of "mxc" to "imx".
I hope this all can happen without much breakage.
For now no #defines are removed only redefined. So all code should
continue to work as before. Assuming this series is accepted new usage
of the #defines without a SoC-prefix should be deprecated. When all
users are converted, the old #defines can go away.
git branch, shortlog and diffstat can be found below. It merges nearly
fine into Sascha's mxc-master. There's only a trivial conflict in
arch/arm/plat-mxc/Makefile .
Best regards
Uwe
The following changes since commit aa021baa3295fa6e3f367d80f8955dd5176656eb:
Linus Torvalds (1):
Merge git://git.kernel.org/.../mason/btrfs-unstable
are available in the git repository at:
git://git.pengutronix.de/git/ukl/linux-2.6.git imx
Uwe Kleine-K?nig (25):
imx: reorder mx2x.h
imx: reorder mx21.h
imx: reorder mx27.h
imx: reorder mx3x.h
imx: add namespace prefixes for symbols in mx2x.h
imx: add namespace prefixes for symbols in mx21.h
imx: add namespace prefixes for symbols in mx27.h
imx: add namespace prefixes for symbols in mx3x.h
imx: add namespace prefixes for symbols in mx31.h
imx: add namespace prefixes for symbols in mx35.h
imx: reformat mx25.h to match the other platform includes
imx: copy constants from mx2x.h to mx21.h using the appropriate namespace
imx: copy constants from mx2x.h to mx27.h using the appropriate namespace
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace
imx: copy constants from mx3x.h to mx35.h using the appropriate namespace
imx: generalize nand device registration
imx/eukrea_cpuimx27: use new nand device registration
imx/mx21ads: use new nand device registration
imx/mx27ads: use new nand device registration
imx/pca100: use new nand device registration
imx/pcm038: use new nand device registration
imx/armadillo5x0: use new nand device registration
imx/mx31lite: use new nand device registration
imx/pcm037: use new nand device registration
imx/mx25pdk: remove unused include
arch/arm/mach-mx2/devices.h | 2 +
arch/arm/mach-mx2/eukrea_cpuimx27.c | 13 +-
arch/arm/mach-mx2/mx21ads.c | 13 +-
arch/arm/mach-mx2/mx27ads.c | 13 +-
arch/arm/mach-mx2/pca100.c | 12 +-
arch/arm/mach-mx2/pcm038.c | 13 +-
arch/arm/mach-mx25/mx25pdk.c | 1 -
arch/arm/mach-mx3/armadillo5x0.c | 16 +-
arch/arm/mach-mx3/devices.h | 1 +
arch/arm/mach-mx3/mx31lite.c | 12 +-
arch/arm/mach-mx3/pcm037.c | 12 +-
arch/arm/mach-mxc91231/devices.h | 2 +
arch/arm/plat-mxc/Makefile | 2 +
arch/arm/plat-mxc/devices/Makefile | 1 +
arch/arm/plat-mxc/devices/platform-mxc_nand.c | 54 +++
arch/arm/plat-mxc/include/mach/devices-common.h | 20 ++
arch/arm/plat-mxc/include/mach/mx21.h | 207 ++++++++++--
arch/arm/plat-mxc/include/mach/mx25.h | 10 +-
arch/arm/plat-mxc/include/mach/mx27.h | 315 ++++++++++++++----
arch/arm/plat-mxc/include/mach/mx2x.h | 339 ++++++++++++-------
arch/arm/plat-mxc/include/mach/mx31.h | 237 +++++++++++--
arch/arm/plat-mxc/include/mach/mx35.h | 201 ++++++++++-
arch/arm/plat-mxc/include/mach/mx3x.h | 413 +++++++++++++++--------
23 files changed, 1438 insertions(+), 471 deletions(-)
create mode 100644 arch/arm/plat-mxc/devices/Makefile
create mode 100644 arch/arm/plat-mxc/devices/platform-mxc_nand.c
create mode 100644 arch/arm/plat-mxc/include/mach/devices-common.h
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 01/25] imx: reorder mx2x.h
2009-11-16 20:34 [PATCH 00/25] imx cleanups Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 02/25] imx: reorder mx21.h Uwe Kleine-König
2009-11-18 9:46 ` [PATCH 00/25] imx cleanups Sascha Hauer
1 sibling, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx2x.h | 138 ++++++++++++++++----------------
1 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index db5d921..c0df87f 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -105,78 +105,78 @@
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
/* fixed interrupt numbers */
-#define MXC_INT_LCDC 61
-#define MXC_INT_SLCDC 60
-#define MXC_INT_EMMAPP 52
-#define MXC_INT_EMMAPRP 51
-#define MXC_INT_DMACH15 47
-#define MXC_INT_DMACH14 46
-#define MXC_INT_DMACH13 45
-#define MXC_INT_DMACH12 44
-#define MXC_INT_DMACH11 43
-#define MXC_INT_DMACH10 42
-#define MXC_INT_DMACH9 41
-#define MXC_INT_DMACH8 40
-#define MXC_INT_DMACH7 39
-#define MXC_INT_DMACH6 38
-#define MXC_INT_DMACH5 37
-#define MXC_INT_DMACH4 36
-#define MXC_INT_DMACH3 35
-#define MXC_INT_DMACH2 34
-#define MXC_INT_DMACH1 33
-#define MXC_INT_DMACH0 32
-#define MXC_INT_CSI 31
-#define MXC_INT_NANDFC 29
-#define MXC_INT_PCMCIA 28
-#define MXC_INT_WDOG 27
-#define MXC_INT_GPT1 26
-#define MXC_INT_GPT2 25
-#define MXC_INT_GPT3 24
-#define MXC_INT_GPT INT_GPT1
-#define MXC_INT_PWM 23
-#define MXC_INT_RTC 22
-#define MXC_INT_KPP 21
-#define MXC_INT_UART1 20
-#define MXC_INT_UART2 19
-#define MXC_INT_UART3 18
-#define MXC_INT_UART4 17
-#define MXC_INT_CSPI1 16
-#define MXC_INT_CSPI2 15
-#define MXC_INT_SSI1 14
-#define MXC_INT_SSI2 13
-#define MXC_INT_I2C 12
-#define MXC_INT_SDHC1 11
-#define MXC_INT_SDHC2 10
-#define MXC_INT_GPIO 8
#define MXC_INT_CSPI3 6
+#define MXC_INT_GPIO 8
+#define MXC_INT_SDHC2 10
+#define MXC_INT_SDHC1 11
+#define MXC_INT_I2C 12
+#define MXC_INT_SSI2 13
+#define MXC_INT_SSI1 14
+#define MXC_INT_CSPI2 15
+#define MXC_INT_CSPI1 16
+#define MXC_INT_UART4 17
+#define MXC_INT_UART3 18
+#define MXC_INT_UART2 19
+#define MXC_INT_UART1 20
+#define MXC_INT_KPP 21
+#define MXC_INT_RTC 22
+#define MXC_INT_PWM 23
+#define MXC_INT_GPT INT_GPT1
+#define MXC_INT_GPT3 24
+#define MXC_INT_GPT2 25
+#define MXC_INT_GPT1 26
+#define MXC_INT_WDOG 27
+#define MXC_INT_PCMCIA 28
+#define MXC_INT_NANDFC 29
+#define MXC_INT_CSI 31
+#define MXC_INT_DMACH0 32
+#define MXC_INT_DMACH1 33
+#define MXC_INT_DMACH2 34
+#define MXC_INT_DMACH3 35
+#define MXC_INT_DMACH4 36
+#define MXC_INT_DMACH5 37
+#define MXC_INT_DMACH6 38
+#define MXC_INT_DMACH7 39
+#define MXC_INT_DMACH8 40
+#define MXC_INT_DMACH9 41
+#define MXC_INT_DMACH10 42
+#define MXC_INT_DMACH11 43
+#define MXC_INT_DMACH12 44
+#define MXC_INT_DMACH13 45
+#define MXC_INT_DMACH14 46
+#define MXC_INT_DMACH15 47
+#define MXC_INT_EMMAPRP 51
+#define MXC_INT_EMMAPP 52
+#define MXC_INT_SLCDC 60
+#define MXC_INT_LCDC 61
/* fixed DMA request numbers */
-#define DMA_REQ_CSI_RX 31
-#define DMA_REQ_CSI_STAT 30
-#define DMA_REQ_UART1_TX 27
-#define DMA_REQ_UART1_RX 26
-#define DMA_REQ_UART2_TX 25
-#define DMA_REQ_UART2_RX 24
-#define DMA_REQ_UART3_TX 23
-#define DMA_REQ_UART3_RX 22
-#define DMA_REQ_UART4_TX 21
-#define DMA_REQ_UART4_RX 20
-#define DMA_REQ_CSPI1_TX 19
-#define DMA_REQ_CSPI1_RX 18
-#define DMA_REQ_CSPI2_TX 17
-#define DMA_REQ_CSPI2_RX 16
-#define DMA_REQ_SSI1_TX1 15
-#define DMA_REQ_SSI1_RX1 14
-#define DMA_REQ_SSI1_TX0 13
-#define DMA_REQ_SSI1_RX0 12
-#define DMA_REQ_SSI2_TX1 11
-#define DMA_REQ_SSI2_RX1 10
-#define DMA_REQ_SSI2_TX0 9
-#define DMA_REQ_SSI2_RX0 8
-#define DMA_REQ_SDHC1 7
-#define DMA_REQ_SDHC2 6
-#define DMA_REQ_EXT 3
-#define DMA_REQ_CSPI3_TX 2
#define DMA_REQ_CSPI3_RX 1
+#define DMA_REQ_CSPI3_TX 2
+#define DMA_REQ_EXT 3
+#define DMA_REQ_SDHC2 6
+#define DMA_REQ_SDHC1 7
+#define DMA_REQ_SSI2_RX0 8
+#define DMA_REQ_SSI2_TX0 9
+#define DMA_REQ_SSI2_RX1 10
+#define DMA_REQ_SSI2_TX1 11
+#define DMA_REQ_SSI1_RX0 12
+#define DMA_REQ_SSI1_TX0 13
+#define DMA_REQ_SSI1_RX1 14
+#define DMA_REQ_SSI1_TX1 15
+#define DMA_REQ_CSPI2_RX 16
+#define DMA_REQ_CSPI2_TX 17
+#define DMA_REQ_CSPI1_RX 18
+#define DMA_REQ_CSPI1_TX 19
+#define DMA_REQ_UART4_RX 20
+#define DMA_REQ_UART4_TX 21
+#define DMA_REQ_UART3_RX 22
+#define DMA_REQ_UART3_TX 23
+#define DMA_REQ_UART2_RX 24
+#define DMA_REQ_UART2_TX 25
+#define DMA_REQ_UART1_RX 26
+#define DMA_REQ_UART1_TX 27
+#define DMA_REQ_CSI_STAT 30
+#define DMA_REQ_CSI_RX 31
#endif /* __ASM_ARCH_MXC_MX2x_H__ */
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 02/25] imx: reorder mx21.h
2009-11-16 20:34 ` [PATCH 01/25] imx: reorder mx2x.h Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 03/25] imx: reorder mx27.h Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx21.h | 24 ++++++++++++------------
1 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 21112c6..2b1fccb 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -34,8 +34,8 @@
#define CS2_BASE_ADDR 0xD0000000
#define CS3_BASE_ADDR 0xD1000000
#define CS4_BASE_ADDR 0xD2000000
-#define CS5_BASE_ADDR 0xDD000000
#define PCMCIA_MEM_BASE_ADDR 0xD4000000
+#define CS5_BASE_ADDR 0xDD000000
/* NAND, SDRAM, WEIM etc controllers */
#define X_MEMC_BASE_ADDR 0xDF000000
@@ -50,21 +50,21 @@
#define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */
/* fixed interrupt numbers */
+#define MXC_INT_FIRI 9
+#define MXC_INT_BMI 30
+#define MXC_INT_EMMAENC 49
+#define MXC_INT_EMMADEC 50
+#define MXC_INT_USBWKUP 53
+#define MXC_INT_USBDMA 54
+#define MXC_INT_USBHOST 55
+#define MXC_INT_USBFUNC 56
+#define MXC_INT_USBMNP 57
#define MXC_INT_USBCTRL 58
#define MXC_INT_USBCTRL 58
-#define MXC_INT_USBMNP 57
-#define MXC_INT_USBFUNC 56
-#define MXC_INT_USBHOST 55
-#define MXC_INT_USBDMA 54
-#define MXC_INT_USBWKUP 53
-#define MXC_INT_EMMADEC 50
-#define MXC_INT_EMMAENC 49
-#define MXC_INT_BMI 30
-#define MXC_INT_FIRI 9
/* fixed DMA request numbers */
-#define DMA_REQ_BMI_RX 29
-#define DMA_REQ_BMI_TX 28
#define DMA_REQ_FIRI_RX 4
+#define DMA_REQ_BMI_TX 28
+#define DMA_REQ_BMI_RX 29
#endif /* __ASM_ARCH_MXC_MX21_H__ */
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 03/25] imx: reorder mx27.h
2009-11-16 20:34 ` [PATCH 02/25] imx: reorder mx21.h Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 04/25] imx: reorder mx3x.h Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx27.h | 63 +++++++++++++++++----------------
1 files changed, 32 insertions(+), 31 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index dc3ad9a..0104c20 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -24,9 +24,6 @@
#ifndef __ASM_ARCH_MXC_MX27_H__
#define __ASM_ARCH_MXC_MX27_H__
-/* IRAM */
-#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */
-
#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000)
#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000)
#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000)
@@ -60,7 +57,6 @@
#define CS3_BASE_ADDR 0xD2000000
#define CS4_BASE_ADDR 0xD4000000
#define CS5_BASE_ADDR 0xD6000000
-#define PCMCIA_MEM_BASE_ADDR 0xDC000000
/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
#define X_MEMC_BASE_ADDR 0xD8000000
@@ -73,38 +69,43 @@
#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
+#define PCMCIA_MEM_BASE_ADDR 0xDC000000
+
+/* IRAM */
+#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */
+
/* fixed interrupt numbers */
-#define MXC_INT_CCM 63
-#define MXC_INT_IIM 62
-#define MXC_INT_SAHARA 59
-#define MXC_INT_SCC_SCM 58
-#define MXC_INT_SCC_SMN 57
-#define MXC_INT_USB3 56
-#define MXC_INT_USB2 55
-#define MXC_INT_USB1 54
-#define MXC_INT_VPU 53
-#define MXC_INT_FEC 50
-#define MXC_INT_UART5 49
-#define MXC_INT_UART6 48
-#define MXC_INT_ATA 30
-#define MXC_INT_SDHC3 9
-#define MXC_INT_SDHC 7
-#define MXC_INT_RTIC 5
-#define MXC_INT_GPT4 4
-#define MXC_INT_GPT5 3
-#define MXC_INT_GPT6 2
#define MXC_INT_I2C2 1
+#define MXC_INT_GPT6 2
+#define MXC_INT_GPT5 3
+#define MXC_INT_GPT4 4
+#define MXC_INT_RTIC 5
+#define MXC_INT_SDHC 7
+#define MXC_INT_SDHC3 9
+#define MXC_INT_ATA 30
+#define MXC_INT_UART6 48
+#define MXC_INT_UART5 49
+#define MXC_INT_FEC 50
+#define MXC_INT_VPU 53
+#define MXC_INT_USB1 54
+#define MXC_INT_USB2 55
+#define MXC_INT_USB3 56
+#define MXC_INT_SCC_SMN 57
+#define MXC_INT_SCC_SCM 58
+#define MXC_INT_SAHARA 59
+#define MXC_INT_IIM 62
+#define MXC_INT_CCM 63
/* fixed DMA request numbers */
-#define DMA_REQ_NFC 37
-#define DMA_REQ_SDHC3 36
-#define DMA_REQ_UART6_RX 35
-#define DMA_REQ_UART6_TX 34
-#define DMA_REQ_UART5_RX 33
-#define DMA_REQ_UART5_TX 32
-#define DMA_REQ_ATA_RCV 29
-#define DMA_REQ_ATA_TX 28
#define DMA_REQ_MSHC 4
+#define DMA_REQ_ATA_TX 28
+#define DMA_REQ_ATA_RCV 29
+#define DMA_REQ_UART5_TX 32
+#define DMA_REQ_UART5_RX 33
+#define DMA_REQ_UART6_TX 34
+#define DMA_REQ_UART6_RX 35
+#define DMA_REQ_SDHC3 36
+#define DMA_REQ_NFC 37
/* silicon revisions specific to i.MX27 */
#define CHIP_REV_1_0 0x00
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 04/25] imx: reorder mx3x.h
2009-11-16 20:34 ` [PATCH 03/25] imx: reorder mx27.h Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 05/25] imx: add namespace prefixes for symbols in mx2x.h Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx3x.h | 45 +++++++++++++++++----------------
1 files changed, 23 insertions(+), 22 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 009f444..3e07d3d 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -34,21 +34,6 @@
* C0000000 64M PCMCIA/CF
*/
-#define CS0_BASE_ADDR 0xA0000000
-#define CS1_BASE_ADDR 0xA8000000
-#define CS2_BASE_ADDR 0xB0000000
-#define CS3_BASE_ADDR 0xB2000000
-
-#define CS4_BASE_ADDR 0xB4000000
-#define CS4_BASE_ADDR_VIRT 0xF4000000
-#define CS4_SIZE SZ_32M
-
-#define CS5_BASE_ADDR 0xB6000000
-#define CS5_BASE_ADDR_VIRT 0xF6000000
-#define CS5_SIZE SZ_32M
-
-#define PCMCIA_MEM_BASE_ADDR 0xBC000000
-
/*
* L2CC
*/
@@ -101,6 +86,7 @@
#define AIPS2_BASE_ADDR 0x53F00000
#define AIPS2_BASE_ADDR_VIRT 0xFC200000
#define AIPS2_SIZE SZ_1M
+
#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
@@ -130,6 +116,27 @@
#define AVIC_SIZE SZ_1M
/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE_ADDR 0x70000000
+#define CSD0_BASE_ADDR 0x80000000
+#define CSD1_BASE_ADDR 0x90000000
+
+#define CS0_BASE_ADDR 0xA0000000
+#define CS1_BASE_ADDR 0xA8000000
+#define CS2_BASE_ADDR 0xB0000000
+#define CS3_BASE_ADDR 0xB2000000
+
+#define CS4_BASE_ADDR 0xB4000000
+#define CS4_BASE_ADDR_VIRT 0xF4000000
+#define CS4_SIZE SZ_32M
+
+#define CS5_BASE_ADDR 0xB6000000
+#define CS5_BASE_ADDR_VIRT 0xF6000000
+#define CS5_SIZE SZ_32M
+
+
+/*
* NAND, SDRAM, WEIM, M3IF, EMI controllers
*/
#define X_MEMC_BASE_ADDR 0xB8000000
@@ -142,12 +149,7 @@
#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
-/*
- * Memory regions and CS
- */
-#define IPU_MEM_BASE_ADDR 0x70000000
-#define CSD0_BASE_ADDR 0x80000000
-#define CSD1_BASE_ADDR 0x90000000
+#define PCMCIA_MEM_BASE_ADDR 0xBC000000
/*!
* This macro defines the physical to virtual address mapping for all the
@@ -272,4 +274,3 @@ static inline int mx31_revision(void)
#endif
#endif /* __ASM_ARCH_MXC_MX31_H__ */
-
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 05/25] imx: add namespace prefixes for symbols in mx2x.h
2009-11-16 20:34 ` [PATCH 04/25] imx: reorder mx3x.h Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 06/25] imx: add namespace prefixes for symbols in mx21.h Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
The old names are still defined using the new names.
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx2x.h | 339 ++++++++++++++++++++++-----------
1 files changed, 224 insertions(+), 115 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index c0df87f..1766c7c 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -26,50 +26,48 @@
/* The following addresses are common between i.MX21 and i.MX27 */
/* Register offests */
-#define AIPI_BASE_ADDR 0x10000000
-#define AIPI_BASE_ADDR_VIRT 0xF4000000
-#define AIPI_SIZE SZ_1M
-
-#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000)
-#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000)
-#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000)
-#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000)
-#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000)
-#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000)
-#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000)
-#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000)
-#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000)
-#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000)
-#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000)
-#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000)
-#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000)
-#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000)
-#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000)
-#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000)
-#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000)
-#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000)
-#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000)
-#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000)
-#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000)
-#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000)
-#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000)
-#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000)
-#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000)
-#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000)
-#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000)
-#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
-#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
-#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
-#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000)
-#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000)
-
-#define AVIC_BASE_ADDR 0x10040000
-
-#define SAHB1_BASE_ADDR 0x80000000
-#define SAHB1_BASE_ADDR_VIRT 0xF4100000
-#define SAHB1_SIZE SZ_1M
-
-#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
+#define MX2x_AIPI_BASE_ADDR 0x10000000
+#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000
+#define MX2x_AIPI_SIZE SZ_1M
+#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
+#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
+#define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
+#define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
+#define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
+#define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
+#define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
+#define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
+#define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
+#define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000)
+#define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000)
+#define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000)
+#define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000)
+#define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000)
+#define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000)
+#define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000)
+#define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000)
+#define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000)
+#define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000)
+#define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000)
+#define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000)
+#define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000)
+#define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000)
+#define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000)
+#define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000)
+#define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000)
+#define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000)
+#define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400)
+#define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000)
+#define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800)
+#define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000)
+#define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000)
+
+#define MX2x_AVIC_BASE_ADDR 0x10040000
+
+#define MX2x_SAHB1_BASE_ADDR 0x80000000
+#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000
+#define MX2x_SAHB1_SIZE SZ_1M
+#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
/*
* This macro defines the physical to virtual address mapping for all the
@@ -105,78 +103,189 @@
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
/* fixed interrupt numbers */
-#define MXC_INT_CSPI3 6
-#define MXC_INT_GPIO 8
-#define MXC_INT_SDHC2 10
-#define MXC_INT_SDHC1 11
-#define MXC_INT_I2C 12
-#define MXC_INT_SSI2 13
-#define MXC_INT_SSI1 14
-#define MXC_INT_CSPI2 15
-#define MXC_INT_CSPI1 16
-#define MXC_INT_UART4 17
-#define MXC_INT_UART3 18
-#define MXC_INT_UART2 19
-#define MXC_INT_UART1 20
-#define MXC_INT_KPP 21
-#define MXC_INT_RTC 22
-#define MXC_INT_PWM 23
-#define MXC_INT_GPT INT_GPT1
-#define MXC_INT_GPT3 24
-#define MXC_INT_GPT2 25
-#define MXC_INT_GPT1 26
-#define MXC_INT_WDOG 27
-#define MXC_INT_PCMCIA 28
-#define MXC_INT_NANDFC 29
-#define MXC_INT_CSI 31
-#define MXC_INT_DMACH0 32
-#define MXC_INT_DMACH1 33
-#define MXC_INT_DMACH2 34
-#define MXC_INT_DMACH3 35
-#define MXC_INT_DMACH4 36
-#define MXC_INT_DMACH5 37
-#define MXC_INT_DMACH6 38
-#define MXC_INT_DMACH7 39
-#define MXC_INT_DMACH8 40
-#define MXC_INT_DMACH9 41
-#define MXC_INT_DMACH10 42
-#define MXC_INT_DMACH11 43
-#define MXC_INT_DMACH12 44
-#define MXC_INT_DMACH13 45
-#define MXC_INT_DMACH14 46
-#define MXC_INT_DMACH15 47
-#define MXC_INT_EMMAPRP 51
-#define MXC_INT_EMMAPP 52
-#define MXC_INT_SLCDC 60
-#define MXC_INT_LCDC 61
+#define MX2x_INT_CSPI3 6
+#define MX2x_INT_GPIO 8
+#define MX2x_INT_SDHC2 10
+#define MX2x_INT_SDHC1 11
+#define MX2x_INT_I2C 12
+#define MX2x_INT_SSI2 13
+#define MX2x_INT_SSI1 14
+#define MX2x_INT_CSPI2 15
+#define MX2x_INT_CSPI1 16
+#define MX2x_INT_UART4 17
+#define MX2x_INT_UART3 18
+#define MX2x_INT_UART2 19
+#define MX2x_INT_UART1 20
+#define MX2x_INT_KPP 21
+#define MX2x_INT_RTC 22
+#define MX2x_INT_PWM 23
+#define MX2x_INT_GPT3 24
+#define MX2x_INT_GPT2 25
+#define MX2x_INT_GPT1 26
+#define MX2x_INT_WDOG 27
+#define MX2x_INT_PCMCIA 28
+#define MX2x_INT_NANDFC 29
+#define MX2x_INT_CSI 31
+#define MX2x_INT_DMACH0 32
+#define MX2x_INT_DMACH1 33
+#define MX2x_INT_DMACH2 34
+#define MX2x_INT_DMACH3 35
+#define MX2x_INT_DMACH4 36
+#define MX2x_INT_DMACH5 37
+#define MX2x_INT_DMACH6 38
+#define MX2x_INT_DMACH7 39
+#define MX2x_INT_DMACH8 40
+#define MX2x_INT_DMACH9 41
+#define MX2x_INT_DMACH10 42
+#define MX2x_INT_DMACH11 43
+#define MX2x_INT_DMACH12 44
+#define MX2x_INT_DMACH13 45
+#define MX2x_INT_DMACH14 46
+#define MX2x_INT_DMACH15 47
+#define MX2x_INT_EMMAPRP 51
+#define MX2x_INT_EMMAPP 52
+#define MX2x_INT_SLCDC 60
+#define MX2x_INT_LCDC 61
/* fixed DMA request numbers */
-#define DMA_REQ_CSPI3_RX 1
-#define DMA_REQ_CSPI3_TX 2
-#define DMA_REQ_EXT 3
-#define DMA_REQ_SDHC2 6
-#define DMA_REQ_SDHC1 7
-#define DMA_REQ_SSI2_RX0 8
-#define DMA_REQ_SSI2_TX0 9
-#define DMA_REQ_SSI2_RX1 10
-#define DMA_REQ_SSI2_TX1 11
-#define DMA_REQ_SSI1_RX0 12
-#define DMA_REQ_SSI1_TX0 13
-#define DMA_REQ_SSI1_RX1 14
-#define DMA_REQ_SSI1_TX1 15
-#define DMA_REQ_CSPI2_RX 16
-#define DMA_REQ_CSPI2_TX 17
-#define DMA_REQ_CSPI1_RX 18
-#define DMA_REQ_CSPI1_TX 19
-#define DMA_REQ_UART4_RX 20
-#define DMA_REQ_UART4_TX 21
-#define DMA_REQ_UART3_RX 22
-#define DMA_REQ_UART3_TX 23
-#define DMA_REQ_UART2_RX 24
-#define DMA_REQ_UART2_TX 25
-#define DMA_REQ_UART1_RX 26
-#define DMA_REQ_UART1_TX 27
-#define DMA_REQ_CSI_STAT 30
-#define DMA_REQ_CSI_RX 31
+#define MX2x_DMA_REQ_CSPI3_RX 1
+#define MX2x_DMA_REQ_CSPI3_TX 2
+#define MX2x_DMA_REQ_EXT 3
+#define MX2x_DMA_REQ_SDHC2 6
+#define MX2x_DMA_REQ_SDHC1 7
+#define MX2x_DMA_REQ_SSI2_RX0 8
+#define MX2x_DMA_REQ_SSI2_TX0 9
+#define MX2x_DMA_REQ_SSI2_RX1 10
+#define MX2x_DMA_REQ_SSI2_TX1 11
+#define MX2x_DMA_REQ_SSI1_RX0 12
+#define MX2x_DMA_REQ_SSI1_TX0 13
+#define MX2x_DMA_REQ_SSI1_RX1 14
+#define MX2x_DMA_REQ_SSI1_TX1 15
+#define MX2x_DMA_REQ_CSPI2_RX 16
+#define MX2x_DMA_REQ_CSPI2_TX 17
+#define MX2x_DMA_REQ_CSPI1_RX 18
+#define MX2x_DMA_REQ_CSPI1_TX 19
+#define MX2x_DMA_REQ_UART4_RX 20
+#define MX2x_DMA_REQ_UART4_TX 21
+#define MX2x_DMA_REQ_UART3_RX 22
+#define MX2x_DMA_REQ_UART3_TX 23
+#define MX2x_DMA_REQ_UART2_RX 24
+#define MX2x_DMA_REQ_UART2_TX 25
+#define MX2x_DMA_REQ_UART1_RX 26
+#define MX2x_DMA_REQ_UART1_TX 27
+#define MX2x_DMA_REQ_CSI_STAT 30
+#define MX2x_DMA_REQ_CSI_RX 31
+
+/* these should go away */
+#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
+#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
+#define AIPI_SIZE MX2x_AIPI_SIZE
+#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
+#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
+#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
+#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
+#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
+#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
+#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
+#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
+#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
+#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
+#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
+#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
+#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
+#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
+#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
+#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
+#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
+#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
+#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
+#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
+#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
+#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
+#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
+#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
+#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
+#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
+#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
+#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
+#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
+#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
+#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
+#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
+#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
+#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
+#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
+#define SAHB1_SIZE MX2x_SAHB1_SIZE
+#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
+#define MXC_INT_CSPI3 MX2x_INT_CSPI3
+#define MXC_INT_GPIO MX2x_INT_GPIO
+#define MXC_INT_SDHC2 MX2x_INT_SDHC2
+#define MXC_INT_SDHC1 MX2x_INT_SDHC1
+#define MXC_INT_I2C MX2x_INT_I2C
+#define MXC_INT_SSI2 MX2x_INT_SSI2
+#define MXC_INT_SSI1 MX2x_INT_SSI1
+#define MXC_INT_CSPI2 MX2x_INT_CSPI2
+#define MXC_INT_CSPI1 MX2x_INT_CSPI1
+#define MXC_INT_UART4 MX2x_INT_UART4
+#define MXC_INT_UART3 MX2x_INT_UART3
+#define MXC_INT_UART2 MX2x_INT_UART2
+#define MXC_INT_UART1 MX2x_INT_UART1
+#define MXC_INT_KPP MX2x_INT_KPP
+#define MXC_INT_RTC MX2x_INT_RTC
+#define MXC_INT_PWM MX2x_INT_PWM
+#define MXC_INT_GPT3 MX2x_INT_GPT3
+#define MXC_INT_GPT2 MX2x_INT_GPT2
+#define MXC_INT_GPT1 MX2x_INT_GPT1
+#define MXC_INT_WDOG MX2x_INT_WDOG
+#define MXC_INT_PCMCIA MX2x_INT_PCMCIA
+#define MXC_INT_NANDFC MX2x_INT_NANDFC
+#define MXC_INT_CSI MX2x_INT_CSI
+#define MXC_INT_DMACH0 MX2x_INT_DMACH0
+#define MXC_INT_DMACH1 MX2x_INT_DMACH1
+#define MXC_INT_DMACH2 MX2x_INT_DMACH2
+#define MXC_INT_DMACH3 MX2x_INT_DMACH3
+#define MXC_INT_DMACH4 MX2x_INT_DMACH4
+#define MXC_INT_DMACH5 MX2x_INT_DMACH5
+#define MXC_INT_DMACH6 MX2x_INT_DMACH6
+#define MXC_INT_DMACH7 MX2x_INT_DMACH7
+#define MXC_INT_DMACH8 MX2x_INT_DMACH8
+#define MXC_INT_DMACH9 MX2x_INT_DMACH9
+#define MXC_INT_DMACH10 MX2x_INT_DMACH10
+#define MXC_INT_DMACH11 MX2x_INT_DMACH11
+#define MXC_INT_DMACH12 MX2x_INT_DMACH12
+#define MXC_INT_DMACH13 MX2x_INT_DMACH13
+#define MXC_INT_DMACH14 MX2x_INT_DMACH14
+#define MXC_INT_DMACH15 MX2x_INT_DMACH15
+#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
+#define MXC_INT_EMMAPP MX2x_INT_EMMAPP
+#define MXC_INT_SLCDC MX2x_INT_SLCDC
+#define MXC_INT_LCDC MX2x_INT_LCDC
+#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
+#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
+#define DMA_REQ_EXT MX2x_DMA_REQ_EXT
+#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
+#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
+#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
+#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
+#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
+#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
+#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
+#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
+#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
+#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
+#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
+#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
+#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
+#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
+#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
+#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
+#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
+#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
+#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
+#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
+#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
+#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
+#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
+#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
#endif /* __ASM_ARCH_MXC_MX2x_H__ */
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 06/25] imx: add namespace prefixes for symbols in mx21.h
2009-11-16 20:34 ` [PATCH 05/25] imx: add namespace prefixes for symbols in mx2x.h Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 07/25] imx: add namespace prefixes for symbols in mx27.h Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
The old names are still defined using the new names.
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx21.h | 95 ++++++++++++++++++++++-----------
1 files changed, 64 insertions(+), 31 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 2b1fccb..986f08b 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -26,45 +26,78 @@
#define __ASM_ARCH_MXC_MX21_H__
/* Memory regions and CS */
-#define SDRAM_BASE_ADDR 0xC0000000
-#define CSD1_BASE_ADDR 0xC4000000
+#define MX21_SDRAM_BASE_ADDR 0xc0000000
+#define MX21_CSD1_BASE_ADDR 0xc4000000
-#define CS0_BASE_ADDR 0xC8000000
-#define CS1_BASE_ADDR 0xCC000000
-#define CS2_BASE_ADDR 0xD0000000
-#define CS3_BASE_ADDR 0xD1000000
-#define CS4_BASE_ADDR 0xD2000000
-#define PCMCIA_MEM_BASE_ADDR 0xD4000000
-#define CS5_BASE_ADDR 0xDD000000
+#define MX21_CS0_BASE_ADDR 0xc8000000
+#define MX21_CS1_BASE_ADDR 0xcc000000
+#define MX21_CS2_BASE_ADDR 0xd0000000
+#define MX21_CS3_BASE_ADDR 0xd1000000
+#define MX21_CS4_BASE_ADDR 0xd2000000
+#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000
+#define MX21_CS5_BASE_ADDR 0xdd000000
/* NAND, SDRAM, WEIM etc controllers */
-#define X_MEMC_BASE_ADDR 0xDF000000
-#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
-#define X_MEMC_SIZE SZ_256K
+#define MX21_X_MEMC_BASE_ADDR 0xdf000000
+#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000
+#define MX21_X_MEMC_SIZE SZ_256K
-#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
-#define EIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
-#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
-#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
+#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
+#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000)
+#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000)
+#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000)
-#define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */
+#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
/* fixed interrupt numbers */
-#define MXC_INT_FIRI 9
-#define MXC_INT_BMI 30
-#define MXC_INT_EMMAENC 49
-#define MXC_INT_EMMADEC 50
-#define MXC_INT_USBWKUP 53
-#define MXC_INT_USBDMA 54
-#define MXC_INT_USBHOST 55
-#define MXC_INT_USBFUNC 56
-#define MXC_INT_USBMNP 57
-#define MXC_INT_USBCTRL 58
-#define MXC_INT_USBCTRL 58
+#define MX21_INT_FIRI 9
+#define MX21_INT_BMI 30
+#define MX21_INT_EMMAENC 49
+#define MX21_INT_EMMADEC 50
+#define MX21_INT_USBWKUP 53
+#define MX21_INT_USBDMA 54
+#define MX21_INT_USBHOST 55
+#define MX21_INT_USBFUNC 56
+#define MX21_INT_USBMNP 57
+#define MX21_INT_USBCTRL 58
+#define MX21_INT_USBCTRL 58
/* fixed DMA request numbers */
-#define DMA_REQ_FIRI_RX 4
-#define DMA_REQ_BMI_TX 28
-#define DMA_REQ_BMI_RX 29
+#define MX21_DMA_REQ_FIRI_RX 4
+#define MX21_DMA_REQ_BMI_TX 28
+#define MX21_DMA_REQ_BMI_RX 29
+
+/* these should go away */
+#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
+#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
+#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
+#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
+#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
+#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
+#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
+#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
+#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
+#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
+#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
+#define X_MEMC_SIZE MX21_X_MEMC_SIZE
+#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
+#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
+#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
+#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
+#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
+#define MXC_INT_FIRI MX21_INT_FIRI
+#define MXC_INT_BMI MX21_INT_BMI
+#define MXC_INT_EMMAENC MX21_INT_EMMAENC
+#define MXC_INT_EMMADEC MX21_INT_EMMADEC
+#define MXC_INT_USBWKUP MX21_INT_USBWKUP
+#define MXC_INT_USBDMA MX21_INT_USBDMA
+#define MXC_INT_USBHOST MX21_INT_USBHOST
+#define MXC_INT_USBFUNC MX21_INT_USBFUNC
+#define MXC_INT_USBMNP MX21_INT_USBMNP
+#define MXC_INT_USBCTRL MX21_INT_USBCTRL
+#define MXC_INT_USBCTRL MX21_INT_USBCTRL
+#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
+#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
+#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
#endif /* __ASM_ARCH_MXC_MX21_H__ */
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 07/25] imx: add namespace prefixes for symbols in mx27.h
2009-11-16 20:34 ` [PATCH 06/25] imx: add namespace prefixes for symbols in mx21.h Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 08/25] imx: add namespace prefixes for symbols in mx3x.h Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
The old names are still defined using the new names.
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx27.h | 201 ++++++++++++++++++++++-----------
1 files changed, 133 insertions(+), 68 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 0104c20..b619aa4 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -24,88 +24,87 @@
#ifndef __ASM_ARCH_MXC_MX27_H__
#define __ASM_ARCH_MXC_MX27_H__
-#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000)
-#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000)
-#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000)
-#define UART5_BASE_ADDR (AIPI_BASE_ADDR + 0x1B000)
-#define UART6_BASE_ADDR (AIPI_BASE_ADDR + 0x1C000)
-#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000)
-#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000)
-#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000)
-#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000)
-#define OTG_BASE_ADDR USBOTG_BASE_ADDR
-#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000)
-#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000)
-#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000)
-#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000)
-#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000)
-#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000)
-#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000)
+#define MX27_MSHC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x18000)
+#define MX27_GPT5_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x19000)
+#define MX27_GPT4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1a000)
+#define MX27_UART5_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1b000)
+#define MX27_UART6_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1c000)
+#define MX27_I2C2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1d000)
+#define MX27_SDHC3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1e000)
+#define MX27_GPT6_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1f000)
+#define MX27_VPU_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x23000)
+#define MX27_OTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
+#define MX27_SAHARA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x25000)
+#define MX27_IIM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x28000)
+#define MX27_RTIC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x2a000)
+#define MX27_FEC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x2b000)
+#define MX27_SCC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x2c000)
+#define MX27_ETB_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3b000)
+#define MX27_ETB_RAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3c000)
/* ROM patch */
-#define ROMP_BASE_ADDR 0x10041000
+#define MX27_ROMP_BASE_ADDR 0x10041000
-#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000)
+#define MX27_ATA_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x1000)
/* Memory regions and CS */
-#define SDRAM_BASE_ADDR 0xA0000000
-#define CSD1_BASE_ADDR 0xB0000000
+#define MX27_SDRAM_BASE_ADDR 0xa0000000
+#define MX27_CSD1_BASE_ADDR 0xb0000000
-#define CS0_BASE_ADDR 0xC0000000
-#define CS1_BASE_ADDR 0xC8000000
-#define CS2_BASE_ADDR 0xD0000000
-#define CS3_BASE_ADDR 0xD2000000
-#define CS4_BASE_ADDR 0xD4000000
-#define CS5_BASE_ADDR 0xD6000000
+#define MX27_CS0_BASE_ADDR 0xc0000000
+#define MX27_CS1_BASE_ADDR 0xc8000000
+#define MX27_CS2_BASE_ADDR 0xd0000000
+#define MX27_CS3_BASE_ADDR 0xd2000000
+#define MX27_CS4_BASE_ADDR 0xd4000000
+#define MX27_CS5_BASE_ADDR 0xd6000000
/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
-#define X_MEMC_BASE_ADDR 0xD8000000
-#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
-#define X_MEMC_SIZE SZ_1M
+#define MX27_X_MEMC_BASE_ADDR 0xd8000000
+#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000
+#define MX27_X_MEMC_SIZE SZ_1M
+#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
+#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
+#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
+#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
+#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
-#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR)
-#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
-#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
-#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
-#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
-
-#define PCMCIA_MEM_BASE_ADDR 0xDC000000
+#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
/* IRAM */
-#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */
+#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
/* fixed interrupt numbers */
-#define MXC_INT_I2C2 1
-#define MXC_INT_GPT6 2
-#define MXC_INT_GPT5 3
-#define MXC_INT_GPT4 4
-#define MXC_INT_RTIC 5
-#define MXC_INT_SDHC 7
-#define MXC_INT_SDHC3 9
-#define MXC_INT_ATA 30
-#define MXC_INT_UART6 48
-#define MXC_INT_UART5 49
-#define MXC_INT_FEC 50
-#define MXC_INT_VPU 53
-#define MXC_INT_USB1 54
-#define MXC_INT_USB2 55
-#define MXC_INT_USB3 56
-#define MXC_INT_SCC_SMN 57
-#define MXC_INT_SCC_SCM 58
-#define MXC_INT_SAHARA 59
-#define MXC_INT_IIM 62
-#define MXC_INT_CCM 63
+#define MX27_INT_I2C2 1
+#define MX27_INT_GPT6 2
+#define MX27_INT_GPT5 3
+#define MX27_INT_GPT4 4
+#define MX27_INT_RTIC 5
+#define MX27_INT_SDHC 7
+#define MX27_INT_SDHC3 9
+#define MX27_INT_ATA 30
+#define MX27_INT_UART6 48
+#define MX27_INT_UART5 49
+#define MX27_INT_FEC 50
+#define MX27_INT_VPU 53
+#define MX27_INT_USB1 54
+#define MX27_INT_USB2 55
+#define MX27_INT_USB3 56
+#define MX27_INT_SCC_SMN 57
+#define MX27_INT_SCC_SCM 58
+#define MX27_INT_SAHARA 59
+#define MX27_INT_IIM 62
+#define MX27_INT_CCM 63
/* fixed DMA request numbers */
-#define DMA_REQ_MSHC 4
-#define DMA_REQ_ATA_TX 28
-#define DMA_REQ_ATA_RCV 29
-#define DMA_REQ_UART5_TX 32
-#define DMA_REQ_UART5_RX 33
-#define DMA_REQ_UART6_TX 34
-#define DMA_REQ_UART6_RX 35
-#define DMA_REQ_SDHC3 36
-#define DMA_REQ_NFC 37
+#define MX27_DMA_REQ_MSHC 4
+#define MX27_DMA_REQ_ATA_TX 28
+#define MX27_DMA_REQ_ATA_RCV 29
+#define MX27_DMA_REQ_UART5_TX 32
+#define MX27_DMA_REQ_UART5_RX 33
+#define MX27_DMA_REQ_UART6_TX 34
+#define MX27_DMA_REQ_UART6_RX 35
+#define MX27_DMA_REQ_SDHC3 36
+#define MX27_DMA_REQ_NFC 37
/* silicon revisions specific to i.MX27 */
#define CHIP_REV_1_0 0x00
@@ -115,6 +114,72 @@
extern int mx27_revision(void);
#endif
-/* Mandatory defines used globally */
+/* these should go away */
+#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
+#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
+#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR
+#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR
+#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR
+#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR
+#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR
+#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR
+#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR
+#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR
+#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR
+#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR
+#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR
+#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR
+#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR
+#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR
+#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR
+#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR
+#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR
+#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR
+#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR
+#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR
+#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR
+#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR
+#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR
+#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
+#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
+#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
+#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT
+#define X_MEMC_SIZE MX27_X_MEMC_SIZE
+#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
+#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
+#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR
+#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR
+#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR
+#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR
+#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR
+#define MXC_INT_I2C2 MX27_INT_I2C2
+#define MXC_INT_GPT6 MX27_INT_GPT6
+#define MXC_INT_GPT5 MX27_INT_GPT5
+#define MXC_INT_GPT4 MX27_INT_GPT4
+#define MXC_INT_RTIC MX27_INT_RTIC
+#define MXC_INT_SDHC MX27_INT_SDHC
+#define MXC_INT_SDHC3 MX27_INT_SDHC3
+#define MXC_INT_ATA MX27_INT_ATA
+#define MXC_INT_UART6 MX27_INT_UART6
+#define MXC_INT_UART5 MX27_INT_UART5
+#define MXC_INT_FEC MX27_INT_FEC
+#define MXC_INT_VPU MX27_INT_VPU
+#define MXC_INT_USB1 MX27_INT_USB1
+#define MXC_INT_USB2 MX27_INT_USB2
+#define MXC_INT_USB3 MX27_INT_USB3
+#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN
+#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM
+#define MXC_INT_SAHARA MX27_INT_SAHARA
+#define MXC_INT_IIM MX27_INT_IIM
+#define MXC_INT_CCM MX27_INT_CCM
+#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC
+#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX
+#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV
+#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX
+#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX
+#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX
+#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
+#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
+#define DMA_REQ_NFC MX27_DMA_REQ_NFC
#endif /* __ASM_ARCH_MXC_MX27_H__ */
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 08/25] imx: add namespace prefixes for symbols in mx3x.h
2009-11-16 20:34 ` [PATCH 07/25] imx: add namespace prefixes for symbols in mx27.h Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 09/25] imx: add namespace prefixes for symbols in mx31.h Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
The old names are still defined using the new names.
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx3x.h | 404 ++++++++++++++++++++++-----------
1 files changed, 266 insertions(+), 138 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 3e07d3d..8cedf29 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -37,119 +37,114 @@
/*
* L2CC
*/
-#define L2CC_BASE_ADDR 0x30000000
-#define L2CC_SIZE SZ_1M
+#define MX3x_L2CC_BASE_ADDR 0x30000000
+#define MX3x_L2CC_SIZE SZ_1M
/*
* AIPS 1
*/
-#define AIPS1_BASE_ADDR 0x43F00000
-#define AIPS1_BASE_ADDR_VIRT 0xFC000000
-#define AIPS1_SIZE SZ_1M
-
-#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
-#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
-#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
-#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
-#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
-#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
-#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
-#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
-#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
-#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
-#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
-#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
-#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
-#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
-#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
-#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
-#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
-#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
+#define MX3x_AIPS1_BASE_ADDR 0x43f00000
+#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000
+#define MX3x_AIPS1_SIZE SZ_1M
+#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
+#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
+#define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
+#define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
+#define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
+#define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
+#define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
+#define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
+#define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000)
+#define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000)
+#define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000)
+#define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000)
+#define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000)
+#define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000)
+#define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000)
+#define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000)
+#define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000)
+#define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000)
/*
* SPBA global module enabled #0
*/
-#define SPBA0_BASE_ADDR 0x50000000
-#define SPBA0_BASE_ADDR_VIRT 0xFC100000
-#define SPBA0_SIZE SZ_1M
-
-#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
-#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
-#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
-#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
-#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
+#define MX3x_SPBA0_BASE_ADDR 0x50000000
+#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000
+#define MX3x_SPBA0_SIZE SZ_1M
+#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000)
+#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000)
+#define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000)
+#define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000)
+#define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000)
+#define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000)
/*
* AIPS 2
*/
-#define AIPS2_BASE_ADDR 0x53F00000
-#define AIPS2_BASE_ADDR_VIRT 0xFC200000
-#define AIPS2_SIZE SZ_1M
-
-#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
-#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
-#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
-#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
-#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
-#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
-#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
-#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
-#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
-#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
-#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
-#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
-#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
-#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
-#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
-#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
+#define MX3x_AIPS2_BASE_ADDR 0x53f00000
+#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000
+#define MX3x_AIPS2_SIZE SZ_1M
+#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000)
+#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000)
+#define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000)
+#define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000)
+#define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000)
+#define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000)
+#define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000)
+#define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000)
+#define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000)
+#define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000)
+#define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000)
+#define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000)
+#define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000)
+#define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000)
+#define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000)
+#define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000)
/*
* ROMP and AVIC
*/
-#define ROMP_BASE_ADDR 0x60000000
-#define ROMP_BASE_ADDR_VIRT 0xFC500000
-#define ROMP_SIZE SZ_1M
+#define MX3x_ROMP_BASE_ADDR 0x60000000
+#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000
+#define MX3x_ROMP_SIZE SZ_1M
-#define AVIC_BASE_ADDR 0x68000000
-#define AVIC_BASE_ADDR_VIRT 0xFC400000
-#define AVIC_SIZE SZ_1M
+#define MX3x_AVIC_BASE_ADDR 0x68000000
+#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000
+#define MX3x_AVIC_SIZE SZ_1M
/*
* Memory regions and CS
*/
-#define IPU_MEM_BASE_ADDR 0x70000000
-#define CSD0_BASE_ADDR 0x80000000
-#define CSD1_BASE_ADDR 0x90000000
-
-#define CS0_BASE_ADDR 0xA0000000
-#define CS1_BASE_ADDR 0xA8000000
-#define CS2_BASE_ADDR 0xB0000000
-#define CS3_BASE_ADDR 0xB2000000
+#define MX3x_IPU_MEM_BASE_ADDR 0x70000000
+#define MX3x_CSD0_BASE_ADDR 0x80000000
+#define MX3x_CSD1_BASE_ADDR 0x90000000
-#define CS4_BASE_ADDR 0xB4000000
-#define CS4_BASE_ADDR_VIRT 0xF4000000
-#define CS4_SIZE SZ_32M
+#define MX3x_CS0_BASE_ADDR 0xa0000000
+#define MX3x_CS1_BASE_ADDR 0xa8000000
+#define MX3x_CS2_BASE_ADDR 0xb0000000
+#define MX3x_CS3_BASE_ADDR 0xb2000000
-#define CS5_BASE_ADDR 0xB6000000
-#define CS5_BASE_ADDR_VIRT 0xF6000000
-#define CS5_SIZE SZ_32M
+#define MX3x_CS4_BASE_ADDR 0xb4000000
+#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000
+#define MX3x_CS4_SIZE SZ_32M
+#define MX3x_CS5_BASE_ADDR 0xb6000000
+#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000
+#define MX3x_CS5_SIZE SZ_32M
/*
* NAND, SDRAM, WEIM, M3IF, EMI controllers
*/
-#define X_MEMC_BASE_ADDR 0xB8000000
-#define X_MEMC_BASE_ADDR_VIRT 0xFC320000
-#define X_MEMC_SIZE SZ_64K
+#define MX3x_X_MEMC_BASE_ADDR 0xb8000000
+#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000
+#define MX3x_X_MEMC_SIZE SZ_64K
+#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000)
+#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000)
+#define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000)
+#define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000)
+#define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
-#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
-#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
-#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
-#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
-#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
-
-#define PCMCIA_MEM_BASE_ADDR 0xBC000000
+#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000
/*!
* This macro defines the physical to virtual address mapping for all the
@@ -204,62 +199,62 @@
/*
* Interrupt numbers
*/
-#define MXC_INT_I2C3 3
-#define MXC_INT_I2C2 4
-#define MXC_INT_RTIC 6
-#define MXC_INT_I2C 10
-#define MXC_INT_CSPI2 13
-#define MXC_INT_CSPI1 14
-#define MXC_INT_ATA 15
-#define MXC_INT_UART3 18
-#define MXC_INT_IIM 19
-#define MXC_INT_RNGA 22
-#define MXC_INT_EVTMON 23
-#define MXC_INT_KPP 24
-#define MXC_INT_RTC 25
-#define MXC_INT_PWM 26
-#define MXC_INT_EPIT2 27
-#define MXC_INT_EPIT1 28
-#define MXC_INT_GPT 29
-#define MXC_INT_POWER_FAIL 30
-#define MXC_INT_UART2 32
-#define MXC_INT_NANDFC 33
-#define MXC_INT_SDMA 34
-#define MXC_INT_MSHC1 39
-#define MXC_INT_IPU_ERR 41
-#define MXC_INT_IPU_SYN 42
-#define MXC_INT_UART1 45
-#define MXC_INT_ECT 48
-#define MXC_INT_SCC_SCM 49
-#define MXC_INT_SCC_SMN 50
-#define MXC_INT_GPIO2 51
-#define MXC_INT_GPIO1 52
-#define MXC_INT_WDOG 55
-#define MXC_INT_GPIO3 56
-#define MXC_INT_EXT_POWER 58
-#define MXC_INT_EXT_TEMPER 59
-#define MXC_INT_EXT_SENSOR60 60
-#define MXC_INT_EXT_SENSOR61 61
-#define MXC_INT_EXT_WDOG 62
-#define MXC_INT_EXT_TV 63
-
-#define PROD_SIGNATURE 0x1 /* For MX31 */
+#define MX3x_INT_I2C3 3
+#define MX3x_INT_I2C2 4
+#define MX3x_INT_RTIC 6
+#define MX3x_INT_I2C 10
+#define MX3x_INT_CSPI2 13
+#define MX3x_INT_CSPI1 14
+#define MX3x_INT_ATA 15
+#define MX3x_INT_UART3 18
+#define MX3x_INT_IIM 19
+#define MX3x_INT_RNGA 22
+#define MX3x_INT_EVTMON 23
+#define MX3x_INT_KPP 24
+#define MX3x_INT_RTC 25
+#define MX3x_INT_PWM 26
+#define MX3x_INT_EPIT2 27
+#define MX3x_INT_EPIT1 28
+#define MX3x_INT_GPT 29
+#define MX3x_INT_POWER_FAIL 30
+#define MX3x_INT_UART2 32
+#define MX3x_INT_NANDFC 33
+#define MX3x_INT_SDMA 34
+#define MX3x_INT_MSHC1 39
+#define MX3x_INT_IPU_ERR 41
+#define MX3x_INT_IPU_SYN 42
+#define MX3x_INT_UART1 45
+#define MX3x_INT_ECT 48
+#define MX3x_INT_SCC_SCM 49
+#define MX3x_INT_SCC_SMN 50
+#define MX3x_INT_GPIO2 51
+#define MX3x_INT_GPIO1 52
+#define MX3x_INT_WDOG 55
+#define MX3x_INT_GPIO3 56
+#define MX3x_INT_EXT_POWER 58
+#define MX3x_INT_EXT_TEMPER 59
+#define MX3x_INT_EXT_SENSOR60 60
+#define MX3x_INT_EXT_SENSOR61 61
+#define MX3x_INT_EXT_WDOG 62
+#define MX3x_INT_EXT_TV 63
+
+#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
/* silicon revisions specific to i.MX31 */
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_1_1 0x11
-#define CHIP_REV_1_2 0x12
-#define CHIP_REV_1_3 0x13
-#define CHIP_REV_2_0 0x20
-#define CHIP_REV_2_1 0x21
-#define CHIP_REV_2_2 0x22
-#define CHIP_REV_2_3 0x23
-#define CHIP_REV_3_0 0x30
-#define CHIP_REV_3_1 0x31
-#define CHIP_REV_3_2 0x32
-
-#define SYSTEM_REV_MIN CHIP_REV_1_0
-#define SYSTEM_REV_NUM 3
+#define MX3x_CHIP_REV_1_0 0x10
+#define MX3x_CHIP_REV_1_1 0x11
+#define MX3x_CHIP_REV_1_2 0x12
+#define MX3x_CHIP_REV_1_3 0x13
+#define MX3x_CHIP_REV_2_0 0x20
+#define MX3x_CHIP_REV_2_1 0x21
+#define MX3x_CHIP_REV_2_2 0x22
+#define MX3x_CHIP_REV_2_3 0x23
+#define MX3x_CHIP_REV_3_0 0x30
+#define MX3x_CHIP_REV_3_1 0x31
+#define MX3x_CHIP_REV_3_2 0x32
+
+#define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
+#define MX3x_SYSTEM_REV_NUM 3
/* Mandatory defines used globally */
@@ -273,4 +268,137 @@ static inline int mx31_revision(void)
}
#endif
+/* these should go away */
+#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
+#define L2CC_SIZE MX3x_L2CC_SIZE
+#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR
+#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT
+#define AIPS1_SIZE MX3x_AIPS1_SIZE
+#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR
+#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR
+#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR
+#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR
+#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR
+#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR
+#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR
+#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR
+#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR
+#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR
+#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR
+#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR
+#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR
+#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR
+#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR
+#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR
+#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
+#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
+#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
+#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT
+#define SPBA0_SIZE MX3x_SPBA0_SIZE
+#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
+#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
+#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR
+#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR
+#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
+#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
+#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
+#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT
+#define AIPS2_SIZE MX3x_AIPS2_SIZE
+#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
+#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
+#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR
+#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR
+#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR
+#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR
+#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR
+#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR
+#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR
+#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR
+#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR
+#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR
+#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR
+#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR
+#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
+#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
+#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
+#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT
+#define ROMP_SIZE MX3x_ROMP_SIZE
+#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
+#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT
+#define AVIC_SIZE MX3x_AVIC_SIZE
+#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
+#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
+#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR
+#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR
+#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR
+#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
+#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
+#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
+#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT
+#define CS4_SIZE MX3x_CS4_SIZE
+#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
+#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT
+#define CS5_SIZE MX3x_CS5_SIZE
+#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
+#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT
+#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
+#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
+#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
+#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR
+#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
+#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR
+#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR
+#define MXC_INT_I2C3 MX3x_INT_I2C3
+#define MXC_INT_I2C2 MX3x_INT_I2C2
+#define MXC_INT_RTIC MX3x_INT_RTIC
+#define MXC_INT_I2C MX3x_INT_I2C
+#define MXC_INT_CSPI2 MX3x_INT_CSPI2
+#define MXC_INT_CSPI1 MX3x_INT_CSPI1
+#define MXC_INT_ATA MX3x_INT_ATA
+#define MXC_INT_UART3 MX3x_INT_UART3
+#define MXC_INT_IIM MX3x_INT_IIM
+#define MXC_INT_RNGA MX3x_INT_RNGA
+#define MXC_INT_EVTMON MX3x_INT_EVTMON
+#define MXC_INT_KPP MX3x_INT_KPP
+#define MXC_INT_RTC MX3x_INT_RTC
+#define MXC_INT_PWM MX3x_INT_PWM
+#define MXC_INT_EPIT2 MX3x_INT_EPIT2
+#define MXC_INT_EPIT1 MX3x_INT_EPIT1
+#define MXC_INT_GPT MX3x_INT_GPT
+#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL
+#define MXC_INT_UART2 MX3x_INT_UART2
+#define MXC_INT_NANDFC MX3x_INT_NANDFC
+#define MXC_INT_SDMA MX3x_INT_SDMA
+#define MXC_INT_MSHC1 MX3x_INT_MSHC1
+#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR
+#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN
+#define MXC_INT_UART1 MX3x_INT_UART1
+#define MXC_INT_ECT MX3x_INT_ECT
+#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM
+#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN
+#define MXC_INT_GPIO2 MX3x_INT_GPIO2
+#define MXC_INT_GPIO1 MX3x_INT_GPIO1
+#define MXC_INT_WDOG MX3x_INT_WDOG
+#define MXC_INT_GPIO3 MX3x_INT_GPIO3
+#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER
+#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER
+#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60
+#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61
+#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
+#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
+#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
+#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
+#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
+#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
+#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
+#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
+#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
+#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
+#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
+#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
+#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
+#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
+#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
+#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
+
#endif /* __ASM_ARCH_MXC_MX31_H__ */
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 09/25] imx: add namespace prefixes for symbols in mx31.h
2009-11-16 20:34 ` [PATCH 08/25] imx: add namespace prefixes for symbols in mx3x.h Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 10/25] imx: add namespace prefixes for symbols in mx35.h Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
The old names are still defined using the new names.
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx31.h | 94 +++++++++++++++++++++-----------
1 files changed, 62 insertions(+), 32 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 14ac0dc..a4d6901 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -1,45 +1,75 @@
/*
* IRAM
*/
-#define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
+#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
#define MX31_IRAM_SIZE SZ_16K
-#define MX31_OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
-#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
-#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
-#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
+#define MX31_OTG_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x88000)
+#define MX31_ATA_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x8c000)
+#define MX31_UART4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb0000)
+#define MX31_UART5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb4000)
-#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
-#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
-#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
-#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000)
+#define MX31_MMC_SDHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x04000)
+#define MX31_MMC_SDHC2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x08000)
+#define MX31_SIM1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x18000)
+#define MX31_IIM_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x1c000)
-#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
-#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
-#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000)
-#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000)
-#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
+#define MX31_CSPI3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x84000)
+#define MX31_FIRI_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x8c000)
+#define MX31_SCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xae000)
+#define MX31_SMN_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xaf000)
+#define MX31_MPEG4_ENC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc8000)
-#define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
+#define MX31_NFC_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x0000)
-#define MXC_INT_MPEG4_ENCODER 5
-#define MXC_INT_FIRI 7
+#define MX31_INT_MPEG4_ENCODER 5
+#define MX31_INT_FIRI 7
#define MX31_INT_MMC_SDHC2 8
-#define MXC_INT_MMC_SDHC1 9
+#define MX31_INT_MMC_SDHC1 9
#define MX31_INT_SSI2 11
#define MX31_INT_SSI1 12
-#define MXC_INT_MBX 16
-#define MXC_INT_CSPI3 17
-#define MXC_INT_SIM2 20
-#define MXC_INT_SIM1 21
-#define MXC_INT_CCM_DVFS 31
-#define MXC_INT_USB1 35
-#define MXC_INT_USB2 36
-#define MXC_INT_USB3 37
-#define MXC_INT_USB4 38
-#define MXC_INT_MSHC2 40
-#define MXC_INT_UART4 46
-#define MXC_INT_UART5 47
-#define MXC_INT_CCM 53
-#define MXC_INT_PCMCIA 54
+#define MX31_INT_MBX 16
+#define MX31_INT_CSPI3 17
+#define MX31_INT_SIM2 20
+#define MX31_INT_SIM1 21
+#define MX31_INT_CCM_DVFS 31
+#define MX31_INT_USB1 35
+#define MX31_INT_USB2 36
+#define MX31_INT_USB3 37
+#define MX31_INT_USB4 38
+#define MX31_INT_MSHC2 40
+#define MX31_INT_UART4 46
+#define MX31_INT_UART5 47
+#define MX31_INT_CCM 53
+#define MX31_INT_PCMCIA 54
+/* these should go away */
+#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
+#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
+#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
+#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
+#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
+#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
+#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
+#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
+#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
+#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
+#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
+#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
+#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
+#define MXC_INT_FIRI MX31_INT_FIRI
+#define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1
+#define MXC_INT_MBX MX31_INT_MBX
+#define MXC_INT_CSPI3 MX31_INT_CSPI3
+#define MXC_INT_SIM2 MX31_INT_SIM2
+#define MXC_INT_SIM1 MX31_INT_SIM1
+#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
+#define MXC_INT_USB1 MX31_INT_USB1
+#define MXC_INT_USB2 MX31_INT_USB2
+#define MXC_INT_USB3 MX31_INT_USB3
+#define MXC_INT_USB4 MX31_INT_USB4
+#define MXC_INT_MSHC2 MX31_INT_MSHC2
+#define MXC_INT_UART4 MX31_INT_UART4
+#define MXC_INT_UART5 MX31_INT_UART5
+#define MXC_INT_CCM MX31_INT_CCM
+#define MXC_INT_PCMCIA MX31_INT_PCMCIA
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 10/25] imx: add namespace prefixes for symbols in mx35.h
2009-11-16 20:34 ` [PATCH 09/25] imx: add namespace prefixes for symbols in mx31.h Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 11/25] imx: reformat mx25.h to match the other platform includes Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
The old names are still defined using the new names.
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx35.h | 49 +++++++++++++++++++++-----------
1 files changed, 32 insertions(+), 17 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index ab4cfec..42b2a99 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -2,29 +2,44 @@
* IRAM
*/
#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
-#define MX35_IRAM_SIZE SZ_128K
+#define MX35_IRAM_SIZE SZ_128K
-#define MXC_FEC_BASE_ADDR 0x50038000
-#define MX35_OTG_BASE_ADDR 0x53ff4000
-#define MX35_NFC_BASE_ADDR 0xBB000000
+#define MX35_FEC_BASE_ADDR 0x50038000
+#define MX35_OTG_BASE_ADDR 0x53ff4000
+#define MX35_NFC_BASE_ADDR 0xbb000000
/*
* Interrupt numbers
*/
-#define MXC_INT_OWIRE 2
+#define MX35_INT_OWIRE 2
#define MX35_INT_MMC_SDHC1 7
-#define MXC_INT_MMC_SDHC2 8
-#define MXC_INT_MMC_SDHC3 9
+#define MX35_INT_MMC_SDHC2 8
+#define MX35_INT_MMC_SDHC3 9
#define MX35_INT_SSI1 11
#define MX35_INT_SSI2 12
-#define MXC_INT_GPU2D 16
-#define MXC_INT_ASRC 17
-#define MXC_INT_USBHS 35
-#define MXC_INT_USBOTG 37
-#define MXC_INT_ESAI 40
-#define MXC_INT_CAN1 43
-#define MXC_INT_CAN2 44
-#define MXC_INT_MLB 46
-#define MXC_INT_SPDIF 47
-#define MXC_INT_FEC 57
+#define MX35_INT_GPU2D 16
+#define MX35_INT_ASRC 17
+#define MX35_INT_USBHS 35
+#define MX35_INT_USBOTG 37
+#define MX35_INT_ESAI 40
+#define MX35_INT_CAN1 43
+#define MX35_INT_CAN2 44
+#define MX35_INT_MLB 46
+#define MX35_INT_SPDIF 47
+#define MX35_INT_FEC 57
+/* these should go away */
+#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
+#define MXC_INT_OWIRE MX35_INT_OWIRE
+#define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2
+#define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3
+#define MXC_INT_GPU2D MX35_INT_GPU2D
+#define MXC_INT_ASRC MX35_INT_ASRC
+#define MXC_INT_USBHS MX35_INT_USBHS
+#define MXC_INT_USBOTG MX35_INT_USBOTG
+#define MXC_INT_ESAI MX35_INT_ESAI
+#define MXC_INT_CAN1 MX35_INT_CAN1
+#define MXC_INT_CAN2 MX35_INT_CAN2
+#define MXC_INT_MLB MX35_INT_MLB
+#define MXC_INT_SPDIF MX35_INT_SPDIF
+#define MXC_INT_FEC MX35_INT_FEC
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 11/25] imx: reformat mx25.h to match the other platform includes
2009-11-16 20:34 ` [PATCH 10/25] imx: add namespace prefixes for symbols in mx35.h Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 12/25] imx: copy constants from mx2x.h to mx21.h using the appropriate namespace Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx25.h | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index ec64bd9..91e7381 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -1,14 +1,14 @@
#ifndef __MACH_MX25_H__
#define __MACH_MX25_H__
-#define MX25_AIPS1_BASE_ADDR 0x43F00000
-#define MX25_AIPS1_BASE_ADDR_VIRT 0xFC000000
+#define MX25_AIPS1_BASE_ADDR 0x43f00000
+#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000
#define MX25_AIPS1_SIZE SZ_1M
-#define MX25_AIPS2_BASE_ADDR 0x53F00000
-#define MX25_AIPS2_BASE_ADDR_VIRT 0xFC200000
+#define MX25_AIPS2_BASE_ADDR 0x53f00000
+#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000
#define MX25_AIPS2_SIZE SZ_1M
#define MX25_AVIC_BASE_ADDR 0x68000000
-#define MX25_AVIC_BASE_ADDR_VIRT 0xFC400000
+#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
#define MX25_AVIC_SIZE SZ_1M
#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 12/25] imx: copy constants from mx2x.h to mx21.h using the appropriate namespace
2009-11-16 20:34 ` [PATCH 11/25] imx: reformat mx25.h to match the other platform includes Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 13/25] imx: copy constants from mx2x.h to mx27.h " Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx21.h | 114 ++++++++++++++++++++++++++++++++-
1 files changed, 113 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 986f08b..bb297d8 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -25,6 +25,49 @@
#ifndef __ASM_ARCH_MXC_MX21_H__
#define __ASM_ARCH_MXC_MX21_H__
+#define MX21_AIPI_BASE_ADDR 0x10000000
+#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000
+#define MX21_AIPI_SIZE SZ_1M
+#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
+#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
+#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000)
+#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000)
+#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000)
+#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000)
+#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000)
+#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000)
+#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000)
+#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000)
+#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000)
+#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000)
+#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000)
+#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000)
+#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000)
+#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000)
+#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000)
+#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000)
+#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
+#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
+#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
+#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
+#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
+#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
+#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000)
+#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000)
+#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000)
+#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400)
+#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000)
+#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800)
+#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000)
+#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000)
+
+#define MX21_AVIC_BASE_ADDR 0x10040000
+
+#define MX21_SAHB1_BASE_ADDR 0x80000000
+#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000
+#define MX21_SAHB1_SIZE SZ_1M
+#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
+
/* Memory regions and CS */
#define MX21_SDRAM_BASE_ADDR 0xc0000000
#define MX21_CSD1_BASE_ADDR 0xc4000000
@@ -50,22 +93,91 @@
#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
/* fixed interrupt numbers */
+#define MX21_INT_CSPI3 6
+#define MX21_INT_GPIO 8
#define MX21_INT_FIRI 9
+#define MX21_INT_SDHC2 10
+#define MX21_INT_SDHC1 11
+#define MX21_INT_I2C 12
+#define MX21_INT_SSI2 13
+#define MX21_INT_SSI1 14
+#define MX21_INT_CSPI2 15
+#define MX21_INT_CSPI1 16
+#define MX21_INT_UART4 17
+#define MX21_INT_UART3 18
+#define MX21_INT_UART2 19
+#define MX21_INT_UART1 20
+#define MX21_INT_KPP 21
+#define MX21_INT_RTC 22
+#define MX21_INT_PWM 23
+#define MX21_INT_GPT3 24
+#define MX21_INT_GPT2 25
+#define MX21_INT_GPT1 26
+#define MX21_INT_WDOG 27
+#define MX21_INT_PCMCIA 28
+#define MX21_INT_NANDFC 29
#define MX21_INT_BMI 30
+#define MX21_INT_CSI 31
+#define MX21_INT_DMACH0 32
+#define MX21_INT_DMACH1 33
+#define MX21_INT_DMACH2 34
+#define MX21_INT_DMACH3 35
+#define MX21_INT_DMACH4 36
+#define MX21_INT_DMACH5 37
+#define MX21_INT_DMACH6 38
+#define MX21_INT_DMACH7 39
+#define MX21_INT_DMACH8 40
+#define MX21_INT_DMACH9 41
+#define MX21_INT_DMACH10 42
+#define MX21_INT_DMACH11 43
+#define MX21_INT_DMACH12 44
+#define MX21_INT_DMACH13 45
+#define MX21_INT_DMACH14 46
+#define MX21_INT_DMACH15 47
#define MX21_INT_EMMAENC 49
#define MX21_INT_EMMADEC 50
+#define MX21_INT_EMMAPRP 51
+#define MX21_INT_EMMAPP 52
#define MX21_INT_USBWKUP 53
#define MX21_INT_USBDMA 54
#define MX21_INT_USBHOST 55
#define MX21_INT_USBFUNC 56
#define MX21_INT_USBMNP 57
#define MX21_INT_USBCTRL 58
-#define MX21_INT_USBCTRL 58
+#define MX21_INT_SLCDC 60
+#define MX21_INT_LCDC 61
/* fixed DMA request numbers */
+#define MX21_DMA_REQ_CSPI3_RX 1
+#define MX21_DMA_REQ_CSPI3_TX 2
+#define MX21_DMA_REQ_EXT 3
#define MX21_DMA_REQ_FIRI_RX 4
+#define MX21_DMA_REQ_SDHC2 6
+#define MX21_DMA_REQ_SDHC1 7
+#define MX21_DMA_REQ_SSI2_RX0 8
+#define MX21_DMA_REQ_SSI2_TX0 9
+#define MX21_DMA_REQ_SSI2_RX1 10
+#define MX21_DMA_REQ_SSI2_TX1 11
+#define MX21_DMA_REQ_SSI1_RX0 12
+#define MX21_DMA_REQ_SSI1_TX0 13
+#define MX21_DMA_REQ_SSI1_RX1 14
+#define MX21_DMA_REQ_SSI1_TX1 15
+#define MX21_DMA_REQ_CSPI2_RX 16
+#define MX21_DMA_REQ_CSPI2_TX 17
+#define MX21_DMA_REQ_CSPI1_RX 18
+#define MX21_DMA_REQ_CSPI1_TX 19
+#define MX21_DMA_REQ_UART4_RX 20
+#define MX21_DMA_REQ_UART4_TX 21
+#define MX21_DMA_REQ_UART3_RX 22
+#define MX21_DMA_REQ_UART3_TX 23
+#define MX21_DMA_REQ_UART2_RX 24
+#define MX21_DMA_REQ_UART2_TX 25
+#define MX21_DMA_REQ_UART1_RX 26
+#define MX21_DMA_REQ_UART1_TX 27
#define MX21_DMA_REQ_BMI_TX 28
#define MX21_DMA_REQ_BMI_RX 29
+#define MX21_DMA_REQ_CSI_STAT 30
+#define MX21_DMA_REQ_CSI_RX 31
/* these should go away */
#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 13/25] imx: copy constants from mx2x.h to mx27.h using the appropriate namespace
2009-11-16 20:34 ` [PATCH 12/25] imx: copy constants from mx2x.h to mx21.h using the appropriate namespace Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 14/25] imx: copy constants from mx3x.h to mx31.h " Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx27.h | 147 +++++++++++++++++++++++++++++----
1 files changed, 129 insertions(+), 18 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index b619aa4..e2ae19f 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -24,28 +24,69 @@
#ifndef __ASM_ARCH_MXC_MX27_H__
#define __ASM_ARCH_MXC_MX27_H__
-#define MX27_MSHC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x18000)
-#define MX27_GPT5_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x19000)
-#define MX27_GPT4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1a000)
-#define MX27_UART5_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1b000)
-#define MX27_UART6_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1c000)
-#define MX27_I2C2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1d000)
-#define MX27_SDHC3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1e000)
-#define MX27_GPT6_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1f000)
-#define MX27_VPU_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x23000)
-#define MX27_OTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
-#define MX27_SAHARA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x25000)
-#define MX27_IIM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x28000)
-#define MX27_RTIC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x2a000)
-#define MX27_FEC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x2b000)
-#define MX27_SCC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x2c000)
-#define MX27_ETB_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3b000)
-#define MX27_ETB_RAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3c000)
+#define MX27_AIPI_BASE_ADDR 0x10000000
+#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
+#define MX27_AIPI_SIZE SZ_1M
+#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
+#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
+#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
+#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
+#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
+#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
+#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
+#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
+#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
+#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
+#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
+#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
+#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
+#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
+#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
+#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
+#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
+#define MX27_I2C_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
+#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
+#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
+#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
+#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
+#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
+#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
+#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
+#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
+#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
+#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
+#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
+#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
+#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
+#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
+#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
+#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
+#define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
+#define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR
+#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
+#define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
+#define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
+#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
+#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
+#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
+#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
+#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
+#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
+#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
+#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
+#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
+#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
+
+#define MX27_AVIC_BASE_ADDR 0x10040000
/* ROM patch */
#define MX27_ROMP_BASE_ADDR 0x10041000
-#define MX27_ATA_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x1000)
+#define MX27_SAHB1_BASE_ADDR 0x80000000
+#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000
+#define MX27_SAHB1_SIZE SZ_1M
+#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
+#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
/* Memory regions and CS */
#define MX27_SDRAM_BASE_ADDR 0xa0000000
@@ -79,12 +120,53 @@
#define MX27_INT_GPT5 3
#define MX27_INT_GPT4 4
#define MX27_INT_RTIC 5
+#define MX27_INT_CSPI3 6
#define MX27_INT_SDHC 7
+#define MX27_INT_GPIO 8
#define MX27_INT_SDHC3 9
+#define MX27_INT_SDHC2 10
+#define MX27_INT_SDHC1 11
+#define MX27_INT_I2C 12
+#define MX27_INT_SSI2 13
+#define MX27_INT_SSI1 14
+#define MX27_INT_CSPI2 15
+#define MX27_INT_CSPI1 16
+#define MX27_INT_UART4 17
+#define MX27_INT_UART3 18
+#define MX27_INT_UART2 19
+#define MX27_INT_UART1 20
+#define MX27_INT_KPP 21
+#define MX27_INT_RTC 22
+#define MX27_INT_PWM 23
+#define MX27_INT_GPT3 24
+#define MX27_INT_GPT2 25
+#define MX27_INT_GPT1 26
+#define MX27_INT_WDOG 27
+#define MX27_INT_PCMCIA 28
+#define MX27_INT_NANDFC 29
#define MX27_INT_ATA 30
+#define MX27_INT_CSI 31
+#define MX27_INT_DMACH0 32
+#define MX27_INT_DMACH1 33
+#define MX27_INT_DMACH2 34
+#define MX27_INT_DMACH3 35
+#define MX27_INT_DMACH4 36
+#define MX27_INT_DMACH5 37
+#define MX27_INT_DMACH6 38
+#define MX27_INT_DMACH7 39
+#define MX27_INT_DMACH8 40
+#define MX27_INT_DMACH9 41
+#define MX27_INT_DMACH10 42
+#define MX27_INT_DMACH11 43
+#define MX27_INT_DMACH12 44
+#define MX27_INT_DMACH13 45
+#define MX27_INT_DMACH14 46
+#define MX27_INT_DMACH15 47
#define MX27_INT_UART6 48
#define MX27_INT_UART5 49
#define MX27_INT_FEC 50
+#define MX27_INT_EMMAPRP 51
+#define MX27_INT_EMMAPP 52
#define MX27_INT_VPU 53
#define MX27_INT_USB1 54
#define MX27_INT_USB2 55
@@ -92,13 +174,42 @@
#define MX27_INT_SCC_SMN 57
#define MX27_INT_SCC_SCM 58
#define MX27_INT_SAHARA 59
+#define MX27_INT_SLCDC 60
+#define MX27_INT_LCDC 61
#define MX27_INT_IIM 62
#define MX27_INT_CCM 63
/* fixed DMA request numbers */
+#define MX27_DMA_REQ_CSPI3_RX 1
+#define MX27_DMA_REQ_CSPI3_TX 2
+#define MX27_DMA_REQ_EXT 3
#define MX27_DMA_REQ_MSHC 4
+#define MX27_DMA_REQ_SDHC2 6
+#define MX27_DMA_REQ_SDHC1 7
+#define MX27_DMA_REQ_SSI2_RX0 8
+#define MX27_DMA_REQ_SSI2_TX0 9
+#define MX27_DMA_REQ_SSI2_RX1 10
+#define MX27_DMA_REQ_SSI2_TX1 11
+#define MX27_DMA_REQ_SSI1_RX0 12
+#define MX27_DMA_REQ_SSI1_TX0 13
+#define MX27_DMA_REQ_SSI1_RX1 14
+#define MX27_DMA_REQ_SSI1_TX1 15
+#define MX27_DMA_REQ_CSPI2_RX 16
+#define MX27_DMA_REQ_CSPI2_TX 17
+#define MX27_DMA_REQ_CSPI1_RX 18
+#define MX27_DMA_REQ_CSPI1_TX 19
+#define MX27_DMA_REQ_UART4_RX 20
+#define MX27_DMA_REQ_UART4_TX 21
+#define MX27_DMA_REQ_UART3_RX 22
+#define MX27_DMA_REQ_UART3_TX 23
+#define MX27_DMA_REQ_UART2_RX 24
+#define MX27_DMA_REQ_UART2_TX 25
+#define MX27_DMA_REQ_UART1_RX 26
+#define MX27_DMA_REQ_UART1_TX 27
#define MX27_DMA_REQ_ATA_TX 28
#define MX27_DMA_REQ_ATA_RCV 29
+#define MX27_DMA_REQ_CSI_STAT 30
+#define MX27_DMA_REQ_CSI_RX 31
#define MX27_DMA_REQ_UART5_TX 32
#define MX27_DMA_REQ_UART5_RX 33
#define MX27_DMA_REQ_UART6_TX 34
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 14/25] imx: copy constants from mx3x.h to mx31.h using the appropriate namespace
2009-11-16 20:34 ` [PATCH 13/25] imx: copy constants from mx2x.h to mx27.h " Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 15/25] imx: copy constants from mx3x.h to mx35.h " Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx31.h | 171 ++++++++++++++++++++++++++++++---
1 files changed, 157 insertions(+), 14 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index a4d6901..b8b47d1 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -4,44 +4,187 @@
#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
#define MX31_IRAM_SIZE SZ_16K
-#define MX31_OTG_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x88000)
-#define MX31_ATA_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x8c000)
-#define MX31_UART4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb0000)
-#define MX31_UART5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb4000)
+#define MX31_L2CC_BASE_ADDR 0x30000000
+#define MX31_L2CC_SIZE SZ_1M
-#define MX31_MMC_SDHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x04000)
-#define MX31_MMC_SDHC2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x08000)
-#define MX31_SIM1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x18000)
-#define MX31_IIM_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x1c000)
+#define MX31_AIPS1_BASE_ADDR 0x43f00000
+#define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000
+#define MX31_AIPS1_SIZE SZ_1M
+#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
+#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
+#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
+#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
+#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
+#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
+#define MX31_I2C_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
+#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
+#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
+#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
+#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
+#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
+#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
+#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
+#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
+#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
+#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
+#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
+#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
+#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
+#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
+#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
-#define MX31_CSPI3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x84000)
-#define MX31_FIRI_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x8c000)
-#define MX31_SCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xae000)
-#define MX31_SMN_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xaf000)
-#define MX31_MPEG4_ENC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc8000)
+#define MX31_SPBA0_BASE_ADDR 0x50000000
+#define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000
+#define MX31_SPBA0_SIZE SZ_1M
+#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
+#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
+#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
+#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
+#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
+#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
+#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
+#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
+#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
+#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
-#define MX31_NFC_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x0000)
+#define MX31_AIPS2_BASE_ADDR 0x53f00000
+#define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000
+#define MX31_AIPS2_SIZE SZ_1M
+#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
+#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
+#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
+#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
+#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
+#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
+#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
+#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
+#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
+#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
+#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
+#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
+#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
+#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
+#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
+#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
+#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
+#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
+#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
+#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
+#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
+#define MX31_ROMP_BASE_ADDR 0x60000000
+#define MX31_ROMP_BASE_ADDR_VIRT 0xfc500000
+#define MX31_ROMP_SIZE SZ_1M
+
+#define MX31_AVIC_BASE_ADDR 0x68000000
+#define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000
+#define MX31_AVIC_SIZE SZ_1M
+
+#define MX31_IPU_MEM_BASE_ADDR 0x70000000
+#define MX31_CSD0_BASE_ADDR 0x80000000
+#define MX31_CSD1_BASE_ADDR 0x90000000
+
+#define MX31_CS0_BASE_ADDR 0xa0000000
+#define MX31_CS1_BASE_ADDR 0xa8000000
+#define MX31_CS2_BASE_ADDR 0xb0000000
+#define MX31_CS3_BASE_ADDR 0xb2000000
+
+#define MX31_CS4_BASE_ADDR 0xb4000000
+#define MX31_CS4_BASE_ADDR_VIRT 0xf4000000
+#define MX31_CS4_SIZE SZ_32M
+
+#define MX31_CS5_BASE_ADDR 0xb6000000
+#define MX31_CS5_BASE_ADDR_VIRT 0xf6000000
+#define MX31_CS5_SIZE SZ_32M
+
+#define MX31_X_MEMC_BASE_ADDR 0xb8000000
+#define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000
+#define MX31_X_MEMC_SIZE SZ_64K
+#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
+#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
+#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
+#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
+#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
+#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
+
+#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
+
+#define MX31_INT_I2C3 3
+#define MX31_INT_I2C2 4
#define MX31_INT_MPEG4_ENCODER 5
+#define MX31_INT_RTIC 6
#define MX31_INT_FIRI 7
#define MX31_INT_MMC_SDHC2 8
#define MX31_INT_MMC_SDHC1 9
+#define MX31_INT_I2C 10
#define MX31_INT_SSI2 11
#define MX31_INT_SSI1 12
+#define MX31_INT_CSPI2 13
+#define MX31_INT_CSPI1 14
+#define MX31_INT_ATA 15
#define MX31_INT_MBX 16
#define MX31_INT_CSPI3 17
+#define MX31_INT_UART3 18
+#define MX31_INT_IIM 19
#define MX31_INT_SIM2 20
#define MX31_INT_SIM1 21
+#define MX31_INT_RNGA 22
+#define MX31_INT_EVTMON 23
+#define MX31_INT_KPP 24
+#define MX31_INT_RTC 25
+#define MX31_INT_PWM 26
+#define MX31_INT_EPIT2 27
+#define MX31_INT_EPIT1 28
+#define MX31_INT_GPT 29
+#define MX31_INT_POWER_FAIL 30
#define MX31_INT_CCM_DVFS 31
+#define MX31_INT_UART2 32
+#define MX31_INT_NANDFC 33
+#define MX31_INT_SDMA 34
#define MX31_INT_USB1 35
#define MX31_INT_USB2 36
#define MX31_INT_USB3 37
#define MX31_INT_USB4 38
+#define MX31_INT_MSHC1 39
#define MX31_INT_MSHC2 40
+#define MX31_INT_IPU_ERR 41
+#define MX31_INT_IPU_SYN 42
+#define MX31_INT_UART1 45
#define MX31_INT_UART4 46
#define MX31_INT_UART5 47
+#define MX31_INT_ECT 48
+#define MX31_INT_SCC_SCM 49
+#define MX31_INT_SCC_SMN 50
+#define MX31_INT_GPIO2 51
+#define MX31_INT_GPIO1 52
#define MX31_INT_CCM 53
#define MX31_INT_PCMCIA 54
+#define MX31_INT_WDOG 55
+#define MX31_INT_GPIO3 56
+#define MX31_INT_EXT_POWER 58
+#define MX31_INT_EXT_TEMPER 59
+#define MX31_INT_EXT_SENSOR60 60
+#define MX31_INT_EXT_SENSOR61 61
+#define MX31_INT_EXT_WDOG 62
+#define MX31_INT_EXT_TV 63
+
+#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
+
+/* silicon revisions specific to i.MX31 */
+#define MX31_CHIP_REV_1_0 0x10
+#define MX31_CHIP_REV_1_1 0x11
+#define MX31_CHIP_REV_1_2 0x12
+#define MX31_CHIP_REV_1_3 0x13
+#define MX31_CHIP_REV_2_0 0x20
+#define MX31_CHIP_REV_2_1 0x21
+#define MX31_CHIP_REV_2_2 0x22
+#define MX31_CHIP_REV_2_3 0x23
+#define MX31_CHIP_REV_3_0 0x30
+#define MX31_CHIP_REV_3_1 0x31
+#define MX31_CHIP_REV_3_2 0x32
+
+#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
+#define MX31_SYSTEM_REV_NUM 3
/* these should go away */
#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 15/25] imx: copy constants from mx3x.h to mx35.h using the appropriate namespace
2009-11-16 20:34 ` [PATCH 14/25] imx: copy constants from mx3x.h to mx31.h " Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 16/25] imx: generalize nand device registration Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-mxc/include/mach/mx35.h | 152 +++++++++++++++++++++++++++++++++
1 files changed, 152 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 42b2a99..af871bc 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -4,29 +4,181 @@
#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
#define MX35_IRAM_SIZE SZ_128K
+#define MX35_L2CC_BASE_ADDR 0x30000000
+#define MX35_L2CC_SIZE SZ_1M
+
+#define MX35_AIPS1_BASE_ADDR 0x43f00000
+#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000
+#define MX35_AIPS1_SIZE SZ_1M
+#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
+#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
+#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
+#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
+#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
+#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
+#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
+#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
+#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
+#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
+#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000)
+#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000)
+#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000)
+#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000)
+#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000)
+#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000)
+#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000)
+#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
+
+#define MX35_SPBA0_BASE_ADDR 0x50000000
+#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000
+#define MX35_SPBA0_SIZE SZ_1M
+#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
+#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
+#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
+#define MX35_ATA_DMA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
+#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
#define MX35_FEC_BASE_ADDR 0x50038000
+#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
+
+#define MX35_AIPS2_BASE_ADDR 0x53f00000
+#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000
+#define MX35_AIPS2_SIZE SZ_1M
+#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
+#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
+#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000)
+#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000)
+#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
+#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
+#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
+#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
+#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
+#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
+#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000)
+#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000)
+#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
+#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
+#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
+#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
#define MX35_OTG_BASE_ADDR 0x53ff4000
+
+#define MX35_ROMP_BASE_ADDR 0x60000000
+#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000
+#define MX35_ROMP_SIZE SZ_1M
+
+#define MX35_AVIC_BASE_ADDR 0x68000000
+#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000
+#define MX35_AVIC_SIZE SZ_1M
+
+/*
+ * Memory regions and CS
+ */
+#define MX35_IPU_MEM_BASE_ADDR 0x70000000
+#define MX35_CSD0_BASE_ADDR 0x80000000
+#define MX35_CSD1_BASE_ADDR 0x90000000
+
+#define MX35_CS0_BASE_ADDR 0xa0000000
+#define MX35_CS1_BASE_ADDR 0xa8000000
+#define MX35_CS2_BASE_ADDR 0xb0000000
+#define MX35_CS3_BASE_ADDR 0xb2000000
+
+#define MX35_CS4_BASE_ADDR 0xb4000000
+#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000
+#define MX35_CS4_SIZE SZ_32M
+
+#define MX35_CS5_BASE_ADDR 0xb6000000
+#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000
+#define MX35_CS5_SIZE SZ_32M
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define MX35_X_MEMC_BASE_ADDR 0xb8000000
+#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000
+#define MX35_X_MEMC_SIZE SZ_64K
+#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
+#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
+#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000)
+#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000)
+#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR
+
#define MX35_NFC_BASE_ADDR 0xbb000000
+#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
/*
* Interrupt numbers
*/
#define MX35_INT_OWIRE 2
+#define MX35_INT_I2C3 3
+#define MX35_INT_I2C2 4
+#define MX35_INT_RTIC 6
#define MX35_INT_MMC_SDHC1 7
#define MX35_INT_MMC_SDHC2 8
#define MX35_INT_MMC_SDHC3 9
+#define MX35_INT_I2C 10
#define MX35_INT_SSI1 11
#define MX35_INT_SSI2 12
+#define MX35_INT_CSPI2 13
+#define MX35_INT_CSPI1 14
+#define MX35_INT_ATA 15
#define MX35_INT_GPU2D 16
#define MX35_INT_ASRC 17
+#define MX35_INT_UART3 18
+#define MX35_INT_IIM 19
+#define MX35_INT_RNGA 22
+#define MX35_INT_EVTMON 23
+#define MX35_INT_KPP 24
+#define MX35_INT_RTC 25
+#define MX35_INT_PWM 26
+#define MX35_INT_EPIT2 27
+#define MX35_INT_EPIT1 28
+#define MX35_INT_GPT 29
+#define MX35_INT_POWER_FAIL 30
+#define MX35_INT_UART2 32
+#define MX35_INT_NANDFC 33
+#define MX35_INT_SDMA 34
#define MX35_INT_USBHS 35
#define MX35_INT_USBOTG 37
+#define MX35_INT_MSHC1 39
#define MX35_INT_ESAI 40
+#define MX35_INT_IPU_ERR 41
+#define MX35_INT_IPU_SYN 42
#define MX35_INT_CAN1 43
#define MX35_INT_CAN2 44
+#define MX35_INT_UART1 45
#define MX35_INT_MLB 46
#define MX35_INT_SPDIF 47
+#define MX35_INT_ECT 48
+#define MX35_INT_SCC_SCM 49
+#define MX35_INT_SCC_SMN 50
+#define MX35_INT_GPIO2 51
+#define MX35_INT_GPIO1 52
+#define MX35_INT_WDOG 55
+#define MX35_INT_GPIO3 56
#define MX35_INT_FEC 57
+#define MX35_INT_EXT_POWER 58
+#define MX35_INT_EXT_TEMPER 59
+#define MX35_INT_EXT_SENSOR60 60
+#define MX35_INT_EXT_SENSOR61 61
+#define MX35_INT_EXT_WDOG 62
+#define MX35_INT_EXT_TV 63
+
+#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
+
+/* silicon revisions specific to i.MX31 */
+#define MX35_CHIP_REV_1_0 0x10
+#define MX35_CHIP_REV_1_1 0x11
+#define MX35_CHIP_REV_1_2 0x12
+#define MX35_CHIP_REV_1_3 0x13
+#define MX35_CHIP_REV_2_0 0x20
+#define MX35_CHIP_REV_2_1 0x21
+#define MX35_CHIP_REV_2_2 0x22
+#define MX35_CHIP_REV_2_3 0x23
+#define MX35_CHIP_REV_3_0 0x30
+#define MX35_CHIP_REV_3_1 0x31
+#define MX35_CHIP_REV_3_2 0x32
+
+#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0
+#define MX35_SYSTEM_REV_NUM 3
/* these should go away */
#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 16/25] imx: generalize nand device registration
2009-11-16 20:34 ` [PATCH 15/25] imx: copy constants from mx3x.h to mx35.h " Uwe Kleine-König
@ 2009-11-16 20:34 ` Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 17/25] imx/eukrea_cpuimx27: use new " Uwe Kleine-König
` (2 more replies)
0 siblings, 3 replies; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:34 UTC (permalink / raw)
To: linux-arm-kernel
create mxc_nand platform_devices dynamically.
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/mach-mx2/devices.h | 2 +
arch/arm/mach-mx3/devices.h | 1 +
arch/arm/mach-mxc91231/devices.h | 2 +
arch/arm/plat-mxc/Makefile | 2 +
arch/arm/plat-mxc/devices/Makefile | 1 +
arch/arm/plat-mxc/devices/platform-mxc_nand.c | 54 +++++++++++++++++++++++
arch/arm/plat-mxc/include/mach/devices-common.h | 20 ++++++++
7 files changed, 82 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/plat-mxc/devices/Makefile
create mode 100644 arch/arm/plat-mxc/devices/platform-mxc_nand.c
create mode 100644 arch/arm/plat-mxc/include/mach/devices-common.h
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
index d315406..7f5ee56 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-mx2/devices.h
@@ -1,3 +1,5 @@
+#include <mach/devices-common.h>
+
extern struct platform_device mxc_gpt1;
extern struct platform_device mxc_gpt2;
extern struct platform_device mxc_gpt3;
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index ab87419..9ce9ea8 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -1,3 +1,4 @@
+#include <mach/devices-common.h>
extern struct platform_device mxc_uart_device0;
extern struct platform_device mxc_uart_device1;
diff --git a/arch/arm/mach-mxc91231/devices.h b/arch/arm/mach-mxc91231/devices.h
index 72a2136..37217df 100644
--- a/arch/arm/mach-mxc91231/devices.h
+++ b/arch/arm/mach-mxc91231/devices.h
@@ -1,3 +1,5 @@
+#include <mach/devices-common.h>
+
extern struct platform_device mxc_uart_device0;
extern struct platform_device mxc_uart_device1;
extern struct platform_device mxc_uart_device2;
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index e3212c8..41a0d25 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -9,3 +9,5 @@ obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
obj-$(CONFIG_MXC_PWM) += pwm.o
+
+obj-y += devices/
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
new file mode 100644
index 0000000..e444c6c
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -0,0 +1 @@
+obj-y += platform-mxc_nand.o
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
new file mode 100644
index 0000000..9d5450f
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2009 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/devices-common.h>
+#include <linux/platform_device.h>
+
+#define DRIVER_NAME "mxc_nand"
+
+int __init imx_add_mxc_nand(resource_size_t base, int irq,
+ const struct mxc_nand_platform_data *pdata)
+{
+ static int id = 0;
+ int ret = -ENOMEM;
+ struct platform_device *pdev;
+
+ struct resource res[] = {
+ {
+ .start = base,
+ .end = base + 0xfff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = irq,
+ .end = irq,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ pdev = platform_device_alloc(DRIVER_NAME, id++);
+ if (!pdev)
+ goto err;
+
+ ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
+ if (ret)
+ goto err;
+
+ ret = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+ if (ret)
+ goto err;
+
+ ret = platform_device_add(pdev);
+ if (ret) {
+err:
+ platform_device_put(pdev);
+ pr_warning("Could not add %s (errno=%d)\n",
+ DRIVER_NAME, ret);
+ }
+
+ return ret;
+}
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
new file mode 100644
index 0000000..d17c2b2
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2009 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <mach/mxc_nand.h>
+
+int __init imx_add_mxc_nand(resource_size_t base, int irq,
+ const struct mxc_nand_platform_data *pdata);
+
+#define imx21_add_mxc_nand(pdata) imx_add_mxc_nand(MX21_NFC_BASE_ADDR, MX21_INT_NFC, pdata)
+#define imx25_add_mxc_nand(pdata) imx_add_mxc_nand(MX25_NFC_BASE_ADDR, MX25_INT_NFC, pdata)
+#define imx27_add_mxc_nand(pdata) imx_add_mxc_nand(MX27_NFC_BASE_ADDR, MX27_INT_NFC, pdata)
+#define imx31_add_mxc_nand(pdata) imx_add_mxc_nand(MX31_NFC_BASE_ADDR, MX31_INT_NFC, pdata)
+#define imx35_add_mxc_nand(pdata) imx_add_mxc_nand(MX35_NFC_BASE_ADDR, MX35_INT_NFC, pdata)
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 17/25] imx/eukrea_cpuimx27: use new nand device registration
2009-11-16 20:34 ` [PATCH 16/25] imx: generalize nand device registration Uwe Kleine-König
@ 2009-11-16 20:35 ` Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 18/25] imx/mx21ads: " Uwe Kleine-König
2009-11-16 22:32 ` [PATCH 17/25] imx/eukrea_cpuimx27: use new nand device registration Russell King - ARM Linux
2009-11-17 9:54 ` [PATCH 16/25] imx: generalize " Uwe Kleine-König
2009-11-17 13:49 ` Uwe Kleine-König
2 siblings, 2 replies; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:35 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/mach-mx2/eukrea_cpuimx27.c | 13 ++++++-------
1 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-mx2/eukrea_cpuimx27.c b/arch/arm/mach-mx2/eukrea_cpuimx27.c
index 7b18760..1a7ce75 100644
--- a/arch/arm/mach-mx2/eukrea_cpuimx27.c
+++ b/arch/arm/mach-mx2/eukrea_cpuimx27.c
@@ -38,7 +38,6 @@
#include <mach/i2c.h>
#include <mach/iomux.h>
#include <mach/imx-uart.h>
-#include <mach/mxc_nand.h>
#include "devices.h"
@@ -119,11 +118,6 @@ static struct imxuart_platform_data uart_pdata[] = {
},
};
-static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
- .width = 1,
- .hw_ecc = 1,
-};
-
static struct platform_device *platform_devices[] __initdata = {
&eukrea_cpuimx27_nor_mtd_device,
&mxc_fec_device,
@@ -184,12 +178,17 @@ static struct platform_device serial_device = {
static void __init eukrea_cpuimx27_init(void)
{
+ struct mxc_nand_platform_data mxc_nand_pdata = {
+ .width = 1,
+ .hw_ecc = 1,
+ };
+
mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
- mxc_register_device(&mxc_nand_device, &eukrea_cpuimx27_nand_board_info);
+ imx27_add_mxc_nand(&mxc_nand_pdata);
i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 18/25] imx/mx21ads: use new nand device registration
2009-11-16 20:35 ` [PATCH 17/25] imx/eukrea_cpuimx27: use new " Uwe Kleine-König
@ 2009-11-16 20:35 ` Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 19/25] imx/mx27ads: " Uwe Kleine-König
2009-11-16 22:32 ` [PATCH 17/25] imx/eukrea_cpuimx27: use new nand device registration Russell King - ARM Linux
1 sibling, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:35 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/mach-mx2/mx21ads.c | 13 ++++++-------
1 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-mx2/mx21ads.c b/arch/arm/mach-mx2/mx21ads.c
index cf5f77c..ae7ff28 100644
--- a/arch/arm/mach-mx2/mx21ads.c
+++ b/arch/arm/mach-mx2/mx21ads.c
@@ -31,7 +31,6 @@
#include <mach/imx-uart.h>
#include <mach/imxfb.h>
#include <mach/iomux.h>
-#include <mach/mxc_nand.h>
#include <mach/mmc.h>
#include <mach/board-mx21ads.h>
@@ -227,11 +226,6 @@ static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
.exit = mx21ads_sdhc_exit,
};
-static struct mxc_nand_platform_data mx21ads_nand_board_info = {
- .width = 1,
- .hw_ecc = 1,
-};
-
static struct map_desc mx21ads_io_desc[] __initdata = {
/*
* Memory-mapped I/O on MX21ADS Base board:
@@ -260,6 +254,11 @@ static struct platform_device *platform_devices[] __initdata = {
static void __init mx21ads_board_init(void)
{
+ struct mxc_nand_platform_data mxc_nand_pdata = {
+ .width = 1,
+ .hw_ecc = 1,
+ };
+
mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
"mx21ads");
@@ -268,7 +267,7 @@ static void __init mx21ads_board_init(void)
mxc_register_device(&mxc_uart_device3, &uart_pdata);
mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
- mxc_register_device(&mxc_nand_device, &mx21ads_nand_board_info);
+ imx21_add_mxc_nand(&mxc_nand_pdata);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 19/25] imx/mx27ads: use new nand device registration
2009-11-16 20:35 ` [PATCH 18/25] imx/mx21ads: " Uwe Kleine-König
@ 2009-11-16 20:35 ` Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 20/25] imx/pca100: " Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:35 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/mach-mx2/mx27ads.c | 13 ++++++-------
1 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
index 83e412b..3710a84 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -35,7 +35,6 @@
#include <mach/imx-uart.h>
#include <mach/iomux.h>
#include <mach/board-mx27ads.h>
-#include <mach/mxc_nand.h>
#include <mach/i2c.h>
#include <mach/imxfb.h>
#include <mach/mmc.h>
@@ -141,11 +140,6 @@ static unsigned int mx27ads_pins[] = {
PB9_PF_SD2_CLK,
};
-static struct mxc_nand_platform_data mx27ads_nand_board_info = {
- .width = 1,
- .hw_ecc = 1,
-};
-
/* ADS's NOR flash */
static struct physmap_flash_data mx27ads_flash_data = {
.width = 2,
@@ -281,6 +275,11 @@ static struct imxuart_platform_data uart_pdata[] = {
static void __init mx27ads_board_init(void)
{
+ struct mxc_nand_platform_data mxc_nand_pdata = {
+ .width = 1,
+ .hw_ecc = 1,
+ };
+
mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
"mx27ads");
@@ -290,7 +289,7 @@ static void __init mx27ads_board_init(void)
mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
- mxc_register_device(&mxc_nand_device, &mx27ads_nand_board_info);
+ imx27_add_mxc_nand(&mxc_nand_pdata);
/* only the i2c master 1 is used on this CPU card */
i2c_register_board_info(1, mx27ads_i2c_devices,
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 20/25] imx/pca100: use new nand device registration
2009-11-16 20:35 ` [PATCH 19/25] imx/mx27ads: " Uwe Kleine-König
@ 2009-11-16 20:35 ` Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 21/25] imx/pcm038: " Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:35 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/mach-mx2/pca100.c | 12 +++++-------
1 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-mx2/pca100.c b/arch/arm/mach-mx2/pca100.c
index fe5b165..a828ed9 100644
--- a/arch/arm/mach-mx2/pca100.c
+++ b/arch/arm/mach-mx2/pca100.c
@@ -38,7 +38,6 @@
#include <mach/spi.h>
#endif
#include <mach/imx-uart.h>
-#include <mach/mxc_nand.h>
#include <mach/irqs.h>
#include <mach/mmc.h>
@@ -98,11 +97,6 @@ static struct imxuart_platform_data uart_pdata = {
.flags = IMXUART_HAVE_RTSCTS,
};
-static struct mxc_nand_platform_data pca100_nand_board_info = {
- .width = 1,
- .hw_ecc = 1,
-};
-
static struct platform_device *platform_devices[] __initdata = {
&mxc_w1_master_device,
&mxc_fec_device,
@@ -184,6 +178,10 @@ static struct imxmmc_platform_data sdhc_pdata = {
static void __init pca100_init(void)
{
+ struct mxc_nand_platform_data mxc_nand_pdata = {
+ .width = 1,
+ .hw_ecc = 1,
+ };
int ret;
ret = mxc_gpio_setup_multiple_pins(pca100_pins,
@@ -196,7 +194,7 @@ static void __init pca100_init(void)
mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
- mxc_register_device(&mxc_nand_device, &pca100_nand_board_info);
+ imx27_add_mxc_nand(&mxc_nand_pdata);
/* only the i2c master 1 is used on this CPU card */
i2c_register_board_info(1, pca100_i2c_devices,
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 21/25] imx/pcm038: use new nand device registration
2009-11-16 20:35 ` [PATCH 20/25] imx/pca100: " Uwe Kleine-König
@ 2009-11-16 20:35 ` Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 22/25] imx/armadillo5x0: " Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:35 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/mach-mx2/pcm038.c | 13 ++++++-------
1 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
index 906d59b..0f2211c 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -38,7 +38,6 @@
#include <mach/i2c.h>
#include <mach/iomux.h>
#include <mach/imx-uart.h>
-#include <mach/mxc_nand.h>
#include <mach/spi.h>
#include "devices.h"
@@ -157,11 +156,6 @@ static struct imxuart_platform_data uart_pdata[] = {
},
};
-static struct mxc_nand_platform_data pcm038_nand_board_info = {
- .width = 1,
- .hw_ecc = 1,
-};
-
static struct platform_device *platform_devices[] __initdata = {
&pcm038_nor_mtd_device,
&mxc_w1_master_device,
@@ -281,6 +275,11 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = {
static void __init pcm038_init(void)
{
+ struct mxc_nand_platform_data mxc_nand_pdata = {
+ .width = 1,
+ .hw_ecc = 1,
+ };
+
mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
"PCM038");
@@ -291,7 +290,7 @@ static void __init pcm038_init(void)
mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
mxc_gpio_mode(PE16_AF_OWIRE);
- mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info);
+ imx27_add_mxc_nand(&mxc_nand_pdata);
/* only the i2c master 1 is used on this CPU card */
i2c_register_board_info(1, pcm038_i2c_devices,
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 22/25] imx/armadillo5x0: use new nand device registration
2009-11-16 20:35 ` [PATCH 21/25] imx/pcm038: " Uwe Kleine-König
@ 2009-11-16 20:35 ` Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 23/25] imx/mx31lite: " Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:35 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/mach-mx3/armadillo5x0.c | 16 ++++++----------
1 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/armadillo5x0.c
index 776c0ee..e2d36b4 100644
--- a/arch/arm/mach-mx3/armadillo5x0.c
+++ b/arch/arm/mach-mx3/armadillo5x0.c
@@ -48,7 +48,6 @@
#include <mach/mmc.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
-#include <mach/mxc_nand.h>
#include "devices.h"
#include "crm_regs.h"
@@ -100,14 +99,6 @@ static int armadillo5x0_pins[] = {
};
/*
- * NAND Flash
- */
-static struct mxc_nand_platform_data armadillo5x0_nand_flash_pdata = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-/*
* MTD NOR Flash
*/
static struct mtd_partition armadillo5x0_nor_flash_partitions[] = {
@@ -307,6 +298,11 @@ static struct platform_device *devices[] __initdata = {
*/
static void __init armadillo5x0_init(void)
{
+ struct mxc_nand_platform_data mxc_nand_pdata = {
+ .width = 1,
+ .hw_ecc = 1,
+ };
+
mxc_iomux_setup_multiple_pins(armadillo5x0_pins,
ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
@@ -331,7 +327,7 @@ static void __init armadillo5x0_init(void)
&armadillo5x0_nor_flash_pdata);
/* Register NAND Flash */
- mxc_register_device(&mxc_nand_device, &armadillo5x0_nand_flash_pdata);
+ imx31_add_mxc_nand(&mxc_nand_pdata);
/* set NAND page size to 2k if not configured via boot mode pins */
__raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 23/25] imx/mx31lite: use new nand device registration
2009-11-16 20:35 ` [PATCH 22/25] imx/armadillo5x0: " Uwe Kleine-König
@ 2009-11-16 20:35 ` Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 24/25] imx/pcm037: " Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:35 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/mach-mx3/mx31lite.c | 12 +++++-------
1 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
index a8d57de..6884e59 100644
--- a/arch/arm/mach-mx3/mx31lite.c
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -38,7 +38,6 @@
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/irqs.h>
-#include <mach/mxc_nand.h>
#include "devices.h"
/*
@@ -59,11 +58,6 @@ static struct imxuart_platform_data uart_pdata = {
.flags = IMXUART_HAVE_RTSCTS,
};
-static struct mxc_nand_platform_data mx31lite_nand_board_info = {
- .width = 1,
- .hw_ecc = 1,
-};
-
static struct smsc911x_platform_config smsc911x_config = {
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
@@ -123,13 +117,17 @@ void __init mx31lite_map_io(void)
*/
static void __init mxc_board_init(void)
{
+ struct mxc_nand_platform_data mxc_nand_pdata = {
+ .width = 1,
+ .hw_ecc = 1,
+ };
int ret;
mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
"mx31lite");
mxc_register_device(&mxc_uart_device0, &uart_pdata);
- mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info);
+ imx31_add_mxc_nand(&mxc_nand_pdata);
/* SMSC9117 IRQ pin */
ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 24/25] imx/pcm037: use new nand device registration
2009-11-16 20:35 ` [PATCH 23/25] imx/mx31lite: " Uwe Kleine-König
@ 2009-11-16 20:35 ` Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 25/25] imx/mx25pdk: remove unused include Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:35 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/mach-mx3/pcm037.c | 12 +++++-------
1 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
index 6cbaabe..2b93c87 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -50,7 +50,6 @@
#include <mach/mmc.h>
#include <mach/mx3_camera.h>
#include <mach/mx3fb.h>
-#include <mach/mxc_nand.h>
#include "devices.h"
#include "pcm037.h"
@@ -296,11 +295,6 @@ static struct platform_device pcm037_sram_device = {
.resource = &pcm038_sram_resource,
};
-static struct mxc_nand_platform_data pcm037_nand_board_info = {
- .width = 1,
- .hw_ecc = 1,
-};
-
static struct imxi2c_platform_data pcm037_i2c_1_data = {
.bitrate = 100000,
};
@@ -548,6 +542,10 @@ static struct platform_device pcm970_sja1000 = {
*/
static void __init mxc_board_init(void)
{
+ struct mxc_nand_platform_data mxc_nand_pdata = {
+ .width = 1,
+ .hw_ecc = 1,
+ };
int ret;
mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
@@ -586,7 +584,7 @@ static void __init mxc_board_init(void)
mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data);
mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data);
- mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
+ imx31_add_mxc_nand(&mxc_nand_pdata);
mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 25/25] imx/mx25pdk: remove unused include
2009-11-16 20:35 ` [PATCH 24/25] imx/pcm037: " Uwe Kleine-König
@ 2009-11-16 20:35 ` Uwe Kleine-König
0 siblings, 0 replies; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-16 20:35 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/mach-mx25/mx25pdk.c | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mx25pdk.c
index d23ae57..9bfa408 100644
--- a/arch/arm/mach-mx25/mx25pdk.c
+++ b/arch/arm/mach-mx25/mx25pdk.c
@@ -33,7 +33,6 @@
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/mx25.h>
-#include <mach/mxc_nand.h>
#include "devices.h"
#include <mach/iomux-v3.h>
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 17/25] imx/eukrea_cpuimx27: use new nand device registration
2009-11-16 20:35 ` [PATCH 17/25] imx/eukrea_cpuimx27: use new " Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 18/25] imx/mx21ads: " Uwe Kleine-König
@ 2009-11-16 22:32 ` Russell King - ARM Linux
2009-11-17 9:56 ` Uwe Kleine-König
1 sibling, 1 reply; 32+ messages in thread
From: Russell King - ARM Linux @ 2009-11-16 22:32 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Nov 16, 2009 at 09:35:00PM +0100, Uwe Kleine-K?nig wrote:
> static void __init eukrea_cpuimx27_init(void)
> {
> + struct mxc_nand_platform_data mxc_nand_pdata = {
> + .width = 1,
> + .hw_ecc = 1,
> + };
> +
Have you checked what code the compiler spits out for this?
What the compiler will do is create a copy of the structure data in the
read-only data section. It will allocate space on the stack, and memcpy
from that read-only version to the stack version. It will then use the
stacked version for mxc_nand_data.
This saves nothing - the data remains in-core.
What you want to do is to keep the original definition, and mark it with
__initdata so that it gets discarded.
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 16/25] imx: generalize nand device registration
2009-11-16 20:34 ` [PATCH 16/25] imx: generalize nand device registration Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 17/25] imx/eukrea_cpuimx27: use new " Uwe Kleine-König
@ 2009-11-17 9:54 ` Uwe Kleine-König
2009-11-17 13:49 ` Uwe Kleine-König
2 siblings, 0 replies; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-17 9:54 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
> +#define imx21_add_mxc_nand(pdata) imx_add_mxc_nand(MX21_NFC_BASE_ADDR, MX21_INT_NFC, pdata)
> +#define imx25_add_mxc_nand(pdata) imx_add_mxc_nand(MX25_NFC_BASE_ADDR, MX25_INT_NFC, pdata)
> +#define imx27_add_mxc_nand(pdata) imx_add_mxc_nand(MX27_NFC_BASE_ADDR, MX27_INT_NFC, pdata)
> +#define imx31_add_mxc_nand(pdata) imx_add_mxc_nand(MX31_NFC_BASE_ADDR, MX31_INT_NFC, pdata)
> +#define imx35_add_mxc_nand(pdata) imx_add_mxc_nand(MX35_NFC_BASE_ADDR, MX35_INT_NFC, pdata)
Here a s/_INT_NFC/_INT_NANDFC/ is needed for all five macros. Already
fixed in my tree.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 17/25] imx/eukrea_cpuimx27: use new nand device registration
2009-11-16 22:32 ` [PATCH 17/25] imx/eukrea_cpuimx27: use new nand device registration Russell King - ARM Linux
@ 2009-11-17 9:56 ` Uwe Kleine-König
2009-11-17 14:09 ` [PATCH] " Uwe Kleine-König
0 siblings, 1 reply; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-17 9:56 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
On Mon, Nov 16, 2009 at 10:32:37PM +0000, Russell King - ARM Linux wrote:
> On Mon, Nov 16, 2009 at 09:35:00PM +0100, Uwe Kleine-K?nig wrote:
> > static void __init eukrea_cpuimx27_init(void)
> > {
> > + struct mxc_nand_platform_data mxc_nand_pdata = {
> > + .width = 1,
> > + .hw_ecc = 1,
> > + };
> > +
>
> Have you checked what code the compiler spits out for this?
>
> What the compiler will do is create a copy of the structure data in the
> read-only data section. It will allocate space on the stack, and memcpy
> from that read-only version to the stack version. It will then use the
> stacked version for mxc_nand_data.
>
> This saves nothing - the data remains in-core.
>
> What you want to do is to keep the original definition, and mark it with
> __initdata so that it gets discarded.
OK, will fix that later today.
Best regards and thanks
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 16/25] imx: generalize nand device registration
2009-11-16 20:34 ` [PATCH 16/25] imx: generalize nand device registration Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 17/25] imx/eukrea_cpuimx27: use new " Uwe Kleine-König
2009-11-17 9:54 ` [PATCH 16/25] imx: generalize " Uwe Kleine-König
@ 2009-11-17 13:49 ` Uwe Kleine-König
2 siblings, 0 replies; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-17 13:49 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
> +int __init imx_add_mxc_nand(resource_size_t base, int irq,
> + const struct mxc_nand_platform_data *pdata)
> +{
> + static int id = 0;
While looking at Russell's suggestion to use __initdata for pdata I
noticed that id lives in .bss. So I fixed that, too, by making the
above line:
static int id __initdata = 0;
(Actually better would be:
static int id __initbss;
but this doesn't exist.)
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH] imx/eukrea_cpuimx27: use new nand device registration
2009-11-17 9:56 ` Uwe Kleine-König
@ 2009-11-17 14:09 ` Uwe Kleine-König
0 siblings, 0 replies; 32+ messages in thread
From: Uwe Kleine-König @ 2009-11-17 14:09 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
Hello,
patches 17-24 now look like below and are updated in my tree[1].
Best regards
Uwe
[1] git://git.pengutronix.de/git/ukl/linux-2.6.git imx
arch/arm/mach-mx2/eukrea_cpuimx27.c | 5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-mx2/eukrea_cpuimx27.c b/arch/arm/mach-mx2/eukrea_cpuimx27.c
index 7b18760..efaea46 100644
--- a/arch/arm/mach-mx2/eukrea_cpuimx27.c
+++ b/arch/arm/mach-mx2/eukrea_cpuimx27.c
@@ -38,7 +38,6 @@
#include <mach/i2c.h>
#include <mach/iomux.h>
#include <mach/imx-uart.h>
-#include <mach/mxc_nand.h>
#include "devices.h"
@@ -119,7 +118,7 @@ static struct imxuart_platform_data uart_pdata[] = {
},
};
-static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
+static const struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
};
@@ -189,7 +188,7 @@ static void __init eukrea_cpuimx27_init(void)
mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
- mxc_register_device(&mxc_nand_device, &eukrea_cpuimx27_nand_board_info);
+ imx27_add_mxc_nand(&eukrea_cpuimx27_nand_board_info);
i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
--
1.6.5.2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 00/25] imx cleanups
2009-11-16 20:34 [PATCH 00/25] imx cleanups Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 01/25] imx: reorder mx2x.h Uwe Kleine-König
@ 2009-11-18 9:46 ` Sascha Hauer
1 sibling, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2009-11-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Nov 16, 2009 at 09:34:06PM +0100, Uwe Kleine-K?nig wrote:
> Hello,
>
> this series is the start of a big cleanup of the imx support. The
> overall goal is to support all SoCs with a single image. Therefor a few
> things need to/should be done:
>
> - clean up headers not to define the same constants (i.e. prefix
> everything with the SoC's name)
> - generalise device creation
> - generalise static mappings
> - probably much more
>
> Here I start with the first two items.
>
> On the way I plan to change all occurences of "mxc" to "imx".
>
> I hope this all can happen without much breakage.
>
> For now no #defines are removed only redefined. So all code should
> continue to work as before. Assuming this series is accepted new usage
> of the #defines without a SoC-prefix should be deprecated. When all
> users are converted, the old #defines can go away.
>
> git branch, shortlog and diffstat can be found below. It merges nearly
> fine into Sascha's mxc-master. There's only a trivial conflict in
> arch/arm/plat-mxc/Makefile .
I merged this series up to patch 15/25. I'm not sure with the device
generalisation as we currently need the device pointers for the IPU and
the regulator framework. So the nand device generalisation as is is not
suitable as a template on how device registration can work in the
future.
Sascha
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^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2009-11-18 9:46 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2009-11-16 20:34 [PATCH 00/25] imx cleanups Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 01/25] imx: reorder mx2x.h Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 02/25] imx: reorder mx21.h Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 03/25] imx: reorder mx27.h Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 04/25] imx: reorder mx3x.h Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 05/25] imx: add namespace prefixes for symbols in mx2x.h Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 06/25] imx: add namespace prefixes for symbols in mx21.h Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 07/25] imx: add namespace prefixes for symbols in mx27.h Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 08/25] imx: add namespace prefixes for symbols in mx3x.h Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 09/25] imx: add namespace prefixes for symbols in mx31.h Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 10/25] imx: add namespace prefixes for symbols in mx35.h Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 11/25] imx: reformat mx25.h to match the other platform includes Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 12/25] imx: copy constants from mx2x.h to mx21.h using the appropriate namespace Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 13/25] imx: copy constants from mx2x.h to mx27.h " Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 14/25] imx: copy constants from mx3x.h to mx31.h " Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 15/25] imx: copy constants from mx3x.h to mx35.h " Uwe Kleine-König
2009-11-16 20:34 ` [PATCH 16/25] imx: generalize nand device registration Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 17/25] imx/eukrea_cpuimx27: use new " Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 18/25] imx/mx21ads: " Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 19/25] imx/mx27ads: " Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 20/25] imx/pca100: " Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 21/25] imx/pcm038: " Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 22/25] imx/armadillo5x0: " Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 23/25] imx/mx31lite: " Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 24/25] imx/pcm037: " Uwe Kleine-König
2009-11-16 20:35 ` [PATCH 25/25] imx/mx25pdk: remove unused include Uwe Kleine-König
2009-11-16 22:32 ` [PATCH 17/25] imx/eukrea_cpuimx27: use new nand device registration Russell King - ARM Linux
2009-11-17 9:56 ` Uwe Kleine-König
2009-11-17 14:09 ` [PATCH] " Uwe Kleine-König
2009-11-17 9:54 ` [PATCH 16/25] imx: generalize " Uwe Kleine-König
2009-11-17 13:49 ` Uwe Kleine-König
2009-11-18 9:46 ` [PATCH 00/25] imx cleanups Sascha Hauer
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