[PATCH] Add Samsung S5PC110 SoC support

[PATCH] Add Samsung S5PC110 SoC support

[Marek Szyprowski]

Hello,

This preliminary patch series adds support for Samsung S5PC110 SoC.
S5PC110 belongs to S5PC1XX family (CortexA8 ARM core), but differs in
many places from the S5PC100 SoC: new memory map, different clock
hierarchy, new gpio banks and much more powerful integrated peripherals.
Such differences cannot be easily handled in the current Samsung
machine&platform framework. To avoid duplication of code and adding yet
another plat-* directory, we decided to introduce sub-platforms in
the current s5pc1xx platform.

First 8 patches prepare s5pc1xx platform code for introduction of the
new sub-platform approach. Then in the next 11 patches all core
functions and drivers are subsequently added, so S5PC110 sub-platform
gets similar level of support as S5PC100.

This patch series has been prepared against latest ARM Kernel tree from
http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm.git/

I know that Ben is working hard on new Samsung SoC platform framework,
but stabilizing it and porting all the existing Samsung platforms would
take time. This sub-platform solution is already prepared and until the
new framework will be available and merged, we would like to use our
approach.

This patch series includes:

[PATCH 01/19] ARM: S5PC100: use 0x30008000 as memory base
[PATCH 02/19] ARM: S5PC1XX: create sub-platform for S5PC100 SoCs
[PATCH 03/19] ARM: S5PC1XX: prepare common cpu&clocks code for S5PC110 sub-platform
[PATCH 04/19] ARM: S5PC1XX: prepare common gpiolib code for S5PC110 sub-platform
[PATCH 05/19] ARM: S5PC1XX: move common s5pc1xx mach/* includes to plat-s5pc1xx/include/mach
[PATCH 06/19] ARM: S5PC1XX: cleanup of s5pc1xx common code
[PATCH 07/19] ARM: S5PC1XX: move s5pc100 specific device helpers to mach-s5pc100 dir
[PATCH 08/19] ARM: S5PC1XX: move common s5pc1xx s3c-fb regs to platform directory
[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart
[PATCH 10/19] ARM: S5PC1XX: add S5PC110 memory map
[PATCH 11/19] ARM: S5PC1XX: add S5PC110 cpu initialization code
[PATCH 12/19] ARM: S5PC1XX: add support for s5pc110 plls and clocks
[PATCH 13/19] ARM: S5PC1XX: add support for s5pc110 irqs
[PATCH 14/19] ARM: S5PC1XX: add support for s5pc110 gpio
[PATCH 15/19] ARM: S5PC1XX: add i2c platform helpers on s5pc110 sub-platform
[PATCH 16/19] ARM: S5PC1XX: enable S5PC110 sub-platform
[PATCH 17/19] ARM: S5PC1XX: add sdhci platform helpers for s5pc110 sub-platform
[PATCH 18/19] ARM: S5PC1XX: add framebuffer platform helpers for s5pc110 sub-platform
[PATCH 19/19] ARM: S5PC1XX: add support for SMDKC110 board

[PATCH 01/19] ARM: S5PC100: use 0x30008000 as memory base

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

We decided to use 0x3000'0000 as base memory address on S5PC1XX SoCs
(s5pc100 and s5pc110).
A patch to u-boot that configures SMDKC100 board and sets base memory
as 0x3000'0000 has been already posted.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>


---
 arch/arm/mach-s5pc100/Makefile.boot         |    4 ++--
 arch/arm/mach-s5pc100/include/mach/map.h    |    2 +-
 arch/arm/mach-s5pc100/include/mach/memory.h |    2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-s5pc100/Makefile.boot b/arch/arm/mach-s5pc100/Makefile.boot
index ff90aa1..b0909e3 100644
--- a/arch/arm/mach-s5pc100/Makefile.boot
+++ b/arch/arm/mach-s5pc100/Makefile.boot
@@ -1,2 +1,2 @@
-   zreladdr-y	:= 0x20008000
-params_phys-y	:= 0x20000100
+   zreladdr-y	:= 0x30008000
+params_phys-y	:= 0x30000100
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 4681ebe..f90c033 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -113,7 +113,7 @@
 #define S5PC100_PA_TSADC	(0xF3000000)
 
 /* ETC */
-#define S5PC100_PA_SDRAM	(0x20000000)
+#define S5PC100_PA_SDRAM	(0x30000000)
 #define S5PC1XX_PA_SDRAM	S5PC100_PA_SDRAM
 
 /* compatibility defines. */
diff --git a/arch/arm/mach-s5pc100/include/mach/memory.h b/arch/arm/mach-s5pc100/include/mach/memory.h
index 4b60d18..21cc182 100644
--- a/arch/arm/mach-s5pc100/include/mach/memory.h
+++ b/arch/arm/mach-s5pc100/include/mach/memory.h
@@ -13,6 +13,6 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
 
-#define PHYS_OFFSET     	UL(0x20000000)
+#define PHYS_OFFSET     	UL(0x30000000)
 
 #endif
-- 
1.6.4

[PATCH 02/19] ARM: S5PC1XX: create sub-platform for S5PC100 SoCs

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC100 and S5PC110 SoCs differs a lot in register map and other
core platform definitions, so it is not possible to have both SoCs in
the current platform framework without runtime hacks. To address this
issue a sub-platform has been introduced, so each SoC in sub-platform
can have its own set of include files (register map, irq&gpio
definitions, etc)

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 arch/arm/Makefile             |    2 +-
 arch/arm/mach-s5pc100/Kconfig |    4 ++++
 arch/arm/plat-s5pc1xx/Kconfig |   10 ++++++++++
 3 files changed, 15 insertions(+), 1 deletions(-)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a73caaf..daea150 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -160,7 +160,7 @@ machine-$(CONFIG_ARCH_RPC)		:= rpc
 machine-$(CONFIG_ARCH_S3C2410)		:= s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
 machine-$(CONFIG_ARCH_S3C24A0)		:= s3c24a0
 machine-$(CONFIG_ARCH_S3C64XX)		:= s3c6400 s3c6410
-machine-$(CONFIG_ARCH_S5PC1XX)		:= s5pc100
+machine-$(CONFIG_ARCH_S5PC100)		:= s5pc100
 machine-$(CONFIG_ARCH_SA1100)		:= sa1100
 machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_STMP378X)		:= stmp378x
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 0dd2b8c..d72f881 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -5,6 +5,8 @@
 #
 # Licensed under GPLv2
 
+if ARCH_S5PC100
+
 # Configuration options for the S5PC100 CPU
 
 config CPU_S5PC100
@@ -34,3 +36,5 @@ config MACH_SMDKC100
 	select S5PC100_SETUP_SDHCI
 	help
 	  Machine support for the Samsung SMDKC100
+
+endif
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index 1608e62..eee2abb 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -23,6 +23,16 @@ config PLAT_S5PC1XX
 
 if PLAT_S5PC1XX
 
+choice
+	prompt "S5PC1xx SoC Type"
+	default ARCH_S5PC100
+
+config ARCH_S5PC100
+	bool "S5PC100"
+
+endchoice
+
+
 # Configuration options shared by all S3C64XX implementations
 
 config CPU_S5PC100_INIT
-- 
1.6.4

[PATCH 03/19] ARM: S5PC1XX: prepare common cpu&clocks code for S5PC110 sub-platform

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

CLK_OTHER register block is specific for S5PC100 SoC, so move the
definition to mach-s5pc100/cpu.c. Size of CLK and PWR register block is
different on S5PC100 and S5PC110, thus new defines are introduced.

Clock and pll hierarchy is completely different between S5PC100 and
S5PC110 SoCs, so move related includes to new sub-platform and rename
plat-s5pc1xx/clocks.c and plat-s5pc1xx/s5pc100-clock.c to
s5pc100-clocks.c (periperal clocks definition) and s5pc100-plls.c (core
pll hierarchy definition).

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>


---
 arch/arm/mach-s5pc100/cpu.c                        |    6 ++++++
 arch/arm/mach-s5pc100/include/mach/map.h           |    2 ++
 .../include/plat/regs-clock.h                      |    2 +-
 .../include/plat/regs-power.h                      |    2 +-
 arch/arm/plat-s5pc1xx/Makefile                     |    3 +--
 arch/arm/plat-s5pc1xx/cpu.c                        |   18 ++++++------------
 .../arm/plat-s5pc1xx/{clock.c => s5pc100-clocks.c} |    4 ++--
 .../{s5pc100-clock.c => s5pc100-plls.c}            |    2 +-
 8 files changed, 20 insertions(+), 19 deletions(-)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/include/plat/regs-clock.h (99%)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/include/plat/regs-power.h (98%)
 rename arch/arm/plat-s5pc1xx/{clock.c => s5pc100-clocks.c} (99%)
 rename arch/arm/plat-s5pc1xx/{s5pc100-clock.c => s5pc100-plls.c} (99%)

diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index d79e757..41fdecf 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -46,6 +46,12 @@
 /* Initial IO mappings */
 
 static struct map_desc s5pc100_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5PC1XX_VA_CLK_OTHER,
+		.pfn		= __phys_to_pfn(S5PC1XX_PA_CLK_OTHER),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}
 };
 
 static void s5pc100_idle(void)
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index f90c033..88f267a 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -46,6 +46,8 @@
 #define S5PC1XX_VA_CLK		(S3C_VA_SYS + 0x10000)
 #define S5PC1XX_VA_PWR		(S3C_VA_SYS + 0x20000)
 #define S5PC1XX_VA_CLK_OTHER	(S3C_VA_SYS + 0x30000)
+#define S5PC1XX_SZ_CLK		SZ_4K
+#define S5PC1XX_SZ_PWR		SZ_4K
 
 /* GPIO */
 #define S5PC100_PA_GPIO		(0xE0300000)
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/mach-s5pc100/include/plat/regs-clock.h
similarity index 99%
rename from arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
rename to arch/arm/mach-s5pc100/include/plat/regs-clock.h
index c5cc86e..f0a007b 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+++ b/arch/arm/mach-s5pc100/include/plat/regs-clock.h
@@ -3,7 +3,7 @@
  * Copyright 2009 Samsung Electronics Co.
  *	Byungho Min <bhmin@samsung.com>
  *
- * S5PC1XX clock register definitions
+ * S5PC100 clock register definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h b/arch/arm/mach-s5pc100/include/plat/regs-power.h
similarity index 98%
rename from arch/arm/plat-s5pc1xx/include/plat/regs-power.h
rename to arch/arm/mach-s5pc100/include/plat/regs-power.h
index 02ffa49..50a9679 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h
+++ b/arch/arm/mach-s5pc100/include/plat/regs-power.h
@@ -3,7 +3,7 @@
  * Copyright 2009 Samsung Electronics Co.
  *	Jongse Won <jongse.won@samsung.com>
  *
- * S5PC1XX clock register definitions
+ * S5PC100 power controll register definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
index 278f268..5da300e 100644
--- a/arch/arm/plat-s5pc1xx/Makefile
+++ b/arch/arm/plat-s5pc1xx/Makefile
@@ -14,13 +14,12 @@ obj-				:=
 obj-y				+= dev-uart.o
 obj-y				+= cpu.o
 obj-y				+= irq.o irq-gpio.o irq-eint.o
-obj-y				+= clock.o
 obj-y				+= gpiolib.o
 
 # CPU support
 
 obj-$(CONFIG_CPU_S5PC100_INIT)	+= s5pc100-init.o
-obj-$(CONFIG_CPU_S5PC100_CLOCK)	+= s5pc100-clock.o
+obj-$(CONFIG_CPU_S5PC100_CLOCK)	+= s5pc100-plls.o s5pc100-clocks.o
 
 # Device setup
 
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c
index 02baeaa..ecd6d38 100644
--- a/arch/arm/plat-s5pc1xx/cpu.c
+++ b/arch/arm/plat-s5pc1xx/cpu.c
@@ -50,18 +50,11 @@ static struct cpu_table cpu_ids[] __initdata = {
 };
 /* minimal IO mapping */
 
-/* see notes on uart map in arch/arm/mach-s5pc100/include/mach/debug-macro.S */
-#define UART_OFFS (S3C_PA_UART & 0xffff)
 
 static struct map_desc s5pc1xx_iodesc[] __initdata = {
 	{
-		.virtual	= (unsigned long)S5PC1XX_VA_CLK_OTHER,
-		.pfn		= __phys_to_pfn(S5PC1XX_PA_CLK_OTHER),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE,
-	}, {
 		.virtual	= (unsigned long)S5PC1XX_VA_GPIO,
-		.pfn		= __phys_to_pfn(S5PC100_PA_GPIO),
+		.pfn		= __phys_to_pfn(S5PC1XX_PA_GPIO),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
 	}, {
@@ -72,15 +65,15 @@ static struct map_desc s5pc1xx_iodesc[] __initdata = {
 	}, {
 		.virtual	= (unsigned long)S5PC1XX_VA_CLK,
 		.pfn		= __phys_to_pfn(S5PC1XX_PA_CLK),
-		.length		= SZ_4K,
+		.length		= S5PC1XX_SZ_CLK,
 		.type		= MT_DEVICE,
 	}, {
 		.virtual	= (unsigned long)S5PC1XX_VA_PWR,
 		.pfn		= __phys_to_pfn(S5PC1XX_PA_PWR),
-		.length		= SZ_4K,
+		.length		= S5PC1XX_SZ_PWR,
 		.type		= MT_DEVICE,
 	}, {
-		.virtual	= (unsigned long)(S5PC1XX_VA_UART),
+		.virtual	= (unsigned long)S5PC1XX_VA_UART,
 		.pfn		= __phys_to_pfn(S5PC1XX_PA_UART),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
@@ -115,8 +108,9 @@ void __init s5pc1xx_init_io(struct map_desc *mach_desc, int size)
 
 	/* initialise the io descriptors we need for initialisation */
 	iotable_init(s5pc1xx_iodesc, ARRAY_SIZE(s5pc1xx_iodesc));
-	iotable_init(mach_desc, size);
 
 	idcode = __raw_readl(S5PC1XX_VA_CHIPID);
 	s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
+
+	iotable_init(mach_desc, size);
 }
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clocks.c
similarity index 99%
rename from arch/arm/plat-s5pc1xx/clock.c
rename to arch/arm/plat-s5pc1xx/s5pc100-clocks.c
index 26c21d8..355e98a 100644
--- a/arch/arm/plat-s5pc1xx/clock.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-clocks.c
@@ -1,8 +1,8 @@
-/* linux/arch/arm/plat-s5pc1xx/clock.c
+/* linux/arch/arm/plat-s5pc100/s5pc100-clocks.c
  *
  * Copyright 2009 Samsung Electronics Co.
  *
- * S5PC1XX Base clock support
+ * S5PC100 - Clocks support
  *
  * Based on plat-s3c64xx/clock.c
  *
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-plls.c
similarity index 99%
rename from arch/arm/plat-s5pc1xx/s5pc100-clock.c
rename to arch/arm/plat-s5pc1xx/s5pc100-plls.c
index b436d44..e620bf2 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-plls.c
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+/* linux/arch/arm/plat-s5pc100/s5pc100-plls.c
  *
  * Copyright 2009 Samsung Electronics, Co.
  *	Byungho Min <bhmin@samsung.com>
-- 
1.6.4

[PATCH 04/19] ARM: S5PC1XX: prepare common gpiolib code for S5PC110 sub-platform

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

S5PC100 GPIO chip definitions has been hidden under sub-platform #ifdef
CONFIG_CPU_S5PC100. Also a new S5PC1XX_GPHx() macros has been introduced
to cover common external interrupt gpio lines (for common code).

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>


---
 arch/arm/mach-s5pc100/include/mach/gpio.h          |    7 ++++++
 .../include/plat/irqs.h                            |    2 +-
 .../include/plat/regs-gpio.h                       |    2 +-
 arch/arm/plat-s5pc1xx/gpiolib.c                    |   17 ++++++++++-----
 arch/arm/plat-s5pc1xx/irq-eint.c                   |   13 +++++------
 arch/arm/plat-s5pc1xx/irq-gpio.c                   |   22 ++++++++++++-------
 6 files changed, 40 insertions(+), 23 deletions(-)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/include/plat/irqs.h (99%)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/include/plat/regs-gpio.h (98%)

diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index 2c4cbe8..851577c 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -159,4 +159,11 @@ enum s3c_gpio_number {
 /* define the number of gpios we need to the one after the MP04() range */
 #define ARCH_NR_GPIOS		(S5PC100_GPIO_END + 1)
 
+/* Common compatibility defines */
+#define S5PC1XX_GPIO_EINT_SFN	S3C_GPIO_SFN(0x2)
+#define S5PC1XX_GPH0(n)		S5PC100_GPH0(n)
+#define S5PC1XX_GPH1(n)		S5PC100_GPH1(n)
+#define S5PC1XX_GPH2(n)		S5PC100_GPH2(n)
+#define S5PC1XX_GPH3(n)		S5PC100_GPH3(n)
+
 #include <asm-generic/gpio.h>
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/mach-s5pc100/include/plat/irqs.h
similarity index 99%
rename from arch/arm/plat-s5pc1xx/include/plat/irqs.h
rename to arch/arm/mach-s5pc100/include/plat/irqs.h
index ef87363..e34e2ef 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h
+++ b/arch/arm/mach-s5pc100/include/plat/irqs.h
@@ -3,7 +3,7 @@
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
- * S5PC1XX - Common IRQ support
+ * S5PC100 - Common IRQ support
  *
  * Based on plat-s3c64xx/include/plat/irqs.h
  */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h b/arch/arm/mach-s5pc100/include/plat/regs-gpio.h
similarity index 98%
rename from arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
rename to arch/arm/mach-s5pc100/include/plat/regs-gpio.h
index 43c7bc8..87e1884 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
+++ b/arch/arm/mach-s5pc100/include/plat/regs-gpio.h
@@ -3,7 +3,7 @@
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
- * S5PC1XX - GPIO register definitions
+ * S5PC100 - GPIO register definitions
  */
 
 #ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H
diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c
index facb410..60bf31d 100644
--- a/arch/arm/plat-s5pc1xx/gpiolib.c
+++ b/arch/arm/plat-s5pc1xx/gpiolib.c
@@ -138,18 +138,19 @@ static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
 {
 	int base;
 
-	base = chip->base - S5PC100_GPH0(0);
+	base = chip->base - S5PC1XX_GPH0(0);
 	if (base == 0)
 		return IRQ_EINT(offset);
-	base = chip->base - S5PC100_GPH1(0);
+	base = chip->base - S5PC1XX_GPH1(0);
 	if (base == 0)
 		return IRQ_EINT(8 + offset);
-	base = chip->base - S5PC100_GPH2(0);
+	base = chip->base - S5PC1XX_GPH2(0);
 	if (base == 0)
 		return IRQ_EINT(16 + offset);
-	base = chip->base - S5PC100_GPH3(0);
+	base = chip->base - S5PC1XX_GPH3(0);
 	if (base == 0)
 		return IRQ_EINT(24 + offset);
+
 	return -EINVAL;
 }
 
@@ -172,6 +173,7 @@ static struct s3c_gpio_cfg gpio_cfg_noint = {
 	.get_pull	= s3c_gpio_getpull_updown,
 };
 
+#ifdef CONFIG_CPU_S5PC100
 static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 	{
 		.base	= S5PC100_GPA0_BASE,
@@ -448,6 +450,9 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 	},
 };
 
+#define s5pc1xx_gpio_chips s5pc100_gpio_chips
+
+#endif
 /* FIXME move from irq-gpio.c */
 extern struct irq_chip s5pc1xx_gpioint;
 extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
@@ -491,8 +496,8 @@ static __init int s5pc1xx_gpiolib_init(void)
 	struct s3c_gpio_chip *chips;
 	int nr_chips;
 
-		chips = s5pc100_gpio_chips;
-		nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
+	chips = s5pc1xx_gpio_chips;
+	nr_chips = ARRAY_SIZE(s5pc1xx_gpio_chips);
 
 	s5pc1xx_gpiolib_add(chips, nr_chips, s5pc1xx_gpiolib_link);
 	/* Interrupt */
diff --git a/arch/arm/plat-s5pc1xx/irq-eint.c b/arch/arm/plat-s5pc1xx/irq-eint.c
index 373122f..9e8bc12 100644
--- a/arch/arm/plat-s5pc1xx/irq-eint.c
+++ b/arch/arm/plat-s5pc1xx/irq-eint.c
@@ -105,7 +105,7 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
 {
 	u32 bank = s3c_get_bank(irq);
 	int real = s3c_get_eint(irq);
-	int gpio, shift, sfn;
+	int gpio, shift;
 	u32 ctrl, con = 0;
 
 	switch (type) {
@@ -148,23 +148,22 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
 
 	switch (real) {
 	case 0 ... 7:
-			gpio = S5PC100_GPH0(gpio);
+		gpio = S5PC1XX_GPH0(gpio);
 		break;
 	case 8 ... 15:
-			gpio = S5PC100_GPH1(gpio);
+		gpio = S5PC1XX_GPH1(gpio);
 		break;
 	case 16 ... 23:
-			gpio = S5PC100_GPH2(gpio);
+		gpio = S5PC1XX_GPH2(gpio);
 		break;
 	case 24 ... 31:
-			gpio = S5PC100_GPH3(gpio);
+		gpio = S5PC1XX_GPH3(gpio);
 		break;
 	default:
 		return -EINVAL;
 	}
 
-	sfn = S3C_GPIO_SFN(0x2);
-	s3c_gpio_cfgpin(gpio, sfn);
+	s3c_gpio_cfgpin(gpio, S5PC1XX_GPIO_EINT_SFN);
 
 	return 0;
 }
diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/plat-s5pc1xx/irq-gpio.c
index fecca7a..f5d8dab 100644
--- a/arch/arm/plat-s5pc1xx/irq-gpio.c
+++ b/arch/arm/plat-s5pc1xx/irq-gpio.c
@@ -49,7 +49,9 @@ static int group_to_pend_offset(int group)
 	return group << 2;
 }
 
-static int s5pc1xx_get_start(unsigned int group)
+#ifdef CONFIG_CPU_S5PC100
+
+static int s5pc100_get_start(unsigned int group)
 {
 	switch (group) {
 	case 0: return S5PC100_GPIO_A0_START;
@@ -76,11 +78,10 @@ static int s5pc1xx_get_start(unsigned int group)
 	default:
 		BUG();
 	}
-
 	return -EINVAL;
 }
 
-static int s5pc1xx_get_group(unsigned int irq)
+static int s5pc100_get_group(unsigned int irq)
 {
 	irq -= S3C_IRQ_GPIO(0);
 
@@ -130,10 +131,17 @@ static int s5pc1xx_get_group(unsigned int irq)
 	default:
 		BUG();
 	}
-
 	return -EINVAL;
 }
 
+static int s5pc100_group_end = 21;
+
+#define s5pc1xx_get_group s5pc100_get_group
+#define s5pc1xx_get_start s5pc100_get_start
+#define s5pc1xx_group_end s5pc100_group_end
+
+#endif
+
 static int s5pc1xx_get_offset(unsigned int irq)
 {
 	struct gpio_chip *chip = get_irq_data(irq);
@@ -241,12 +249,10 @@ struct irq_chip s5pc1xx_gpioint = {
 void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
 {
 	int group, offset, pend_offset, mask_offset;
-	int real_irq, group_end;
+	int real_irq;
 	unsigned int pend, mask;
 
-	group_end = 21;
-
-	for (group = 0; group < group_end; group++) {
+	for (group = 0; group < s5pc1xx_group_end; group++) {
 		pend_offset = group_to_pend_offset(group);
 		pend = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
 		if (!pend)
-- 
1.6.4

[PATCH 05/19] ARM: S5PC1XX: move common s5pc1xx mach/* includes to plat-s5pc1xx/include/mach

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

All includes that are common for S5PC100 and S5PC110 are moved to
plat-s5pc1xx/include/mach, so they can be used by both sub-platforms.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 .../include/mach/gpio-core.h                       |    2 +-
 .../include/mach/hardware.h                        |    2 +-
 .../include/mach/irqs.h                            |    2 +-
 .../include/mach/memory.h                          |    2 +-
 .../include/mach/pwm-clock.h                       |    2 +-
 .../include/mach/tick.h                            |    2 +-
 .../include/mach/uncompress.h                      |    2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)
 rename arch/arm/{mach-s5pc100 => plat-s5pc1xx}/include/mach/gpio-core.h (91%)
 rename arch/arm/{mach-s5pc100 => plat-s5pc1xx}/include/mach/hardware.h (83%)
 rename arch/arm/{mach-s5pc100 => plat-s5pc1xx}/include/mach/irqs.h (87%)
 rename arch/arm/{mach-s5pc100 => plat-s5pc1xx}/include/mach/memory.h (89%)
 rename arch/arm/{mach-s5pc100 => plat-s5pc1xx}/include/mach/pwm-clock.h (96%)
 rename arch/arm/{mach-s5pc100 => plat-s5pc1xx}/include/mach/tick.h (93%)
 rename arch/arm/{mach-s5pc100 => plat-s5pc1xx}/include/mach/uncompress.h (92%)

diff --git a/arch/arm/mach-s5pc100/include/mach/gpio-core.h b/arch/arm/plat-s5pc1xx/include/mach/gpio-core.h
similarity index 91%
rename from arch/arm/mach-s5pc100/include/mach/gpio-core.h
rename to arch/arm/plat-s5pc1xx/include/mach/gpio-core.h
index ad28d8e..6364800 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio-core.h
+++ b/arch/arm/plat-s5pc1xx/include/mach/gpio-core.h
@@ -1,4 +1,4 @@
-/* arch/arm/mach-s5pc100/include/mach/gpio-core.h
+/* arch/arm/plat-s5pc1xx/include/mach/gpio-core.h
  *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
diff --git a/arch/arm/mach-s5pc100/include/mach/hardware.h b/arch/arm/plat-s5pc1xx/include/mach/hardware.h
similarity index 83%
rename from arch/arm/mach-s5pc100/include/mach/hardware.h
rename to arch/arm/plat-s5pc1xx/include/mach/hardware.h
index 6b38618..c47affb 100644
--- a/arch/arm/mach-s5pc100/include/mach/hardware.h
+++ b/arch/arm/plat-s5pc1xx/include/mach/hardware.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/hardware.h
+/* linux/arch/arm/plat-s5pc1xx/include/mach/hardware.h
  *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/plat-s5pc1xx/include/mach/irqs.h
similarity index 87%
rename from arch/arm/mach-s5pc100/include/mach/irqs.h
rename to arch/arm/plat-s5pc1xx/include/mach/irqs.h
index b53fa48..198cff8 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/plat-s5pc1xx/include/mach/irqs.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/irqs.h
+/* linux/arch/arm/plat-s5pc1xx/include/mach/irqs.h
  *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
diff --git a/arch/arm/mach-s5pc100/include/mach/memory.h b/arch/arm/plat-s5pc1xx/include/mach/memory.h
similarity index 89%
rename from arch/arm/mach-s5pc100/include/mach/memory.h
rename to arch/arm/plat-s5pc1xx/include/mach/memory.h
index 21cc182..d378f45 100644
--- a/arch/arm/mach-s5pc100/include/mach/memory.h
+++ b/arch/arm/plat-s5pc1xx/include/mach/memory.h
@@ -1,4 +1,4 @@
-/* arch/arm/mach-s5pc100/include/mach/memory.h
+/* linux/arch/arm/plat-s5pc1xx/include/mach/memory.h
  *
  * Copyright 2008 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
diff --git a/arch/arm/mach-s5pc100/include/mach/pwm-clock.h b/arch/arm/plat-s5pc1xx/include/mach/pwm-clock.h
similarity index 96%
rename from arch/arm/mach-s5pc100/include/mach/pwm-clock.h
rename to arch/arm/plat-s5pc1xx/include/mach/pwm-clock.h
index b34d2f7..09a2834 100644
--- a/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
+++ b/arch/arm/plat-s5pc1xx/include/mach/pwm-clock.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
+/* linux/arch/arm/plat-s5pc1xx/include/mach/pwm-clock.h
  *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/plat-s5pc1xx/include/mach/tick.h
similarity index 93%
rename from arch/arm/mach-s5pc100/include/mach/tick.h
rename to arch/arm/plat-s5pc1xx/include/mach/tick.h
index d3de0f3..e43d1fd 100644
--- a/arch/arm/mach-s5pc100/include/mach/tick.h
+++ b/arch/arm/plat-s5pc1xx/include/mach/tick.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/tick.h
+/* linux/arch/arm/plat-s5pc1xx/include/mach/tick.h
  *
  * Copyright 2009 Samsung Electronics Co.
  *	Byungho Min <bhmin@samsung.com>
diff --git a/arch/arm/mach-s5pc100/include/mach/uncompress.h b/arch/arm/plat-s5pc1xx/include/mach/uncompress.h
similarity index 92%
rename from arch/arm/mach-s5pc100/include/mach/uncompress.h
rename to arch/arm/plat-s5pc1xx/include/mach/uncompress.h
index 01ccf53..e9ee0be 100644
--- a/arch/arm/mach-s5pc100/include/mach/uncompress.h
+++ b/arch/arm/plat-s5pc1xx/include/mach/uncompress.h
@@ -1,4 +1,4 @@
-/* arch/arm/mach-s5pc100/include/mach/uncompress.h
+/* linux/arch/arm/plat-s5pc1xx/include/mach/uncompress.h
  *
  * Copyright 2009 Samsung Electronics Co.
  *	Byungho Min <bhmin@samsung.com>
-- 
1.6.4

[PATCH 06/19] ARM: S5PC1XX: cleanup of s5pc1xx common code

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

This patch removes all useless definitions from plat/s5pc100.h and
introduces new common plat/s5pc1xx.h include.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 arch/arm/mach-s5pc100/cpu.c                     |    2 +-
 arch/arm/mach-s5pc100/include/plat/regs-clock.h |    8 ++--
 arch/arm/mach-s5pc100/mach-smdkc100.c           |    2 +-
 arch/arm/plat-s5pc1xx/cpu.c                     |    2 +-
 arch/arm/plat-s5pc1xx/include/plat/s5pc100.h    |   51 ++++++-----------------
 arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h    |   21 +++++++++
 arch/arm/plat-s5pc1xx/s5pc100-init.c            |    7 ++-
 arch/arm/plat-s5pc1xx/s5pc100-plls.c            |    2 +-
 8 files changed, 46 insertions(+), 49 deletions(-)
 create mode 100644 arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h

diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index 41fdecf..f383e33 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -41,7 +41,7 @@
 #include <plat/clock.h>
 #include <plat/sdhci.h>
 #include <plat/iic-core.h>
-#include <plat/s5pc100.h>
+#include <plat/s5pc1xx.h>
 
 /* Initial IO mappings */
 
diff --git a/arch/arm/mach-s5pc100/include/plat/regs-clock.h b/arch/arm/mach-s5pc100/include/plat/regs-clock.h
index f0a007b..637ff71 100644
--- a/arch/arm/mach-s5pc100/include/plat/regs-clock.h
+++ b/arch/arm/mach-s5pc100/include/plat/regs-clock.h
@@ -341,10 +341,10 @@
 #define S5PC100_HDMI_PHY_CON0	S5PC100_CLKREG_OTHER(0x420)
 
 #define S5PC100_SWRESET_RESETVAL	0xc100
-#define S5PC100_OTHER_SYS_INT	24
-#define S5PC100_OTHER_STA_TYPE	23
-#define STA_TYPE_EXPON		0
-#define STA_TYPE_SFR		1
+#define S5PC100_OTHERS_PMU_INT_DISALBE		(1 << 24)
+#define S5PC100_OTHERS_STABLE_COUNTER_TYPE_MASK	(1 << 23)
+#define S5PC100_OTHERS_STABLE_COUNTER_TYPE_SFR	(1 << 23)
+#define S5PC100_OTHERS_STABLE_COUNTER_TYPE_EXP	(0 << 23)
 
 #define S5PC100_SLEEP_CFG_OSC_EN	0
 
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index ae3c52c..29b95f1 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -40,7 +40,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/s5pc100.h>
+#include <plat/s5pc1xx.h>
 #include <plat/fb.h>
 #include <plat/iic.h>
 
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c
index ecd6d38..d30998d 100644
--- a/arch/arm/plat-s5pc1xx/cpu.c
+++ b/arch/arm/plat-s5pc1xx/cpu.c
@@ -31,7 +31,7 @@
 #include <plat/devs.h>
 #include <plat/clock.h>
 
-#include <plat/s5pc100.h>
+#include <plat/s5pc1xx.h>
 
 /* table of supported CPUs */
 
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
index 2531f34..32eb6e7 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
@@ -13,52 +13,27 @@
 */
 
 /* Common init code for S5PC100 related SoCs */
+
+#ifdef CONFIG_CPU_S5PC100
+
 extern  int s5pc100_init(void);
 extern void s5pc100_map_io(void);
 extern void s5pc100_init_clocks(int xtal);
 extern  int s5pc100_register_baseclocks(unsigned long xtal);
 extern void s5pc100_init_irq(void);
 extern void s5pc100_init_io(struct map_desc *mach_desc, int size);
-extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s5pc100_register_clocks(void);
 extern void s5pc100_setup_clocks(void);
-extern struct sysdev_class s5pc100_sysclass;
-
-#define s5pc100_init_uarts s5pc100_common_init_uarts
-
-/* Some day, belows will be moved to plat-s5pc/include/plat/cpu.h */
-extern void s5pc1xx_init_irq(u32 *vic_valid, int num);
-extern void s5pc1xx_init_io(struct map_desc *mach_desc, int size);
-
-/* Some day, belows will be moved to plat-s5pc/include/plat/clock.h */
-extern struct clk clk_hpll;
-extern struct clk clk_hd0;
-extern struct clk clk_pd0;
+extern  int s5pc100_sclk0_ctrl(struct clk *clk, int enable);
+extern  int s5pc100_sclk1_ctrl(struct clk *clk, int enable);
 extern struct clk clk_54m;
-extern void s5pc1xx_register_clocks(void);
-extern int s5pc100_sclk0_ctrl(struct clk *clk, int enable);
-extern int s5pc100_sclk1_ctrl(struct clk *clk, int enable);
 
-/* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */
-extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
-extern struct platform_device s3c_device_g2d;
-extern struct platform_device s3c_device_g3d;
-extern struct platform_device s3c_device_vpp;
-extern struct platform_device s3c_device_tvenc;
-extern struct platform_device s3c_device_tvscaler;
-extern struct platform_device s3c_device_rotator;
-extern struct platform_device s3c_device_jpeg;
-extern struct platform_device s3c_device_onenand;
-extern struct platform_device s3c_device_usb_otghcd;
-extern struct platform_device s3c_device_keypad;
-extern struct platform_device s3c_device_ts;
-extern struct platform_device s3c_device_g3d;
-extern struct platform_device s3c_device_smc911x;
-extern struct platform_device s3c_device_fimc0;
-extern struct platform_device s3c_device_fimc1;
-extern struct platform_device s3c_device_mfc;
-extern struct platform_device s3c_device_ac97;
-extern struct platform_device s3c_device_fimc0;
-extern struct platform_device s3c_device_fimc1;
-extern struct platform_device s3c_device_fimc2;
+#else
+
+#define s5pc100_map_io NULL
+#define s5pc100_init_clocks NULL
+#define s5pc100_init_uarts NULL
+#define s5pc100_init NULL
 
+#endif
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h
new file mode 100644
index 0000000..398251f
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h
@@ -0,0 +1,21 @@
+/* arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Marek Szyprowski <m.szyprowski@samsung.com>
+ *
+ * Header file for s5pc1xx cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for S5PC1XX related SoCs */
+
+extern void s5pc1xx_init_irq(u32 *vic_valid, int num);
+extern void s5pc1xx_init_io(struct map_desc *mach_desc, int size);
+extern void s5pc1xx_register_clocks(void);
+
+extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
+
+#include <plat/s5pc100.h>
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-init.c b/arch/arm/plat-s5pc1xx/s5pc100-init.c
index c587108..24b57b9 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-init.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-init.c
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5pc1xx/s5pc100-init.c
+/* linux/arch/arm/plat-s5pc100/s5pc100-init.c
  *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
@@ -13,14 +13,15 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/init.h>
+#include <linux/clk.h>
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/s5pc100.h>
+#include <plat/s5pc1xx.h>
 
 /* uart registration process */
 
-void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
 	/* The driver name is s3c6400-uart to reuse s3c6400_serial_drv  */
 	s3c24xx_init_uartdevs("s3c6400-uart", s5pc1xx_uart_resources, cfg, no);
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-plls.c b/arch/arm/plat-s5pc1xx/s5pc100-plls.c
index e620bf2..45f073e 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-plls.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-plls.c
@@ -32,7 +32,7 @@
 #include <plat/cpu.h>
 #include <plat/pll.h>
 #include <plat/devs.h>
-#include <plat/s5pc100.h>
+#include <plat/s5pc1xx.h>
 
 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
  * ext_xtal_mux for want of an actual name from the manual.
-- 
1.6.4

[PATCH 07/19] ARM: S5PC1XX: move s5pc100 specific device helpers to mach-s5pc100 dir

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

All device helpers that are defined in plat-s5pc1xx are S5PC100
specific. This patch moves them to mach-s5pc100 directory to make use of
newly created sub-platform support.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 arch/arm/mach-s5pc100/Kconfig                      |   32 +++++++++++++++++--
 arch/arm/mach-s5pc100/Makefile                     |    4 ++
 .../setup-fb-24bpp.c                               |    0
 .../{plat-s5pc1xx => mach-s5pc100}/setup-i2c0.c    |    0
 .../{plat-s5pc1xx => mach-s5pc100}/setup-i2c1.c    |    0
 .../setup-sdhci-gpio.c                             |    0
 arch/arm/plat-s5pc1xx/Kconfig                      |   24 ---------------
 arch/arm/plat-s5pc1xx/Makefile                     |    4 --
 8 files changed, 32 insertions(+), 32 deletions(-)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/setup-fb-24bpp.c (100%)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/setup-i2c0.c (100%)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/setup-i2c1.c (100%)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/setup-sdhci-gpio.c (100%)

diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index d72f881..7f73353 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -16,12 +16,36 @@ config CPU_S5PC100
 	help
 	  Enable S5PC100 CPU support
 
+config S5PC100_SETUP_FB_24BPP
+	bool
+	help
+          Common setup code for S5PC1XX with an 24bpp RGB display helper.
+
+config S5PC100_SETUP_I2C0
+	bool
+	default y
+	help
+	  Common setup code for i2c bus 0.
+
+	  Note, currently since i2c0 is always compiled, this setup helper
+	  is always compiled with it.
+
+config S5PC100_SETUP_I2C1
+	bool
+	help
+	  Common setup code for i2c bus 1.
+
 config S5PC100_SETUP_SDHCI
         bool
-        select S5PC1XX_SETUP_SDHCI_GPIO
+        select S5PC100_SETUP_SDHCI_GPIO
         help
           Internal helper functions for S5PC100 based SDHCI systems
 
+config S5PC100_SETUP_SDHCI_GPIO
+	bool
+	help
+	  Common setup code for SDHCI gpio.
+
 config MACH_SMDKC100
 	bool "SMDKC100"
 	select CPU_S5PC100
@@ -30,9 +54,9 @@ config MACH_SMDKC100
 	select S3C_DEV_HSMMC
 	select S3C_DEV_HSMMC1
 	select S3C_DEV_HSMMC2
-	select S5PC1XX_SETUP_I2C0
-	select S5PC1XX_SETUP_I2C1
-	select S5PC1XX_SETUP_FB_24BPP
+	select S5PC100_SETUP_I2C0
+	select S5PC100_SETUP_I2C1
+	select S5PC100_SETUP_FB_24BPP
 	select S5PC100_SETUP_SDHCI
 	help
 	  Machine support for the Samsung SMDKC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 809ff10..8846169 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -15,7 +15,11 @@ obj-$(CONFIG_CPU_S5PC100)	+= cpu.o
 
 # Helper and device support
 
+obj-$(CONFIG_S5PC100_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
+obj-$(CONFIG_S5PC100_SETUP_I2C0)	+= setup-i2c0.o
+obj-$(CONFIG_S5PC100_SETUP_I2C1)	+= setup-i2c1.o
 obj-$(CONFIG_S5PC100_SETUP_SDHCI)       += setup-sdhci.o
+obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
 
 # machine support
 obj-$(CONFIG_MACH_SMDKC100)	+= mach-smdkc100.o
diff --git a/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
similarity index 100%
rename from arch/arm/plat-s5pc1xx/setup-fb-24bpp.c
rename to arch/arm/mach-s5pc100/setup-fb-24bpp.c
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c
similarity index 100%
rename from arch/arm/plat-s5pc1xx/setup-i2c0.c
rename to arch/arm/mach-s5pc100/setup-i2c0.c
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c
similarity index 100%
rename from arch/arm/plat-s5pc1xx/setup-i2c1.c
rename to arch/arm/mach-s5pc100/setup-i2c1.c
diff --git a/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
similarity index 100%
rename from arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
rename to arch/arm/mach-s5pc100/setup-sdhci-gpio.c
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index eee2abb..9f76a9b 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -47,28 +47,4 @@ config CPU_S5PC100_CLOCK
 
 # platform specific device setup
 
-config S5PC1XX_SETUP_FB_24BPP
-	bool
-	help
-          Common setup code for S5PC1XX with an 24bpp RGB display helper.
-
-config S5PC1XX_SETUP_I2C0
-	bool
-	default y
-	help
-	  Common setup code for i2c bus 0.
-
-	  Note, currently since i2c0 is always compiled, this setup helper
-	  is always compiled with it.
-
-config S5PC1XX_SETUP_I2C1
-	bool
-	help
-	  Common setup code for i2c bus 1.
-
-config S5PC1XX_SETUP_SDHCI_GPIO
-	bool
-	help
-	  Common setup code for SDHCI gpio.
-
 endif
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
index 5da300e..cc06606 100644
--- a/arch/arm/plat-s5pc1xx/Makefile
+++ b/arch/arm/plat-s5pc1xx/Makefile
@@ -24,7 +24,3 @@ obj-$(CONFIG_CPU_S5PC100_CLOCK)	+= s5pc100-plls.o s5pc100-clocks.o
 # Device setup
 
 obj-$(CONFIG_S5P_GPIO_CFG_S5PC1XX) += gpio-config.o
-obj-$(CONFIG_S5PC1XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
-obj-$(CONFIG_S5PC1XX_SETUP_I2C0) += setup-i2c0.o
-obj-$(CONFIG_S5PC1XX_SETUP_I2C1) += setup-i2c1.o
-obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
-- 
1.6.4

[PATCH 08/19] ARM: S5PC1XX: move common s5pc1xx s3c-fb regs to platform directory

[Marek Szyprowski]

From: Pawel Osciak <p.osciak@samsung.com>

From: Pawel Osciak <p.osciak@samsung.com>

Frame buffer register block on S5PC100 and S5PC110 differs slightly.
This patch moves all register definitions that are common for S5PC100
and S5PC110 to plat-s3c/plat/regs-fb-v5.h.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 arch/arm/mach-s5pc100/include/mach/regs-fb.h |  133 ++-----------------------
 arch/arm/plat-s3c/include/plat/regs-fb-v5.h  |  138 ++++++++++++++++++++++++++
 2 files changed, 146 insertions(+), 125 deletions(-)
 create mode 100644 arch/arm/plat-s3c/include/plat/regs-fb-v5.h

diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
index 1732cd2..49764cb 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-fb.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
@@ -1,139 +1,22 @@
-/* arch/arm/mach-s5pc100/include/mach/regs-fb.h
- *
+/*
  * Copyright 2009 Samsung Electronics Co.
  *   Pawel Osciak <p.osciak@samsung.com>
  *
- * Framebuffer register definitions for Samsung S5PC100.
+ * Machine-specific framebuffer definitions for Samsung S5PC100.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_FB_H
-#define __ASM_ARCH_REGS_FB_H __FILE__
-
-#include <plat/regs-fb-v4.h>
-
-/* VP1 interface timing control */
-#define VP1CON0						(0x118)
-#define VP1_RATECON_EN					(1 << 31)
-#define VP1_CLKRATE_MASK				(0xff)
-
-#define VP1CON1						(0x11c)
-#define VP1_VTREGCON_EN					(1 << 31)
-#define VP1_VBPD_MASK					(0xfff)
-#define VP1_VBPD_SHIFT					(16)
-
-
-#define WPALCON_H					(0x19c)
-#define WPALCON_L					(0x1a0)
-
-/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but
- * different for WPAL2-4
- */
-/* In WPALCON_L (aka WPALCON) */
-#define WPALCON_W1PAL_32BPP_A888			(0x7 << 3)
-#define WPALCON_W0PAL_32BPP_A888			(0x7 << 0)
-
-/* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H,
- * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]).
- */
-#define WPALCON_L_WxPAL_L_MASK				(0x1)
-#define WPALCON_L_W2PAL_L_SHIFT				(6)
-#define WPALCON_L_W3PAL_L_SHIFT				(7)
-#define WPALCON_L_W4PAL_L_SHIFT				(8)
-
-#define WPALCON_L_WxPAL_H_MASK				(0x3)
-#define WPALCON_H_W2PAL_H_SHIFT				(9)
-#define WPALCON_H_W3PAL_H_SHIFT				(13)
-#define WPALCON_H_W4PAL_H_SHIFT				(17)
-
-/* Per-window alpha value registers */
-/* For window 0 8-bit alpha values are in VIDW0ALPHAx,
- * for windows 1-4 alpha values consist of two parts, the 4 low bits are
- * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC,
- * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0])
- */
-#define VIDWxALPHA0(_win)				(0x200 + (_win * 8))
-#define VIDWxALPHA1(_win)				(0x204 + (_win * 8))
-
-/* Only for window 0 in VIDW0ALPHAx. */
-#define VIDW0ALPHAx_R(_x)				((_x) << 16)
-#define VIDW0ALPHAx_R_MASK				(0xff << 16)
-#define VIDW0ALPHAx_R_SHIFT				(16)
-#define VIDW0ALPHAx_G(_x)				((_x) << 8)
-#define VIDW0ALPHAx_G_MASK				(0xff << 8)
-#define VIDW0ALPHAx_G_SHIFT				(8)
-#define VIDW0ALPHAx_B(_x)				((_x) << 0)
-#define VIDW0ALPHAx_B_MASK				(0xff << 0)
-#define VIDW0ALPHAx_B_SHIFT				(0)
-
-/* Low 4 bits of alpha0-1 for windows 1-4 */
-#define VIDW14ALPHAx_R_L(_x)				((_x) << 16)
-#define VIDW14ALPHAx_R_L_MASK				(0xf << 16)
-#define VIDW14ALPHAx_R_L_SHIFT				(16)
-#define VIDW14ALPHAx_G_L(_x)				((_x) << 8)
-#define VIDW14ALPHAx_G_L_MASK				(0xf << 8)
-#define VIDW14ALPHAx_G_L_SHIFT				(8)
-#define VIDW14ALPHAx_B_L(_x)				((_x) << 0)
-#define VIDW14ALPHAx_B_L_MASK				(0xf << 0)
-#define VIDW14ALPHAx_B_L_SHIFT				(0)
-
-
-/* Per-window blending equation control registers */
-#define BLENDEQx(_win)					(0x244 + ((_win) * 4))
-#define BLENDEQ1					(0x244)
-#define BLENDEQ2					(0x248)
-#define BLENDEQ3					(0x24c)
-#define BLENDEQ4					(0x250)
-
-#define BLENDEQx_Q_FUNC(_x)				((_x) << 18)
-#define BLENDEQx_Q_FUNC_MASK				(0xf << 18)
-#define BLENDEQx_P_FUNC(_x)				((_x) << 12)
-#define BLENDEQx_P_FUNC_MASK				(0xf << 12)
-#define BLENDEQx_B_FUNC(_x)				((_x) << 6)
-#define BLENDEQx_B_FUNC_MASK				(0xf << 6)
-#define BLENDEQx_A_FUNC(_x)				((_x) << 0)
-#define BLENDEQx_A_FUNC_MASK				(0xf << 0)
-
-#define BLENDCON					(0x260)
-#define BLENDCON_8BIT_ALPHA				(1 << 0)
-
-/* Per-window palette base addresses (start of palette memory).
- * Each window palette area consists of 256 32-bit entries.
- * START is the first address (entry 0th), END is the address of 255th entry.
  */
-#define WIN0_PAL_BASE					(0x2400)
-#define WIN0_PAL_END					(0x27fc)
-#define WIN1_PAL_BASE					(0x2800)
-#define WIN1_PAL_END					(0x2bfc)
-#define WIN2_PAL_BASE					(0x2c00)
-#define WIN2_PAL_END					(0x2ffc)
-#define WIN3_PAL_BASE					(0x3000)
-#define WIN3_PAL_END					(0x33fc)
-#define WIN4_PAL_BASE					(0x3400)
-#define WIN4_PAL_END					(0x37fc)
 
-#define WIN0_PAL(_entry)			(WIN0_PAL_BASE + ((_entry) * 4))
-#define WIN1_PAL(_entry)			(WIN1_PAL_BASE + ((_entry) * 4))
-#define WIN2_PAL(_entry)			(WIN2_PAL_BASE + ((_entry) * 4))
-#define WIN3_PAL(_entry)			(WIN3_PAL_BASE + ((_entry) * 4))
-#define WIN4_PAL(_entry)			(WIN4_PAL_BASE + ((_entry) * 4))
+#ifndef __ASM_ARCH_MACH_REGS_FB_H
+#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
 
-static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
-{
-	switch (window) {
-	case 0: return WIN0_PAL(reg);
-	case 1: return WIN1_PAL(reg);
-	case 2: return WIN2_PAL(reg);
-	case 3: return WIN3_PAL(reg);
-	case 4: return WIN4_PAL(reg);
-	}
+#include <plat/regs-fb-v5.h>
 
-	BUG();
-}
+#define PRTCON						(0xc)
+#define PRTCON_PROTECT					(1 << 11)
 
 
-#endif /* __ASM_ARCH_REGS_FB_H */
+#endif /* __ASM_ARCH_MACH_REGS_FB_H */
 
diff --git a/arch/arm/plat-s3c/include/plat/regs-fb-v5.h b/arch/arm/plat-s3c/include/plat/regs-fb-v5.h
new file mode 100644
index 0000000..198c7f5
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-fb-v5.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright 2009 Samsung Electronics Co.
+ *   Pawel Osciak <p.osciak@samsung.com>
+ *
+ * Framebuffer register definitions for Samsung S5PC1xx.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_REGS_FB_V5_H
+#define __ASM_ARCH_REGS_FB_V5_H __FILE__
+
+#include <plat/regs-fb-v4.h>
+
+/* VP1 interface timing control */
+#define VP1CON0						(0x118)
+#define VP1_RATECON_EN					(1 << 31)
+#define VP1_CLKRATE_MASK				(0xff)
+
+#define VP1CON1						(0x11c)
+#define VP1_VTREGCON_EN					(1 << 31)
+#define VP1_VBPD_MASK					(0xfff)
+#define VP1_VBPD_SHIFT					(16)
+
+
+#define WPALCON_H					(0x19c)
+#define WPALCON_L					(0x1a0)
+
+/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but
+ * different for WPAL2-4
+ */
+/* In WPALCON_L (aka WPALCON) */
+#define WPALCON_W1PAL_32BPP_A888			(0x7 << 3)
+#define WPALCON_W0PAL_32BPP_A888			(0x7 << 0)
+
+/* W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H,
+ * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]).
+ */
+#define WPALCON_L_WxPAL_L_MASK				(0x1)
+#define WPALCON_L_W2PAL_L_SHIFT				(6)
+#define WPALCON_L_W3PAL_L_SHIFT				(7)
+#define WPALCON_L_W4PAL_L_SHIFT				(8)
+
+#define WPALCON_L_WxPAL_H_MASK				(0x3)
+#define WPALCON_H_W2PAL_H_SHIFT				(9)
+#define WPALCON_H_W3PAL_H_SHIFT				(13)
+#define WPALCON_H_W4PAL_H_SHIFT				(17)
+
+/* Per-window alpha value registers */
+/* For window 0 8-bit alpha values are in VIDW0ALPHAx,
+ * for windows 1-4 alpha values consist of two parts, the 4 low bits are
+ * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC,
+ * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0])
+ */
+#define VIDWxALPHA0(_win)				(0x200 + (_win * 8))
+#define VIDWxALPHA1(_win)				(0x204 + (_win * 8))
+
+/* Only for window 0 in VIDW0ALPHAx. */
+#define VIDW0ALPHAx_R(_x)				((_x) << 16)
+#define VIDW0ALPHAx_R_MASK				(0xff << 16)
+#define VIDW0ALPHAx_R_SHIFT				(16)
+#define VIDW0ALPHAx_G(_x)				((_x) << 8)
+#define VIDW0ALPHAx_G_MASK				(0xff << 8)
+#define VIDW0ALPHAx_G_SHIFT				(8)
+#define VIDW0ALPHAx_B(_x)				((_x) << 0)
+#define VIDW0ALPHAx_B_MASK				(0xff << 0)
+#define VIDW0ALPHAx_B_SHIFT				(0)
+
+/* Low 4 bits of alpha0-1 for windows 1-4 */
+#define VIDW14ALPHAx_R_L(_x)				((_x) << 16)
+#define VIDW14ALPHAx_R_L_MASK				(0xf << 16)
+#define VIDW14ALPHAx_R_L_SHIFT				(16)
+#define VIDW14ALPHAx_G_L(_x)				((_x) << 8)
+#define VIDW14ALPHAx_G_L_MASK				(0xf << 8)
+#define VIDW14ALPHAx_G_L_SHIFT				(8)
+#define VIDW14ALPHAx_B_L(_x)				((_x) << 0)
+#define VIDW14ALPHAx_B_L_MASK				(0xf << 0)
+#define VIDW14ALPHAx_B_L_SHIFT				(0)
+
+
+/* Per-window blending equation control registers */
+#define BLENDEQx(_win)					(0x244 + ((_win) * 4))
+#define BLENDEQ1					(0x244)
+#define BLENDEQ2					(0x248)
+#define BLENDEQ3					(0x24c)
+#define BLENDEQ4					(0x250)
+
+#define BLENDEQx_Q_FUNC(_x)				((_x) << 18)
+#define BLENDEQx_Q_FUNC_MASK				(0xf << 18)
+#define BLENDEQx_P_FUNC(_x)				((_x) << 12)
+#define BLENDEQx_P_FUNC_MASK				(0xf << 12)
+#define BLENDEQx_B_FUNC(_x)				((_x) << 6)
+#define BLENDEQx_B_FUNC_MASK				(0xf << 6)
+#define BLENDEQx_A_FUNC(_x)				((_x) << 0)
+#define BLENDEQx_A_FUNC_MASK				(0xf << 0)
+
+#define BLENDCON					(0x260)
+#define BLENDCON_8BIT_ALPHA				(1 << 0)
+
+/* Per-window palette base addresses (start of palette memory).
+ * Each window palette area consists of 256 32-bit entries.
+ * START is the first address (entry 0th), END is the address of 255th entry.
+ */
+#define WIN0_PAL_BASE					(0x2400)
+#define WIN0_PAL_END					(0x27fc)
+#define WIN1_PAL_BASE					(0x2800)
+#define WIN1_PAL_END					(0x2bfc)
+#define WIN2_PAL_BASE					(0x2c00)
+#define WIN2_PAL_END					(0x2ffc)
+#define WIN3_PAL_BASE					(0x3000)
+#define WIN3_PAL_END					(0x33fc)
+#define WIN4_PAL_BASE					(0x3400)
+#define WIN4_PAL_END					(0x37fc)
+
+#define WIN0_PAL(_entry)			(WIN0_PAL_BASE + ((_entry) * 4))
+#define WIN1_PAL(_entry)			(WIN1_PAL_BASE + ((_entry) * 4))
+#define WIN2_PAL(_entry)			(WIN2_PAL_BASE + ((_entry) * 4))
+#define WIN3_PAL(_entry)			(WIN3_PAL_BASE + ((_entry) * 4))
+#define WIN4_PAL(_entry)			(WIN4_PAL_BASE + ((_entry) * 4))
+
+static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
+{
+	switch (window) {
+	case 0: return WIN0_PAL(reg);
+	case 1: return WIN1_PAL(reg);
+	case 2: return WIN2_PAL(reg);
+	case 3: return WIN3_PAL(reg);
+	case 4: return WIN4_PAL(reg);
+	}
+
+	BUG();
+}
+
+
+#endif /* __ASM_ARCH_REGS_FB_V5_H */
+
-- 
1.6.4

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoCs have UART that differs a bit from the one known
from the previous Samsung SoCs. This patch adds support for this new
driver.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>


---
 arch/arm/plat-s3c/include/plat/regs-serial.h |   31 ++++++
 drivers/serial/Kconfig                       |    7 ++
 drivers/serial/Makefile                      |    1 +
 drivers/serial/s5pc110.c                     |  143 ++++++++++++++++++++++++++
 4 files changed, 182 insertions(+), 0 deletions(-)
 create mode 100644 drivers/serial/s5pc110.c

diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h
index 66af75a..910cfba 100644
--- a/arch/arm/plat-s3c/include/plat/regs-serial.h
+++ b/arch/arm/plat-s3c/include/plat/regs-serial.h
@@ -194,6 +194,37 @@
 #define S3C64XX_UINTSP		0x34
 #define S3C64XX_UINTM		0x38
 
+/* S5PC110 UCON */
+#define S5PC110_UCON_CLKMASK	(1<<10)
+#define S5PC110_UCON_PCLK	(0<<10)
+#define S5PC110_UCON_SCLK_UART	(1<<10)
+
+/* S5PC110 FIFO trigger levels */
+#define S5PC110_UFCON_RXTRIG1	(0<<4)
+#define S5PC110_UFCON_RXTRIG4	(1<<4)
+#define S5PC110_UFCON_RXTRIG8	(2<<4)
+#define S5PC110_UFCON_RXTRIG16	(3<<4)
+#define S5PC110_UFCON_RXTRIG32	(4<<4)
+#define S5PC110_UFCON_RXTRIG64	(5<<4)
+#define S5PC110_UFCON_RXTRIG128	(6<<4)
+#define S5PC110_UFCON_RXTRIG256	(7<<4)
+
+#define S5PC110_UFCON_TXTRIG1	(0<<8)
+#define S5PC110_UFCON_TXTRIG4	(1<<8)
+#define S5PC110_UFCON_TXTRIG8	(2<<8)
+#define S5PC110_UFCON_TXTRIG16	(3<<8)
+#define S5PC110_UFCON_TXTRIG32	(4<<8)
+#define S5PC110_UFCON_TXTRIG64	(5<<8)
+#define S5PC110_UFCON_TXTRIG128	(6<<8)
+#define S5PC110_UFCON_TXTRIG256	(7<<8)
+
+#define S5PC110_UFSTAT_TXFULL	(1<<24)
+#define S5PC110_UFSTAT_RXFULL	(1<<8)
+#define S5PC110_UFSTAT_TXSHIFT	(16)
+#define S5PC110_UFSTAT_RXSHIFT	(0)
+#define S5PC110_UFSTAT_TXMASK	(255<<16)
+#define S5PC110_UFSTAT_RXMASK	(255)
+
 #ifndef __ASSEMBLY__
 
 /* struct s3c24xx_uart_clksrc
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index e522572..d119cac 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -540,6 +540,13 @@ config SERIAL_S5PC100
 	help
 	  Serial port support for the Samsung S5PC100 SoCs
 
+config SERIAL_S5PC110
+	tristate "Samsung S5PC110 Serial port support"
+	depends on SERIAL_SAMSUNG && CPU_S5PC110
+	default y
+	help
+	  Serial port support for the Samsung S5PC110 SoCs
+
 config SERIAL_MAX3100
 	tristate "MAX3100 support"
 	depends on SPI
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index d21d5dd..43d6123 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
 obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
 obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
 obj-$(CONFIG_SERIAL_S5PC100) += s3c6400.o
+obj-$(CONFIG_SERIAL_S5PC110) += s5pc110.o
 obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
 obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
 obj-$(CONFIG_SERIAL_MUX) += mux.o
diff --git a/drivers/serial/s5pc110.c b/drivers/serial/s5pc110.c
new file mode 100644
index 0000000..1e1e229
--- /dev/null
+++ b/drivers/serial/s5pc110.c
@@ -0,0 +1,143 @@
+/*
+ * linux/drivers/serial/s5pc110.c
+ *
+ * Driver for Samsung S5PC110 SoC onboard UARTs.
+ *
+ *  Copyright 2009 Samsung Electronics
+ *  Kyungin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+
+#include <asm/irq.h>
+#include <mach/hardware.h>
+
+#include <plat/regs-serial.h>
+
+#include "samsung.h"
+
+static int s5pc110_serial_setsource(struct uart_port *port,
+				    struct s3c24xx_uart_clksrc *clk)
+{
+	unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+	if (strcmp(clk->name, "uclk0") == 0)
+		ucon |= S5PC110_UCON_SCLK_UART;
+	else if (strcmp(clk->name, "pclk") == 0)
+		/* See notes about transitioning from UCLK to PCLK */
+		ucon &= ~S5PC110_UCON_SCLK_UART;
+	else {
+		printk(KERN_ERR "unknown clock source %s\n", clk->name);
+		return -EINVAL;
+	}
+
+	wr_regl(port, S3C2410_UCON, ucon);
+	return 0;
+}
+
+static int s5pc110_serial_getsource(struct uart_port *port,
+				    struct s3c24xx_uart_clksrc *clk)
+{
+	u32 ucon = rd_regl(port, S3C2410_UCON);
+
+	clk->divisor = 1;
+
+	switch (ucon & S5PC110_UCON_CLKMASK) {
+	case S5PC110_UCON_SCLK_UART:
+		clk->name = "uclk0";
+		break;
+
+	case S5PC110_UCON_PCLK:
+		clk->name = "pclk";
+		break;
+	}
+
+	return 0;
+}
+
+static int s5pc110_serial_resetport(struct uart_port *port,
+				    struct s3c2410_uartcfg *cfg)
+{
+	unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+	dbg("s5pc110_serial_resetport: port=%p (%08lx), cfg=%p\n",
+	    port, port->mapbase, cfg);
+
+	/* ensure we don't change the clock settings... */
+
+	ucon &= S5PC110_UCON_CLKMASK;
+
+	wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
+	wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+	/* reset both fifos */
+
+	wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+	wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+	return 0;
+}
+
+static struct s3c24xx_uart_info s5pc110_uart_inf = {
+	.name		= "Samsung S5PC110 UART",
+	.type		= PORT_S3C6400,
+	.fifosize	= 16,
+	.has_divslot	= 1,
+	.rx_fifomask	= S5PC110_UFSTAT_RXMASK,
+	.rx_fifoshift	= S5PC110_UFSTAT_RXSHIFT,
+	.rx_fifofull	= S5PC110_UFSTAT_RXFULL,
+	.tx_fifofull	= S5PC110_UFSTAT_TXFULL,
+	.tx_fifomask	= S5PC110_UFSTAT_TXMASK,
+	.tx_fifoshift	= S5PC110_UFSTAT_TXSHIFT,
+	.get_clksrc	= s5pc110_serial_getsource,
+	.set_clksrc	= s5pc110_serial_setsource,
+	.reset_port	= s5pc110_serial_resetport,
+};
+
+/* device management */
+
+static int s5pc110_serial_probe(struct platform_device *dev)
+{
+	dbg("s5pc110_serial_probe: dev=%p\n", dev);
+
+	return s3c24xx_serial_probe(dev, &s5pc110_uart_inf);
+}
+
+static struct platform_driver s5pc110_serial_driver = {
+	.probe		= s5pc110_serial_probe,
+	.remove		= __devexit_p(s3c24xx_serial_remove),
+	.driver		= {
+		.name	= "s5pc110-uart",
+		.owner	= THIS_MODULE,
+	},
+};
+
+s3c24xx_console_init(&s5pc110_serial_driver, &s5pc110_uart_inf);
+
+static int __init s5pc110_serial_init(void)
+{
+	return s3c24xx_serial_init(&s5pc110_serial_driver, &s5pc110_uart_inf);
+}
+
+static void __exit s5pc110_serial_exit(void)
+{
+	platform_driver_unregister(&s5pc110_serial_driver);
+}
+
+module_init(s5pc110_serial_init);
+module_exit(s5pc110_serial_exit);
+
+MODULE_DESCRIPTION("Samsung S5PC110 SoC Serial port driver");
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:s5pc110-uart");
-- 
1.6.4

[PATCH 10/19] ARM: S5PC1XX: add S5PC110 memory map

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds register map for S5PC110 sub-platform.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 arch/arm/mach-s5pc110/include/mach/map.h |  157 ++++++++++++++++++++++++++++++
 1 files changed, 157 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/include/mach/map.h

diff --git a/arch/arm/mach-s5pc110/include/mach/map.h b/arch/arm/mach-s5pc110/include/mach/map.h
new file mode 100644
index 0000000..1a673d3
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/mach/map.h
@@ -0,0 +1,157 @@
+/* linux/arch/arm/mach-s5pc110/include/mach/map.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Based on mach-s3c6400/include/mach/map.h
+ *
+ * S5PC110 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H __FILE__
+
+#include <plat/map-base.h>
+
+/*
+ * map-base.h has already defined virtual memory address
+ * S3C_VA_IRQ		S3C_ADDR(0x00000000)	irq controller(s)
+ * S3C_VA_SYS		S3C_ADDR(0x00100000)	system control
+ * S3C_VA_MEM		S3C_ADDR(0x00200000)	system control (not used)
+ * S3C_VA_TIMER		S3C_ADDR(0x00300000)	timer block
+ * S3C_VA_WATCHDOG	S3C_ADDR(0x00400000)	watchdog
+ * S3C_VA_UART		S3C_ADDR(0x01000000)	UART
+ *
+ * S5PC110 specific virtual memory address can be defined here
+ * S5PC1XX_VA_GPIO	S3C_ADDR(0x00500000)	GPIO
+ *
+ */
+
+/* Chip ID */
+#define S5PC110_PA_CHIPID	(0xE0000000)
+#define S5PC1XX_PA_CHIPID	S5PC110_PA_CHIPID
+#define S5PC1XX_VA_CHIPID	S3C_VA_SYS
+
+/* System */
+#define S5PC110_PA_CLK		(0xE0100000)
+#define S5PC110_PA_PWR		(0xE010C000)
+#define S5PC1XX_PA_CLK		S5PC110_PA_CLK
+#define S5PC1XX_PA_PWR		S5PC110_PA_PWR
+#define S5PC1XX_VA_CLK		(S3C_VA_SYS + 0x10000)
+#define S5PC1XX_VA_PWR		(S3C_VA_SYS + 0x20000)
+#define S5PC1XX_SZ_CLK		SZ_32K
+#define S5PC1XX_SZ_PWR		SZ_16K
+
+/* GPIO */
+#define S5PC110_PA_GPIO		(0xE0200000)
+#define S5PC1XX_PA_GPIO		S5PC110_PA_GPIO
+#define S5PC1XX_VA_GPIO		S3C_ADDR(0x00500000)
+
+/* Interrupt */
+#define S5PC110_PA_VIC		(0xF2000000)
+#define S5PC110_PA_VIC_OFFSET	0x100000
+#define S5PC1XX_PA_VIC(x)	(S5PC110_PA_VIC + ((x) * S5PC110_PA_VIC_OFFSET))
+#define S5PC110_VA_VIC		S3C_VA_IRQ
+#define S5PC110_VA_VIC_OFFSET	0x10000
+#define S5PC1XX_VA_VIC(x)	(S5PC110_VA_VIC + ((x) * S5PC110_VA_VIC_OFFSET))
+
+/* DMA */
+#define S5PC110_PA_MDMA		(0xFA200000)
+#define S5PC110_PA_PDMA0	(0xE0900000)
+#define S5PC110_PA_PDMA1	(0xE0A00000)
+
+/* Timer */
+#define S5PC110_PA_TIMER	(0xE2500000)
+#define S5PC1XX_PA_TIMER	S5PC110_PA_TIMER
+#define S5PC1XX_VA_TIMER	S3C_VA_TIMER
+
+/* RTC */
+#define S5PC110_PA_RTC		(0xEA300000)
+#define S5PC1XX_PA_RTC		S5PC110_PA_RTC
+
+/* UART */
+#define S5PC110_PA_UART		(0xE2900000)
+#define S5PC1XX_PA_UART		S5PC110_PA_UART
+#define S5PC110_PA_UART0	(S5PC110_PA_UART + 0x0)
+#define S5PC110_PA_UART1	(S5PC110_PA_UART + 0x400)
+#define S5PC110_PA_UART2	(S5PC110_PA_UART + 0x800)
+#define S5PC110_PA_UART3	(S5PC110_PA_UART + 0xC00)
+#define S5PC1XX_VA_UART		S3C_VA_UART
+
+/* MFC */
+#define S5PC110_PA_MFC		(0xF1700000)
+
+/* I2C */
+#define S5PC110_PA_I2C		(0xE1800000)
+#define S5PC110_PA_I2C1		(0xFAB00000)
+#define S5PC110_PA_I2C2		(0xE1A00000)
+
+/* USB HS OTG */
+#define S5PC110_PA_USB_HSOTG	(0xEC000000)
+#define S5PC110_PA_USB_HSPHY	(0xEC100000)
+
+/* SD/MMC */
+#define S5PC110_PA_HSMMC(x)	(0xEB000000 + ((x) * 0x100000))
+#define S5PC110_PA_HSMMC0	S5PC110_PA_HSMMC(0)
+#define S5PC110_PA_HSMMC1	S5PC110_PA_HSMMC(1)
+#define S5PC110_PA_HSMMC2	S5PC110_PA_HSMMC(2)
+#define S5PC110_PA_HSMMC3	S5PC110_PA_HSMMC(2)
+
+/* LCD */
+#define S5PC110_PA_FB		(0xF8000000)
+
+/* Multimedia */
+#define S5PC11X_PA_MFC		(0xF1700000)
+#define S5PC11X_SZ_MFC		(0x0000FFFF)
+
+/* I2S */
+#define S5PC110_PA_I2S0		(0xEEE30000)
+#define S5PC110_PA_I2S1		(0xE2100000)
+#define S5PC110_PA_I2S2		(0xE2A00000)
+
+/* KEYPAD */
+#define S5PC110_PA_KEYPAD	(0xE1600000)
+
+/* ADC & TouchScreen */
+#define S5PC110_PA_TSADC	(0xE1700000)
+
+/* ETC */
+#define S5PC110_PA_SDRAM	(0x30000000)
+#define S5PC1XX_PA_SDRAM	S5PC110_PA_SDRAM
+
+/* compatibility defines. */
+#define S3C_PA_RTC		S5PC1XX_PA_RTC
+#define S3C_PA_UART		S5PC1XX_PA_UART
+#define S3C_PA_UART0		S5PC110_PA_UART0
+#define S3C_PA_UART1		S5PC110_PA_UART1
+#define S3C_PA_UART2		S5PC110_PA_UART2
+#define S3C_PA_UART3		S5PC110_PA_UART3
+
+#define S3C_VA_UART0		(S3C_VA_UART + 0x0)
+#define S3C_VA_UART1		(S3C_VA_UART + 0x400)
+#define S3C_VA_UART2		(S3C_VA_UART + 0x800)
+#define S3C_VA_UART3		(S3C_VA_UART + 0xC00)
+#define S3C_UART_OFFSET		0x400
+#define S3C_VA_UARTx(x)		(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+
+#define S3C_PA_FB		S5PC110_PA_FB
+#define S3C_VA_VIC0		(S3C_VA_IRQ + 0x0)
+#define S3C_VA_VIC1		(S3C_VA_IRQ + 0x10000)
+#define S3C_VA_VIC2		(S3C_VA_IRQ + 0x20000)
+#define S3C_VA_VIC3		(S3C_VA_IRQ + 0x30000)
+#define S3C_PA_IIC		S5PC110_PA_I2C
+#define S3C_PA_IIC1		S5PC110_PA_I2C1
+#define S3C_PA_IIC2		S5PC110_PA_I2C2
+#define S3C_PA_USB_HSOTG	S5PC110_PA_USB_HSOTG
+#define S3C_PA_USB_HSPHY	S5PC110_PA_USB_HSPHY
+#define S3C_PA_HSMMC0		S5PC110_PA_HSMMC0
+#define S3C_PA_HSMMC1		S5PC110_PA_HSMMC1
+#define S3C_PA_HSMMC2		S5PC110_PA_HSMMC2
+#define S3C_PA_KEYPAD		S5PC110_PA_KEYPAD
+#define S3C_PA_TSADC		S5PC110_PA_TSADC
+
+#endif /* __ASM_ARCH_C100_MAP_H */
-- 
1.6.4

[PATCH 11/19] ARM: S5PC1XX: add S5PC110 cpu initialization code

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds CPU initialization code for S5PC110 sub-platform.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 arch/arm/mach-s5pc110/Kconfig                    |   18 ++++
 arch/arm/mach-s5pc110/Makefile                   |   18 ++++
 arch/arm/mach-s5pc110/Makefile.boot              |    2 +
 arch/arm/mach-s5pc110/cpu.c                      |  117 ++++++++++++++++++++++
 arch/arm/mach-s5pc110/include/mach/debug-macro.S |   54 ++++++++++
 arch/arm/mach-s5pc110/include/mach/entry-macro.S |   56 ++++++++++
 arch/arm/mach-s5pc110/include/mach/system.h      |   31 ++++++
 arch/arm/mach-s5pc110/include/plat/regs-power.h  |   80 +++++++++++++++
 arch/arm/plat-s5pc1xx/Kconfig                    |    5 +
 arch/arm/plat-s5pc1xx/Makefile                   |    1 +
 arch/arm/plat-s5pc1xx/cpu.c                      |    9 ++
 arch/arm/plat-s5pc1xx/include/plat/s5pc110.h     |   36 +++++++
 arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h     |    1 +
 arch/arm/plat-s5pc1xx/s5pc110-init.c             |   28 +++++
 14 files changed, 456 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/Kconfig
 create mode 100644 arch/arm/mach-s5pc110/Makefile
 create mode 100644 arch/arm/mach-s5pc110/Makefile.boot
 create mode 100644 arch/arm/mach-s5pc110/cpu.c
 create mode 100644 arch/arm/mach-s5pc110/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-s5pc110/include/mach/entry-macro.S
 create mode 100644 arch/arm/mach-s5pc110/include/mach/system.h
 create mode 100644 arch/arm/mach-s5pc110/include/plat/regs-power.h
 create mode 100644 arch/arm/plat-s5pc1xx/include/plat/s5pc110.h
 create mode 100644 arch/arm/plat-s5pc1xx/s5pc110-init.c

diff --git a/arch/arm/mach-s5pc110/Kconfig b/arch/arm/mach-s5pc110/Kconfig
new file mode 100644
index 0000000..fb298e2
--- /dev/null
+++ b/arch/arm/mach-s5pc110/Kconfig
@@ -0,0 +1,18 @@
+# arch/arm/mach-s5pc110/Kconfig
+#
+#  Copyright 2009 Samsung Electronics Co.
+#  Kyungmin Park <kyungmin.park@samsung.com>
+#
+# Licensed under GPLv2
+
+if ARCH_S5PC110
+
+# Configuration options for the S5PC110 CPU
+
+config CPU_S5PC110
+	bool
+	select CPU_S5PC110_INIT
+	help
+	  Enable S5PC110 CPU support
+
+endif
diff --git a/arch/arm/mach-s5pc110/Makefile b/arch/arm/mach-s5pc110/Makefile
new file mode 100644
index 0000000..d9fecf0
--- /dev/null
+++ b/arch/arm/mach-s5pc110/Makefile
@@ -0,0 +1,18 @@
+# arch/arm/mach-s5pc100/Makefile
+#
+# Copyright 2009 Samsung Electronics Co.
+#
+# Licensed under GPLv2
+
+obj-y                           :=
+obj-m                           :=
+obj-n                           :=
+obj-                            :=
+
+# Core support for S5PC110 system
+
+obj-$(CONFIG_CPU_S5PC110)	+= cpu.o
+
+# Helper and device support
+
+# machine support
diff --git a/arch/arm/mach-s5pc110/Makefile.boot b/arch/arm/mach-s5pc110/Makefile.boot
new file mode 100644
index 0000000..b0909e3
--- /dev/null
+++ b/arch/arm/mach-s5pc110/Makefile.boot
@@ -0,0 +1,2 @@
+   zreladdr-y	:= 0x30008000
+params_phys-y	:= 0x30000100
diff --git a/arch/arm/mach-s5pc110/cpu.c b/arch/arm/mach-s5pc110/cpu.c
new file mode 100644
index 0000000..1a4a5e4
--- /dev/null
+++ b/arch/arm/mach-s5pc110/cpu.c
@@ -0,0 +1,117 @@
+/* linux/arch/arm/mach-s5pc110/cpu.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Based on mach-s3c6410/cpu.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+
+#include <asm/proc-fns.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/regs-serial.h>
+#include <plat/regs-power.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/sdhci.h>
+#include <plat/iic-core.h>
+#include <plat/s5pc1xx.h>
+
+/* Initial IO mappings */
+
+static struct map_desc s5pc110_iodesc[] __initdata = {
+};
+
+static void s5pc110_idle(void)
+{
+	unsigned long tmp;
+
+	tmp = __raw_readl(S5PC110_IDLE_CFG);
+	tmp &= ~(S5PC110_IDLECFG_TOP_LOGIC_MASK |
+			S5PC110_IDLECFG_TOP_MEMORY_MASK |
+			S5PC110_IDLECFG_OSC_EN);
+	tmp |= S5PC110_IDLECFG_TOP_LOGIC_ON |
+		S5PC110_IDLECFG_TOP_MEMORY_ON;
+	__raw_writel(tmp, S5PC110_IDLE_CFG);
+
+	tmp = __raw_readl(S5PC110_PWR_CFG);
+	tmp &= ~S5PC110_PWRCFG_CFG_WFI_MASK;
+	/* S5pc110 EVT0 chip bug */
+	/* tmp |= S5PC110_PWRCFG_CFG_WFI_IDLE; */
+	__raw_writel(tmp, S5PC110_PWR_CFG);
+
+	tmp = __raw_readl(S5PC110_OTHERS);
+	tmp |= S5PC110_SYSCON_INT_DISABLE;
+	__raw_writel(tmp, S5PC110_OTHERS);
+
+	cpu_do_idle();
+}
+
+/* s5pc110_map_io
+ *
+ * register the standard cpu IO areas
+*/
+
+void __init s5pc110_map_io(void)
+{
+	iotable_init(s5pc110_iodesc, ARRAY_SIZE(s5pc110_iodesc));
+
+	/* initialise device information early */
+}
+
+void __init s5pc110_init_clocks(int xtal)
+{
+	printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
+	s3c24xx_register_baseclocks(xtal);
+}
+
+void __init s5pc110_init_irq(void)
+{
+}
+
+struct sysdev_class s5pc110_sysclass = {
+	.name	= "s5pc110-core",
+};
+
+static struct sys_device s5pc110_sysdev = {
+	.cls	= &s5pc110_sysclass,
+};
+
+static int __init s5pc110_core_init(void)
+{
+	return sysdev_class_register(&s5pc110_sysclass);
+}
+
+core_initcall(s5pc110_core_init);
+
+int __init s5pc110_init(void)
+{
+	printk(KERN_DEBUG "S5PC110: Initialising architecture\n");
+
+	s5pc1xx_idle = s5pc110_idle;
+
+	return sysdev_register(&s5pc110_sysdev);
+}
diff --git a/arch/arm/mach-s5pc110/include/mach/debug-macro.S b/arch/arm/mach-s5pc110/include/mach/debug-macro.S
new file mode 100644
index 0000000..1f75af5
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/mach/debug-macro.S
@@ -0,0 +1,54 @@
+/* arch/arm/mach-s5pc110/include/mach/debug-macro.S
+ *
+ *  Copyright (C) 2009 Samsung Electronics Co.
+ *  Byungho Min <bhmin@samsung.com>
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Based on mach-s3c6400/include/mach/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* pull in the relevant register and map files. */
+
+#include <mach/map.h>
+#include <plat/regs-serial.h>
+
+	/* note, for the boot process to work we have to keep the UART
+	 * virtual address aligned to an 1MiB boundary for the L1
+	 * mapping the head code makes. We keep the UART virtual address
+	 * aligned and add in the offset when we load the value here.
+	 */
+
+	.macro addruart, rx
+		mrc	p15, 0, \rx, c1, c0
+		tst	\rx, #1
+		ldreq	\rx, = S3C_PA_UART
+		ldrne	\rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
+		add	\rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
+	.endm
+
+	/*
+	 * S5PC110 has different TXMASK & TXFULL
+	 */
+        .macro fifo_level_s5pc110 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                and     \rd, \rd, #S5PC110_UFSTAT_TXMASK
+        .endm
+
+	.macro  fifo_full_s5pc110 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                tst     \rd, #S5PC110_UFSTAT_TXFULL
+        .endm
+
+#define fifo_level	fifo_level_s5pc110
+#define fifo_full	fifo_full_s5pc110
+
+/* include the reset of the code which will do the work, we're only
+ * compiling for a single cpu processor type so the default of s3c2440
+ * will be fine with us.
+ */
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5pc110/include/mach/entry-macro.S b/arch/arm/mach-s5pc110/include/mach/entry-macro.S
new file mode 100644
index 0000000..7695b9d
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/mach/entry-macro.S
@@ -0,0 +1,56 @@
+/* arch/arm/mach-s5pc110/include/mach/entry-macro.S
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Based on mach-s3c6400/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for the Samsung S5PC110 series
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+#include <asm/hardware/vic.h>
+#include <mach/map.h>
+#include <plat/irqs.h>
+
+	.macro	disable_fiq
+	.endm
+
+	.macro	get_irqnr_preamble, base, tmp
+	ldr	\base, =S3C_VA_VIC0
+	.endm
+
+	.macro	arch_ret_to_user, tmp1, tmp2
+	.endm
+
+	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+	@ check the vic0
+	mov	\irqnr, # S3C_IRQ_OFFSET + 31
+	ldr	\irqstat, [ \base, # VIC_IRQ_STATUS ]
+	teq	\irqstat, #0
+
+	@ otherwise try vic1
+	addeq	\tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0)
+	addeq	\irqnr, \irqnr, #32
+	ldreq	\irqstat, [ \tmp, # VIC_IRQ_STATUS ]
+	teqeq	\irqstat, #0
+
+	@ otherwise try vic2
+	addeq	\tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0)
+	addeq	\irqnr, \irqnr, #32
+	ldreq	\irqstat, [ \tmp, # VIC_IRQ_STATUS ]
+	teqeq	\irqstat, #0
+
+	@ otherwise try vic3
+	addeq	\tmp, \base, #(S3C_VA_VIC3 - S3C_VA_VIC0)
+	addeq	\irqnr, \irqnr, #32
+	ldreq	\irqstat, [ \tmp, # VIC_IRQ_STATUS ]
+	teqeq	\irqstat, #0
+
+	clzne	\irqstat, \irqstat
+	subne	\irqnr, \irqnr, \irqstat
+	.endm
diff --git a/arch/arm/mach-s5pc110/include/mach/system.h b/arch/arm/mach-s5pc110/include/mach/system.h
new file mode 100644
index 0000000..be40aa6
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/mach/system.h
@@ -0,0 +1,31 @@
+/* linux/arch/arm/mach-s5pc110/include/mach/system.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC110 - system implementation
+ *
+ * Based on mach-s3c6400/include/mach/system.h
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H __FILE__
+
+#include <linux/io.h>
+#include <mach/map.h>
+#include <plat/regs-clock.h>
+
+void (*s5pc1xx_idle)(void);
+
+static void arch_idle(void)
+{
+	if (s5pc1xx_idle)
+		s5pc1xx_idle();
+}
+
+static void arch_reset(char mode, const char *cmd)
+{
+	__raw_writel(0x1, S5PC110_SWRESET);
+	return;
+}
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pc110/include/plat/regs-power.h b/arch/arm/mach-s5pc110/include/plat/regs-power.h
new file mode 100644
index 0000000..33899a2
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/plat/regs-power.h
@@ -0,0 +1,80 @@
+/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Jongse Won <jongse.won@samsung.com>
+ *
+ * S5PC110 power control register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARM_REGS_PWR
+#define __ASM_ARM_REGS_PWR __FILE__
+
+#define S5PC1XX_PWRREG(x)			(S5PC1XX_VA_PWR + (x))
+
+/* s5pc110 (0xE010C000) register for power management */
+#define S5PC110_PWR_CFG				S5PC1XX_PWRREG(0x0)
+#define S5PC110_EINT_WAKEUP_MASK		S5PC1XX_PWRREG(0x4)
+#define S5PC110_WAKEUP_MASK			S5PC1XX_PWRREG(0x8)
+#define S5PC110_NORMAL_CFG			S5PC1XX_PWRREG(0x10)
+#define S5PC110_IDLE_CFG			S5PC1XX_PWRREG(0x20)
+#define S5PC110_STOP_CFG			S5PC1XX_PWRREG(0x30)
+#define S5PC110_STOP_MEM_CFG			S5PC1XX_PWRREG(0x34)
+#define S5PC110_SLEEP_CFG			S5PC1XX_PWRREG(0x40)
+#define S5PC110_OSC_FREQ			S5PC1XX_PWRREG(0x100)
+#define S5PC110_OSC_STABLE			S5PC1XX_PWRREG(0x104)
+#define S5PC110_PWR_STABLE			S5PC1XX_PWRREG(0x108)
+#define S5PC110_MTC_STABLE			S5PC1XX_PWRREG(0x110)
+#define S5PC110_CLAMP_STABLE			S5PC1XX_PWRREG(0x114)
+#define S5PC110_WAKEUP_STAT			S5PC1XX_PWRREG(0x200)
+#define S5PC110_BLK_PWR_STAT			S5PC1XX_PWRREG(0x204)
+#define S5PC110_BODY_BIAS_CON			S5PC1XX_PWRREG(0x300)
+#define S5PC110_ION_SKEW_CON			S5PC1XX_PWRREG(0x310)
+#define S5PC110_ION_SKEW_MON			S5PC1XX_PWRREG(0x314)
+#define S5PC110_IOFF_SKEW_CON			S5PC1XX_PWRREG(0x320)
+#define S5PC110_IOFF_SKEW_MON			S5PC1XX_PWRREG(0x324)
+#define S5PC110_OTHERS				S5PC1XX_PWRREG(0x2000)
+#define S5PC110_OM_STAT				S5PC1XX_PWRREG(0x2100)
+#define S5PC110_MIE_CONTROL			S5PC1XX_PWRREG(0x2800)
+#define S5PC110_HDMI_CONTROL			S5PC1XX_PWRREG(0x2804)
+#define S5PC110_USB_PHY_CONTROL			S5PC1XX_PWRREG(0x280C)
+#define S5PC110_DAC_CONTROL			S5PC1XX_PWRREG(0x2810)
+#define S5PC110_MIPI_DPHY_CONTROL		S5PC1XX_PWRREG(0x2814)
+#define S5PC110_ADC_CONTROL			S5PC1XX_PWRREG(0x2818)
+#define S5PC110_PS_HOLD_CONTROL			S5PC1XX_PWRREG(0x281C)
+#define S5PC110_INFORM0				S5PC1XX_PWRREG(0x3000)
+#define S5PC110_INFORM1				S5PC1XX_PWRREG(0x3004)
+#define S5PC110_INFORM2				S5PC1XX_PWRREG(0x3008)
+#define S5PC110_INFORM3				S5PC1XX_PWRREG(0x300C)
+#define S5PC110_INFORM4				S5PC1XX_PWRREG(0x3010)
+#define S5PC110_INFORM5				S5PC1XX_PWRREG(0x3014)
+#define S5PC110_INFORM6				S5PC1XX_PWRREG(0x3018)
+#define S5PC110_INFORM7				S5PC1XX_PWRREG(0x301C)
+
+/* PWR_CFG */
+#define S5PC110_PWRCFG_CFG_WFI_MASK		(3 << 8)
+#define S5PC110_PWRCFG_CFG_WFI_IGNORE		(0 << 8)
+#define S5PC110_PWRCFG_CFG_WFI_IDLE		(1 << 8)
+#define S5PC110_PWRCFG_CFG_WFI_STOP		(2 << 8)
+#define S5PC110_PWRCFG_CFG_WFI_SLEEP		(3 << 8)
+
+/* IDLE_CFG */
+#define S5PC110_IDLECFG_TOP_LOGIC_MASK		(3 << 30)
+#define S5PC110_IDLECFG_TOP_LOGIC_RET		(1 << 30)
+#define S5PC110_IDLECFG_TOP_LOGIC_ON		(2 << 30)
+#define S5PC110_IDLECFG_TOP_MEMORY_MASK		(3 << 28)
+#define S5PC110_IDLECFG_TOP_MEMORY_RET		(1 << 28)
+#define S5PC110_IDLECFG_TOP_MEMORY_ON		(2 << 28)
+#define S5PC110_IDLECFG_OSC_EN			(1 << 0)
+
+/* SLEEP_CFG */
+#define S5PC110_SLEEP_OSCUSB_EN			(1 << 1)
+#define S5PC110_SLEEP_OSC_EN			(1 << 0)
+
+/* OTHERS */
+#define S5PC110_SYSCON_INT_DISABLE		(1 << 0)
+
+#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index 9f76a9b..679e145 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -45,6 +45,11 @@ config CPU_S5PC100_CLOCK
 	help
 	  Common clock support code for the S5PC1XX
 
+config CPU_S5PC110_INIT
+	bool
+	help
+	  Common initialisation code for the S5PC1XX
+
 # platform specific device setup
 
 endif
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
index cc06606..3e8ebf1 100644
--- a/arch/arm/plat-s5pc1xx/Makefile
+++ b/arch/arm/plat-s5pc1xx/Makefile
@@ -20,6 +20,7 @@ obj-y				+= gpiolib.o
 
 obj-$(CONFIG_CPU_S5PC100_INIT)	+= s5pc100-init.o
 obj-$(CONFIG_CPU_S5PC100_CLOCK)	+= s5pc100-plls.o s5pc100-clocks.o
+obj-$(CONFIG_CPU_S5PC110_INIT)	+= s5pc110-init.o
 
 # Device setup
 
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c
index d30998d..893d433 100644
--- a/arch/arm/plat-s5pc1xx/cpu.c
+++ b/arch/arm/plat-s5pc1xx/cpu.c
@@ -36,6 +36,7 @@
 /* table of supported CPUs */
 
 static const char name_s5pc100[] = "S5PC100";
+static const char name_s5pc110[] = "S5PC110";
 
 static struct cpu_table cpu_ids[] __initdata = {
 	{
@@ -46,6 +47,14 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.init_uarts	= s5pc100_init_uarts,
 		.init		= s5pc100_init,
 		.name		= name_s5pc100,
+	}, {
+		.idcode		= 0x43110000,
+		.idmask		= 0xfffff000,
+		.map_io		= s5pc110_map_io,
+		.init_clocks	= s5pc110_init_clocks,
+		.init_uarts	= s5pc110_init_uarts,
+		.init		= s5pc110_init,
+		.name		= name_s5pc110,
 	},
 };
 /* minimal IO mapping */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h
new file mode 100644
index 0000000..93c623b
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h
@@ -0,0 +1,36 @@
+/* arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Header file for s5pc100 cpu support
+ *
+ * Based on plat-s3c64xx/include/plat/s3c6400.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for S5PC110 related SoCs */
+
+#ifdef CONFIG_CPU_S5PC110
+
+extern void s5pc110_map_io(void);
+extern void s5pc110_init_clocks(int xtal);
+extern void s5pc110_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern  int s5pc110_init(void);
+
+extern void s5pc110_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s5pc110_init_irq(void);
+extern void s5pc110_register_clocks(void);
+extern void s5pc110_setup_clocks(void);
+
+#else
+
+#define s5pc110_map_io NULL
+#define s5pc110_init_clocks NULL
+#define s5pc110_init_uarts NULL
+#define s5pc110_init NULL
+
+#endif
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h
index 398251f..d8d7a43 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h
@@ -19,3 +19,4 @@ extern void s5pc1xx_register_clocks(void);
 extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
 
 #include <plat/s5pc100.h>
+#include <plat/s5pc110.h>
diff --git a/arch/arm/plat-s5pc1xx/s5pc110-init.c b/arch/arm/plat-s5pc1xx/s5pc110-init.c
new file mode 100644
index 0000000..dc3c6d7
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/s5pc110-init.c
@@ -0,0 +1,28 @@
+/*
+ * linux/arch/arm/plat-s5pc1xx/s5pc110-init.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *
+ * S5PC110 - CPU initialisation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/s5pc1xx.h>
+
+/* uart registration process */
+
+void __init s5pc110_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+	/* The driver name is s5pc1xx-uart to reuse s5pc1xx_serial_drv  */
+	s3c24xx_init_uartdevs("s5pc110-uart", s5pc1xx_uart_resources, cfg, no);
+}
-- 
1.6.4

[PATCH 12/19] ARM: S5PC1XX: add support for s5pc110 plls and clocks

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds clocks and plls definition for S5PC110 SoCs.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 arch/arm/mach-s5pc110/Kconfig                   |    1 +
 arch/arm/mach-s5pc110/cpu.c                     |    3 +
 arch/arm/mach-s5pc110/include/plat/regs-clock.h |  347 ++++++
 arch/arm/plat-s5pc1xx/Kconfig                   |    5 +
 arch/arm/plat-s5pc1xx/Makefile                  |    1 +
 arch/arm/plat-s5pc1xx/include/plat/pll.h        |    8 +-
 arch/arm/plat-s5pc1xx/include/plat/s5pc110.h    |   11 +
 arch/arm/plat-s5pc1xx/s5pc100-plls.c            |    8 +-
 arch/arm/plat-s5pc1xx/s5pc110-clocks.c          |  254 +++++
 arch/arm/plat-s5pc1xx/s5pc110-plls.c            | 1292 +++++++++++++++++++++++
 10 files changed, 1924 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/include/plat/regs-clock.h
 create mode 100644 arch/arm/plat-s5pc1xx/s5pc110-clocks.c
 create mode 100644 arch/arm/plat-s5pc1xx/s5pc110-plls.c

diff --git a/arch/arm/mach-s5pc110/Kconfig b/arch/arm/mach-s5pc110/Kconfig
index fb298e2..420b585 100644
--- a/arch/arm/mach-s5pc110/Kconfig
+++ b/arch/arm/mach-s5pc110/Kconfig
@@ -12,6 +12,7 @@ if ARCH_S5PC110
 config CPU_S5PC110
 	bool
 	select CPU_S5PC110_INIT
+	select CPU_S5PC110_CLOCK
 	help
 	  Enable S5PC110 CPU support
 
diff --git a/arch/arm/mach-s5pc110/cpu.c b/arch/arm/mach-s5pc110/cpu.c
index 1a4a5e4..6c9ebcb 100644
--- a/arch/arm/mach-s5pc110/cpu.c
+++ b/arch/arm/mach-s5pc110/cpu.c
@@ -86,6 +86,9 @@ void __init s5pc110_init_clocks(int xtal)
 {
 	printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
 	s3c24xx_register_baseclocks(xtal);
+	s5pc1xx_register_clocks();
+	s5pc110_register_clocks();
+	s5pc110_setup_clocks();
 }
 
 void __init s5pc110_init_irq(void)
diff --git a/arch/arm/mach-s5pc110/include/plat/regs-clock.h b/arch/arm/mach-s5pc110/include/plat/regs-clock.h
new file mode 100644
index 0000000..4305a07
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/plat/regs-clock.h
@@ -0,0 +1,347 @@
+/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC110 clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_CLOCK_H
+#define __PLAT_REGS_CLOCK_H __FILE__
+
+#define S5PC1XX_CLKREG(x)		(S5PC1XX_VA_CLK + (x))
+
+/* s5pc110 register for clock */
+#define S5PC110_APLL_LOCK		S5PC1XX_CLKREG(0x00)
+#define S5PC110_MPLL_LOCK		S5PC1XX_CLKREG(0x08)
+#define S5PC110_EPLL_LOCK		S5PC1XX_CLKREG(0x10)
+#define S5PC110_VPLL_LOCK		S5PC1XX_CLKREG(0x20)
+
+#define S5PC110_APLL_CON		S5PC1XX_CLKREG(0x100)
+#define S5PC110_MPLL_CON		S5PC1XX_CLKREG(0x108)
+#define S5PC110_EPLL_CON		S5PC1XX_CLKREG(0x110)
+#define S5PC110_VPLL_CON		S5PC1XX_CLKREG(0x120)
+
+#define S5PC110_CLKSRC0			S5PC1XX_CLKREG(0x200)
+#define S5PC110_CLKSRC1			S5PC1XX_CLKREG(0x204)
+#define S5PC110_CLKSRC2			S5PC1XX_CLKREG(0x208)
+#define S5PC110_CLKSRC3			S5PC1XX_CLKREG(0x20C)
+#define S5PC110_CLKSRC4			S5PC1XX_CLKREG(0x210)
+#define S5PC110_CLKSRC5			S5PC1XX_CLKREG(0x214)
+#define S5PC110_CLKSRC6			S5PC1XX_CLKREG(0x218)
+
+#define S5PC110_CLKSRC_MASK0		S5PC1XX_CLKREG(0x280)
+#define S5PC110_CLKSRC_MASK1		S5PC1XX_CLKREG(0x284)
+
+#define S5PC110_CLKDIV0		S5PC1XX_CLKREG(0x300)
+#define S5PC110_CLKDIV1		S5PC1XX_CLKREG(0x304)
+#define S5PC110_CLKDIV2		S5PC1XX_CLKREG(0x308)
+#define S5PC110_CLKDIV3		S5PC1XX_CLKREG(0x30C)
+#define S5PC110_CLKDIV4		S5PC1XX_CLKREG(0x310)
+#define S5PC110_CLKDIV5		S5PC1XX_CLKREG(0x314)
+#define S5PC110_CLKDIV6		S5PC1XX_CLKREG(0x318)
+#define S5PC110_CLKDIV7		S5PC1XX_CLKREG(0x31C)
+
+#define S5PC110_CLKGATE_IP0		S5PC1XX_CLKREG(0x460)
+#define S5PC110_CLKGATE_IP1		S5PC1XX_CLKREG(0x464)
+#define S5PC110_CLKGATE_IP2		S5PC1XX_CLKREG(0x468)
+#define S5PC110_CLKGATE_IP3		S5PC1XX_CLKREG(0x46C)
+#define S5PC110_CLKGATE_IP4		S5PC1XX_CLKREG(0x470)
+#define S5PC110_CLKGATE_BLOCK		S5PC1XX_CLKREG(0x480)
+#define S5PC110_CLKGATE_BUS0		S5PC1XX_CLKREG(0x484)
+#define S5PC110_CLKGATE_BUS1		S5PC1XX_CLKREG(0x488)
+
+#define S5PC110_CLK_OUT			S5PC1XX_CLKREG(0x500)
+#define S5PC110_MDNIE_SEL		S5PC1XX_CLKREG(0x7008)
+
+#define S5PC110_CLKDIV_STAT0		S5PC1XX_CLKREG(0x1000)
+#define S5PC110_CLKDIV_STAT1		S5PC1XX_CLKREG(0x1004)
+
+#define S5PC110_CLK_MUX_STAT0		S5PC1XX_CLKREG(0x1100)
+#define S5PC110_CLK_MUX_STAT1		S5PC1XX_CLKREG(0x1104)
+
+#define S5PC110_SWRESET		S5PC1XX_CLKREG(0x2000)
+
+#define S5PC110_CLKSRC0_APLL_MASK		(0x1<<0)
+#define S5PC110_CLKSRC0_APLL_SHIFT		(0)
+#define S5PC110_CLKSRC0_MPLL_MASK		(0x1<<4)
+#define S5PC110_CLKSRC0_MPLL_SHIFT		(4)
+#define S5PC110_CLKSRC0_EPLL_MASK		(0x1<<8)
+#define S5PC110_CLKSRC0_EPLL_SHIFT		(8)
+#define S5PC110_CLKSRC0_VPLL_MASK		(0x1<<12)
+#define S5PC110_CLKSRC0_VPLL_SHIFT		(12)
+#define S5PC110_CLKSRC0_MUX200_MASK		(0x1<<16)
+#define S5PC110_CLKSRC0_MUX200_SHIFT		(16)
+#define S5PC110_CLKSRC0_MUX166_MASK		(0x1<<20)
+#define S5PC110_CLKSRC0_MUX166_SHIFT		(20)
+#define S5PC110_CLKSRC0_MUX133_MASK		(0x1<<24)
+#define S5PC110_CLKSRC0_MUX133_SHIFT		(24)
+#define S5PC110_CLKSRC0_ONENAND_MASK		(0x1<<28)
+#define S5PC110_CLKSRC0_ONENAND_SHIFT		(28)
+
+#define S5PC110_CLKSRC1_HDMI_MASK		(0x1<<0)
+#define S5PC110_CLKSRC1_HDMI_SHIFT		(0)
+#define S5PC110_CLKSRC1_MIXER_MASK		(0x7<<1)
+#define S5PC110_CLKSRC1_MIXER_SHIFT		(1)
+#define S5PC110_CLKSRC1_DAC_MASK		(0x1<<8)
+#define S5PC110_CLKSRC1_DAC_SHIFT		(8)
+#define S5PC110_CLKSRC1_CAM0_MASK		(0xf<<12)
+#define S5PC110_CLKSRC1_CAM0_SHIFT		(12)
+#define S5PC110_CLKSRC1_CAM1_MASK		(0xf<<16)
+#define S5PC110_CLKSRC1_CAM1_SHIFT		(16)
+#define S5PC110_CLKSRC1_FIMD_MASK		(0xf<<20)
+#define S5PC110_CLKSRC1_FIMD_SHIFT		(20)
+#define S5PC110_CLKSRC1_CSIS_MASK		(0xf<<24)
+#define S5PC110_CLKSRC1_CSIS_SHIFT		(24)
+#define S5PC110_CLKSRC1_VPLLSRC_MASK		(0x1<<28)
+#define S5PC110_CLKSRC1_VPLLSRC_SHIFT		(28)
+
+#define S5PC110_CLKSRC2_G3D_MASK		(0x3<<0)
+#define S5PC110_CLKSRC2_G3D_SHIFT		(0)
+#define S5PC110_CLKSRC2_MFC_MASK		(0x3<<4)
+#define S5PC110_CLKSRC2_MFC_SHIFT		(4)
+
+#define S5PC110_CLKSRC3_MDNIE_MASK		(0xf<<0)
+#define S5PC110_CLKSRC3_MDNIE_SHIFT		(0)
+#define S5PC110_CLKSRC3_MDNIE_PWMCLK_MASK	(0xf<<4)
+#define S5PC110_CLKSRC3_MDNIE_PWMCLK_SHIFT	(4)
+#define S5PC110_CLKSRC3_FIMC0_LCLK_MASK		(0xf<<12)
+#define S5PC110_CLKSRC3_FIMC0_LCLK_SHIFT	(12)
+#define S5PC110_CLKSRC3_FIMC1_LCLK_MASK		(0xf<<16)
+#define S5PC110_CLKSRC3_FIMC1_LCLK_SHIFT	(16)
+#define S5PC110_CLKSRC3_FIMC2_LCLK_MASK		(0xf<<20)
+#define S5PC110_CLKSRC3_FIMC2_LCLK_SHIFT	(20)
+
+/* CLKSRC4 */
+#define S5PC110_CLKSRC4_MMC0_MASK		(0xf<<0)
+#define S5PC110_CLKSRC4_MMC0_SHIFT		(0)
+#define S5PC110_CLKSRC4_MMC1_MASK		(0xf<<4)
+#define S5PC110_CLKSRC4_MMC1_SHIFT		(4)
+#define S5PC110_CLKSRC4_MMC2_MASK		(0xf<<8)
+#define S5PC110_CLKSRC4_MMC2_SHIFT		(8)
+#define S5PC110_CLKSRC4_MMC3_MASK		(0xf<<12)
+#define S5PC110_CLKSRC4_MMC3_SHIFT		(12)
+#define S5PC110_CLKSRC4_UART0_MASK		(0xf<<16)
+#define S5PC110_CLKSRC4_UART0_SHIFT		(16)
+#define S5PC110_CLKSRC4_UART1_MASK		(0xf<<20)
+#define S5PC110_CLKSRC4_UART1_SHIFT		(20)
+#define S5PC110_CLKSRC4_UART2_MASK		(0xf<<24)
+#define S5PC110_CLKSRC4_UART2_SHIFT		(24)
+#define S5PC110_CLKSRC4_UART3_MASK		(0xf<<28)
+#define S5PC110_CLKSRC4_UART3_SHIFT		(28)
+
+/* CLKSRC5 */
+#define S5PC110_CLKSRC5_SPI0_MASK		(0xf<<0)
+#define S5PC110_CLKSRC5_SPI0_SHIFT		(0)
+#define S5PC110_CLKSRC5_SPI1_MASK		(0xf<<4)
+#define S5PC110_CLKSRC5_SPI1_SHIFT		(4)
+#define S5PC110_CLKSRC5_SPI2_MASK		(0xf<<8)
+#define S5PC110_CLKSRC5_SPI2_SHIFT		(8)
+#define S5PC110_CLKSRC5_PWM_MASK		(0xf<<12)
+#define S5PC110_CLKSRC5_PWM_SHIFT		(12)
+
+/* CLKSRC6 */
+#define S5PC110_CLKSRC6_AUDIO0_MASK		(0xf<<0)
+#define S5PC110_CLKSRC6_AUDIO0_SHIFT		(0)
+#define S5PC110_CLKSRC6_AUDIO1_MASK		(0xf<<4)
+#define S5PC110_CLKSRC6_AUDIO1_SHIFT		(4)
+#define S5PC110_CLKSRC6_AUDIO2_MASK		(0xf<<8)
+#define S5PC110_CLKSRC6_AUDIO2_SHIFT		(4)
+#define S5PC110_CLKSRC6_SPDIF_MASK		(0x3<<12)
+#define S5PC110_CLKSRC6_SPDIF_SHIFT		(12)
+#define S5PC110_CLKSRC6_HPM_MASK		(0x1<<16)
+#define S5PC110_CLKSRC6_HPM_SHIFT		(16)
+#define S5PC110_CLKSRC6_PWI_MASK		(0xf<<20)
+#define S5PC110_CLKSRC6_PWI_SHIFT		(20)
+#define S5PC110_CLKSRC6_ONEDRAM_MASK		(0x3<<24)
+#define S5PC110_CLKSRC6_ONEDRAM_SHIFT		(24)
+
+#define S5PC110_CLKDIV0_APLL_MASK		(0x7<<0)
+#define S5PC110_CLKDIV0_APLL_SHIFT		(0)
+#define S5PC110_CLKDIV0_A2M_MASK		(0x7<<4)
+#define S5PC110_CLKDIV0_A2M_SHIFT		(4)
+#define S5PC110_CLKDIV0_HCLK_MSYS_MASK		(0x7<<8)
+#define S5PC110_CLKDIV0_HCLK_MSYS_SHIFT	(8)
+#define S5PC110_CLKDIV0_PCLK_MSYS_MASK		(0x7<<12)
+#define S5PC110_CLKDIV0_PCLK_MSYS_SHIFT	(12)
+#define S5PC110_CLKDIV0_HCLK_DSYS_MASK		(0xf<<16)
+#define S5PC110_CLKDIV0_HCLK_DSYS_SHIFT	(16)
+#define S5PC110_CLKDIV0_PCLK_DSYS_MASK		(0x7<<20)
+#define S5PC110_CLKDIV0_PCLK_DSYS_SHIFT	(20)
+#define S5PC110_CLKDIV0_HCLK_PSYS_MASK		(0xf<<24)
+#define S5PC110_CLKDIV0_HCLK_PSYS_SHIFT	(24)
+#define S5PC110_CLKDIV0_PCLK_PSYS_MASK		(0x7<<28)
+#define S5PC110_CLKDIV0_PCLK_PSYS_SHIFT	(28)
+
+#define S5PC110_CLKDIV1_TBLK_MASK		(0xf<<0)
+#define S5PC110_CLKDIV1_TBLK_SHIFT		(0)
+#define S5PC110_CLKDIV1_FIMC_MASK		(0xf<<8)
+#define S5PC110_CLKDIV1_FIMC_SHIFT		(8)
+#define S5PC110_CLKDIV1_CAM0_MASK		(0xf<<12)
+#define S5PC110_CLKDIV1_CAM0_SHIFT		(12)
+#define S5PC110_CLKDIV1_CAM1_MASK		(0xf<<16)
+#define S5PC110_CLKDIV1_CAM1_SHIFT		(16)
+#define S5PC110_CLKDIV1_FIMD_MASK		(0xf<<20)
+#define S5PC110_CLKDIV1_FIMD_SHIFT		(20)
+#define S5PC110_CLKDIV1_CSIS_MASK		(0xf<<28)
+#define S5PC110_CLKDIV1_CSIS_SHIFT		(28)
+
+#define S5PC110_CLKDIV2_G3D_MASK		(0xf<<0)
+#define S5PC110_CLKDIV2_G3D_SHIFT		(0)
+#define S5PC110_CLKDIV2_MFC_MASK		(0xf<<4)
+#define S5PC110_CLKDIV2_MFC_SHIFT		(4)
+
+#define S5PC110_CLKDIV3_MDNIE_MASK		(0xf<<0)
+#define S5PC110_CLKDIV3_MDNIE_SHIFT		(0)
+#define S5PC110_CLKDIV3_MDNIE_PWM_MASK		(0x7f<<4)
+#define S5PC110_CLKDIV3_MDNIE_PWM_SHIFT	(4)
+#define S5PC110_CLKDIV3_FIMC0_LCLK_MASK	(0xf<<12)
+#define S5PC110_CLKDIV3_FIMC0_LCLK_SHIFT	(12)
+#define S5PC110_CLKDIV3_FIMC1_LCLK_MASK	(0xf<<16)
+#define S5PC110_CLKDIV3_FIMC1_LCLK_SHIFT	(16)
+#define S5PC110_CLKDIV3_FIMC2_LCLK_MASK	(0xf<<20)
+#define S5PC110_CLKDIV3_FIMC2_LCLK_SHIFT	(20)
+
+#define S5PC110_CLKDIV4_MMC0_MASK		(0xf<<0)
+#define S5PC110_CLKDIV4_MMC0_SHIFT		(0)
+#define S5PC110_CLKDIV4_MMC1_MASK		(0xf<<4)
+#define S5PC110_CLKDIV4_MMC1_SHIFT		(4)
+#define S5PC110_CLKDIV4_MMC2_MASK		(0xf<<8)
+#define S5PC110_CLKDIV4_MMC2_SHIFT		(8)
+#define S5PC110_CLKDIV4_MMC3_MASK		(0xf<<12)
+#define S5PC110_CLKDIV4_MMC3_SHIFT		(12)
+#define S5PC110_CLKDIV4_UART0_MASK		(0xf<<16)
+#define S5PC110_CLKDIV4_UART0_SHIFT		(16)
+#define S5PC110_CLKDIV4_UART1_MASK		(0xf<<20)
+#define S5PC110_CLKDIV4_UART1_SHIFT		(20)
+#define S5PC110_CLKDIV4_UART2_MASK		(0xf<<24)
+#define S5PC110_CLKDIV4_UART2_SHIFT		(24)
+#define S5PC110_CLKDIV4_UART3_MASK		(0xf<<28)
+#define S5PC110_CLKDIV4_UART3_SHIFT		(28)
+
+/* CLK_DIV5 */
+#define S5PC110_CLKDIV5_SPI0_MASK		(0xf<<0)
+#define S5PC110_CLKDIV5_SPI0_SHIFT		(0)
+#define S5PC110_CLKDIV5_SPI1_MASK		(0xf<<4)
+#define S5PC110_CLKDIV5_SPI1_SHIFT		(4)
+#define S5PC110_CLKDIV5_SPI2_MASK		(0xf<<8)
+#define S5PC110_CLKDIV5_SPI2_SHIFT		(8)
+#define S5PC110_CLKDIV5_PWM_MASK		(0xf<<120)
+#define S5PC110_CLKDIV5_PWM_SHIFT		(12)
+
+/* CLK_DIV6 */
+#define S5PC110_CLKDIV6_AUDIO0_MASK		(0xf<<0)
+#define S5PC110_CLKDIV6_AUDIO0_SHIFT		(0)
+#define S5PC110_CLKDIV6_AUDIO1_MASK		(0xf<<4)
+#define S5PC110_CLKDIV6_AUDIO1_SHIFT		(4)
+#define S5PC110_CLKDIV6_AUDIO2_MASK		(0xf<<8)
+#define S5PC110_CLKDIV6_AUDIO2_SHIFT		(8)
+#define S5PC110_CLKDIV6_ONENAND_MASK		(0x7<<12)
+#define S5PC110_CLKDIV6_ONENAND_SHIFT		(12)
+#define S5PC110_CLKDIV6_COPY_MASK		(0x7<<16)
+#define S5PC110_CLKDIV6_COPY_SHIFT		(16)
+#define S5PC110_CLKDIV6_HPM_MASK		(0x7<<20)
+#define S5PC110_CLKDIV6_HPM_SHIFT		(20)
+#define S5PC110_CLKDIV6_PWI_MASK		(0xf<<24)
+#define S5PC110_CLKDIV6_PWI_SHIFT		(24)
+#define S5PC110_CLKDIV6_ONEDRAM_MASK		(0xf<<28)
+#define S5PC110_CLKDIV6_ONEDRAM_SHIFT		(28)
+
+/* Clock Gate IP0 */
+#define S5PC110_CLKGATE_IP0_DMC0		(1<<0)
+#define S5PC110_CLKGATE_IP0_DMC1		(1<<1)
+#define S5PC110_CLKGATE_IP0_MDMA		(1<<2)
+#define S5PC110_CLKGATE_IP0_PDMA0		(1<<3)
+#define S5PC110_CLKGATE_IP0_PDMA1		(1<<4)
+#define S5PC110_CLKGATE_IP0_IMEM		(1<<5)
+#define S5PC110_CLKGATE_IP0_G3D			(1<<8)
+#define S5PC110_CLKGATE_IP0_MFC			(1<<16)
+#define S5PC110_CLKGATE_IP0_FIMC0		(1<<24)
+#define S5PC110_CLKGATE_IP0_FIMC1		(1<<25)
+#define S5PC110_CLKGATE_IP0_FIMC2		(1<<26)
+#define S5PC110_CLKGATE_IP0_JPEG		(1<<28)
+#define S5PC110_CLKGATE_IP0_ROTATOR		(1<<29)
+#define S5PC110_CLKGATE_IP0_IPC			(1<<30)
+#define S5PC110_CLKGATE_IP0_CSIS		(1<<31)
+
+/* Clock Gate IP1 */
+#define S5PC110_CLKGATE_IP1_FIMD		(1<<0)
+#define S5PC110_CLKGATE_IP1_MIE			(1<<1)
+#define S5PC110_CLKGATE_IP1_DSIM		(1<<2)
+#define S5PC110_CLKGATE_IP1_VP			(1<<8)
+#define S5PC110_CLKGATE_IP1_MIXER		(1<<9)
+#define S5PC110_CLKGATE_IP1_TVENC		(1<<10)
+#define S5PC110_CLKGATE_IP1_HDMI		(1<<11)
+#define S5PC110_CLKGATE_IP1_USBOTG		(1<<16)
+#define S5PC110_CLKGATE_IP1_USBHOST		(1<<17)
+#define S5PC110_CLKGATE_IP1_NANDXL		(1<<24)
+#define S5PC110_CLKGATE_IP1_CFCON		(1<<25)
+#define S5PC110_CLKGATE_IP1_SROMC		(1<<26)
+#define S5PC110_CLKGATE_IP1_NFCON		(1<<28)
+
+/* Clock Gate IP2 */
+#define S5PC110_CLKGATE_IP2_SECSS		(1<<0)
+#define S5PC110_CLKGATE_IP2_SDM			(1<<1)
+#define S5PC110_CLKGATE_IP2_CORESIGHT		(1<<8)
+#define S5PC110_CLKGATE_IP2_MODEM		(1<<9)
+#define S5PC110_CLKGATE_IP2_HOSTIF		(1<<10)
+#define S5PC110_CLKGATE_IP2_SECJTAG		(1<<11)
+#define S5PC110_CLKGATE_IP2_HSMMC0		(1<<16)
+#define S5PC110_CLKGATE_IP2_HSMMC1		(1<<17)
+#define S5PC110_CLKGATE_IP2_HSMMC2		(1<<18)
+#define S5PC110_CLKGATE_IP2_HSMMC3		(1<<19)
+#define S5PC110_CLKGATE_IP2_TSI			(1<<20)
+#define S5PC110_CLKGATE_IP2_VIC0		(1<<24)
+#define S5PC110_CLKGATE_IP2_VIC1		(1<<25)
+#define S5PC110_CLKGATE_IP2_VIC2		(1<<26)
+#define S5PC110_CLKGATE_IP2_VIC3		(1<<27)
+#define S5PC110_CLKGATE_IP2_TZIC0		(1<<28)
+#define S5PC110_CLKGATE_IP2_TZIC1		(1<<29)
+#define S5PC110_CLKGATE_IP2_TZIC2		(1<<30)
+#define S5PC110_CLKGATE_IP2_TZIC3		(1<<31)
+
+/* Clock Gate IP3 */
+#define S5PC110_CLKGATE_IP3_SPDIF		(1<<0)
+#define S5PC110_CLKGATE_IP3_AC97		(1<<1)
+#define S5PC110_CLKGATE_IP3_I2S0		(1<<4)
+#define S5PC110_CLKGATE_IP3_I2S1		(1<<5)
+#define S5PC110_CLKGATE_IP3_I2S2		(1<<6)
+#define S5PC110_CLKGATE_IP3_I2C0		(1<<7)
+#define S5PC110_CLKGATE_IP3_I2C1		(1<<8)
+#define S5PC110_CLKGATE_IP3_I2C2		(1<<9)
+#define S5PC110_CLKGATE_IP3_I2C_HDMI_DDC	(1<<10)
+#define S5PC110_CLKGATE_IP3_I2C_HDMI_PHY	(1<<11)
+#define S5PC110_CLKGATE_IP3_SPI0		(1<<12)
+#define S5PC110_CLKGATE_IP3_SPI1		(1<<13)
+#define S5PC110_CLKGATE_IP3_SPI2		(1<<14)
+#define S5PC110_CLKGATE_IP3_RTC			(1<<15)
+#define S5PC110_CLKGATE_IP3_SYSTIMER		(1<<16)
+#define S5PC110_CLKGATE_IP3_UART0		(1<<17)
+#define S5PC110_CLKGATE_IP3_UART1		(1<<18)
+#define S5PC110_CLKGATE_IP3_UART2		(1<<19)
+#define S5PC110_CLKGATE_IP3_UART3		(1<<20)
+#define S5PC110_CLKGATE_IP3_KEYIF		(1<<21)
+#define S5PC110_CLKGATE_IP3_WDT			(1<<22)
+#define S5PC110_CLKGATE_IP3_PWM			(1<<23)
+#define S5PC110_CLKGATE_IP3_TSADC		(1<<24)
+#define S5PC110_CLKGATE_IP3_GPIO		(1<<26)
+#define S5PC110_CLKGATE_IP3_SYSCON		(1<<27)
+#define S5PC110_CLKGATE_IP3_PCM0		(1<<28)
+#define S5PC110_CLKGATE_IP3_PCM1		(1<<29)
+#define S5PC110_CLKGATE_IP3_PCM2		(1<<30)
+
+/* Clock Gate IP4 */
+#define S5PC110_CLKGATE_IP4_CHIP_ID		(1<<0)
+#define S5PC110_CLKGATE_IP4_IEM_IEC		(1<<1)
+#define S5PC110_CLKGATE_IP4_IEM_APC		(1<<2)
+#define S5PC110_CLKGATE_IP4_SECKEY		(1<<3)
+#define S5PC110_CLKGATE_IP4_TZPC0		(1<<5)
+#define S5PC110_CLKGATE_IP4_TZPC1		(1<<6)
+#define S5PC110_CLKGATE_IP4_TZPC2		(1<<7)
+#define S5PC110_CLKGATE_IP4_TZPC3		(1<<8)
+
+#endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index 679e145..898cd82 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -50,6 +50,11 @@ config CPU_S5PC110_INIT
 	help
 	  Common initialisation code for the S5PC1XX
 
+config CPU_S5PC110_CLOCK
+	bool
+	help
+	  Common clock support code for the S5PC1XX
+
 # platform specific device setup
 
 endif
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
index 3e8ebf1..b03a983 100644
--- a/arch/arm/plat-s5pc1xx/Makefile
+++ b/arch/arm/plat-s5pc1xx/Makefile
@@ -21,6 +21,7 @@ obj-y				+= gpiolib.o
 obj-$(CONFIG_CPU_S5PC100_INIT)	+= s5pc100-init.o
 obj-$(CONFIG_CPU_S5PC100_CLOCK)	+= s5pc100-plls.o s5pc100-clocks.o
 obj-$(CONFIG_CPU_S5PC110_INIT)	+= s5pc110-init.o
+obj-$(CONFIG_CPU_S5PC110_CLOCK)	+= s5pc110-plls.o s5pc110-clocks.o
 
 # Device setup
 
diff --git a/arch/arm/plat-s5pc1xx/include/plat/pll.h b/arch/arm/plat-s5pc1xx/include/plat/pll.h
index 21afef1..7380d16 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/pll.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/pll.h
@@ -22,7 +22,7 @@
 #include <asm/div64.h>
 
 static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk,
-					    u32 pllcon)
+					    u32 pllcon, int sub)
 {
 	u32 mdiv, pdiv, sdiv;
 	u64 fvco = baseclk;
@@ -32,7 +32,11 @@ static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk,
 	sdiv = (pllcon >> S5P_PLL_SDIV_SHIFT) & S5P_PLL_SDIV_MASK;
 
 	fvco *= mdiv;
-	do_div(fvco, (pdiv << sdiv));
+
+	if (sub)
+		do_div(fvco, (pdiv << (sdiv - 1)));
+	else
+		do_div(fvco, (pdiv << sdiv));
 
 	return (unsigned long)fvco;
 }
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h
index 93c623b..86d4952 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h
@@ -26,6 +26,17 @@ extern void s5pc110_init_irq(void);
 extern void s5pc110_register_clocks(void);
 extern void s5pc110_setup_clocks(void);
 
+extern struct clk clk_hpll;
+extern struct clk clk_hd0;
+extern struct clk clk_pd0;
+extern struct clk clk_54m;
+extern struct clk clk_30m;
+extern int s5pc110_ip0_ctrl(struct clk *clk, int enable);
+extern int s5pc110_ip1_ctrl(struct clk *clk, int enable);
+extern int s5pc110_ip2_ctrl(struct clk *clk, int enable);
+extern int s5pc110_ip3_ctrl(struct clk *clk, int enable);
+extern int s5pc110_ip4_ctrl(struct clk *clk, int enable);
+
 #else
 
 #define s5pc110_map_io NULL
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-plls.c b/arch/arm/plat-s5pc1xx/s5pc100-plls.c
index 45f073e..b7559f8 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-plls.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-plls.c
@@ -1050,10 +1050,10 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
 
 	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 
-	apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON));
-	mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON));
-	epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON));
-	hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
+	apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON), 0);
+	mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON), 0);
+	epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON), 0);
+	hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON), 0);
 
 	printk(KERN_INFO "S5PC100: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz"
 		", Epll=%ld.%03ld Mhz, Hpll=%ld.%03ld Mhz\n",
diff --git a/arch/arm/plat-s5pc1xx/s5pc110-clocks.c b/arch/arm/plat-s5pc1xx/s5pc110-clocks.c
new file mode 100644
index 0000000..456bd5e
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/s5pc110-clocks.c
@@ -0,0 +1,254 @@
+/* linux/arch/arm/plat-s5pc1xx/s5pc110-clocks.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *
+ * S5PC110 - Clocks support
+ *
+ * Based on plat-s3c64xx/clock.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/regs-clock.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+
+struct clk clk_27m = {
+	.name		= "clk_27m",
+	.id		= -1,
+	.rate		= 27000000,
+};
+
+struct clk clk_48m = {
+	.name		= "clk_48m",
+	.id		= -1,
+	.rate		= 48000000,
+};
+
+struct clk clk_54m = {
+	.name		= "clk_54m",
+	.id		= -1,
+	.rate		= 54000000,
+};
+
+struct clk clk_30m = {
+	.name		= "clk_30m",
+	.id		= -1,
+	.rate		= 30000000,
+};
+
+static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
+{
+	unsigned int ctrlbit = clk->ctrlbit;
+	u32 con;
+
+	con = __raw_readl(reg);
+	if (enable)
+		con |= ctrlbit;
+	else
+		con &= ~ctrlbit;
+	__raw_writel(con, reg);
+
+	return 0;
+}
+
+int s5pc110_ip0_ctrl(struct clk *clk, int enable)
+{
+	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP0, clk, enable);
+}
+
+int s5pc110_ip1_ctrl(struct clk *clk, int enable)
+{
+	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP1, clk, enable);
+}
+
+int s5pc110_ip2_ctrl(struct clk *clk, int enable)
+{
+	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP2, clk, enable);
+}
+
+int s5pc110_ip3_ctrl(struct clk *clk, int enable)
+{
+	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP3, clk, enable);
+}
+
+int s5pc110_ip4_ctrl(struct clk *clk, int enable)
+{
+	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP4, clk, enable);
+}
+
+extern struct clk clk_dout_hclkm;
+extern struct clk clk_dout_hclkd;
+extern struct clk clk_dout_hclkp;
+extern struct clk clk_dout_pclkd;
+extern struct clk clk_dout_pclkp;
+
+static struct clk s5pc110_init_clocks_disable[] = {
+	{
+		.name		= "keypad",
+		.id		= -1,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_KEYIF,
+	},
+};
+
+static struct clk s5pc110_init_clocks[] = {
+	/* IP0 */
+	{
+		.name		= "mfc",
+		.id		= -1,
+		.parent		= NULL,
+		.enable		= s5pc110_ip0_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP0_MFC,
+	},
+
+	/* IP1 */
+	{
+		.name		= "lcd",
+		.id		= -1,
+		.parent		= &clk_dout_hclkd,
+		.enable		= s5pc110_ip1_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP1_FIMD,
+	}, {
+		.name		= "otg",
+		.id		= -1,
+		.parent		= &clk_dout_hclkp,
+		.enable		= s5pc110_ip1_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP1_USBOTG,
+	},
+
+	/* IP2 */
+	{
+		.name		= "hsmmc",
+		.id		= 0,
+		.parent		= &clk_dout_hclkp,
+		.enable		= s5pc110_ip2_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC0,
+	}, {
+		.name		= "hsmmc",
+		.id		= 1,
+		.parent		= &clk_dout_hclkp,
+		.enable		= s5pc110_ip2_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC1,
+	}, {
+		.name		= "hsmmc",
+		.id		= 2,
+		.parent		= &clk_dout_hclkp,
+		.enable		= s5pc110_ip2_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC2,
+	}, {
+		.name		= "hsmmc",
+		.id		= 3,
+		.parent		= &clk_dout_hclkp,
+		.enable		= s5pc110_ip2_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC3,
+	},
+	/* IP3 */
+	{
+		.name           = "iis",
+		.id             = 0,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_I2S0,
+	}, {
+		.name           = "iis",
+		.id             = 1,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_I2S1,
+	}, {
+		.name           = "iis",
+		.id             = 2,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_I2S2,
+	}, {
+		.name		= "i2c",
+		.id		= 0,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_I2C0,
+	}, {
+		.name		= "i2c",
+		.id		= 1,
+		.parent		= &clk_dout_pclkd,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_I2C1,
+	}, {
+		.name		= "i2c",
+		.id		= 2,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_I2C2,
+	}, {
+		.name		= "timers",
+		.id		= -1,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_PWM,
+	}, {
+		.name		= "adc",
+		.id		= -1,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_TSADC,
+	},
+};
+
+static struct clk *clks[] __initdata = {
+	&clk_ext,
+	&clk_epll,
+	&clk_27m,
+	&clk_30m,
+	&clk_48m,
+	&clk_54m,
+};
+
+void __init s5pc1xx_register_clocks(void)
+{
+	struct clk *clkp;
+	int ret;
+	int ptr;
+	int size;
+
+	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+
+	clkp = s5pc110_init_clocks;
+	size = ARRAY_SIZE(s5pc110_init_clocks);
+
+	for (ptr = 0; ptr < size; ptr++, clkp++) {
+		ret = s3c24xx_register_clock(clkp);
+		if (ret < 0) {
+			printk(KERN_ERR "Failed to register clock %s (%d)\n",
+			       clkp->name, ret);
+		}
+	}
+
+	clkp = s5pc110_init_clocks_disable;
+	size = ARRAY_SIZE(s5pc110_init_clocks_disable);
+
+	for (ptr = 0; ptr < size; ptr++, clkp++) {
+		ret = s3c24xx_register_clock(clkp);
+		if (ret < 0) {
+			printk(KERN_ERR "Failed to register clock %s (%d)\n",
+			       clkp->name, ret);
+		}
+
+		(clkp->enable)(clkp, 0);
+	}
+
+	s3c_pwmclk_init();
+}
diff --git a/arch/arm/plat-s5pc1xx/s5pc110-plls.c b/arch/arm/plat-s5pc1xx/s5pc110-plls.c
new file mode 100644
index 0000000..05ac43c
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/s5pc110-plls.c
@@ -0,0 +1,1288 @@
+/*
+ * linux/arch/arm/plat-s5pc1xx/s5pc110-plls.c
+ *
+ * Copyright 2009 Samsung Electronics, Co.
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * S5PC110 based common clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/cpu-freq.h>
+
+#include <plat/regs-clock.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/devs.h>
+#include <plat/s5pc1xx.h>
+
+static struct clk clk_ext_xtal_mux = {
+	.name		= "ext_xtal",
+	.id		= -1,
+};
+
+#define clk_fin_apll	clk_ext_xtal_mux
+#define clk_fin_mpll	clk_ext_xtal_mux
+#define clk_fin_epll	clk_ext_xtal_mux
+#define clk_fin_vpll	clk_ext_xtal_mux
+#define clk_hdmi_phy	clk_ext_xtal_mux
+
+#define clk_fout_mpll	clk_mpll
+#define clk_hdmi_27m	clk_27m
+#define clk_usbphy0	clk_30m
+#define clk_usbphy1	clk_48m
+
+static struct clk clk_usb_xtal = {
+	.name		= "usb_xtal",
+	.id		= -1,
+};
+
+static struct clk clk_pcm_cd0 = {
+	.name		= "pcm_cdclk0",
+	.id		= -1,
+};
+
+static struct clk clk_pcm_cd1 = {
+	.name		= "pcm_cdclk1",
+	.id		= -1,
+};
+
+static struct clk clk_iis_cd1 = {
+	.name		= "iis_cdclk1",
+	.id		= -1,
+};
+
+struct clk_sources {
+	unsigned int	nr_sources;
+	struct clk	**sources;
+};
+
+struct clksrc_clk {
+	struct clk		clk;
+	unsigned int		mask;
+	unsigned int		shift;
+
+	struct clk_sources	*sources;
+
+	unsigned int		divider_shift;
+	void __iomem		*reg_divider;
+	void __iomem		*reg_source;
+};
+
+/* APLL */
+static struct clk clk_fout_apll = {
+	.name		= "fout_apll",
+	.id		= -1,
+};
+
+static struct clk *clk_src_apll_list[] = {
+	[0] = &clk_fin_apll,
+	[1] = &clk_fout_apll,
+};
+
+static struct clk_sources clk_src_apll = {
+	.sources	= clk_src_apll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),
+};
+
+static struct clksrc_clk clk_mout_apll = {
+	.clk	= {
+		.name		= "mout_apll",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_APLL_SHIFT,
+	.mask		= S5PC110_CLKSRC0_APLL_MASK,
+	.sources	= &clk_src_apll,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+/* MPLL */
+static struct clk *clk_src_mpll_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &clk_fout_mpll,
+};
+
+static struct clk_sources clk_src_mpll = {
+	.sources	= clk_src_mpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_mpll_list),
+};
+
+static struct clksrc_clk clk_mout_mpll = {
+	.clk = {
+		.name		= "mout_mpll",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_MPLL_SHIFT,
+	.mask		= S5PC110_CLKSRC0_MPLL_MASK,
+	.sources	= &clk_src_mpll,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+static int s5pc110_default_enable(struct clk *clk, int enable)
+{
+	return 0;
+}
+
+/* EPLL */
+static struct clk clk_fout_epll = {
+	.name		= "fout_epll",
+	.id		= -1,
+	.enable		= s5pc110_default_enable,
+};
+
+static struct clk *clk_src_epll_list[] = {
+	[0] = &clk_fin_epll,
+	[1] = &clk_fout_epll,
+};
+
+static struct clk_sources clk_src_epll = {
+	.sources	= clk_src_epll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_epll_list),
+};
+
+static struct clksrc_clk clk_mout_epll = {
+	.clk = {
+		.name		= "mout_epll",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_EPLL_SHIFT,
+	.mask		= S5PC110_CLKSRC0_EPLL_MASK,
+	.sources	= &clk_src_epll,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+/* VPLLSRC */
+static struct clk *clk_src_vpllsrc_list[] = {
+	[0] = &clk_fin_vpll,
+	[1] = &clk_hdmi_27m,
+};
+
+static struct clk_sources clk_src_vpllsrc = {
+	.sources	= clk_src_vpllsrc_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_vpllsrc_list),
+};
+
+static struct clksrc_clk clk_mout_vpllsrc = {
+	.clk = {
+		.name		= "mout_vpllsrc",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC1_VPLLSRC_SHIFT,
+	.mask		= S5PC110_CLKSRC1_VPLLSRC_MASK,
+	.sources	= &clk_src_vpllsrc,
+	.reg_source	= S5PC110_CLKSRC1,
+};
+
+/* VPLL */
+static struct clk clk_fout_vpll = {
+	.name		= "fout_vpll",
+	.id		= -1,
+};
+
+static struct clk *clk_src_vpll_list[] = {
+	[0] = &clk_mout_vpllsrc.clk,
+	[1] = &clk_fout_vpll,
+};
+
+static struct clk_sources clk_src_vpll = {
+	.sources	= clk_src_vpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_vpll_list),
+};
+
+static struct clksrc_clk clk_mout_vpll = {
+	.clk = {
+		.name		= "mout_vpll",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_VPLL_SHIFT,
+	.mask		= S5PC110_CLKSRC0_VPLL_MASK,
+	.sources	= &clk_src_vpll,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+/* Dout A2M */
+static unsigned long s5pc110_clk_dout_a2m_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_A2M_MASK;
+	ratio >>= S5PC110_CLKDIV0_A2M_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+static struct clk clk_dout_a2m = {
+	.name		= "dout_a2m",
+	.id		= -1,
+	.parent		= &clk_mout_apll.clk,
+	.get_rate	= s5pc110_clk_dout_a2m_get_rate,
+};
+
+/* HPM */
+static struct clk *clk_src_hpm_list[] = {
+	[0] = &clk_mout_apll.clk,
+	[1] = &clk_mout_mpll.clk,
+};
+
+static struct clk_sources clk_src_hpm = {
+	.sources	= clk_src_hpm_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_hpm_list),
+};
+
+static struct clksrc_clk clk_mout_hpm = {
+	.clk = {
+		.name		= "mout_hpm",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC6_HPM_SHIFT,
+	.mask		= S5PC110_CLKSRC6_HPM_MASK,
+	.sources	= &clk_src_hpm,
+	.reg_source	= S5PC110_CLKSRC6,
+};
+
+/* MSYS */
+static struct clk *clk_src_msys_list[] = {
+	[0] = &clk_mout_apll.clk,
+	[1] = &clk_mout_mpll.clk,
+};
+
+static struct clk_sources clk_src_msys = {
+	.sources	= clk_src_msys_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_msys_list),
+};
+
+static struct clksrc_clk clk_mout_msys = {
+	.clk = {
+		.name		= "mout_msys",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_MUX200_SHIFT,
+	.mask		= S5PC110_CLKSRC0_MUX200_MASK,
+	.sources	= &clk_src_msys,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+/* DSYS */
+static struct clk *clk_src_dsys_list[] = {
+	[0] = &clk_mout_mpll.clk,
+	[1] = &clk_dout_a2m,
+};
+
+static struct clk_sources clk_src_dsys = {
+	.sources	= clk_src_dsys_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_dsys_list),
+};
+
+struct clksrc_clk clk_mout_dsys = {
+	.clk = {
+		.name		= "mout_dsys",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_MUX166_SHIFT,
+	.mask		= S5PC110_CLKSRC0_MUX166_MASK,
+	.sources	= &clk_src_dsys,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+/* PSYS */
+static struct clk *clk_src_psys_list[] = {
+	[0] = &clk_mout_mpll.clk,
+	[1] = &clk_dout_a2m,
+};
+
+static struct clk_sources clk_src_psys = {
+	.sources	= clk_src_psys_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_psys_list),
+};
+
+static struct clksrc_clk clk_mout_psys = {
+	.clk = {
+		.name		= "mout_psys",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_MUX133_SHIFT,
+	.mask		= S5PC110_CLKSRC0_MUX133_MASK,
+	.sources	= &clk_src_psys,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+/* Dout COPY */
+static unsigned long s5pc110_clk_dout_copy_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV6) & S5PC110_CLKDIV6_COPY_MASK;
+	ratio >>= S5PC110_CLKDIV6_COPY_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+static struct clk clk_dout_copy = {
+	.name		= "dout_copy",
+	.id		= -1,
+	.parent		= &clk_mout_hpm.clk,
+	.get_rate	= s5pc110_clk_dout_copy_get_rate,
+};
+
+/* Dout HPM */
+static unsigned long s5pc110_clk_dout_hpm_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV6) & S5PC110_CLKDIV6_HPM_MASK;
+	ratio >>= S5PC110_CLKDIV6_HPM_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+static struct clk clk_dout_hpm = {
+	.name		= "dout_hpm",
+	.id		= -1,
+	.parent		= &clk_dout_copy,
+	.get_rate	= s5pc110_clk_dout_hpm_get_rate,
+};
+
+/* Dout APLL - ARMCLK */
+static unsigned long s5pc110_clk_dout_apll_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_APLL_MASK;
+	ratio >>= S5PC110_CLKDIV0_APLL_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+static struct clk clk_dout_apll = {
+	.name		= "dout_apll",
+	.id		= -1,
+	.parent		= &clk_mout_msys.clk,
+	.get_rate	= s5pc110_clk_dout_apll_get_rate,
+};
+
+/* Dout HCLKM - ACLK200, HCLK_MSYS */
+static unsigned long s5pc110_clk_dout_hclkm_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_HCLK_MSYS_MASK;
+	ratio >>= S5PC110_CLKDIV0_HCLK_MSYS_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+struct clk clk_dout_hclkm = {
+	.name		= "dout_hclkm",
+	.id		= -1,
+	.parent		= &clk_dout_apll,
+	.get_rate	= s5pc110_clk_dout_hclkm_get_rate,
+};
+
+/* Dout PCLKM - PCLK_MSYS */
+static unsigned long s5pc110_clk_dout_pclkm_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_PCLK_MSYS_MASK;
+	ratio >>= S5PC110_CLKDIV0_HCLK_PSYS_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+struct clk clk_dout_pclkm = {
+	.name		= "dout_pclkm",
+	.id		= -1,
+	.parent		= &clk_dout_hclkm,
+	.get_rate	= s5pc110_clk_dout_pclkm_get_rate,
+};
+
+/* Dout IMEM - HCLK100 */
+static unsigned long s5pc110_clk_dout_imem_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	return rate / 2;
+}
+
+static struct clk clk_dout_imem = {
+	.name		= "dout_imem",
+	.id		= -1,
+	.parent		= &clk_dout_hclkm,
+	.get_rate	= s5pc110_clk_dout_imem_get_rate,
+};
+
+/* Dout HCLKD - HCLK_DSYS */
+static unsigned long s5pc110_clk_dout_hclkd_get_rate(struct clk *clk)
+{
+	unsigned long rate;
+	unsigned int ratio;
+
+	rate = clk_get_rate(clk->parent);
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_HCLK_DSYS_MASK;
+	ratio >>= S5PC110_CLKDIV0_HCLK_DSYS_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+struct clk clk_dout_hclkd = {
+	.name		= "dout_hclkd",
+	.id		= -1,
+	.parent		= &clk_mout_dsys.clk,
+	.get_rate	= s5pc110_clk_dout_hclkd_get_rate,
+};
+
+/* Dout PCLKD - PCLK_DSYS */
+static unsigned long s5pc110_clk_dout_pclkd_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_PCLK_DSYS_MASK;
+	ratio >>= S5PC110_CLKDIV0_PCLK_DSYS_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+struct clk clk_dout_pclkd = {
+	.name		= "dout_pclkd",
+	.id		= -1,
+	.parent		= &clk_dout_hclkd,
+	.get_rate	= s5pc110_clk_dout_pclkd_get_rate,
+};
+
+/* Dout FIMC - SCLK_FIMC */
+static unsigned long s5pc110_clk_dout_fimc_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV1) & S5PC110_CLKDIV1_FIMC_MASK;
+	ratio >>= S5PC110_CLKDIV1_FIMC_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+static struct clk clk_dout_fimc = {
+	.name		= "dout_fimc",
+	.id		= -1,
+	.parent		= &clk_mout_dsys.clk,
+	.get_rate	= s5pc110_clk_dout_fimc_get_rate,
+};
+
+/* Dout HCLKP - ARMATCLK, HCLK_PSYS */
+static unsigned long s5pc110_clk_dout_hclkp_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_HCLK_PSYS_MASK;
+	ratio >>= S5PC110_CLKDIV0_HCLK_PSYS_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+struct clk clk_dout_hclkp = {
+	.name		= "dout_hclkp",
+	.id		= -1,
+	.parent		= &clk_mout_psys.clk,
+	.get_rate	= s5pc110_clk_dout_hclkp_get_rate,
+};
+
+/* Dout PCLKD - PCLK_DSYS */
+static unsigned long s5pc110_clk_dout_pclkp_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_PCLK_PSYS_MASK;
+	ratio >>= S5PC110_CLKDIV0_PCLK_PSYS_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+struct clk clk_dout_pclkp = {
+	.name		= "dout_pclkp",
+	.id		= -1,
+	.parent		= &clk_dout_hclkp,
+	.get_rate	= s5pc110_clk_dout_pclkp_get_rate,
+};
+
+/* FLASH */
+static struct clk *clk_src_onenand_list[] = {
+	[0] = &clk_dout_hclkd,
+	[1] = &clk_dout_hclkp,
+};
+
+static struct clk_sources clk_src_onenand = {
+	.sources	= clk_src_onenand_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_onenand_list),
+};
+
+static struct clksrc_clk clk_mout_onenand = {
+	.clk = {
+		.name		= "mout_onenand",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_ONENAND_SHIFT,
+	.mask		= S5PC110_CLKSRC0_ONENAND_MASK,
+	.sources	= &clk_src_onenand,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+/* Dout FLASH - SCLK_ONENAND */
+static unsigned long s5pc110_clk_dout_onenand_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV6) & S5PC110_CLKDIV6_ONENAND_MASK;
+	ratio >>= S5PC110_CLKDIV6_ONENAND_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+static struct clk clk_dout_onenand = {
+	.name		= "dout_onenand",
+	.id		= -1,
+	.parent		= &clk_mout_onenand.clk,
+	.get_rate	= s5pc110_clk_dout_onenand_get_rate,
+};
+
+/* Dout FLASH2 - SCLK_ONENAND2 */
+static unsigned long s5pc110_clk_dout_onenand2_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	return rate / 2;
+}
+
+static struct clk clk_dout_onenand2 = {
+	.name		= "dout_onenand2",
+	.id		= -1,
+	.parent		= &clk_dout_onenand,
+	.get_rate	= s5pc110_clk_dout_onenand2_get_rate,
+};
+
+/* Peripherals */
+static inline struct clksrc_clk *to_clksrc(struct clk *clk)
+{
+	return container_of(clk, struct clksrc_clk, clk);
+}
+
+static unsigned long s5pc110_getrate_clksrc(struct clk *clk)
+{
+	struct clksrc_clk *sclk = to_clksrc(clk);
+	unsigned long rate = clk_get_rate(clk->parent);
+	u32 clkdiv = __raw_readl(sclk->reg_divider);
+
+	clkdiv >>= sclk->divider_shift;
+	clkdiv &= 0xf;
+	clkdiv++;
+
+	rate /= clkdiv;
+	return rate;
+}
+
+static int s5pc110_setrate_clksrc(struct clk *clk, unsigned long rate)
+{
+	struct clksrc_clk *sclk = to_clksrc(clk);
+	void __iomem *reg = sclk->reg_divider;
+	unsigned int div;
+	u32 val;
+
+	rate = clk_round_rate(clk, rate);
+	div = clk_get_rate(clk->parent) / rate;
+	if (div > 16)
+		return -EINVAL;
+
+	val = __raw_readl(reg);
+	val &= ~(0xf << sclk->divider_shift);
+	val |= (div - 1) << sclk->divider_shift;
+	__raw_writel(val, reg);
+
+	return 0;
+}
+
+static int s5pc110_setparent_clksrc(struct clk *clk, struct clk *parent)
+{
+	struct clksrc_clk *sclk = to_clksrc(clk);
+	struct clk_sources *srcs = sclk->sources;
+	u32 clksrc = __raw_readl(sclk->reg_source);
+	int src_nr = -1;
+	int ptr;
+
+	for (ptr = 0; ptr < srcs->nr_sources; ptr++) {
+		if (srcs->sources[ptr] == parent) {
+			src_nr = ptr;
+			break;
+		}
+	}
+
+	if (src_nr >= 0) {
+		clksrc &= ~sclk->mask;
+		clksrc |= src_nr << sclk->shift;
+
+		__raw_writel(clksrc, sclk->reg_source);
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+static unsigned long s5pc110_roundrate_clksrc(struct clk *clk,
+					      unsigned long rate)
+{
+	unsigned long parent_rate = clk_get_rate(clk->parent);
+	int div;
+
+	if (rate > parent_rate)
+		rate = parent_rate;
+	else {
+		div = parent_rate / rate;
+
+		if (div == 0)
+			div = 1;
+		if (div > 16)
+			div = 16;
+
+		rate = parent_rate / div;
+	}
+
+	return rate;
+}
+
+static struct clk *clkset_default_list[] = {
+	&clk_fin_apll,
+	&clk_usb_xtal,
+	&clk_hdmi_27m,
+	&clk_usbphy0,
+	&clk_usbphy1,
+	&clk_hdmi_phy,
+	&clk_mout_mpll.clk,
+	&clk_mout_epll.clk,
+	&clk_mout_vpll.clk,
+};
+
+
+/* CAM */
+static struct clk_sources clkset_cam = {
+	.sources	= clkset_default_list,
+	.nr_sources	= ARRAY_SIZE(clkset_default_list),
+};
+
+static struct clksrc_clk clk_cam0 = {
+	.clk	= {
+		.name		= "cam",
+		.id		= 0,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC1_CAM0_SHIFT,
+	.mask		= S5PC110_CLKSRC1_CAM0_MASK,
+	.sources	= &clkset_cam,
+	.divider_shift	= S5PC110_CLKDIV1_CAM0_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV1,
+	.reg_source	= S5PC110_CLKSRC1,
+};
+
+static struct clksrc_clk clk_cam1 = {
+	.clk	= {
+		.name		= "cam",
+		.id		= 1,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC1_CAM1_SHIFT,
+	.mask		= S5PC110_CLKSRC1_CAM1_MASK,
+	.sources	= &clkset_cam,
+	.divider_shift	= S5PC110_CLKDIV1_CAM1_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV1,
+	.reg_source	= S5PC110_CLKSRC1,
+};
+
+/* FIMD */
+static struct clk_sources clkset_fimd = {
+	.sources	= clkset_default_list,
+	.nr_sources	= ARRAY_SIZE(clkset_default_list),
+};
+
+static struct clksrc_clk clk_fimd = {
+	.clk	= {
+		.name		= "fimd",
+		.id		= -1,
+		.ctrlbit	= S5PC110_CLKGATE_IP1_FIMD,
+		.enable		= s5pc110_ip1_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC1_FIMD_SHIFT,
+	.mask		= S5PC110_CLKSRC1_FIMD_MASK,
+	.sources	= &clkset_fimd,
+	.divider_shift	= S5PC110_CLKDIV1_FIMD_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV1,
+	.reg_source	= S5PC110_CLKSRC1,
+};
+
+/* MMC */
+static struct clk_sources clkset_mmc = {
+	.sources	= clkset_default_list,
+	.nr_sources	= ARRAY_SIZE(clkset_default_list),
+};
+
+static struct clksrc_clk clk_mmc0 = {
+	.clk	= {
+		.name		= "mmc-bus",
+		.id		= 0,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC0,
+		.enable		= s5pc110_ip2_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_MMC0_SHIFT,
+	.mask		= S5PC110_CLKSRC4_MMC0_MASK,
+	.sources	= &clkset_mmc,
+	.divider_shift	= S5PC110_CLKDIV4_MMC0_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+static struct clksrc_clk clk_mmc1 = {
+	.clk	= {
+		.name		= "mmc-bus",
+		.id		= 1,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC1,
+		.enable		= s5pc110_ip2_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_MMC1_SHIFT,
+	.mask		= S5PC110_CLKSRC4_MMC1_MASK,
+	.sources	= &clkset_mmc,
+	.divider_shift	= S5PC110_CLKDIV4_MMC1_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+static struct clksrc_clk clk_mmc2 = {
+	.clk	= {
+		.name		= "mmc-bus",
+		.id		= 2,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC2,
+		.enable		= s5pc110_ip2_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_MMC2_SHIFT,
+	.mask		= S5PC110_CLKSRC4_MMC2_MASK,
+	.sources	= &clkset_mmc,
+	.divider_shift	= S5PC110_CLKDIV4_MMC2_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+static struct clksrc_clk clk_mmc3 = {
+	.clk	= {
+		.name		= "mmc-bus",
+		.id		= 3,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC3,
+		.enable		= s5pc110_ip2_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_MMC3_SHIFT,
+	.mask		= S5PC110_CLKSRC4_MMC3_MASK,
+	.sources	= &clkset_mmc,
+	.divider_shift	= S5PC110_CLKDIV4_MMC3_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+/* AUDIO0 */
+static struct clk_sources clkset_audio0 = {
+	.sources	= clkset_default_list,
+	.nr_sources	= ARRAY_SIZE(clkset_default_list),
+};
+
+static struct clksrc_clk clk_audio0 = {
+	.clk	= {
+		.name		= "audio-bus",
+		.id		= 0,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC6_AUDIO0_SHIFT,
+	.mask		= S5PC110_CLKSRC6_AUDIO0_MASK,
+	.sources	= &clkset_audio0,
+	.divider_shift	= S5PC110_CLKDIV6_AUDIO0_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV6,
+	.reg_source	= S5PC110_CLKSRC6,
+};
+
+/* AUDIO1 */
+static struct clk *clkset_audio1_list[] = {
+	&clk_iis_cd1,
+	&clk_pcm_cd1,
+	&clk_hdmi_27m,
+	&clk_usbphy0,
+	&clk_usbphy1,
+	&clk_hdmi_phy,
+	&clk_mout_mpll.clk,
+	&clk_mout_epll.clk,
+	&clk_mout_vpll.clk,
+};
+
+static struct clk_sources clkset_audio1 = {
+	.sources	= clkset_audio1_list,
+	.nr_sources	= ARRAY_SIZE(clkset_audio1_list),
+};
+
+static struct clksrc_clk clk_audio1 = {
+	.clk	= {
+		.name		= "audio-bus",
+		.id		= 1,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC6_AUDIO1_SHIFT,
+	.mask		= S5PC110_CLKSRC6_AUDIO1_MASK,
+	.sources	= &clkset_audio1,
+	.divider_shift	= S5PC110_CLKDIV6_AUDIO1_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV6,
+	.reg_source	= S5PC110_CLKSRC6,
+};
+
+/* AUDIO2 */
+static struct clk *clkset_audio2_list[] = {
+	&clk_fin_apll,
+	&clk_pcm_cd0,
+	&clk_hdmi_27m,
+	&clk_usbphy0,
+	&clk_usbphy1,
+	&clk_hdmi_phy,
+	&clk_mout_mpll.clk,
+	&clk_mout_epll.clk,
+	&clk_mout_vpll.clk,
+};
+
+static struct clk_sources clkset_audio2 = {
+	.sources	= clkset_audio2_list,
+	.nr_sources	= ARRAY_SIZE(clkset_audio2_list),
+};
+
+static struct clksrc_clk clk_audio2 = {
+	.clk	= {
+		.name		= "audio-bus",
+		.id		= 2,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC6_AUDIO2_SHIFT,
+	.mask		= S5PC110_CLKSRC6_AUDIO2_MASK,
+	.sources	= &clkset_audio2,
+	.divider_shift	= S5PC110_CLKDIV6_AUDIO2_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV6,
+	.reg_source	= S5PC110_CLKSRC6,
+};
+
+/* FIMC */
+static struct clk_sources clkset_fimc = {
+	.sources	= clkset_default_list,
+	.nr_sources	= ARRAY_SIZE(clkset_default_list),
+};
+
+static struct clksrc_clk clk_fimc0 = {
+	.clk	= {
+		.name		= "fimc",
+		.id		= 0,
+		.ctrlbit	= S5PC110_CLKGATE_IP0_FIMC0,
+		.enable		= s5pc110_ip0_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC3_FIMC0_LCLK_SHIFT,
+	.mask		= S5PC110_CLKSRC3_FIMC0_LCLK_MASK,
+	.sources	= &clkset_fimc,
+	.divider_shift	= S5PC110_CLKDIV3_FIMC0_LCLK_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV3,
+	.reg_source	= S5PC110_CLKSRC3,
+};
+
+static struct clksrc_clk clk_fimc1 = {
+	.clk	= {
+		.name		= "fimc",
+		.id		= 1,
+		.ctrlbit	= S5PC110_CLKGATE_IP0_FIMC1,
+		.enable		= s5pc110_ip0_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC3_FIMC1_LCLK_SHIFT,
+	.mask		= S5PC110_CLKSRC3_FIMC1_LCLK_MASK,
+	.sources	= &clkset_fimc,
+	.divider_shift	= S5PC110_CLKDIV3_FIMC1_LCLK_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV3,
+	.reg_source	= S5PC110_CLKSRC3,
+};
+
+static struct clksrc_clk clk_fimc2 = {
+	.clk	= {
+		.name		= "fimc",
+		.id		= 2,
+		.ctrlbit	= S5PC110_CLKGATE_IP0_FIMC2,
+		.enable		= s5pc110_ip0_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC3_FIMC2_LCLK_SHIFT,
+	.mask		= S5PC110_CLKSRC3_FIMC2_LCLK_MASK,
+	.sources	= &clkset_fimc,
+	.divider_shift	= S5PC110_CLKDIV3_FIMC2_LCLK_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV3,
+	.reg_source	= S5PC110_CLKSRC3,
+};
+
+/* UART */
+static struct clk_sources clkset_uart = {
+	.sources	= clkset_default_list,
+	.nr_sources	= ARRAY_SIZE(clkset_default_list),
+};
+
+static struct clksrc_clk clk_uart0 = {
+	.clk	= {
+		.name		= "uart",
+		.id		= 0,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_UART0,
+		.enable		= s5pc110_ip3_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_UART0_SHIFT,
+	.mask		= S5PC110_CLKSRC4_UART0_MASK,
+	.sources	= &clkset_uart,
+	.divider_shift	= S5PC110_CLKDIV4_UART0_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+static struct clksrc_clk clk_uart1 = {
+	.clk	= {
+		.name		= "uart",
+		.id		= 1,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_UART1,
+		.enable		= s5pc110_ip3_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_UART1_SHIFT,
+	.mask		= S5PC110_CLKSRC4_UART1_MASK,
+	.sources	= &clkset_uart,
+	.divider_shift	= S5PC110_CLKDIV4_UART1_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+static struct clksrc_clk clk_uart2 = {
+	.clk	= {
+		.name		= "uart",
+		.id		= 2,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_UART2,
+		.enable		= s5pc110_ip3_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_UART2_SHIFT,
+	.mask		= S5PC110_CLKSRC4_UART2_MASK,
+	.sources	= &clkset_uart,
+	.divider_shift	= S5PC110_CLKDIV4_UART2_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+static struct clksrc_clk clk_uart3 = {
+	.clk	= {
+		.name		= "uart",
+		.id		= 3,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_UART3,
+		.enable		= s5pc110_ip3_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_UART3_SHIFT,
+	.mask		= S5PC110_CLKSRC4_UART3_MASK,
+	.sources	= &clkset_uart,
+	.divider_shift	= S5PC110_CLKDIV4_UART3_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+/* PWM */
+static struct clk_sources clkset_pwm = {
+	.sources	= clkset_default_list,
+	.nr_sources	= ARRAY_SIZE(clkset_default_list),
+};
+
+static struct clksrc_clk clk_pwm = {
+	.clk	= {
+		.name		= "pwm",
+		.id		= -1,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_PWM,
+		.enable		= s5pc110_ip3_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC5_PWM_SHIFT,
+	.mask		= S5PC110_CLKSRC5_PWM_MASK,
+	.sources	= &clkset_pwm,
+	.divider_shift	= S5PC110_CLKDIV5_PWM_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV5,
+	.reg_source	= S5PC110_CLKSRC5,
+};
+
+/* Clock initialisation code */
+static struct clksrc_clk *init_parents[] = {
+	&clk_mout_apll,
+	&clk_mout_mpll,
+	&clk_mout_epll,
+	&clk_mout_vpllsrc,
+	&clk_mout_vpll,
+	&clk_mout_hpm,
+	&clk_mout_msys,
+	&clk_mout_dsys,
+	&clk_mout_psys,
+	&clk_mout_onenand,
+	&clk_cam0,
+	&clk_cam1,
+	&clk_fimd,
+	&clk_mmc0,
+	&clk_mmc1,
+	&clk_mmc2,
+	&clk_mmc3,
+	&clk_audio0,
+	&clk_audio1,
+	&clk_audio2,
+	&clk_fimc0,
+	&clk_fimc1,
+	&clk_fimc2,
+	&clk_uart0,
+	&clk_uart1,
+	&clk_uart2,
+	&clk_uart3,
+	&clk_pwm,
+};
+
+static void __init_or_cpufreq s5pc110_set_clksrc(struct clksrc_clk *clk)
+{
+	struct clk_sources *srcs = clk->sources;
+	u32 clksrc = __raw_readl(clk->reg_source);
+
+	clksrc &= clk->mask;
+	clksrc >>= clk->shift;
+
+	if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
+		printk(KERN_ERR "%s: bad source %d\n",
+		       clk->clk.name, clksrc);
+		return;
+	}
+
+	clk->clk.parent = srcs->sources[clksrc];
+
+	printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n",
+		clk->clk.name, clk->clk.parent->name, clksrc,
+		print_mhz(clk_get_rate(&clk->clk)));
+}
+
+#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
+
+void __init_or_cpufreq s5pc110_setup_clocks(void)
+{
+	struct clk *xtal_clk;
+	unsigned long xtal;
+	unsigned long armclk;
+	unsigned long hclk_msys, hclk_dsys, hclk_psys;
+	unsigned long pclk_msys, pclk_dsys, pclk_psys;
+	unsigned long apll, mpll, epll, vpll;
+	unsigned int clkdiv0;
+	unsigned int ptr;
+
+	printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+	clkdiv0 = __raw_readl(S5PC110_CLKDIV0);
+
+	printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
+
+	xtal_clk = clk_get(NULL, "xtal");
+	BUG_ON(IS_ERR(xtal_clk));
+
+	xtal = clk_get_rate(xtal_clk);
+	clk_put(xtal_clk);
+
+	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+	apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC110_APLL_CON), 1);
+	mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC110_MPLL_CON), 0);
+	epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC110_EPLL_CON), 0);
+	vpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC110_VPLL_CON), 0);
+
+	printk(KERN_INFO "S5PC110: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz"
+		", Epll=%ld.%03ld Mhz, Vpll=%ld.%03ld Mhz\n",
+		print_mhz(apll), print_mhz(mpll),
+		print_mhz(epll), print_mhz(vpll));
+
+	armclk = apll / GET_DIV(clkdiv0, S5PC110_CLKDIV0_APLL);
+	hclk_msys = armclk / GET_DIV(clkdiv0, S5PC110_CLKDIV0_HCLK_MSYS);
+	hclk_dsys = mpll / GET_DIV(clkdiv0, S5PC110_CLKDIV0_HCLK_DSYS);
+	hclk_psys = mpll / GET_DIV(clkdiv0, S5PC110_CLKDIV0_HCLK_PSYS);
+	pclk_msys = hclk_msys / GET_DIV(clkdiv0, S5PC110_CLKDIV0_PCLK_MSYS);
+	pclk_dsys = hclk_dsys / GET_DIV(clkdiv0, S5PC110_CLKDIV0_PCLK_DSYS);
+	pclk_psys = hclk_psys / GET_DIV(clkdiv0, S5PC110_CLKDIV0_PCLK_PSYS);
+
+	printk(KERN_INFO "S5PC110: ARMCLK=%ld.%03ld MHz\n"
+		"HCLK: Msys %ld.%03ld MHz, Dsys %ld.%03ld MHz, Psys %ld.%03ld MHz\n"
+		"PCLK: Msys %ld.%03ld MHz, Dsys %ld.%03ld MHz, Psys %ld.%03ld MHz\n",
+		print_mhz(armclk),
+		print_mhz(hclk_msys), print_mhz(hclk_dsys), print_mhz(hclk_psys),
+		print_mhz(pclk_msys), print_mhz(pclk_dsys), print_mhz(pclk_psys));
+
+	clk_ext_xtal_mux.rate = xtal;
+	clk_fout_apll.rate = apll;
+	clk_fout_mpll.rate = mpll;
+	clk_fout_epll.rate = epll;
+	clk_fout_vpll.rate = vpll;
+
+	clk_dout_hclkm.rate = hclk_msys;
+	clk_dout_hclkd.rate = hclk_dsys;
+	clk_dout_hclkp.rate = hclk_psys;
+	clk_dout_pclkm.rate = pclk_msys;
+	clk_dout_pclkd.rate = pclk_dsys;
+	clk_dout_pclkp.rate = pclk_psys;
+
+	clk_h.rate = hclk_psys;
+	clk_p.rate = pclk_psys;
+	clk_f.rate = armclk;
+
+	for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
+		s5pc110_set_clksrc(init_parents[ptr]);
+}
+
+static struct clk *clks[] __initdata = {
+	&clk_ext_xtal_mux,
+	&clk_usb_xtal,
+	&clk_pcm_cd0,
+	&clk_pcm_cd1,
+	&clk_iis_cd1,
+	&clk_mout_apll.clk,
+	&clk_mout_mpll.clk,
+	&clk_mout_epll.clk,
+	&clk_mout_vpllsrc.clk,
+	&clk_mout_vpll.clk,
+	&clk_dout_a2m,
+	&clk_mout_hpm.clk,
+	&clk_mout_msys.clk,
+	&clk_mout_dsys.clk,
+	&clk_mout_psys.clk,
+	&clk_dout_copy,
+	&clk_dout_hpm,
+	&clk_dout_apll,
+	&clk_dout_hclkm,
+	&clk_dout_pclkm,
+	&clk_dout_hclkd,
+	&clk_dout_pclkd,
+	&clk_dout_hclkp,
+	&clk_dout_pclkp,
+	&clk_dout_fimc,
+	&clk_dout_imem,
+	&clk_mout_onenand.clk,
+	&clk_dout_onenand,
+	&clk_dout_onenand2,
+	&clk_cam0.clk,
+	&clk_cam1.clk,
+	&clk_fimd.clk,
+	&clk_mmc0.clk,
+	&clk_mmc1.clk,
+	&clk_mmc2.clk,
+	&clk_mmc3.clk,
+	&clk_audio0.clk,
+	&clk_audio1.clk,
+	&clk_audio2.clk,
+	&clk_fimc0.clk,
+	&clk_fimc1.clk,
+	&clk_fimc2.clk,
+	&clk_uart0.clk,
+	&clk_uart1.clk,
+	&clk_uart2.clk,
+	&clk_uart3.clk,
+	&clk_pwm.clk,
+};
+
+void __init s5pc110_register_clocks(void)
+{
+	struct clk *clkp;
+	int ret;
+	int ptr;
+
+	for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
+		clkp = clks[ptr];
+		ret = s3c24xx_register_clock(clkp);
+		if (ret < 0) {
+			printk(KERN_ERR "Failed to register clock %s (%d)\n",
+			       clkp->name, ret);
+		}
+	}
+}
-- 
1.6.4

[PATCH 13/19] ARM: S5PC1XX: add support for s5pc110 irqs

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds interrupt support on S5PC110 SoCs. Unlike S5PC100,
S5PC110 has 4 VICs, so the S5PC110 specifi virtual memory area is
extended to cover VIC3 register block.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 arch/arm/mach-s5pc110/cpu.c                   |   10 ++
 arch/arm/mach-s5pc110/include/mach/regs-irq.h |   25 +++
 arch/arm/mach-s5pc110/include/plat/irqs.h     |  209 +++++++++++++++++++++++++
 3 files changed, 244 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/include/mach/regs-irq.h
 create mode 100644 arch/arm/mach-s5pc110/include/plat/irqs.h

diff --git a/arch/arm/mach-s5pc110/cpu.c b/arch/arm/mach-s5pc110/cpu.c
index 6c9ebcb..3ea26ff 100644
--- a/arch/arm/mach-s5pc110/cpu.c
+++ b/arch/arm/mach-s5pc110/cpu.c
@@ -43,6 +43,12 @@
 /* Initial IO mappings */
 
 static struct map_desc s5pc110_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5PC1XX_VA_VIC(3),
+		.pfn		= __phys_to_pfn(S5PC1XX_PA_VIC(3)),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
 };
 
 static void s5pc110_idle(void)
@@ -93,6 +99,10 @@ void __init s5pc110_init_clocks(int xtal)
 
 void __init s5pc110_init_irq(void)
 {
+	u32 vic_valid[] = {~0, ~0, ~0, ~0};
+
+	/* VIC0, VIC1, VIC2, and VIC3 are fully populated. */
+	s5pc1xx_init_irq(vic_valid, ARRAY_SIZE(vic_valid));
 }
 
 struct sysdev_class s5pc110_sysclass = {
diff --git a/arch/arm/mach-s5pc110/include/mach/regs-irq.h b/arch/arm/mach-s5pc110/include/mach/regs-irq.h
new file mode 100644
index 0000000..b467e3b
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/mach/regs-irq.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s5pc110/include/mach/regs-irq.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC110 - IRQ register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_IRQ_H
+#define __ASM_ARCH_REGS_IRQ_H __FILE__
+
+#include <mach/map.h>
+#include <asm/hardware/vic.h>
+
+/* interrupt controller */
+#define S5PC1XX_VIC0REG(x)          		((x) + S5PC1XX_VA_VIC(0))
+#define S5PC1XX_VIC1REG(x)          		((x) + S5PC1XX_VA_VIC(1))
+#define S5PC1XX_VIC2REG(x)         		((x) + S5PC1XX_VA_VIC(2))
+#define S5PC1XX_VIC3REG(x)         		((x) + S5PC1XX_VA_VIC(3))
+
+#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pc110/include/plat/irqs.h b/arch/arm/mach-s5pc110/include/plat/irqs.h
new file mode 100644
index 0000000..a650251
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/plat/irqs.h
@@ -0,0 +1,209 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/irqs.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC110 - Common IRQ support
+ *
+ * Based on plat-s3c64xx/include/plat/irqs.h
+ */
+
+#ifndef __ASM_PLAT_S5PC110_IRQS_H
+#define __ASM_PLAT_S5PC110_IRQS_H __FILE__
+
+/* we keep the first set of CPU IRQs out of the range of
+ * the ISA space, so that the PC104 has them to itself
+ * and we don't end up having to do horrible things to the
+ * standard ISA drivers....
+ *
+ * note, since we're using the VICs, our start must be a
+ * mulitple of 32 to allow the common code to work
+ */
+
+#define S3C_IRQ_OFFSET		(32)
+
+#define S3C_IRQ(x)		((x) + S3C_IRQ_OFFSET)
+
+#define S3C_VIC0_BASE		S3C_IRQ(0)
+#define S3C_VIC1_BASE		S3C_IRQ(32)
+#define S3C_VIC2_BASE		S3C_IRQ(64)
+#define S3C_VIC3_BASE		S3C_IRQ(96)
+
+/* UART interrupts, each UART has 4 interupts per channel so
+ * use the space between the ISA and S3C main interrupts. Note, these
+ * are not in the same order as the S3C24XX series! */
+
+#define IRQ_S3CUART_BASE0	(16)
+#define IRQ_S3CUART_BASE1	(20)
+#define IRQ_S3CUART_BASE2	(24)
+#define IRQ_S3CUART_BASE3	(28)
+
+#define UART_IRQ_RXD		(0)
+#define UART_IRQ_ERR		(1)
+#define UART_IRQ_TXD		(2)
+#define UART_IRQ_MODEM		(3)
+
+#define IRQ_S3CUART_RX0		(IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX0		(IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR0	(IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX1		(IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX1		(IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR1	(IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX2		(IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX2		(IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR2	(IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX3		(IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX3		(IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR3	(IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
+
+/* VIC based IRQs */
+
+#define S5PC1XX_IRQ_VIC0(x)	(S3C_VIC0_BASE + (x))
+#define S5PC1XX_IRQ_VIC1(x)	(S3C_VIC1_BASE + (x))
+#define S5PC1XX_IRQ_VIC2(x)	(S3C_VIC2_BASE + (x))
+#define S5PC110_IRQ_VIC3(x)	(S3C_VIC3_BASE + (x))
+
+/*
+ * VIC0: system, DMA, timer
+ */
+#define IRQ_EINT0		S5PC1XX_IRQ_VIC0(0)
+#define IRQ_EINT1		S5PC1XX_IRQ_VIC0(1)
+#define IRQ_EINT2		S5PC1XX_IRQ_VIC0(2)
+#define IRQ_EINT3		S5PC1XX_IRQ_VIC0(3)
+#define IRQ_EINT4		S5PC1XX_IRQ_VIC0(4)
+#define IRQ_EINT5		S5PC1XX_IRQ_VIC0(5)
+#define IRQ_EINT6		S5PC1XX_IRQ_VIC0(6)
+#define IRQ_EINT7		S5PC1XX_IRQ_VIC0(7)
+#define IRQ_EINT8		S5PC1XX_IRQ_VIC0(8)
+#define IRQ_EINT9		S5PC1XX_IRQ_VIC0(9)
+#define IRQ_EINT10		S5PC1XX_IRQ_VIC0(10)
+#define IRQ_EINT11		S5PC1XX_IRQ_VIC0(11)
+#define IRQ_EINT12		S5PC1XX_IRQ_VIC0(12)
+#define IRQ_EINT13		S5PC1XX_IRQ_VIC0(13)
+#define IRQ_EINT14		S5PC1XX_IRQ_VIC0(14)
+#define IRQ_EINT15		S5PC1XX_IRQ_VIC0(15)
+#define IRQ_EINT16_31		S5PC1XX_IRQ_VIC0(16)
+#define IRQ_BATF		S5PC1XX_IRQ_VIC0(17)
+#define IRQ_MDMA		S5PC1XX_IRQ_VIC0(18)
+#define IRQ_PDMA0		S5PC1XX_IRQ_VIC0(19)
+#define IRQ_PDMA1		S5PC1XX_IRQ_VIC0(20)
+#define IRQ_TIMER0		S5PC1XX_IRQ_VIC0(21)
+#define IRQ_TIMER1		S5PC1XX_IRQ_VIC0(22)
+#define IRQ_TIMER2		S5PC1XX_IRQ_VIC0(23)
+#define IRQ_TIMER3		S5PC1XX_IRQ_VIC0(24)
+#define IRQ_TIMER4		S5PC1XX_IRQ_VIC0(25)
+#define IRQ_SYSTIMER		S5PC1XX_IRQ_VIC0(26)
+#define IRQ_WDT			S5PC1XX_IRQ_VIC0(27)
+#define IRQ_RTC_ALARM		S5PC1XX_IRQ_VIC0(28)
+#define IRQ_RTC			IRQ_RTC_ALARM
+#define IRQ_RTC_TIC		S5PC1XX_IRQ_VIC0(29)
+#define IRQ_TICK		IRQ_RTC_TIC
+#define IRQ_GPIOINT		S5PC1XX_IRQ_VIC0(30)
+#define IRQ_FIMC3		S5PC1XX_IRQ_VIC0(31)
+
+/*
+ * VIC1: ARM, power, memory, connectivity
+ */
+#define IRQ_CORTEX0		S5PC1XX_IRQ_VIC1(0)
+#define IRQ_CORTEX1		S5PC1XX_IRQ_VIC1(1)
+#define IRQ_CORTEX2		S5PC1XX_IRQ_VIC1(2)
+#define IRQ_CORTEX3		S5PC1XX_IRQ_VIC1(3)
+#define IRQ_CORTEX4		S5PC1XX_IRQ_VIC1(4)
+#define IRQ_IEMAPC		S5PC1XX_IRQ_VIC1(5)
+#define IRQ_IEMIEC		S5PC1XX_IRQ_VIC1(6)
+#define IRQ_NFC			S5PC1XX_IRQ_VIC1(8)
+#define IRQ_CFC			S5PC1XX_IRQ_VIC1(9)
+#define IRQ_UART0		S5PC1XX_IRQ_VIC1(10)
+#define IRQ_UART1		S5PC1XX_IRQ_VIC1(11)
+#define IRQ_UART2		S5PC1XX_IRQ_VIC1(12)
+#define IRQ_UART3		S5PC1XX_IRQ_VIC1(13)
+#define IRQ_IIC			S5PC1XX_IRQ_VIC1(14)
+#define IRQ_SPI0		S5PC1XX_IRQ_VIC1(15)
+#define IRQ_SPI1		S5PC1XX_IRQ_VIC1(16)
+#define IRQ_SPI2		S5PC1XX_IRQ_VIC1(17)
+#define IRQ_IRDA		S5PC1XX_IRQ_VIC1(18)
+#define IRQ_I2C_PMIC_LINK	S5PC1XX_IRQ_VIC1(19)
+#define IRQ_I2C_HDMI_PHY	S5PC1XX_IRQ_VIC1(20)
+#define IRQ_HSIRX		S5PC1XX_IRQ_VIC1(21)
+#define IRQ_HSITX		S5PC1XX_IRQ_VIC1(22)
+#define IRQ_UHOST		S5PC1XX_IRQ_VIC1(23)
+#define IRQ_OTG			S5PC1XX_IRQ_VIC1(24)
+#define IRQ_MSM			S5PC1XX_IRQ_VIC1(25)
+#define IRQ_HSMMC0		S5PC1XX_IRQ_VIC1(26)
+#define IRQ_HSMMC1		S5PC1XX_IRQ_VIC1(27)
+#define IRQ_HSMMC2		S5PC1XX_IRQ_VIC1(28)
+#define IRQ_MIPICSI		S5PC1XX_IRQ_VIC1(29)
+#define IRQ_MIPIDSI		S5PC1XX_IRQ_VIC1(30)
+#define IRQ_ONENAND_AUDI	S5PC1XX_IRQ_VIC1(31)
+
+/*
+ * VIC2: multimedia, audio, security
+ */
+#define IRQ_LCD0		S5PC1XX_IRQ_VIC2(0)
+#define IRQ_LCD1		S5PC1XX_IRQ_VIC2(1)
+#define IRQ_LCD2		S5PC1XX_IRQ_VIC2(2)
+#define IRQ_LCD3		S5PC1XX_IRQ_VIC2(3)
+#define IRQ_ROTATOR		S5PC1XX_IRQ_VIC2(4)
+#define IRQ_FIMC0		S5PC1XX_IRQ_VIC2(5)
+#define IRQ_FIMC1		S5PC1XX_IRQ_VIC2(6)
+#define IRQ_FIMC2		S5PC1XX_IRQ_VIC2(7)
+#define IRQ_JPEG		S5PC1XX_IRQ_VIC2(8)
+#define IRQ_2D			S5PC1XX_IRQ_VIC2(9)
+#define IRQ_3D			S5PC1XX_IRQ_VIC2(10)
+#define IRQ_MIXER		S5PC1XX_IRQ_VIC2(11)
+#define IRQ_HDMI		S5PC1XX_IRQ_VIC2(12)
+#define IRQ_IIC1		S5PC1XX_IRQ_VIC2(13)
+#define IRQ_HDMI_I2C		S5PC1XX_IRQ_VIC2(13)
+#define IRQ_MFC			S5PC1XX_IRQ_VIC2(14)
+#define IRQ_TVENC		S5PC1XX_IRQ_VIC2(15)
+#define IRQ_I2S0		S5PC1XX_IRQ_VIC2(16)
+#define IRQ_I2S1		S5PC1XX_IRQ_VIC2(17)
+#define IRQ_AC97		S5PC1XX_IRQ_VIC2(19)
+#define IRQ_PCM0		S5PC1XX_IRQ_VIC2(20)
+#define IRQ_PCM1		S5PC1XX_IRQ_VIC2(21)
+#define IRQ_SPDIF		S5PC1XX_IRQ_VIC2(22)
+#define IRQ_ADC			S5PC1XX_IRQ_VIC2(23)
+#define IRQ_PENDN		S5PC1XX_IRQ_VIC2(24)
+#define IRQ_TC			IRQ_PENDN
+#define IRQ_KEYPAD		S5PC1XX_IRQ_VIC2(25)
+#define IRQ_CG			S5PC1XX_IRQ_VIC2(26)
+#define IRQ_SEC			S5PC1XX_IRQ_VIC2(27)
+#define IRQ_SECRX		S5PC1XX_IRQ_VIC2(28)
+#define IRQ_SECTX		S5PC1XX_IRQ_VIC2(29)
+#define IRQ_SDMIRQ		S5PC1XX_IRQ_VIC2(30)
+#define IRQ_SDMFIQ		S5PC1XX_IRQ_VIC2(31)
+
+/* VIC3 used at S5PC110 */
+#define IRQ_IPC			S5PC110_IRQ_VIC3(0)
+#define IRQ_HOSTIF		S5PC110_IRQ_VIC3(1)
+#define IRQ_MMC3		S5PC110_IRQ_VIC3(2)
+#define IRQ_CEC			S5PC110_IRQ_VIC3(3)
+#define IRQ_TSI			S5PC110_IRQ_VIC3(4)
+#define IRQ_MDNIE0		S5PC110_IRQ_VIC3(5)
+#define IRQ_MDNIE1		S5PC110_IRQ_VIC3(6)
+#define IRQ_MDNIE2		S5PC110_IRQ_VIC3(7)
+#define IRQ_MDNIE3		S5PC110_IRQ_VIC3(8)
+#define IRQ_ADC1		S5PC110_IRQ_VIC3(9)
+#define IRQ_PENDN1		S5PC110_IRQ_VIC3(10)
+
+/* External interrupt */
+#define S3C_IRQ_EINT_BASE	(S5PC110_IRQ_VIC3(31) + 1)
+
+#define S3C_EINT(x)		(S3C_IRQ_EINT_BASE + (x - 16))
+#define IRQ_EINT(x)		(x < 16 ? IRQ_EINT0 + x : S3C_EINT(x))
+#define IRQ_EINT_BIT(x)		(x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0))
+
+/* GPIO interrupt */
+#define S3C_IRQ_GPIO_BASE	(IRQ_EINT(31) + 1)
+#define S3C_IRQ_GPIO(x)		(S3C_IRQ_GPIO_BASE + (x))
+
+/*
+ * Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs
+ */
+#define NR_IRQS			(S3C_IRQ_GPIO(320) + 1)
+
+#endif /* __ASM_PLAT_S5PC1XX_IRQS_H */
+
-- 
1.6.4

[PATCH 14/19] ARM: S5PC1XX: add support for s5pc110 gpio

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds gpiolib support for S5PC110 sub-platform.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 arch/arm/mach-s5pc110/include/mach/gpio.h      |  149 +++++++++++++
 arch/arm/mach-s5pc110/include/plat/regs-gpio.h |   65 ++++++
 arch/arm/plat-s5pc1xx/gpiolib.c                |  266 ++++++++++++++++++++++++
 arch/arm/plat-s5pc1xx/irq-gpio.c               |  110 ++++++++++
 4 files changed, 590 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/include/mach/gpio.h
 create mode 100644 arch/arm/mach-s5pc110/include/plat/regs-gpio.h

diff --git a/arch/arm/mach-s5pc110/include/mach/gpio.h b/arch/arm/mach-s5pc110/include/mach/gpio.h
new file mode 100644
index 0000000..f83e5c9
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/mach/gpio.h
@@ -0,0 +1,149 @@
+/* arch/arm/mach-s5pc110/include/mach/gpio.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC110 - GPIO lib support
+ *
+ * Base on mach-s3c6400/include/mach/gpio.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define gpio_get_value	__gpio_get_value
+#define gpio_set_value	__gpio_set_value
+#define gpio_cansleep	__gpio_cansleep
+#define gpio_to_irq	__gpio_to_irq
+
+/* GPIO bank sizes */
+#define S5PC110_GPIO_A0_NR	(8)
+#define S5PC110_GPIO_A1_NR	(8)
+#define S5PC110_GPIO_B_NR	(8)
+#define S5PC110_GPIO_C0_NR	(8)
+#define S5PC110_GPIO_C1_NR	(8)
+#define S5PC110_GPIO_D0_NR	(8)
+#define S5PC110_GPIO_D1_NR	(8)
+#define S5PC110_GPIO_E0_NR	(8)
+#define S5PC110_GPIO_E1_NR	(8)
+#define S5PC110_GPIO_F0_NR	(8)
+#define S5PC110_GPIO_F1_NR	(8)
+#define S5PC110_GPIO_F2_NR	(8)
+#define S5PC110_GPIO_F3_NR	(8)
+#define S5PC110_GPIO_G0_NR	(8)
+#define S5PC110_GPIO_G1_NR	(8)
+#define S5PC110_GPIO_G2_NR	(8)
+#define S5PC110_GPIO_G3_NR	(8)
+#define S5PC110_GPIO_H0_NR	(8)
+#define S5PC110_GPIO_H1_NR	(8)
+#define S5PC110_GPIO_H2_NR	(8)
+#define S5PC110_GPIO_H3_NR	(8)
+#define S5PC110_GPIO_I_NR	(8)
+#define S5PC110_GPIO_J0_NR	(8)
+#define S5PC110_GPIO_J1_NR	(8)
+#define S5PC110_GPIO_J2_NR	(8)
+#define S5PC110_GPIO_J3_NR	(8)
+#define S5PC110_GPIO_J4_NR	(8)
+#define S5PC110_GPIO_MP0_1_NR	(8)
+#define S5PC110_GPIO_MP0_2_NR	(8)
+#define S5PC110_GPIO_MP0_3_NR	(8)
+#define S5PC110_GPIO_MP0_4_NR	(8)
+#define S5PC110_GPIO_MP0_5_NR	(8)
+#define S5PC110_GPIO_MP0_6_NR	(8)
+
+/* GPIO bank numbes */
+
+/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
+ * space for debugging purposes so that any accidental
+ * change from one gpio bank to another can be caught.
+*/
+
+#define S5PC1XX_GPIO_NEXT(__gpio) \
+	((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+enum s5pc110_gpio_number {
+	S5PC110_GPIO_A0_START	= 0,
+	S5PC110_GPIO_A1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_A0),
+	S5PC110_GPIO_B_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_A1),
+	S5PC110_GPIO_C0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_B),
+	S5PC110_GPIO_C1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_C0),
+	S5PC110_GPIO_D0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_C1),
+	S5PC110_GPIO_D1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_D0),
+	S5PC110_GPIO_E0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_D1),
+	S5PC110_GPIO_E1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_E0),
+	S5PC110_GPIO_F0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_E1),
+	S5PC110_GPIO_F1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_F0),
+	S5PC110_GPIO_F2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_F1),
+	S5PC110_GPIO_F3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_F2),
+	S5PC110_GPIO_G0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_F3),
+	S5PC110_GPIO_G1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_G0),
+	S5PC110_GPIO_G2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_G1),
+	S5PC110_GPIO_G3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_G2),
+	S5PC110_GPIO_H0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_G3),
+	S5PC110_GPIO_H1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_H0),
+	S5PC110_GPIO_H2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_H1),
+	S5PC110_GPIO_H3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_H2),
+	S5PC110_GPIO_I_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_H3),
+	S5PC110_GPIO_J0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_I),
+	S5PC110_GPIO_J1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J0),
+	S5PC110_GPIO_J2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J1),
+	S5PC110_GPIO_J3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J2),
+	S5PC110_GPIO_J4_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J3),
+	S5PC110_GPIO_MP0_1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J4),
+	S5PC110_GPIO_MP0_2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_1),
+	S5PC110_GPIO_MP0_3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_2),
+	S5PC110_GPIO_MP0_4_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_3),
+	S5PC110_GPIO_MP0_5_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_4),
+	S5PC110_GPIO_MP0_6_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_5),
+	S5PC110_GPIO_END        = S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_6),
+};
+
+#define S5PC110_GPA0(_nr)	(S5PC110_GPIO_A0_START + (_nr))
+#define S5PC110_GPA1(_nr)	(S5PC110_GPIO_A1_START + (_nr))
+#define S5PC110_GPB(_nr)	(S5PC110_GPIO_B_START + (_nr))
+#define S5PC110_GPC0(_nr)	(S5PC110_GPIO_C0_START + (_nr))
+#define S5PC110_GPC1(_nr)	(S5PC110_GPIO_C1_START + (_nr))
+#define S5PC110_GPD0(_nr)	(S5PC110_GPIO_D0_START + (_nr))
+#define S5PC110_GPD1(_nr)	(S5PC110_GPIO_D1_START + (_nr))
+#define S5PC110_GPE0(_nr)	(S5PC110_GPIO_E0_START + (_nr))
+#define S5PC110_GPE1(_nr)	(S5PC110_GPIO_E1_START + (_nr))
+#define S5PC110_GPF0(_nr)	(S5PC110_GPIO_F0_START + (_nr))
+#define S5PC110_GPF1(_nr)	(S5PC110_GPIO_F1_START + (_nr))
+#define S5PC110_GPF2(_nr)	(S5PC110_GPIO_F2_START + (_nr))
+#define S5PC110_GPF3(_nr)	(S5PC110_GPIO_F3_START + (_nr))
+#define S5PC110_GPG0(_nr)	(S5PC110_GPIO_G0_START + (_nr))
+#define S5PC110_GPG1(_nr)	(S5PC110_GPIO_G1_START + (_nr))
+#define S5PC110_GPG2(_nr)	(S5PC110_GPIO_G2_START + (_nr))
+#define S5PC110_GPG3(_nr)	(S5PC110_GPIO_G3_START + (_nr))
+#define S5PC110_GPH0(_nr)	(S5PC110_GPIO_H0_START + (_nr))
+#define S5PC110_GPH1(_nr)	(S5PC110_GPIO_H1_START + (_nr))
+#define S5PC110_GPH2(_nr)	(S5PC110_GPIO_H2_START + (_nr))
+#define S5PC110_GPH3(_nr)	(S5PC110_GPIO_H3_START + (_nr))
+#define S5PC110_GPI(_nr)	(S5PC110_GPIO_I_START + (_nr))
+#define S5PC110_GPJ0(_nr)	(S5PC110_GPIO_J0_START + (_nr))
+#define S5PC110_GPJ1(_nr)	(S5PC110_GPIO_J1_START + (_nr))
+#define S5PC110_GPJ2(_nr)	(S5PC110_GPIO_J2_START + (_nr))
+#define S5PC110_GPJ3(_nr)	(S5PC110_GPIO_J3_START + (_nr))
+#define S5PC110_GPJ4(_nr)	(S5PC110_GPIO_J4_START + (_nr))
+#define S5PC110_MP0_1(_nr)	(S5PC110_GPIO_MP0_1_START + (_nr))
+#define S5PC110_MP0_2(_nr)	(S5PC110_GPIO_MP0_2_START + (_nr))
+#define S5PC110_MP0_3(_nr)	(S5PC110_GPIO_MP0_3_START + (_nr))
+#define S5PC110_MP0_4(_nr)	(S5PC110_GPIO_MP0_4_START + (_nr))
+#define S5PC110_MP0_5(_nr)	(S5PC110_GPIO_MP0_5_START + (_nr))
+#define S5PC110_MP0_6(_nr)	(S5PC110_GPIO_MP0_6_START + (_nr))
+
+/* It used the end of the S5PC100 gpios */
+#define S3C_GPIO_END		S5PC110_GPIO_END
+
+/* define the number of gpios we need to the one after the MP05() range */
+#define ARCH_NR_GPIOS		(S5PC110_GPIO_END + 1)
+
+/* Common compatibility defines */
+#define S5PC1XX_GPIO_EINT_SFN	S3C_GPIO_SFN(0xf)
+#define S5PC1XX_GPH0(n)		S5PC110_GPH0(n)
+#define S5PC1XX_GPH1(n)		S5PC110_GPH1(n)
+#define S5PC1XX_GPH2(n)		S5PC110_GPH2(n)
+#define S5PC1XX_GPH3(n)		S5PC110_GPH3(n)
+
+#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s5pc110/include/plat/regs-gpio.h b/arch/arm/mach-s5pc110/include/plat/regs-gpio.h
new file mode 100644
index 0000000..24663b8
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/plat/regs-gpio.h
@@ -0,0 +1,65 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC110 - GPIO register definitions
+ */
+
+#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H
+#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__
+
+#include <mach/map.h>
+
+/* S5PC110 */
+#define S5PC110_GPIO_BASE	S5PC1XX_VA_GPIO
+#define S5PC110_GPA0_BASE	(S5PC110_GPIO_BASE + 0x0000)
+#define S5PC110_GPA1_BASE	(S5PC110_GPIO_BASE + 0x0020)
+#define S5PC110_GPB_BASE	(S5PC110_GPIO_BASE + 0x0040)
+#define S5PC110_GPC0_BASE	(S5PC110_GPIO_BASE + 0x0060)
+#define S5PC110_GPC1_BASE	(S5PC110_GPIO_BASE + 0x0080)
+#define S5PC110_GPD0_BASE	(S5PC110_GPIO_BASE + 0x00A0)
+#define S5PC110_GPD1_BASE	(S5PC110_GPIO_BASE + 0x00C0)
+#define S5PC110_GPE0_BASE	(S5PC110_GPIO_BASE + 0x00E0)
+#define S5PC110_GPE1_BASE	(S5PC110_GPIO_BASE + 0x0100)
+#define S5PC110_GPF0_BASE	(S5PC110_GPIO_BASE + 0x0120)
+#define S5PC110_GPF1_BASE	(S5PC110_GPIO_BASE + 0x0140)
+#define S5PC110_GPF2_BASE	(S5PC110_GPIO_BASE + 0x0160)
+#define S5PC110_GPF3_BASE	(S5PC110_GPIO_BASE + 0x0180)
+#define S5PC110_GPG0_BASE	(S5PC110_GPIO_BASE + 0x01A0)
+#define S5PC110_GPG1_BASE	(S5PC110_GPIO_BASE + 0x01C0)
+#define S5PC110_GPG2_BASE	(S5PC110_GPIO_BASE + 0x01E0)
+#define S5PC110_GPG3_BASE	(S5PC110_GPIO_BASE + 0x0200)
+#define S5PC110_GPH0_BASE	(S5PC110_GPIO_BASE + 0x0C00)
+#define S5PC110_GPH1_BASE	(S5PC110_GPIO_BASE + 0x0C20)
+#define S5PC110_GPH2_BASE	(S5PC110_GPIO_BASE + 0x0C40)
+#define S5PC110_GPH3_BASE	(S5PC110_GPIO_BASE + 0x0C60)
+#define S5PC110_GPI_BASE	(S5PC110_GPIO_BASE + 0x0220)
+#define S5PC110_GPJ0_BASE	(S5PC110_GPIO_BASE + 0x0240)
+#define S5PC110_GPJ1_BASE	(S5PC110_GPIO_BASE + 0x0260)
+#define S5PC110_GPJ2_BASE	(S5PC110_GPIO_BASE + 0x0280)
+#define S5PC110_GPJ3_BASE	(S5PC110_GPIO_BASE + 0x02A0)
+#define S5PC110_GPJ4_BASE	(S5PC110_GPIO_BASE + 0x02C0)
+#define S5PC110_MP0_1_BASE	(S5PC110_GPIO_BASE + 0x02E0)
+#define S5PC110_MP0_2_BASE	(S5PC110_GPIO_BASE + 0x0300)
+#define S5PC110_MP0_3_BASE	(S5PC110_GPIO_BASE + 0x0320)
+#define S5PC110_MP0_4_BASE	(S5PC110_GPIO_BASE + 0x0340)
+#define S5PC110_MP0_5_BASE	(S5PC110_GPIO_BASE + 0x0360)
+#define S5PC110_EXT_INT_BASE	(S5PC110_GPIO_BASE + 0x0E00)
+#define S5PC110_PDNEN		(S5PC110_GPIO_BASE + 0x0F80)
+#define S5PC100_PDNEN_NORMAL	(0 << 0)
+
+#define S5PC110_PDNEN_CFG_PDNEN	(1 << 1)
+#define S5PC110_PDNEN_CFG_AUTO	(0 << 1)
+#define S5PC110_PDNEN_POWERDOWN	(1 << 0)
+#define S5PC110_PDNEN_NORMAL	(0 << 0)
+
+/* Common part */
+#define S5PC1XX_EINT_BASE	(S5PC110_EXT_INT_BASE)
+
+#define S5PC1XX_GPx_INPUT(__gpio)	(0x0 << ((__gpio) * 4))
+#define S5PC1XX_GPx_OUTPUT(__gpio)	(0x1 << ((__gpio) * 4))
+#define S5PC1XX_GPx_CONMASK(__gpio)	(0xf << ((__gpio) * 4))
+
+#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */
+
diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c
index 60bf31d..2cd095c 100644
--- a/arch/arm/plat-s5pc1xx/gpiolib.c
+++ b/arch/arm/plat-s5pc1xx/gpiolib.c
@@ -453,6 +453,272 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 #define s5pc1xx_gpio_chips s5pc100_gpio_chips
 
 #endif
+
+#ifdef CONFIG_CPU_S5PC110
+static struct s3c_gpio_chip s5pc110_gpio_chips[] = {
+	{
+		.base	= S5PC110_GPA0_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPA0(0),
+			.ngpio	= S5PC110_GPIO_A0_NR,
+			.label	= "GPA0",
+		},
+	}, {
+		.base	= S5PC110_GPA1_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPA1(0),
+			.ngpio	= S5PC110_GPIO_A1_NR,
+			.label	= "GPA1",
+		},
+	}, {
+		.base	= S5PC110_GPB_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPB(0),
+			.ngpio	= S5PC110_GPIO_B_NR,
+			.label	= "GPB",
+		},
+	}, {
+		.base	= S5PC110_GPC0_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPC0(0),
+			.ngpio	= S5PC110_GPIO_C0_NR,
+			.label	= "GPC0",
+		},
+	}, {
+		.base	= S5PC110_GPC1_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPC1(0),
+			.ngpio	= S5PC110_GPIO_C1_NR,
+			.label	= "GPC1",
+		},
+	}, {
+		.base	= S5PC110_GPD0_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPD0(0),
+			.ngpio	= S5PC110_GPIO_D0_NR,
+			.label	= "GPD0",
+		},
+	}, {
+		.base	= S5PC110_GPD1_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPD1(0),
+			.ngpio	= S5PC110_GPIO_D1_NR,
+			.label	= "GPD1",
+		},
+	}, {
+		.base	= S5PC110_GPE0_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPE0(0),
+			.ngpio	= S5PC110_GPIO_E0_NR,
+			.label	= "GPE0",
+		},
+	}, {
+		.base	= S5PC110_GPE1_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPE1(0),
+			.ngpio	= S5PC110_GPIO_E1_NR,
+			.label	= "GPE1",
+		},
+	}, {
+		.base	= S5PC110_GPF0_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPF0(0),
+			.ngpio	= S5PC110_GPIO_F0_NR,
+			.label	= "GPF0",
+		},
+	}, {
+		.base	= S5PC110_GPF1_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPF1(0),
+			.ngpio	= S5PC110_GPIO_F1_NR,
+			.label	= "GPF1",
+		},
+	}, {
+		.base	= S5PC110_GPF2_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPF2(0),
+			.ngpio	= S5PC110_GPIO_F2_NR,
+			.label	= "GPF2",
+		},
+	}, {
+		.base	= S5PC110_GPF3_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPF3(0),
+			.ngpio	= S5PC110_GPIO_F3_NR,
+			.label	= "GPF3",
+		},
+	}, {
+		.base	= S5PC110_GPG0_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPG0(0),
+			.ngpio	= S5PC110_GPIO_G0_NR,
+			.label	= "GPG0",
+		},
+	}, {
+		.base	= S5PC110_GPG1_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPG1(0),
+			.ngpio	= S5PC110_GPIO_G1_NR,
+			.label	= "GPG1",
+		},
+	}, {
+		.base	= S5PC110_GPG2_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPG2(0),
+			.ngpio	= S5PC110_GPIO_G2_NR,
+			.label	= "GPG2",
+		},
+	}, {
+		.base	= S5PC110_GPG3_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPG3(0),
+			.ngpio	= S5PC110_GPIO_G3_NR,
+			.label	= "GPG3",
+		},
+	}, {
+		.base	= S5PC110_GPH0_BASE,
+		.config	= &gpio_cfg_eint,
+		.chip	= {
+			.base	= S5PC110_GPH0(0),
+			.ngpio	= S5PC110_GPIO_H0_NR,
+			.label	= "GPH0",
+		},
+	}, {
+		.base	= S5PC110_GPH1_BASE,
+		.config	= &gpio_cfg_eint,
+		.chip	= {
+			.base	= S5PC110_GPH1(0),
+			.ngpio	= S5PC110_GPIO_H1_NR,
+			.label	= "GPH1",
+		},
+	}, {
+		.base	= S5PC110_GPH2_BASE,
+		.config	= &gpio_cfg_eint,
+		.chip	= {
+			.base	= S5PC110_GPH2(0),
+			.ngpio	= S5PC110_GPIO_H2_NR,
+			.label	= "GPH2",
+		},
+	}, {
+		.base	= S5PC110_GPH3_BASE,
+		.config	= &gpio_cfg_eint,
+		.chip	= {
+			.base	= S5PC110_GPH3(0),
+			.ngpio	= S5PC110_GPIO_H3_NR,
+			.label	= "GPH3",
+		},
+	}, {
+		.base	= S5PC110_GPI_BASE,
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= S5PC110_GPI(0),
+			.ngpio	= S5PC110_GPIO_I_NR,
+			.label	= "GPI",
+		},
+	}, {
+		.base	= S5PC110_GPJ0_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPJ0(0),
+			.ngpio	= S5PC110_GPIO_J0_NR,
+			.label	= "GPJ0",
+		},
+	}, {
+		.base	= S5PC110_GPJ1_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPJ1(0),
+			.ngpio	= S5PC110_GPIO_J1_NR,
+			.label	= "GPJ1",
+		},
+	}, {
+		.base	= S5PC110_GPJ2_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPJ2(0),
+			.ngpio	= S5PC110_GPIO_J2_NR,
+			.label	= "GPJ2",
+		},
+	}, {
+		.base	= S5PC110_GPJ3_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPJ3(0),
+			.ngpio	= S5PC110_GPIO_J3_NR,
+			.label	= "GPJ3",
+		},
+	}, {
+		.base	= S5PC110_GPJ4_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_GPJ4(0),
+			.ngpio	= S5PC110_GPIO_J4_NR,
+			.label	= "GPJ4",
+		},
+	}, {
+		.base	= S5PC110_MP0_1_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_MP0_1(0),
+			.ngpio	= S5PC110_GPIO_MP0_1_NR,
+			.label	= "MP0_1",
+		},
+	}, {
+		.base	= S5PC110_MP0_2_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_MP0_2(0),
+			.ngpio	= S5PC110_GPIO_MP0_2_NR,
+			.label	= "MP0_2",
+		},
+	}, {
+		.base	= S5PC110_MP0_3_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_MP0_3(0),
+			.ngpio	= S5PC110_GPIO_MP0_3_NR,
+			.label	= "MP0_3",
+		},
+	}, {
+		.base	= S5PC110_MP0_4_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_MP0_4(0),
+			.ngpio	= S5PC110_GPIO_MP0_4_NR,
+			.label	= "MP0_4",
+		},
+	}, {
+		.base	= S5PC110_MP0_5_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC110_MP0_5(0),
+			.ngpio	= S5PC110_GPIO_MP0_5_NR,
+			.label	= "MP0_5",
+		},
+	},
+};
+
+#define s5pc1xx_gpio_chips s5pc110_gpio_chips
+
+#endif
+
 /* FIXME move from irq-gpio.c */
 extern struct irq_chip s5pc1xx_gpioint;
 extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/plat-s5pc1xx/irq-gpio.c
index f5d8dab..b13308f 100644
--- a/arch/arm/plat-s5pc1xx/irq-gpio.c
+++ b/arch/arm/plat-s5pc1xx/irq-gpio.c
@@ -142,6 +142,116 @@ static int s5pc100_group_end = 21;
 
 #endif
 
+#ifdef CONFIG_CPU_S5PC110
+static int s5pc110_get_start(unsigned int group)
+{
+	switch (group) {
+	case 0: return S5PC110_GPIO_A0_START;
+	case 1: return S5PC110_GPIO_A1_START;
+	case 2: return S5PC110_GPIO_B_START;
+	case 3: return S5PC110_GPIO_C0_START;
+	case 4: return S5PC110_GPIO_C1_START;
+	case 5: return S5PC110_GPIO_D0_START;
+	case 6: return S5PC110_GPIO_D1_START;
+	case 7: return S5PC110_GPIO_E0_START;
+	case 8: return S5PC110_GPIO_E1_START;
+	case 9: return S5PC110_GPIO_F0_START;
+	case 10: return S5PC110_GPIO_F1_START;
+	case 11: return S5PC110_GPIO_F2_START;
+	case 12: return S5PC110_GPIO_F3_START;
+	case 13: return S5PC110_GPIO_G0_START;
+	case 14: return S5PC110_GPIO_G1_START;
+	case 15: return S5PC110_GPIO_G2_START;
+	case 16: return S5PC110_GPIO_G3_START;
+	case 17: return S5PC110_GPIO_J0_START;
+	case 18: return S5PC110_GPIO_J1_START;
+	case 19: return S5PC110_GPIO_J2_START;
+	case 20: return S5PC110_GPIO_J3_START;
+	case 21: return S5PC110_GPIO_J4_START;
+	case 22: return S5PC110_GPIO_MP0_1_START;
+	case 23: return S5PC110_GPIO_MP0_2_START;
+	case 24: return S5PC110_GPIO_MP0_3_START;
+	case 25: return S5PC110_GPIO_MP0_4_START;
+	case 26: return S5PC110_GPIO_MP0_5_START;
+	default:
+		BUG();
+	}
+	return -EINVAL;
+}
+
+static int s5pc110_get_group(unsigned int irq)
+{
+	irq -= S3C_IRQ_GPIO(0);
+
+	switch (irq) {
+	case S5PC110_GPIO_A0_START ... S5PC110_GPIO_A1_START - 1:
+		return 0;
+	case S5PC110_GPIO_A1_START ... S5PC110_GPIO_B_START - 1:
+		return 1;
+	case S5PC110_GPIO_B_START ... S5PC110_GPIO_C0_START - 1:
+		return 2;
+	case S5PC110_GPIO_C0_START ... S5PC110_GPIO_C1_START - 1:
+		return 3;
+	case S5PC110_GPIO_C1_START ... S5PC110_GPIO_D0_START - 1:
+		return 4;
+	case S5PC110_GPIO_D0_START ... S5PC110_GPIO_D1_START - 1:
+		return 5;
+	case S5PC110_GPIO_D1_START ... S5PC110_GPIO_E0_START - 1:
+		return 6;
+	case S5PC110_GPIO_E0_START ... S5PC110_GPIO_E1_START - 1:
+		return 7;
+	case S5PC110_GPIO_E1_START ... S5PC110_GPIO_F0_START - 1:
+		return 8;
+	case S5PC110_GPIO_F0_START ... S5PC110_GPIO_F1_START - 1:
+		return 9;
+	case S5PC110_GPIO_F1_START ... S5PC110_GPIO_F2_START - 1:
+		return 10;
+	case S5PC110_GPIO_F2_START ... S5PC110_GPIO_F3_START - 1:
+		return 11;
+	case S5PC110_GPIO_F3_START ... S5PC110_GPIO_G0_START - 1:
+		return 12;
+	case S5PC110_GPIO_G0_START ... S5PC110_GPIO_G1_START - 1:
+		return 13;
+	case S5PC110_GPIO_G1_START ... S5PC110_GPIO_G2_START - 1:
+		return 14;
+	case S5PC110_GPIO_G2_START ... S5PC110_GPIO_G3_START - 1:
+		return 15;
+	case S5PC110_GPIO_G3_START ... S5PC110_GPIO_H0_START - 1:
+		return 16;
+	case S5PC110_GPIO_J0_START ... S5PC110_GPIO_J1_START - 1:
+		return 17;
+	case S5PC110_GPIO_J1_START ... S5PC110_GPIO_J2_START - 1:
+		return 18;
+	case S5PC110_GPIO_J2_START ... S5PC110_GPIO_J3_START - 1:
+		return 19;
+	case S5PC110_GPIO_J3_START ... S5PC110_GPIO_J4_START - 1:
+		return 20;
+	case S5PC110_GPIO_J4_START ... S5PC110_GPIO_MP0_1_START - 1:
+		return 21;
+	case S5PC110_GPIO_MP0_1_START ... S5PC110_GPIO_MP0_2_START - 1:
+		return 22;
+	case S5PC110_GPIO_MP0_2_START ... S5PC110_GPIO_MP0_3_START - 1:
+		return 23;
+	case S5PC110_GPIO_MP0_3_START ... S5PC110_GPIO_MP0_4_START - 1:
+		return 24;
+	case S5PC110_GPIO_MP0_4_START ... S5PC110_GPIO_MP0_5_START - 1:
+		return 25;
+	case S5PC110_GPIO_MP0_5_START ... S5PC110_GPIO_MP0_6_START - 1:
+		return 26;
+	default:
+		BUG();
+	}
+	return -EINVAL;
+}
+
+static int s5pc110_group_end = 27;
+
+#define s5pc1xx_get_group s5pc110_get_group
+#define s5pc1xx_get_start s5pc110_get_start
+#define s5pc1xx_group_end s5pc110_group_end
+
+#endif
+
 static int s5pc1xx_get_offset(unsigned int irq)
 {
 	struct gpio_chip *chip = get_irq_data(irq);
-- 
1.6.4

[PATCH 15/19] ARM: S5PC1XX: add i2c platform helpers on s5pc110 sub-platform

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds required I2C platform helpers. S5PC110 SoCs has 3 I2C
controllers.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 arch/arm/mach-s5pc110/Kconfig        |   18 +++++++++
 arch/arm/mach-s5pc110/Makefile       |    3 +
 arch/arm/mach-s5pc110/cpu.c          |    3 +
 arch/arm/mach-s5pc110/setup-i2c0.c   |   31 +++++++++++++++
 arch/arm/mach-s5pc110/setup-i2c1.c   |   31 +++++++++++++++
 arch/arm/mach-s5pc110/setup-i2c2.c   |   32 ++++++++++++++++
 arch/arm/plat-s3c/Kconfig            |    5 ++
 arch/arm/plat-s3c/Makefile           |    1 +
 arch/arm/plat-s3c/dev-i2c2.c         |   69 ++++++++++++++++++++++++++++++++++
 arch/arm/plat-s3c/include/plat/iic.h |    2 +
 10 files changed, 195 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/setup-i2c0.c
 create mode 100644 arch/arm/mach-s5pc110/setup-i2c1.c
 create mode 100644 arch/arm/mach-s5pc110/setup-i2c2.c
 create mode 100644 arch/arm/plat-s3c/dev-i2c2.c

diff --git a/arch/arm/mach-s5pc110/Kconfig b/arch/arm/mach-s5pc110/Kconfig
index 420b585..123dbd3 100644
--- a/arch/arm/mach-s5pc110/Kconfig
+++ b/arch/arm/mach-s5pc110/Kconfig
@@ -16,4 +16,22 @@ config CPU_S5PC110
 	help
 	  Enable S5PC110 CPU support
 
+config S5PC110_SETUP_I2C0
+	bool
+	default y
+	help
+	  Common setup code for i2c bus 0.
+
+	  Note, currently since i2c0 is always compiled, this setup helper
+	  is always compiled with it.
+
+config S5PC110_SETUP_I2C1
+	bool
+	help
+	  Common setup code for i2c bus 1.
+
+config S5PC110_SETUP_I2C2
+	bool
+	help
+	  Common setup code for i2c bus 2.
 endif
diff --git a/arch/arm/mach-s5pc110/Makefile b/arch/arm/mach-s5pc110/Makefile
index d9fecf0..38be30f 100644
--- a/arch/arm/mach-s5pc110/Makefile
+++ b/arch/arm/mach-s5pc110/Makefile
@@ -14,5 +14,8 @@ obj-                            :=
 obj-$(CONFIG_CPU_S5PC110)	+= cpu.o
 
 # Helper and device support
+obj-$(CONFIG_S5PC110_SETUP_I2C0)	+= setup-i2c0.o
+obj-$(CONFIG_S5PC110_SETUP_I2C1)	+= setup-i2c1.o
+obj-$(CONFIG_S5PC110_SETUP_I2C2)	+= setup-i2c2.o
 
 # machine support
diff --git a/arch/arm/mach-s5pc110/cpu.c b/arch/arm/mach-s5pc110/cpu.c
index 3ea26ff..d16ba68 100644
--- a/arch/arm/mach-s5pc110/cpu.c
+++ b/arch/arm/mach-s5pc110/cpu.c
@@ -86,6 +86,9 @@ void __init s5pc110_map_io(void)
 	iotable_init(s5pc110_iodesc, ARRAY_SIZE(s5pc110_iodesc));
 
 	/* initialise device information early */
+	/* the i2c devices are directly compatible with s3c2440 */
+	s3c_i2c0_setname("s3c2440-i2c");
+	s3c_i2c1_setname("s3c2440-i2c");
 }
 
 void __init s5pc110_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5pc110/setup-i2c0.c b/arch/arm/mach-s5pc110/setup-i2c0.c
new file mode 100644
index 0000000..596b139
--- /dev/null
+++ b/arch/arm/mach-s5pc110/setup-i2c0.c
@@ -0,0 +1,31 @@
+/*
+ * linux/arch/arm/mach-s5pc110/setup-i2c2.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Base S5PC110 I2C bus 0 gpio configuration
+ *
+ * Based on plat-s3c64xx/setup-i2c0.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <mach/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c0_cfg_gpio(struct platform_device *dev)
+{
+	s3c_gpio_cfgpin(S5PC110_GPD1(0), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC110_GPD1(0), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC110_GPD1(1), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC110_GPD1(1), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pc110/setup-i2c1.c b/arch/arm/mach-s5pc110/setup-i2c1.c
new file mode 100644
index 0000000..cd9649b
--- /dev/null
+++ b/arch/arm/mach-s5pc110/setup-i2c1.c
@@ -0,0 +1,31 @@
+/*
+ * linux/arch/arm/mach-s5pc110/setup-i2c1.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Base S5PC110 I2C bus 1 gpio configuration
+ *
+ * Based on plat-s3c64xx/setup-i2c1.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <mach/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c1_cfg_gpio(struct platform_device *dev)
+{
+	s3c_gpio_cfgpin(S5PC110_GPD1(2), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC110_GPD1(2), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC110_GPD1(3), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC110_GPD1(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pc110/setup-i2c2.c b/arch/arm/mach-s5pc110/setup-i2c2.c
new file mode 100644
index 0000000..b233e28
--- /dev/null
+++ b/arch/arm/mach-s5pc110/setup-i2c2.c
@@ -0,0 +1,32 @@
+/*
+ * linux/arch/arm/mach-s5pc110/setup-i2c2.c
+ *
+ * Copyright (C) 2009 Samsung Electronics Co.Ltd
+ *	Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * Base S5PC110 I2C bus 2 gpio configuration
+ *
+ * Based on plat-s3c64xx/setup-i2c1.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <mach/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c2_cfg_gpio(struct platform_device *dev)
+{
+	s3c_gpio_cfgpin(S5PC110_GPD1(4), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC110_GPD1(4), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC110_GPD1(5), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC110_GPD1(5), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig
index e139a72..afdfca2 100644
--- a/arch/arm/plat-s3c/Kconfig
+++ b/arch/arm/plat-s3c/Kconfig
@@ -194,6 +194,11 @@ config S3C_DEV_I2C1
 	help
 	  Compile in platform device definitions for I2C channel 1
 
+config S3C_DEV_I2C2
+	bool
+	help
+	  Compile in platform device definitions for I2C channel 2
+
 config S3C_DEV_FB
 	bool
 	help
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index 50444da..c40e312 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_S3C_DEV_HSMMC1)	+= dev-hsmmc1.o
 obj-$(CONFIG_S3C_DEV_HSMMC2)	+= dev-hsmmc2.o
 obj-y				+= dev-i2c0.o
 obj-$(CONFIG_S3C_DEV_I2C1)	+= dev-i2c1.o
+obj-$(CONFIG_S3C_DEV_I2C2)	+= dev-i2c2.o
 obj-$(CONFIG_S3C_DEV_FB)	+= dev-fb.o
 obj-$(CONFIG_S3C_DEV_USB_HOST)	+= dev-usb.o
 obj-$(CONFIG_S3C_DEV_USB_HSOTG)	+= dev-usb-hsotg.o
diff --git a/arch/arm/plat-s3c/dev-i2c2.c b/arch/arm/plat-s3c/dev-i2c2.c
new file mode 100644
index 0000000..c1231e0
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-i2c2.c
@@ -0,0 +1,69 @@
+/*
+ * linux/arch/arm/plat-s3c/dev-i2c2.c
+ *
+ * Copyright (C) 2009 Samsung Electronics Co.Ltd
+ *	Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * S3C series device definition for i2c device 2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/cpu.h>
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+
+static struct resource s3c_i2c_resource[] = {
+	[0] = {
+		.start = S3C_PA_IIC2,
+		.end   = S3C_PA_IIC2 + SZ_4K - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_I2C_PMIC_LINK,
+		.end   = IRQ_I2C_PMIC_LINK,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device s3c_device_i2c2 = {
+	.name		  = "s3c2440-i2c",
+	.id		  = 2,
+	.num_resources	  = ARRAY_SIZE(s3c_i2c_resource),
+	.resource	  = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data2 __initdata = {
+	.flags		= 0,
+	.bus_num	= 2,
+	.slave_addr	= 0x10,
+	.frequency	= 400*1000,
+	.sda_delay	= 100,
+};
+
+void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+	struct s3c2410_platform_i2c *npd;
+
+	if (!pd)
+		pd = &default_i2c_data2;
+
+	npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+	if (!npd)
+		printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+	else if (!npd->cfg_gpio)
+		npd->cfg_gpio = s3c_i2c2_cfg_gpio;
+
+	s3c_device_i2c2.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-s3c/include/plat/iic.h b/arch/arm/plat-s3c/include/plat/iic.h
index 67450f1..9f22675 100644
--- a/arch/arm/plat-s3c/include/plat/iic.h
+++ b/arch/arm/plat-s3c/include/plat/iic.h
@@ -54,9 +54,11 @@ struct s3c2410_platform_i2c {
  */
 extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
 extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *i2c);
 
 /* defined by architecture to configure gpio */
 extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
 extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c2_cfg_gpio(struct platform_device *dev);
 
 #endif /* __ASM_ARCH_IIC_H */
-- 
1.6.4

[PATCH 16/19] ARM: S5PC1XX: enable S5PC110 sub-platform

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch enables S5PC110 sub-platform.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 arch/arm/Kconfig              |    1 +
 arch/arm/Makefile             |    1 +
 arch/arm/plat-s5pc1xx/Kconfig |    3 +++
 3 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1c4119c..280c38e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -770,6 +770,7 @@ source "arch/arm/plat-stmp3xxx/Kconfig"
 
 if ARCH_S5PC1XX
 source "arch/arm/mach-s5pc100/Kconfig"
+source "arch/arm/mach-s5pc110/Kconfig"
 endif
 
 source "arch/arm/mach-lh7a40x/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index daea150..d9daa45 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -161,6 +161,7 @@ machine-$(CONFIG_ARCH_S3C2410)		:= s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c24
 machine-$(CONFIG_ARCH_S3C24A0)		:= s3c24a0
 machine-$(CONFIG_ARCH_S3C64XX)		:= s3c6400 s3c6410
 machine-$(CONFIG_ARCH_S5PC100)		:= s5pc100
+machine-$(CONFIG_ARCH_S5PC110)		:= s5pc110
 machine-$(CONFIG_ARCH_SA1100)		:= sa1100
 machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_STMP378X)		:= stmp378x
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index 898cd82..137371f 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -30,6 +30,9 @@ choice
 config ARCH_S5PC100
 	bool "S5PC100"
 
+config ARCH_S5PC110
+	bool "S5PC110"
+
 endchoice
 
 
-- 
1.6.4

[PATCH 17/19] ARM: S5PC1XX: add sdhci platform helpers for s5pc110 sub-platform

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds common SDHCI platform helper for S5PC110 sub-platform.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 arch/arm/mach-s5pc110/Kconfig            |   12 +++
 arch/arm/mach-s5pc110/Makefile           |    2 +
 arch/arm/mach-s5pc110/cpu.c              |    5 +
 arch/arm/mach-s5pc110/setup-sdhci-gpio.c |  123 ++++++++++++++++++++++++++++++
 arch/arm/mach-s5pc110/setup-sdhci.c      |   59 ++++++++++++++
 arch/arm/plat-s3c/include/plat/sdhci.h   |   64 +++++++++++++++
 6 files changed, 265 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/setup-sdhci-gpio.c
 create mode 100644 arch/arm/mach-s5pc110/setup-sdhci.c

diff --git a/arch/arm/mach-s5pc110/Kconfig b/arch/arm/mach-s5pc110/Kconfig
index 123dbd3..47fe703 100644
--- a/arch/arm/mach-s5pc110/Kconfig
+++ b/arch/arm/mach-s5pc110/Kconfig
@@ -34,4 +34,16 @@ config S5PC110_SETUP_I2C2
 	bool
 	help
 	  Common setup code for i2c bus 2.
+
+config S5PC110_SETUP_SDHCI
+        bool
+        select S5PC110_SETUP_SDHCI_GPIO
+        help
+          Internal helper functions for S5PC110 based SDHCI systems
+
+config S5PC110_SETUP_SDHCI_GPIO
+	bool
+	help
+	  Common setup code for SDHCI gpio.
+
 endif
diff --git a/arch/arm/mach-s5pc110/Makefile b/arch/arm/mach-s5pc110/Makefile
index 38be30f..ca1ff96 100644
--- a/arch/arm/mach-s5pc110/Makefile
+++ b/arch/arm/mach-s5pc110/Makefile
@@ -17,5 +17,7 @@ obj-$(CONFIG_CPU_S5PC110)	+= cpu.o
 obj-$(CONFIG_S5PC110_SETUP_I2C0)	+= setup-i2c0.o
 obj-$(CONFIG_S5PC110_SETUP_I2C1)	+= setup-i2c1.o
 obj-$(CONFIG_S5PC110_SETUP_I2C2)	+= setup-i2c2.o
+obj-$(CONFIG_S5PC110_SETUP_SDHCI)       += setup-sdhci.o
+obj-$(CONFIG_S5PC110_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
 
 # machine support
diff --git a/arch/arm/mach-s5pc110/cpu.c b/arch/arm/mach-s5pc110/cpu.c
index d16ba68..e72582f 100644
--- a/arch/arm/mach-s5pc110/cpu.c
+++ b/arch/arm/mach-s5pc110/cpu.c
@@ -86,6 +86,11 @@ void __init s5pc110_map_io(void)
 	iotable_init(s5pc110_iodesc, ARRAY_SIZE(s5pc110_iodesc));
 
 	/* initialise device information early */
+	s5pc110_default_sdhci0();
+	s5pc110_default_sdhci1();
+	s5pc110_default_sdhci2();
+	s5pc110_default_sdhci3();
+
 	/* the i2c devices are directly compatible with s3c2440 */
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
diff --git a/arch/arm/mach-s5pc110/setup-sdhci-gpio.c b/arch/arm/mach-s5pc110/setup-sdhci-gpio.c
new file mode 100644
index 0000000..49db2a0
--- /dev/null
+++ b/arch/arm/mach-s5pc110/setup-sdhci-gpio.c
@@ -0,0 +1,123 @@
+/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
+ *
+ * Copyright 2009 Samsung Eletronics
+ *
+ * S5PC110 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-sdhci.h>
+
+void s5pc110_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+
+	/* Set all the necessary GPG0/GPG1 pins to special-function 2 */
+	for (gpio = S5PC110_GPG0(0); gpio < S5PC110_GPG0(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+	switch (width) {
+	case 8:
+		/* GPG1[3:6] special-funtion 3 */
+		for (gpio = S5PC110_GPG1(3); gpio <= S5PC110_GPG1(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		}
+	case 4:
+		/* GPG0[3:6] special-funtion 2 */
+		for (gpio = S5PC110_GPG0(3); gpio <= S5PC110_GPG0(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		}
+	default:
+		break;
+	}
+
+	s3c_gpio_setpull(S5PC110_GPG0(2), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC110_GPG0(2), S3C_GPIO_SFN(2));
+}
+
+void s5pc110_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+
+	/* Set all the necessary GPG1[0:1] pins to special-function 2 */
+	for (gpio = S5PC110_GPG1(0); gpio < S5PC110_GPG1(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	/* Data pin GPG1[3:6] to special-function 2 */
+	for (gpio = S5PC110_GPG1(3); gpio <= S5PC110_GPG1(6); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	s3c_gpio_setpull(S5PC110_GPG1(2), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC110_GPG1(2), S3C_GPIO_SFN(2));
+}
+
+void s5pc110_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+
+	/* Set all the necessary GPG2[0:1] pins to special-function 2 */
+	for (gpio = S5PC110_GPG2(0); gpio < S5PC110_GPG2(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	switch (width) {
+	case 8:
+		/* Data pin GPG3[3:6] to special-function 3 */
+		for (gpio = S5PC110_GPG3(3); gpio <= S5PC110_GPG3(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		}
+	case 4:
+		/* Data pin GPG2[3:6] to special-function 2 */
+		for (gpio = S5PC110_GPG2(3); gpio <= S5PC110_GPG2(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		}
+	default:
+		break;
+	}
+
+	s3c_gpio_setpull(S5PC110_GPG2(2), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC110_GPG2(2), S3C_GPIO_SFN(2));
+}
+
+void s5pc110_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+
+	/* Set all the necessary GPG3[0:1] pins to special-function 2 */
+	for (gpio = S5PC110_GPG3(0); gpio < S5PC110_GPG3(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	/* Data pin GPG3[3:6] to special-function 2 */
+	for (gpio = S5PC110_GPG3(3); gpio <= S5PC110_GPG3(6); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	s3c_gpio_setpull(S5PC110_GPG3(2), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC110_GPG3(2), S3C_GPIO_SFN(2));
+}
diff --git a/arch/arm/mach-s5pc110/setup-sdhci.c b/arch/arm/mach-s5pc110/setup-sdhci.c
new file mode 100644
index 0000000..c368bb5
--- /dev/null
+++ b/arch/arm/mach-s5pc110/setup-sdhci.c
@@ -0,0 +1,59 @@
+/* linux/arch/arm/mach-s5pc100/setup-sdhci.c
+ *
+ * Copyright 2008 Samsung Electronics
+ *
+ * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+
+char *s5pc110_hsmmc_clksrcs[4] = {
+	[0] = "mmc-bus",
+};
+
+void s5pc110_setup_sdhci_cfg_card(struct platform_device *dev,
+				    void __iomem *r,
+				    struct mmc_ios *ios,
+				    struct mmc_card *card)
+{
+	u32 ctrl2, ctrl3;
+
+	/* don't need to alter anything acording to card-type */
+
+	writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
+
+	ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
+	ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+	ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
+		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
+		  S3C_SDHCI_CTRL2_ENFBCLKRX |
+		  S3C_SDHCI_CTRL2_DFCNT_NONE |
+		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+
+	if (ios->clock < 25 * 1000000)
+		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
+			 S3C_SDHCI_CTRL3_FCSEL2 |
+			 S3C_SDHCI_CTRL3_FCSEL1 |
+			 S3C_SDHCI_CTRL3_FCSEL0);
+	else
+		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
+
+	writel(ctrl2, r + S3C_SDHCI_CONTROL2);
+	writel(ctrl3, r + S3C_SDHCI_CONTROL3);
+}
diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-s3c/include/plat/sdhci.h
index c71d078..cf71b93 100644
--- a/arch/arm/plat-s3c/include/plat/sdhci.h
+++ b/arch/arm/plat-s3c/include/plat/sdhci.h
@@ -74,6 +74,10 @@ extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s5pc110_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s5pc110_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5pc110_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s5pc110_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
 
 /* S3C6400 SDHCI setup */
 
@@ -200,4 +204,64 @@ static inline void s5pc100_default_sdhci1(void) { }
 static inline void s5pc100_default_sdhci2(void) { }
 #endif /* CONFIG_S5PC100_SETUP_SDHCI */
 
+/* S5PC110 SDHCI setup */
+#ifdef CONFIG_S5PC110_SETUP_SDHCI
+extern char *s5pc110_hsmmc_clksrcs[4];
+
+extern void s5pc110_setup_sdhci_cfg_card(struct platform_device *dev,
+					   void __iomem *r,
+					   struct mmc_ios *ios,
+					   struct mmc_card *card);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static inline void s5pc110_default_sdhci0(void)
+{
+	s3c_hsmmc0_def_platdata.clocks = s5pc110_hsmmc_clksrcs;
+	s3c_hsmmc0_def_platdata.cfg_gpio = s5pc110_setup_sdhci0_cfg_gpio;
+	s3c_hsmmc0_def_platdata.cfg_card = s5pc110_setup_sdhci_cfg_card;
+}
+#else
+static inline void s5pc100_default_sdhci0(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC */
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static inline void s5pc110_default_sdhci1(void)
+{
+	s3c_hsmmc1_def_platdata.clocks = s5pc110_hsmmc_clksrcs;
+	s3c_hsmmc1_def_platdata.cfg_gpio = s5pc110_setup_sdhci1_cfg_gpio;
+	s3c_hsmmc1_def_platdata.cfg_card = s5pc110_setup_sdhci_cfg_card;
+}
+#else
+static inline void s5pc110_default_sdhci1(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static inline void s5pc110_default_sdhci2(void)
+{
+	s3c_hsmmc2_def_platdata.clocks = s5pc110_hsmmc_clksrcs;
+	s3c_hsmmc2_def_platdata.cfg_gpio = s5pc110_setup_sdhci2_cfg_gpio;
+	s3c_hsmmc2_def_platdata.cfg_card = s5pc110_setup_sdhci_cfg_card;
+}
+#else
+static inline void s5pc110_default_sdhci2(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC2 */
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+static inline void s5pc110_default_sdhci3(void)
+{
+	s3c_hsmmc3_def_platdata.clocks = s5pc110_hsmmc_clksrcs;
+	s3c_hsmmc3_def_platdata.cfg_gpio = s5pc110_setup_sdhci3_cfg_gpio;
+	s3c_hsmmc3_def_platdata.cfg_card = s5pc110_setup_sdhci_cfg_card;
+}
+#else
+static inline void s5pc110_default_sdhci3(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC3 */
+
+#else
+static inline void s5pc110_default_sdhci0(void) { }
+static inline void s5pc110_default_sdhci1(void) { }
+static inline void s5pc110_default_sdhci2(void) { }
+static inline void s5pc110_default_sdhci3(void) { }
+#endif /* CONFIG_S5PC100_SETUP_SDHCI */
+
 #endif /* __PLAT_S3C_SDHCI_H */
-- 
1.6.4

[PATCH 18/19] ARM: S5PC1XX: add framebuffer platform helpers for s5pc110 sub-platform

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds common framebuffer device helpers and register defines
for S5PC110 sub-platform.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 arch/arm/mach-s5pc110/Kconfig                |    5 ++
 arch/arm/mach-s5pc110/Makefile               |    1 +
 arch/arm/mach-s5pc110/include/mach/regs-fb.h |   91 ++++++++++++++++++++++++++
 arch/arm/mach-s5pc110/setup-fb-24bpp.c       |   63 ++++++++++++++++++
 arch/arm/plat-s3c/include/plat/fb.h          |    7 ++
 5 files changed, 167 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/include/mach/regs-fb.h
 create mode 100644 arch/arm/mach-s5pc110/setup-fb-24bpp.c

diff --git a/arch/arm/mach-s5pc110/Kconfig b/arch/arm/mach-s5pc110/Kconfig
index 47fe703..d06ff1e 100644
--- a/arch/arm/mach-s5pc110/Kconfig
+++ b/arch/arm/mach-s5pc110/Kconfig
@@ -16,6 +16,11 @@ config CPU_S5PC110
 	help
 	  Enable S5PC110 CPU support
 
+config S5PC110_SETUP_FB_24BPP
+	bool
+	help
+          Common setup code for S5PC110 with an 24bpp RGB display helper.
+
 config S5PC110_SETUP_I2C0
 	bool
 	default y
diff --git a/arch/arm/mach-s5pc110/Makefile b/arch/arm/mach-s5pc110/Makefile
index ca1ff96..6fa014c 100644
--- a/arch/arm/mach-s5pc110/Makefile
+++ b/arch/arm/mach-s5pc110/Makefile
@@ -14,6 +14,7 @@ obj-                            :=
 obj-$(CONFIG_CPU_S5PC110)	+= cpu.o
 
 # Helper and device support
+obj-$(CONFIG_S5PC110_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
 obj-$(CONFIG_S5PC110_SETUP_I2C0)	+= setup-i2c0.o
 obj-$(CONFIG_S5PC110_SETUP_I2C1)	+= setup-i2c1.o
 obj-$(CONFIG_S5PC110_SETUP_I2C2)	+= setup-i2c2.o
diff --git a/arch/arm/mach-s5pc110/include/mach/regs-fb.h b/arch/arm/mach-s5pc110/include/mach/regs-fb.h
new file mode 100644
index 0000000..27fa497
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/mach/regs-fb.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2009 Samsung Electronics Co.
+ *   Pawel Osciak <p.osciak@samsung.com>
+ *
+ * Machine-specific framebuffer definitions for Samsung S5PC110.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MACH_REGS_FB_H
+#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
+
+#include <plat/regs-fb-v5.h>
+
+/* WINCONx */
+#define WINCONx_BUFSTATUS_H				(1 << 31)
+#define WINCONx_BUFSEL_H				(1 << 30)
+#define WINCONx_LIMIT_ON				(1 << 29)
+#define WINCONx_EQ709					(1 << 28)
+
+
+/* VIDCON3 */
+#define VIDCON3						(0x0c)
+#define VIDCON3_VE_ON					(1 << 20)
+#define VIDCON3_CG_ON					(1 << 18)
+#define VIDCON3_GM_ON					(1 << 16)
+#define VIDCON3_HU_CSC_F_NARROW				(1 << 14)
+#define VIDCON3_HU_CSC_F_EQ709				(1 << 13)
+#define VIDCON3_HU_CSC_F_EN				(1 << 12)
+#define VIDCON3_HU_CSC_B_NARROW				(1 << 10)
+#define VIDCON3_HU_CSC_B_EQ709				(1 << 9)
+#define VIDCON3_HU_CSC_B_EN				(1 << 8)
+#define VIDCON3_HUE_EN					(1 << 7)
+#define VIDCON3_PC_DIR_NEG				(1 << 1)
+#define VIDCON3_PC_EN					(1 << 0)
+
+
+/* VIDTCON3 */
+#define VIDTCON3					(0x1c)
+#define VIDTCON3_VSYNC_EN				(1 << 31)
+#define VIDTCON3_FRM_EN					(1 << 29)
+#define VIDTCON3_INVFRM_LOW				(1 << 28)
+#define VIDTCON3_FRMVRATE_MASK				0xf
+#define VIDTCON3_FRMVRATE_SHIFT				(24)
+#define VIDTCON3_FRMVFPD_MASK				0xff
+#define VIDTCON3_FRMVFPD_SHIFT				(8)
+#define VIDTCON3_FRMVSPW_MASK				0xff
+#define VIDTCON3_FRMVSPW_SHIFT				(0)
+
+
+#define SHADOWCON					(0x34)
+/* Set to disable window 4-0 shadow registers' update */
+#define SHADOWCON_W4_PROTECT				(1 << 14)
+#define SHADOWCON_W3_PROTECT				(1 << 13)
+#define SHADOWCON_W2_PROTECT				(1 << 12)
+#define SHADOWCON_W1_PROTECT				(1 << 11)
+#define SHADOWCON_W0_PROTECT				(1 << 10)
+
+
+/* Video buffer address shadow registers (read-only) */
+#define VIDW_BUF_START_SHADOW(_buf)			(0x20a0 + ((_buf) * 8))
+#define VIDW_BUF_END_SHADOW(_buf)			(0x20d0 + ((_buf) * 8))
+
+/* For windows 1-4 */
+#define WxKEY_ALPHA(_win)				(0x160 + ((_win) * 4))
+
+#define COLORGAINCON					(0x1c0)
+#define VESFRCON0					(0x1c4)
+#define VESFRCON1					(0x1c8)
+#define VESFRCON2					(0x1cc)
+
+/* Hue matrix coefficients */
+#define HUECOEF00					(0x1ec)
+#define HUECOEF01					(0x1f0)
+#define HUECOEF10					(0x1f4)
+#define HUECOEF11					(0x1f8)
+#define HUEOFFSET					(0x1fc)
+
+/* RTQOS control for windows 0-4*/
+#define WxRTQOSCON(_win)				(0x264 + ((_win) * 4))
+
+/* Gamma LUT data for index I1 and I0, where
+ * I0 = _index, I1 = _index + 1.
+ */
+#define GAMMALUT_BASE					(0x37c)
+#define GAMMALUT_I1I0(_index)			(GAMMALUT_BASE + ((_index) * 4))
+
+#endif /* __ASM_ARCH_MACH_REGS_FB_H */
+
diff --git a/arch/arm/mach-s5pc110/setup-fb-24bpp.c b/arch/arm/mach-s5pc110/setup-fb-24bpp.c
new file mode 100644
index 0000000..da3fed7
--- /dev/null
+++ b/arch/arm/mach-s5pc110/setup-fb-24bpp.c
@@ -0,0 +1,67 @@
+/*
+ * linux/arch/arm/plat-s5pc100/setup-fb-24bpp.c
+ *
+ * Copyright 2009 Samsung Electronics
+ *
+ * Base S5PC110 setup information for 24bpp LCD framebuffer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/fb.h>
+
+#include <mach/regs-fb.h>
+#include <mach/gpio.h>
+#include <mach/map.h>
+#include <plat/fb.h>
+#include <plat/regs-clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-s5pc1xx.h>
+
+void s5pc110_fb_gpio_setup_24bpp(void)
+{
+	unsigned int gpio = 0;
+
+	for (gpio = S5PC110_GPF0(0); gpio <= S5PC110_GPF0(7); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, gpio-S5PC110_GPF0(0),
+				    S5P_GPIO_DRVSTR_LV4);
+	}
+
+	for (gpio = S5PC110_GPF1(0); gpio <= S5PC110_GPF1(7); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, gpio-S5PC110_GPF1(0),
+				    S5P_GPIO_DRVSTR_LV4);
+	}
+
+	for (gpio = S5PC110_GPF2(0); gpio <= S5PC110_GPF2(7); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, gpio-S5PC110_GPF2(0),
+				    S5P_GPIO_DRVSTR_LV4);
+	}
+
+	for (gpio = S5PC110_GPF3(0); gpio <= S5PC110_GPF3(3); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, gpio-S5PC110_GPF3(0),
+				    S5P_GPIO_DRVSTR_LV4);
+	}
+
+	/* Set DISPLAY_CONTROL register for Display path selection.
+	 *
+	 * ouput   |   RGB   |   I80   |   ITU
+	 * -----------------------------------
+	 *  00     |   MIE   |  FIMD   |  FIMD
+	 *  01     | MDNIE   | MDNIE   |  FIMD
+	 *  10     |  FIMD   |  FIMD   |  FIMD
+	 *  11     |  FIMD   |  FIMD   |  FIMD
+	 */
+	writel(0x2, S5PC110_MDNIE_SEL);
+}
diff --git a/arch/arm/plat-s3c/include/plat/fb.h b/arch/arm/plat-s3c/include/plat/fb.h
index f8db879..ee5cdd0 100644
--- a/arch/arm/plat-s3c/include/plat/fb.h
+++ b/arch/arm/plat-s3c/include/plat/fb.h
@@ -77,4 +77,11 @@ extern void s3c64xx_fb_gpio_setup_24bpp(void);
  */
 extern void s5pc100_fb_gpio_setup_24bpp(void);
 
+/**
+ * s5pc110_fb_gpio_setup_24bpp() - S5PC110 setup function for 24bpp LCD
+ *
+ * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
+ */
+extern void s5pc110_fb_gpio_setup_24bpp(void);
+
 #endif /* __PLAT_S3C_FB_H */
-- 
1.6.4

[PATCH 19/19] ARM: S5PC1XX: add support for SMDKC110 board

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds support for SMDKC110 evaluation board. The board can be
obtained from Meritech (http://www.meritech.co.kr).

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 arch/arm/mach-s5pc110/Kconfig         |    6 ++
 arch/arm/mach-s5pc110/Makefile        |    1 +
 arch/arm/mach-s5pc110/mach-smdkc110.c |  102 +++++++++++++++++++++++++++++++++
 3 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/mach-smdkc110.c

diff --git a/arch/arm/mach-s5pc110/Kconfig b/arch/arm/mach-s5pc110/Kconfig
index d06ff1e..7c72c23 100644
--- a/arch/arm/mach-s5pc110/Kconfig
+++ b/arch/arm/mach-s5pc110/Kconfig
@@ -51,4 +51,10 @@ config S5PC110_SETUP_SDHCI_GPIO
 	help
 	  Common setup code for SDHCI gpio.
 
+config MACH_SMDKC110
+	bool "SMDKC110"
+	select CPU_S5PC110
+	help
+	  Machine support for the SMDKC110 board
+
 endif
diff --git a/arch/arm/mach-s5pc110/Makefile b/arch/arm/mach-s5pc110/Makefile
index 6fa014c..deceeb8 100644
--- a/arch/arm/mach-s5pc110/Makefile
+++ b/arch/arm/mach-s5pc110/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_S5PC110_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_S5PC110_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
 
 # machine support
+obj-$(CONFIG_MACH_SMDKC110)	+= mach-smdkc110.o
diff --git a/arch/arm/mach-s5pc110/mach-smdkc110.c b/arch/arm/mach-s5pc110/mach-smdkc110.c
new file mode 100644
index 0000000..62c23ae
--- /dev/null
+++ b/arch/arm/mach-s5pc110/mach-smdkc110.c
@@ -0,0 +1,102 @@
+/*
+ * linux/arch/arm/mach-s5pc110/mach-smdkc110.c
+ *
+ *  Copyright (C) 2009 Samsung Electronics Co.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/map.h>
+
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/s5pc1xx.h>
+
+#define UCON	(S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
+#define ULCON	(S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
+#define UFCON	(S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+
+static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport	     = 0,
+		.flags	     = 0,
+		.ucon	     = 0x3c5,
+		.ulcon	     = 0x03,
+		.ufcon	     = 0x51,
+	},
+	[1] = {
+		.hwport	     = 1,
+		.flags	     = 0,
+		.ucon	     = 0x3c5,
+		.ulcon	     = 0x03,
+		.ufcon	     = 0x51,
+	},
+	[2] = {
+		.hwport	     = 2,
+		.flags	     = 0,
+		.ucon	     = 0x3c5,
+		.ulcon	     = 0x03,
+		.ufcon	     = 0x51,
+	},
+	[3] = {
+		.hwport	     = 3,
+		.flags	     = 0,
+		.ucon	     = 0x3c5,
+		.ulcon	     = 0x03,
+		.ufcon	     = 0x51,
+	},
+};
+
+static struct platform_device *universal_devices[] __initdata = {
+};
+
+static struct map_desc universal_iodesc[] = {};
+
+static void __init universal_map_io(void)
+{
+	s5pc1xx_init_io(universal_iodesc, ARRAY_SIZE(universal_iodesc));
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
+}
+
+static void __init universal_machine_init(void)
+{
+	platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
+}
+
+MACHINE_START(SMDKC110, "SMDKC110")
+	/* Maintainer: Samsung Electronics */
+	.phys_io	= S5PC110_PA_UART & 0xfff00000,
+	.io_pg_offst	= (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc,
+	.boot_params	= S5PC110_PA_SDRAM + 0x100,
+	.init_irq	= s5pc110_init_irq,
+	.map_io		= universal_map_io,
+	.init_machine	= universal_machine_init,
+	.timer		= &s3c24xx_timer,
+MACHINE_END
-- 
1.6.4

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[jassi brar]

On Wed, Nov 18, 2009 at 10:33 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> From: Kyungmin Park <kyungmin.park@samsung.com>
>
> Samsung S5PC110 SoCs have UART that differs a bit from the one known
> from the previous Samsung SoCs. This patch adds support for this new
> driver.
>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>
>
> ---
> ?arch/arm/plat-s3c/include/plat/regs-serial.h | ? 31 ++++++
> ?drivers/serial/Kconfig ? ? ? ? ? ? ? ? ? ? ? | ? ?7 ++
> ?drivers/serial/Makefile ? ? ? ? ? ? ? ? ? ? ?| ? ?1 +
> ?drivers/serial/s5pc110.c ? ? ? ? ? ? ? ? ? ? | ?143 ++++++++++++++++++++++++++
> ?4 files changed, 182 insertions(+), 0 deletions(-)
> ?create mode 100644 drivers/serial/s5pc110.c
>
> diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h
> index 66af75a..910cfba 100644
> --- a/arch/arm/plat-s3c/include/plat/regs-serial.h
> +++ b/arch/arm/plat-s3c/include/plat/regs-serial.h
> @@ -194,6 +194,37 @@
> ?#define S3C64XX_UINTSP ? ? ? ? 0x34
> ?#define S3C64XX_UINTM ? ? ? ? ?0x38
>
> +/* S5PC110 UCON */
> +#define S5PC110_UCON_CLKMASK ? (1<<10)
> +#define S5PC110_UCON_PCLK ? ? ?(0<<10)
> +#define S5PC110_UCON_SCLK_UART (1<<10)
> +
> +/* S5PC110 FIFO trigger levels */
> +#define S5PC110_UFCON_RXTRIG1 ?(0<<4)
> +#define S5PC110_UFCON_RXTRIG4 ?(1<<4)
> +#define S5PC110_UFCON_RXTRIG8 ?(2<<4)
> +#define S5PC110_UFCON_RXTRIG16 (3<<4)
> +#define S5PC110_UFCON_RXTRIG32 (4<<4)
> +#define S5PC110_UFCON_RXTRIG64 (5<<4)
> +#define S5PC110_UFCON_RXTRIG128 ? ? ? ?(6<<4)
> +#define S5PC110_UFCON_RXTRIG256 ? ? ? ?(7<<4)
> +
> +#define S5PC110_UFCON_TXTRIG1 ?(0<<8)
> +#define S5PC110_UFCON_TXTRIG4 ?(1<<8)
> +#define S5PC110_UFCON_TXTRIG8 ?(2<<8)
> +#define S5PC110_UFCON_TXTRIG16 (3<<8)
> +#define S5PC110_UFCON_TXTRIG32 (4<<8)
> +#define S5PC110_UFCON_TXTRIG64 (5<<8)
> +#define S5PC110_UFCON_TXTRIG128 ? ? ? ?(6<<8)
> +#define S5PC110_UFCON_TXTRIG256 ? ? ? ?(7<<8)
> +
> +#define S5PC110_UFSTAT_TXFULL ?(1<<24)
> +#define S5PC110_UFSTAT_RXFULL ?(1<<8)
> +#define S5PC110_UFSTAT_TXSHIFT (16)
> +#define S5PC110_UFSTAT_RXSHIFT (0)
> +#define S5PC110_UFSTAT_TXMASK ?(255<<16)
> +#define S5PC110_UFSTAT_RXMASK ?(255)
> +
> ?#ifndef __ASSEMBLY__
>
> ?/* struct s3c24xx_uart_clksrc
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index e522572..d119cac 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -540,6 +540,13 @@ config SERIAL_S5PC100
> ? ? ? ?help
> ? ? ? ? ?Serial port support for the Samsung S5PC100 SoCs
>
> +config SERIAL_S5PC110
> + ? ? ? tristate "Samsung S5PC110 Serial port support"
> + ? ? ? depends on SERIAL_SAMSUNG && CPU_S5PC110
> + ? ? ? default y
> + ? ? ? help
> + ? ? ? ? Serial port support for the Samsung S5PC110 SoCs
> +
> ?config SERIAL_MAX3100
> ? ? ? ?tristate "MAX3100 support"
> ? ? ? ?depends on SPI
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index d21d5dd..43d6123 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -45,6 +45,7 @@ obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
> ?obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
> ?obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
> ?obj-$(CONFIG_SERIAL_S5PC100) += s3c6400.o
> +obj-$(CONFIG_SERIAL_S5PC110) += s5pc110.o
> ?obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
> ?obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
> ?obj-$(CONFIG_SERIAL_MUX) += mux.o
> diff --git a/drivers/serial/s5pc110.c b/drivers/serial/s5pc110.c
> new file mode 100644
> index 0000000..1e1e229
> --- /dev/null
> +++ b/drivers/serial/s5pc110.c
> @@ -0,0 +1,143 @@
> +/*
> + * linux/drivers/serial/s5pc110.c
> + *
> + * Driver for Samsung S5PC110 SoC onboard UARTs.
> + *
> + * ?Copyright 2009 Samsung Electronics
> + * ?Kyungin Park <kyungmin.park@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/ioport.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +#include <linux/init.h>
> +#include <linux/serial_core.h>
> +#include <linux/serial.h>
> +
> +#include <asm/irq.h>
> +#include <mach/hardware.h>
> +
> +#include <plat/regs-serial.h>
> +
> +#include "samsung.h"
> +
> +static int s5pc110_serial_setsource(struct uart_port *port,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct s3c24xx_uart_clksrc *clk)
> +{
> + ? ? ? unsigned long ucon = rd_regl(port, S3C2410_UCON);
> +
> + ? ? ? if (strcmp(clk->name, "uclk0") == 0)
> + ? ? ? ? ? ? ? ucon |= S5PC110_UCON_SCLK_UART;
> + ? ? ? else if (strcmp(clk->name, "pclk") == 0)
> + ? ? ? ? ? ? ? /* See notes about transitioning from UCLK to PCLK */
> + ? ? ? ? ? ? ? ucon &= ~S5PC110_UCON_SCLK_UART;
> + ? ? ? else {
> + ? ? ? ? ? ? ? printk(KERN_ERR "unknown clock source %s\n", clk->name);
> + ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? }
> +
> + ? ? ? wr_regl(port, S3C2410_UCON, ucon);
> + ? ? ? return 0;
> +}
Not just about this c110 patch: I think this string comparison thing
isn't very neat.
I think we'd better be doing it by indexing into an array of clock
names(which can be
defined in some platform specific code).

> +static int s5pc110_serial_getsource(struct uart_port *port,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct s3c24xx_uart_clksrc *clk)
> +{
> + ? ? ? u32 ucon = rd_regl(port, S3C2410_UCON);
> +
> + ? ? ? clk->divisor = 1;
> +
> + ? ? ? switch (ucon & S5PC110_UCON_CLKMASK) {
> + ? ? ? case S5PC110_UCON_SCLK_UART:
> + ? ? ? ? ? ? ? clk->name = "uclk0";
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case S5PC110_UCON_PCLK:
> + ? ? ? ? ? ? ? clk->name = "pclk";
> + ? ? ? ? ? ? ? break;
> + ? ? ? }
> +
> + ? ? ? return 0;
> +}
> +
> +static int s5pc110_serial_resetport(struct uart_port *port,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct s3c2410_uartcfg *cfg)
> +{
> + ? ? ? unsigned long ucon = rd_regl(port, S3C2410_UCON);
> +
> + ? ? ? dbg("s5pc110_serial_resetport: port=%p (%08lx), cfg=%p\n",
> + ? ? ? ? ? port, port->mapbase, cfg);
> +
> + ? ? ? /* ensure we don't change the clock settings... */
> +
> + ? ? ? ucon &= S5PC110_UCON_CLKMASK;
> +
> + ? ? ? wr_regl(port, S3C2410_UCON, ?ucon | cfg->ucon);
> + ? ? ? wr_regl(port, S3C2410_ULCON, cfg->ulcon);
> +
> + ? ? ? /* reset both fifos */
> +
> + ? ? ? wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
> + ? ? ? wr_regl(port, S3C2410_UFCON, cfg->ufcon);
> +
> + ? ? ? return 0;
> +}
> +
> +static struct s3c24xx_uart_info s5pc110_uart_inf = {
> + ? ? ? .name ? ? ? ? ? = "Samsung S5PC110 UART",
> + ? ? ? .type ? ? ? ? ? = PORT_S3C6400,
> + ? ? ? .fifosize ? ? ? = 16,
> + ? ? ? .has_divslot ? ?= 1,
> + ? ? ? .rx_fifomask ? ?= S5PC110_UFSTAT_RXMASK,
> + ? ? ? .rx_fifoshift ? = S5PC110_UFSTAT_RXSHIFT,
> + ? ? ? .rx_fifofull ? ?= S5PC110_UFSTAT_RXFULL,
> + ? ? ? .tx_fifofull ? ?= S5PC110_UFSTAT_TXFULL,
> + ? ? ? .tx_fifomask ? ?= S5PC110_UFSTAT_TXMASK,
> + ? ? ? .tx_fifoshift ? = S5PC110_UFSTAT_TXSHIFT,
> + ? ? ? .get_clksrc ? ? = s5pc110_serial_getsource,
> + ? ? ? .set_clksrc ? ? = s5pc110_serial_setsource,
> + ? ? ? .reset_port ? ? = s5pc110_serial_resetport,
> +};
> +
> +/* device management */
> +
> +static int s5pc110_serial_probe(struct platform_device *dev)
> +{
> + ? ? ? dbg("s5pc110_serial_probe: dev=%p\n", dev);
> +
> + ? ? ? return s3c24xx_serial_probe(dev, &s5pc110_uart_inf);
> +}
> +
> +static struct platform_driver s5pc110_serial_driver = {
> + ? ? ? .probe ? ? ? ? ?= s5pc110_serial_probe,
> + ? ? ? .remove ? ? ? ? = __devexit_p(s3c24xx_serial_remove),
> + ? ? ? .driver ? ? ? ? = {
> + ? ? ? ? ? ? ? .name ? = "s5pc110-uart",
> + ? ? ? ? ? ? ? .owner ?= THIS_MODULE,
> + ? ? ? },
> +};
> +
> +s3c24xx_console_init(&s5pc110_serial_driver, &s5pc110_uart_inf);
> +
> +static int __init s5pc110_serial_init(void)
> +{
> + ? ? ? return s3c24xx_serial_init(&s5pc110_serial_driver, &s5pc110_uart_inf);
> +}
> +
> +static void __exit s5pc110_serial_exit(void)
> +{
> + ? ? ? platform_driver_unregister(&s5pc110_serial_driver);
> +}
> +
> +module_init(s5pc110_serial_init);
> +module_exit(s5pc110_serial_exit);
> +
> +MODULE_DESCRIPTION("Samsung S5PC110 SoC Serial port driver");
> +MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:s5pc110-uart");
> --
> 1.6.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>

[PATCH 08/19] ARM: S5PC1XX: move common s5pc1xx s3c-fb regs to platform directory

[Ben Dooks]

On Wed, Nov 18, 2009 at 02:33:03PM +0100, Marek Szyprowski wrote:
> From: Pawel Osciak <p.osciak@samsung.com>
> 
> From: Pawel Osciak <p.osciak@samsung.com>
> 
> Frame buffer register block on S5PC100 and S5PC110 differs slightly.
> This patch moves all register definitions that are common for S5PC100
> and S5PC110 to plat-s3c/plat/regs-fb-v5.h.

From: Pawel Osciak <p.osciak@samsung.com> but no signoff from him.
 
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> 
> ---
>  arch/arm/mach-s5pc100/include/mach/regs-fb.h |  133 ++-----------------------
>  arch/arm/plat-s3c/include/plat/regs-fb-v5.h  |  138 ++++++++++++++++++++++++++
>  2 files changed, 146 insertions(+), 125 deletions(-)
>  create mode 100644 arch/arm/plat-s3c/include/plat/regs-fb-v5.h
> 
> diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
> index 1732cd2..49764cb 100644
> --- a/arch/arm/mach-s5pc100/include/mach/regs-fb.h
> +++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
> @@ -1,139 +1,22 @@
> -/* arch/arm/mach-s5pc100/include/mach/regs-fb.h
> - *
> +/*
>   * Copyright 2009 Samsung Electronics Co.
>   *   Pawel Osciak <p.osciak@samsung.com>
>   *
> - * Framebuffer register definitions for Samsung S5PC100.
> + * Machine-specific framebuffer definitions for Samsung S5PC100.
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 as
>   * published by the Free Software Foundation.
> -*/
> -
> -#ifndef __ASM_ARCH_REGS_FB_H
> -#define __ASM_ARCH_REGS_FB_H __FILE__
> -
> -#include <plat/regs-fb-v4.h>
> -
> -/* VP1 interface timing control */
> -#define VP1CON0						(0x118)
> -#define VP1_RATECON_EN					(1 << 31)
> -#define VP1_CLKRATE_MASK				(0xff)
> -
> -#define VP1CON1						(0x11c)
> -#define VP1_VTREGCON_EN					(1 << 31)
> -#define VP1_VBPD_MASK					(0xfff)
> -#define VP1_VBPD_SHIFT					(16)
> -
> -
> -#define WPALCON_H					(0x19c)
> -#define WPALCON_L					(0x1a0)
> -
> -/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but
> - * different for WPAL2-4
> - */
> -/* In WPALCON_L (aka WPALCON) */
> -#define WPALCON_W1PAL_32BPP_A888			(0x7 << 3)
> -#define WPALCON_W0PAL_32BPP_A888			(0x7 << 0)
> -
> -/* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H,
> - * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]).
> - */
> -#define WPALCON_L_WxPAL_L_MASK				(0x1)
> -#define WPALCON_L_W2PAL_L_SHIFT				(6)
> -#define WPALCON_L_W3PAL_L_SHIFT				(7)
> -#define WPALCON_L_W4PAL_L_SHIFT				(8)
> -
> -#define WPALCON_L_WxPAL_H_MASK				(0x3)
> -#define WPALCON_H_W2PAL_H_SHIFT				(9)
> -#define WPALCON_H_W3PAL_H_SHIFT				(13)
> -#define WPALCON_H_W4PAL_H_SHIFT				(17)
> -
> -/* Per-window alpha value registers */
> -/* For window 0 8-bit alpha values are in VIDW0ALPHAx,
> - * for windows 1-4 alpha values consist of two parts, the 4 low bits are
> - * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC,
> - * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0])
> - */
> -#define VIDWxALPHA0(_win)				(0x200 + (_win * 8))
> -#define VIDWxALPHA1(_win)				(0x204 + (_win * 8))
> -
> -/* Only for window 0 in VIDW0ALPHAx. */
> -#define VIDW0ALPHAx_R(_x)				((_x) << 16)
> -#define VIDW0ALPHAx_R_MASK				(0xff << 16)
> -#define VIDW0ALPHAx_R_SHIFT				(16)
> -#define VIDW0ALPHAx_G(_x)				((_x) << 8)
> -#define VIDW0ALPHAx_G_MASK				(0xff << 8)
> -#define VIDW0ALPHAx_G_SHIFT				(8)
> -#define VIDW0ALPHAx_B(_x)				((_x) << 0)
> -#define VIDW0ALPHAx_B_MASK				(0xff << 0)
> -#define VIDW0ALPHAx_B_SHIFT				(0)
> -
> -/* Low 4 bits of alpha0-1 for windows 1-4 */
> -#define VIDW14ALPHAx_R_L(_x)				((_x) << 16)
> -#define VIDW14ALPHAx_R_L_MASK				(0xf << 16)
> -#define VIDW14ALPHAx_R_L_SHIFT				(16)
> -#define VIDW14ALPHAx_G_L(_x)				((_x) << 8)
> -#define VIDW14ALPHAx_G_L_MASK				(0xf << 8)
> -#define VIDW14ALPHAx_G_L_SHIFT				(8)
> -#define VIDW14ALPHAx_B_L(_x)				((_x) << 0)
> -#define VIDW14ALPHAx_B_L_MASK				(0xf << 0)
> -#define VIDW14ALPHAx_B_L_SHIFT				(0)
> -
> -
> -/* Per-window blending equation control registers */
> -#define BLENDEQx(_win)					(0x244 + ((_win) * 4))
> -#define BLENDEQ1					(0x244)
> -#define BLENDEQ2					(0x248)
> -#define BLENDEQ3					(0x24c)
> -#define BLENDEQ4					(0x250)
> -
> -#define BLENDEQx_Q_FUNC(_x)				((_x) << 18)
> -#define BLENDEQx_Q_FUNC_MASK				(0xf << 18)
> -#define BLENDEQx_P_FUNC(_x)				((_x) << 12)
> -#define BLENDEQx_P_FUNC_MASK				(0xf << 12)
> -#define BLENDEQx_B_FUNC(_x)				((_x) << 6)
> -#define BLENDEQx_B_FUNC_MASK				(0xf << 6)
> -#define BLENDEQx_A_FUNC(_x)				((_x) << 0)
> -#define BLENDEQx_A_FUNC_MASK				(0xf << 0)
> -
> -#define BLENDCON					(0x260)
> -#define BLENDCON_8BIT_ALPHA				(1 << 0)
> -
> -/* Per-window palette base addresses (start of palette memory).
> - * Each window palette area consists of 256 32-bit entries.
> - * START is the first address (entry 0th), END is the address of 255th entry.
>   */
> -#define WIN0_PAL_BASE					(0x2400)
> -#define WIN0_PAL_END					(0x27fc)
> -#define WIN1_PAL_BASE					(0x2800)
> -#define WIN1_PAL_END					(0x2bfc)
> -#define WIN2_PAL_BASE					(0x2c00)
> -#define WIN2_PAL_END					(0x2ffc)
> -#define WIN3_PAL_BASE					(0x3000)
> -#define WIN3_PAL_END					(0x33fc)
> -#define WIN4_PAL_BASE					(0x3400)
> -#define WIN4_PAL_END					(0x37fc)
>  
> -#define WIN0_PAL(_entry)			(WIN0_PAL_BASE + ((_entry) * 4))
> -#define WIN1_PAL(_entry)			(WIN1_PAL_BASE + ((_entry) * 4))
> -#define WIN2_PAL(_entry)			(WIN2_PAL_BASE + ((_entry) * 4))
> -#define WIN3_PAL(_entry)			(WIN3_PAL_BASE + ((_entry) * 4))
> -#define WIN4_PAL(_entry)			(WIN4_PAL_BASE + ((_entry) * 4))
> +#ifndef __ASM_ARCH_MACH_REGS_FB_H
> +#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
>  
> -static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
> -{
> -	switch (window) {
> -	case 0: return WIN0_PAL(reg);
> -	case 1: return WIN1_PAL(reg);
> -	case 2: return WIN2_PAL(reg);
> -	case 3: return WIN3_PAL(reg);
> -	case 4: return WIN4_PAL(reg);
> -	}
> +#include <plat/regs-fb-v5.h>
>  
> -	BUG();
> -}
> +#define PRTCON						(0xc)
> +#define PRTCON_PROTECT					(1 << 11)
>  
>  
> -#endif /* __ASM_ARCH_REGS_FB_H */
> +#endif /* __ASM_ARCH_MACH_REGS_FB_H */
>  
> diff --git a/arch/arm/plat-s3c/include/plat/regs-fb-v5.h b/arch/arm/plat-s3c/include/plat/regs-fb-v5.h
> new file mode 100644
> index 0000000..198c7f5
> --- /dev/null
> +++ b/arch/arm/plat-s3c/include/plat/regs-fb-v5.h
> @@ -0,0 +1,138 @@
> +/*
> + * Copyright 2009 Samsung Electronics Co.
> + *   Pawel Osciak <p.osciak@samsung.com>
> + *
> + * Framebuffer register definitions for Samsung S5PC1xx.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __ASM_ARCH_REGS_FB_V5_H
> +#define __ASM_ARCH_REGS_FB_V5_H __FILE__
> +
> +#include <plat/regs-fb-v4.h>
> +
> +/* VP1 interface timing control */
> +#define VP1CON0						(0x118)
> +#define VP1_RATECON_EN					(1 << 31)
> +#define VP1_CLKRATE_MASK				(0xff)
> +
> +#define VP1CON1						(0x11c)
> +#define VP1_VTREGCON_EN					(1 << 31)
> +#define VP1_VBPD_MASK					(0xfff)
> +#define VP1_VBPD_SHIFT					(16)
> +
> +
> +#define WPALCON_H					(0x19c)
> +#define WPALCON_L					(0x1a0)
> +
> +/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but
> + * different for WPAL2-4
> + */
> +/* In WPALCON_L (aka WPALCON) */
> +#define WPALCON_W1PAL_32BPP_A888			(0x7 << 3)
> +#define WPALCON_W0PAL_32BPP_A888			(0x7 << 0)
> +
> +/* W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H,
> + * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]).
> + */
> +#define WPALCON_L_WxPAL_L_MASK				(0x1)
> +#define WPALCON_L_W2PAL_L_SHIFT				(6)
> +#define WPALCON_L_W3PAL_L_SHIFT				(7)
> +#define WPALCON_L_W4PAL_L_SHIFT				(8)
> +
> +#define WPALCON_L_WxPAL_H_MASK				(0x3)
> +#define WPALCON_H_W2PAL_H_SHIFT				(9)
> +#define WPALCON_H_W3PAL_H_SHIFT				(13)
> +#define WPALCON_H_W4PAL_H_SHIFT				(17)
> +
> +/* Per-window alpha value registers */
> +/* For window 0 8-bit alpha values are in VIDW0ALPHAx,
> + * for windows 1-4 alpha values consist of two parts, the 4 low bits are
> + * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC,
> + * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0])
> + */
> +#define VIDWxALPHA0(_win)				(0x200 + (_win * 8))
> +#define VIDWxALPHA1(_win)				(0x204 + (_win * 8))
> +
> +/* Only for window 0 in VIDW0ALPHAx. */
> +#define VIDW0ALPHAx_R(_x)				((_x) << 16)
> +#define VIDW0ALPHAx_R_MASK				(0xff << 16)
> +#define VIDW0ALPHAx_R_SHIFT				(16)
> +#define VIDW0ALPHAx_G(_x)				((_x) << 8)
> +#define VIDW0ALPHAx_G_MASK				(0xff << 8)
> +#define VIDW0ALPHAx_G_SHIFT				(8)
> +#define VIDW0ALPHAx_B(_x)				((_x) << 0)
> +#define VIDW0ALPHAx_B_MASK				(0xff << 0)
> +#define VIDW0ALPHAx_B_SHIFT				(0)
> +
> +/* Low 4 bits of alpha0-1 for windows 1-4 */
> +#define VIDW14ALPHAx_R_L(_x)				((_x) << 16)
> +#define VIDW14ALPHAx_R_L_MASK				(0xf << 16)
> +#define VIDW14ALPHAx_R_L_SHIFT				(16)
> +#define VIDW14ALPHAx_G_L(_x)				((_x) << 8)
> +#define VIDW14ALPHAx_G_L_MASK				(0xf << 8)
> +#define VIDW14ALPHAx_G_L_SHIFT				(8)
> +#define VIDW14ALPHAx_B_L(_x)				((_x) << 0)
> +#define VIDW14ALPHAx_B_L_MASK				(0xf << 0)
> +#define VIDW14ALPHAx_B_L_SHIFT				(0)
> +
> +
> +/* Per-window blending equation control registers */
> +#define BLENDEQx(_win)					(0x244 + ((_win) * 4))
> +#define BLENDEQ1					(0x244)
> +#define BLENDEQ2					(0x248)
> +#define BLENDEQ3					(0x24c)
> +#define BLENDEQ4					(0x250)
> +
> +#define BLENDEQx_Q_FUNC(_x)				((_x) << 18)
> +#define BLENDEQx_Q_FUNC_MASK				(0xf << 18)
> +#define BLENDEQx_P_FUNC(_x)				((_x) << 12)
> +#define BLENDEQx_P_FUNC_MASK				(0xf << 12)
> +#define BLENDEQx_B_FUNC(_x)				((_x) << 6)
> +#define BLENDEQx_B_FUNC_MASK				(0xf << 6)
> +#define BLENDEQx_A_FUNC(_x)				((_x) << 0)
> +#define BLENDEQx_A_FUNC_MASK				(0xf << 0)
> +
> +#define BLENDCON					(0x260)
> +#define BLENDCON_8BIT_ALPHA				(1 << 0)
> +
> +/* Per-window palette base addresses (start of palette memory).
> + * Each window palette area consists of 256 32-bit entries.
> + * START is the first address (entry 0th), END is the address of 255th entry.
> + */
> +#define WIN0_PAL_BASE					(0x2400)
> +#define WIN0_PAL_END					(0x27fc)
> +#define WIN1_PAL_BASE					(0x2800)
> +#define WIN1_PAL_END					(0x2bfc)
> +#define WIN2_PAL_BASE					(0x2c00)
> +#define WIN2_PAL_END					(0x2ffc)
> +#define WIN3_PAL_BASE					(0x3000)
> +#define WIN3_PAL_END					(0x33fc)
> +#define WIN4_PAL_BASE					(0x3400)
> +#define WIN4_PAL_END					(0x37fc)
> +
> +#define WIN0_PAL(_entry)			(WIN0_PAL_BASE + ((_entry) * 4))
> +#define WIN1_PAL(_entry)			(WIN1_PAL_BASE + ((_entry) * 4))
> +#define WIN2_PAL(_entry)			(WIN2_PAL_BASE + ((_entry) * 4))
> +#define WIN3_PAL(_entry)			(WIN3_PAL_BASE + ((_entry) * 4))
> +#define WIN4_PAL(_entry)			(WIN4_PAL_BASE + ((_entry) * 4))
> +
> +static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
> +{
> +	switch (window) {
> +	case 0: return WIN0_PAL(reg);
> +	case 1: return WIN1_PAL(reg);
> +	case 2: return WIN2_PAL(reg);
> +	case 3: return WIN3_PAL(reg);
> +	case 4: return WIN4_PAL(reg);
> +	}
> +
> +	BUG();
> +}
> +
> +
> +#endif /* __ASM_ARCH_REGS_FB_V5_H */
> +
> -- 
> 1.6.4
> 

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.

[PATCH 10/19] ARM: S5PC1XX: add S5PC110 memory map

[Ben Dooks]

There's stuff in here from 'Byungho Min <bhmin@samsung.com>'
but no mention of an ack or signoff from this person.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.

[PATCH 14/19] ARM: S5PC1XX: add support for s5pc110 gpio

[Ben Dooks]

On Wed, Nov 18, 2009 at 02:33:09PM +0100, Marek Szyprowski wrote:
> From: Kyungmin Park <kyungmin.park@samsung.com>
> 
> Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
> on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
> This patch adds gpiolib support for S5PC110 sub-platform.

Hmm, another file with Byungho Min <bhmin@samsung.com> in and no signoff
from this person.
 
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> 
> ---
>  arch/arm/mach-s5pc110/include/mach/gpio.h      |  149 +++++++++++++
>  arch/arm/mach-s5pc110/include/plat/regs-gpio.h |   65 ++++++
>  arch/arm/plat-s5pc1xx/gpiolib.c                |  266 ++++++++++++++++++++++++
>  arch/arm/plat-s5pc1xx/irq-gpio.c               |  110 ++++++++++
>  4 files changed, 590 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-s5pc110/include/mach/gpio.h
>  create mode 100644 arch/arm/mach-s5pc110/include/plat/regs-gpio.h
> 
> diff --git a/arch/arm/mach-s5pc110/include/mach/gpio.h b/arch/arm/mach-s5pc110/include/mach/gpio.h
> new file mode 100644
> index 0000000..f83e5c9
> --- /dev/null
> +++ b/arch/arm/mach-s5pc110/include/mach/gpio.h
> @@ -0,0 +1,149 @@
> +/* arch/arm/mach-s5pc110/include/mach/gpio.h
> + *
> + * Copyright 2009 Samsung Electronics Co.
> + *	Byungho Min <bhmin@samsung.com>
> + *
> + * S5PC110 - GPIO lib support
> + *
> + * Base on mach-s3c6400/include/mach/gpio.h
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#define gpio_get_value	__gpio_get_value
> +#define gpio_set_value	__gpio_set_value
> +#define gpio_cansleep	__gpio_cansleep
> +#define gpio_to_irq	__gpio_to_irq
> +
> +/* GPIO bank sizes */
> +#define S5PC110_GPIO_A0_NR	(8)
> +#define S5PC110_GPIO_A1_NR	(8)
> +#define S5PC110_GPIO_B_NR	(8)
> +#define S5PC110_GPIO_C0_NR	(8)
> +#define S5PC110_GPIO_C1_NR	(8)
> +#define S5PC110_GPIO_D0_NR	(8)
> +#define S5PC110_GPIO_D1_NR	(8)
> +#define S5PC110_GPIO_E0_NR	(8)
> +#define S5PC110_GPIO_E1_NR	(8)
> +#define S5PC110_GPIO_F0_NR	(8)
> +#define S5PC110_GPIO_F1_NR	(8)
> +#define S5PC110_GPIO_F2_NR	(8)
> +#define S5PC110_GPIO_F3_NR	(8)
> +#define S5PC110_GPIO_G0_NR	(8)
> +#define S5PC110_GPIO_G1_NR	(8)
> +#define S5PC110_GPIO_G2_NR	(8)
> +#define S5PC110_GPIO_G3_NR	(8)
> +#define S5PC110_GPIO_H0_NR	(8)
> +#define S5PC110_GPIO_H1_NR	(8)
> +#define S5PC110_GPIO_H2_NR	(8)
> +#define S5PC110_GPIO_H3_NR	(8)
> +#define S5PC110_GPIO_I_NR	(8)
> +#define S5PC110_GPIO_J0_NR	(8)
> +#define S5PC110_GPIO_J1_NR	(8)
> +#define S5PC110_GPIO_J2_NR	(8)
> +#define S5PC110_GPIO_J3_NR	(8)
> +#define S5PC110_GPIO_J4_NR	(8)
> +#define S5PC110_GPIO_MP0_1_NR	(8)
> +#define S5PC110_GPIO_MP0_2_NR	(8)
> +#define S5PC110_GPIO_MP0_3_NR	(8)
> +#define S5PC110_GPIO_MP0_4_NR	(8)
> +#define S5PC110_GPIO_MP0_5_NR	(8)
> +#define S5PC110_GPIO_MP0_6_NR	(8)
> +
> +/* GPIO bank numbes */
> +
> +/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
> + * space for debugging purposes so that any accidental
> + * change from one gpio bank to another can be caught.
> +*/
> +
> +#define S5PC1XX_GPIO_NEXT(__gpio) \
> +	((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
> +
> +enum s5pc110_gpio_number {
> +	S5PC110_GPIO_A0_START	= 0,
> +	S5PC110_GPIO_A1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_A0),
> +	S5PC110_GPIO_B_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_A1),
> +	S5PC110_GPIO_C0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_B),
> +	S5PC110_GPIO_C1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_C0),
> +	S5PC110_GPIO_D0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_C1),
> +	S5PC110_GPIO_D1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_D0),
> +	S5PC110_GPIO_E0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_D1),
> +	S5PC110_GPIO_E1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_E0),
> +	S5PC110_GPIO_F0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_E1),
> +	S5PC110_GPIO_F1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_F0),
> +	S5PC110_GPIO_F2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_F1),
> +	S5PC110_GPIO_F3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_F2),
> +	S5PC110_GPIO_G0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_F3),
> +	S5PC110_GPIO_G1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_G0),
> +	S5PC110_GPIO_G2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_G1),
> +	S5PC110_GPIO_G3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_G2),
> +	S5PC110_GPIO_H0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_G3),
> +	S5PC110_GPIO_H1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_H0),
> +	S5PC110_GPIO_H2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_H1),
> +	S5PC110_GPIO_H3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_H2),
> +	S5PC110_GPIO_I_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_H3),
> +	S5PC110_GPIO_J0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_I),
> +	S5PC110_GPIO_J1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J0),
> +	S5PC110_GPIO_J2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J1),
> +	S5PC110_GPIO_J3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J2),
> +	S5PC110_GPIO_J4_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J3),
> +	S5PC110_GPIO_MP0_1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J4),
> +	S5PC110_GPIO_MP0_2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_1),
> +	S5PC110_GPIO_MP0_3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_2),
> +	S5PC110_GPIO_MP0_4_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_3),
> +	S5PC110_GPIO_MP0_5_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_4),
> +	S5PC110_GPIO_MP0_6_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_5),
> +	S5PC110_GPIO_END        = S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_6),
> +};
> +
> +#define S5PC110_GPA0(_nr)	(S5PC110_GPIO_A0_START + (_nr))
> +#define S5PC110_GPA1(_nr)	(S5PC110_GPIO_A1_START + (_nr))
> +#define S5PC110_GPB(_nr)	(S5PC110_GPIO_B_START + (_nr))
> +#define S5PC110_GPC0(_nr)	(S5PC110_GPIO_C0_START + (_nr))
> +#define S5PC110_GPC1(_nr)	(S5PC110_GPIO_C1_START + (_nr))
> +#define S5PC110_GPD0(_nr)	(S5PC110_GPIO_D0_START + (_nr))
> +#define S5PC110_GPD1(_nr)	(S5PC110_GPIO_D1_START + (_nr))
> +#define S5PC110_GPE0(_nr)	(S5PC110_GPIO_E0_START + (_nr))
> +#define S5PC110_GPE1(_nr)	(S5PC110_GPIO_E1_START + (_nr))
> +#define S5PC110_GPF0(_nr)	(S5PC110_GPIO_F0_START + (_nr))
> +#define S5PC110_GPF1(_nr)	(S5PC110_GPIO_F1_START + (_nr))
> +#define S5PC110_GPF2(_nr)	(S5PC110_GPIO_F2_START + (_nr))
> +#define S5PC110_GPF3(_nr)	(S5PC110_GPIO_F3_START + (_nr))
> +#define S5PC110_GPG0(_nr)	(S5PC110_GPIO_G0_START + (_nr))
> +#define S5PC110_GPG1(_nr)	(S5PC110_GPIO_G1_START + (_nr))
> +#define S5PC110_GPG2(_nr)	(S5PC110_GPIO_G2_START + (_nr))
> +#define S5PC110_GPG3(_nr)	(S5PC110_GPIO_G3_START + (_nr))
> +#define S5PC110_GPH0(_nr)	(S5PC110_GPIO_H0_START + (_nr))
> +#define S5PC110_GPH1(_nr)	(S5PC110_GPIO_H1_START + (_nr))
> +#define S5PC110_GPH2(_nr)	(S5PC110_GPIO_H2_START + (_nr))
> +#define S5PC110_GPH3(_nr)	(S5PC110_GPIO_H3_START + (_nr))
> +#define S5PC110_GPI(_nr)	(S5PC110_GPIO_I_START + (_nr))
> +#define S5PC110_GPJ0(_nr)	(S5PC110_GPIO_J0_START + (_nr))
> +#define S5PC110_GPJ1(_nr)	(S5PC110_GPIO_J1_START + (_nr))
> +#define S5PC110_GPJ2(_nr)	(S5PC110_GPIO_J2_START + (_nr))
> +#define S5PC110_GPJ3(_nr)	(S5PC110_GPIO_J3_START + (_nr))
> +#define S5PC110_GPJ4(_nr)	(S5PC110_GPIO_J4_START + (_nr))
> +#define S5PC110_MP0_1(_nr)	(S5PC110_GPIO_MP0_1_START + (_nr))
> +#define S5PC110_MP0_2(_nr)	(S5PC110_GPIO_MP0_2_START + (_nr))
> +#define S5PC110_MP0_3(_nr)	(S5PC110_GPIO_MP0_3_START + (_nr))
> +#define S5PC110_MP0_4(_nr)	(S5PC110_GPIO_MP0_4_START + (_nr))
> +#define S5PC110_MP0_5(_nr)	(S5PC110_GPIO_MP0_5_START + (_nr))
> +#define S5PC110_MP0_6(_nr)	(S5PC110_GPIO_MP0_6_START + (_nr))
> +
> +/* It used the end of the S5PC100 gpios */
> +#define S3C_GPIO_END		S5PC110_GPIO_END
> +
> +/* define the number of gpios we need to the one after the MP05() range */
> +#define ARCH_NR_GPIOS		(S5PC110_GPIO_END + 1)
> +
> +/* Common compatibility defines */
> +#define S5PC1XX_GPIO_EINT_SFN	S3C_GPIO_SFN(0xf)
> +#define S5PC1XX_GPH0(n)		S5PC110_GPH0(n)
> +#define S5PC1XX_GPH1(n)		S5PC110_GPH1(n)
> +#define S5PC1XX_GPH2(n)		S5PC110_GPH2(n)
> +#define S5PC1XX_GPH3(n)		S5PC110_GPH3(n)
> +
> +#include <asm-generic/gpio.h>
> diff --git a/arch/arm/mach-s5pc110/include/plat/regs-gpio.h b/arch/arm/mach-s5pc110/include/plat/regs-gpio.h
> new file mode 100644
> index 0000000..24663b8
> --- /dev/null
> +++ b/arch/arm/mach-s5pc110/include/plat/regs-gpio.h
> @@ -0,0 +1,65 @@
> +/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
> + *
> + * Copyright 2009 Samsung Electronics Co.
> + *      Byungho Min <bhmin@samsung.com>
> + *
> + * S5PC110 - GPIO register definitions
> + */
> +
> +#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H
> +#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__
> +
> +#include <mach/map.h>
> +
> +/* S5PC110 */
> +#define S5PC110_GPIO_BASE	S5PC1XX_VA_GPIO
> +#define S5PC110_GPA0_BASE	(S5PC110_GPIO_BASE + 0x0000)
> +#define S5PC110_GPA1_BASE	(S5PC110_GPIO_BASE + 0x0020)
> +#define S5PC110_GPB_BASE	(S5PC110_GPIO_BASE + 0x0040)
> +#define S5PC110_GPC0_BASE	(S5PC110_GPIO_BASE + 0x0060)
> +#define S5PC110_GPC1_BASE	(S5PC110_GPIO_BASE + 0x0080)
> +#define S5PC110_GPD0_BASE	(S5PC110_GPIO_BASE + 0x00A0)
> +#define S5PC110_GPD1_BASE	(S5PC110_GPIO_BASE + 0x00C0)
> +#define S5PC110_GPE0_BASE	(S5PC110_GPIO_BASE + 0x00E0)
> +#define S5PC110_GPE1_BASE	(S5PC110_GPIO_BASE + 0x0100)
> +#define S5PC110_GPF0_BASE	(S5PC110_GPIO_BASE + 0x0120)
> +#define S5PC110_GPF1_BASE	(S5PC110_GPIO_BASE + 0x0140)
> +#define S5PC110_GPF2_BASE	(S5PC110_GPIO_BASE + 0x0160)
> +#define S5PC110_GPF3_BASE	(S5PC110_GPIO_BASE + 0x0180)
> +#define S5PC110_GPG0_BASE	(S5PC110_GPIO_BASE + 0x01A0)
> +#define S5PC110_GPG1_BASE	(S5PC110_GPIO_BASE + 0x01C0)
> +#define S5PC110_GPG2_BASE	(S5PC110_GPIO_BASE + 0x01E0)
> +#define S5PC110_GPG3_BASE	(S5PC110_GPIO_BASE + 0x0200)
> +#define S5PC110_GPH0_BASE	(S5PC110_GPIO_BASE + 0x0C00)
> +#define S5PC110_GPH1_BASE	(S5PC110_GPIO_BASE + 0x0C20)
> +#define S5PC110_GPH2_BASE	(S5PC110_GPIO_BASE + 0x0C40)
> +#define S5PC110_GPH3_BASE	(S5PC110_GPIO_BASE + 0x0C60)
> +#define S5PC110_GPI_BASE	(S5PC110_GPIO_BASE + 0x0220)
> +#define S5PC110_GPJ0_BASE	(S5PC110_GPIO_BASE + 0x0240)
> +#define S5PC110_GPJ1_BASE	(S5PC110_GPIO_BASE + 0x0260)
> +#define S5PC110_GPJ2_BASE	(S5PC110_GPIO_BASE + 0x0280)
> +#define S5PC110_GPJ3_BASE	(S5PC110_GPIO_BASE + 0x02A0)
> +#define S5PC110_GPJ4_BASE	(S5PC110_GPIO_BASE + 0x02C0)
> +#define S5PC110_MP0_1_BASE	(S5PC110_GPIO_BASE + 0x02E0)
> +#define S5PC110_MP0_2_BASE	(S5PC110_GPIO_BASE + 0x0300)
> +#define S5PC110_MP0_3_BASE	(S5PC110_GPIO_BASE + 0x0320)
> +#define S5PC110_MP0_4_BASE	(S5PC110_GPIO_BASE + 0x0340)
> +#define S5PC110_MP0_5_BASE	(S5PC110_GPIO_BASE + 0x0360)
> +#define S5PC110_EXT_INT_BASE	(S5PC110_GPIO_BASE + 0x0E00)
> +#define S5PC110_PDNEN		(S5PC110_GPIO_BASE + 0x0F80)
> +#define S5PC100_PDNEN_NORMAL	(0 << 0)
> +
> +#define S5PC110_PDNEN_CFG_PDNEN	(1 << 1)
> +#define S5PC110_PDNEN_CFG_AUTO	(0 << 1)
> +#define S5PC110_PDNEN_POWERDOWN	(1 << 0)
> +#define S5PC110_PDNEN_NORMAL	(0 << 0)
> +
> +/* Common part */
> +#define S5PC1XX_EINT_BASE	(S5PC110_EXT_INT_BASE)
> +
> +#define S5PC1XX_GPx_INPUT(__gpio)	(0x0 << ((__gpio) * 4))
> +#define S5PC1XX_GPx_OUTPUT(__gpio)	(0x1 << ((__gpio) * 4))
> +#define S5PC1XX_GPx_CONMASK(__gpio)	(0xf << ((__gpio) * 4))
> +
> +#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */
> +
> diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c
> index 60bf31d..2cd095c 100644
> --- a/arch/arm/plat-s5pc1xx/gpiolib.c
> +++ b/arch/arm/plat-s5pc1xx/gpiolib.c
> @@ -453,6 +453,272 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
>  #define s5pc1xx_gpio_chips s5pc100_gpio_chips
>  
>  #endif
> +
> +#ifdef CONFIG_CPU_S5PC110

this amount of #ifdef screams seperate file.

> +static struct s3c_gpio_chip s5pc110_gpio_chips[] = {
> +	{
> +		.base	= S5PC110_GPA0_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPA0(0),
> +			.ngpio	= S5PC110_GPIO_A0_NR,
> +			.label	= "GPA0",
> +		},
> +	}, {
> +		.base	= S5PC110_GPA1_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPA1(0),
> +			.ngpio	= S5PC110_GPIO_A1_NR,
> +			.label	= "GPA1",
> +		},
> +	}, {
> +		.base	= S5PC110_GPB_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPB(0),
> +			.ngpio	= S5PC110_GPIO_B_NR,
> +			.label	= "GPB",
> +		},
> +	}, {
> +		.base	= S5PC110_GPC0_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPC0(0),
> +			.ngpio	= S5PC110_GPIO_C0_NR,
> +			.label	= "GPC0",
> +		},
> +	}, {
> +		.base	= S5PC110_GPC1_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPC1(0),
> +			.ngpio	= S5PC110_GPIO_C1_NR,
> +			.label	= "GPC1",
> +		},
> +	}, {
> +		.base	= S5PC110_GPD0_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPD0(0),
> +			.ngpio	= S5PC110_GPIO_D0_NR,
> +			.label	= "GPD0",
> +		},
> +	}, {
> +		.base	= S5PC110_GPD1_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPD1(0),
> +			.ngpio	= S5PC110_GPIO_D1_NR,
> +			.label	= "GPD1",
> +		},
> +	}, {
> +		.base	= S5PC110_GPE0_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPE0(0),
> +			.ngpio	= S5PC110_GPIO_E0_NR,
> +			.label	= "GPE0",
> +		},
> +	}, {
> +		.base	= S5PC110_GPE1_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPE1(0),
> +			.ngpio	= S5PC110_GPIO_E1_NR,
> +			.label	= "GPE1",
> +		},
> +	}, {
> +		.base	= S5PC110_GPF0_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPF0(0),
> +			.ngpio	= S5PC110_GPIO_F0_NR,
> +			.label	= "GPF0",
> +		},
> +	}, {
> +		.base	= S5PC110_GPF1_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPF1(0),
> +			.ngpio	= S5PC110_GPIO_F1_NR,
> +			.label	= "GPF1",
> +		},
> +	}, {
> +		.base	= S5PC110_GPF2_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPF2(0),
> +			.ngpio	= S5PC110_GPIO_F2_NR,
> +			.label	= "GPF2",
> +		},
> +	}, {
> +		.base	= S5PC110_GPF3_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPF3(0),
> +			.ngpio	= S5PC110_GPIO_F3_NR,
> +			.label	= "GPF3",
> +		},
> +	}, {
> +		.base	= S5PC110_GPG0_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPG0(0),
> +			.ngpio	= S5PC110_GPIO_G0_NR,
> +			.label	= "GPG0",
> +		},
> +	}, {
> +		.base	= S5PC110_GPG1_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPG1(0),
> +			.ngpio	= S5PC110_GPIO_G1_NR,
> +			.label	= "GPG1",
> +		},
> +	}, {
> +		.base	= S5PC110_GPG2_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPG2(0),
> +			.ngpio	= S5PC110_GPIO_G2_NR,
> +			.label	= "GPG2",
> +		},
> +	}, {
> +		.base	= S5PC110_GPG3_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPG3(0),
> +			.ngpio	= S5PC110_GPIO_G3_NR,
> +			.label	= "GPG3",
> +		},
> +	}, {
> +		.base	= S5PC110_GPH0_BASE,
> +		.config	= &gpio_cfg_eint,
> +		.chip	= {
> +			.base	= S5PC110_GPH0(0),
> +			.ngpio	= S5PC110_GPIO_H0_NR,
> +			.label	= "GPH0",
> +		},
> +	}, {
> +		.base	= S5PC110_GPH1_BASE,
> +		.config	= &gpio_cfg_eint,
> +		.chip	= {
> +			.base	= S5PC110_GPH1(0),
> +			.ngpio	= S5PC110_GPIO_H1_NR,
> +			.label	= "GPH1",
> +		},
> +	}, {
> +		.base	= S5PC110_GPH2_BASE,
> +		.config	= &gpio_cfg_eint,
> +		.chip	= {
> +			.base	= S5PC110_GPH2(0),
> +			.ngpio	= S5PC110_GPIO_H2_NR,
> +			.label	= "GPH2",
> +		},
> +	}, {
> +		.base	= S5PC110_GPH3_BASE,
> +		.config	= &gpio_cfg_eint,
> +		.chip	= {
> +			.base	= S5PC110_GPH3(0),
> +			.ngpio	= S5PC110_GPIO_H3_NR,
> +			.label	= "GPH3",
> +		},
> +	}, {
> +		.base	= S5PC110_GPI_BASE,
> +		.config	= &gpio_cfg_noint,
> +		.chip	= {
> +			.base	= S5PC110_GPI(0),
> +			.ngpio	= S5PC110_GPIO_I_NR,
> +			.label	= "GPI",
> +		},
> +	}, {
> +		.base	= S5PC110_GPJ0_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPJ0(0),
> +			.ngpio	= S5PC110_GPIO_J0_NR,
> +			.label	= "GPJ0",
> +		},
> +	}, {
> +		.base	= S5PC110_GPJ1_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPJ1(0),
> +			.ngpio	= S5PC110_GPIO_J1_NR,
> +			.label	= "GPJ1",
> +		},
> +	}, {
> +		.base	= S5PC110_GPJ2_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPJ2(0),
> +			.ngpio	= S5PC110_GPIO_J2_NR,
> +			.label	= "GPJ2",
> +		},
> +	}, {
> +		.base	= S5PC110_GPJ3_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPJ3(0),
> +			.ngpio	= S5PC110_GPIO_J3_NR,
> +			.label	= "GPJ3",
> +		},
> +	}, {
> +		.base	= S5PC110_GPJ4_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_GPJ4(0),
> +			.ngpio	= S5PC110_GPIO_J4_NR,
> +			.label	= "GPJ4",
> +		},
> +	}, {
> +		.base	= S5PC110_MP0_1_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_MP0_1(0),
> +			.ngpio	= S5PC110_GPIO_MP0_1_NR,
> +			.label	= "MP0_1",
> +		},
> +	}, {
> +		.base	= S5PC110_MP0_2_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_MP0_2(0),
> +			.ngpio	= S5PC110_GPIO_MP0_2_NR,
> +			.label	= "MP0_2",
> +		},
> +	}, {
> +		.base	= S5PC110_MP0_3_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_MP0_3(0),
> +			.ngpio	= S5PC110_GPIO_MP0_3_NR,
> +			.label	= "MP0_3",
> +		},
> +	}, {
> +		.base	= S5PC110_MP0_4_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_MP0_4(0),
> +			.ngpio	= S5PC110_GPIO_MP0_4_NR,
> +			.label	= "MP0_4",
> +		},
> +	}, {
> +		.base	= S5PC110_MP0_5_BASE,
> +		.config	= &gpio_cfg,
> +		.chip	= {
> +			.base	= S5PC110_MP0_5(0),
> +			.ngpio	= S5PC110_GPIO_MP0_5_NR,
> +			.label	= "MP0_5",
> +		},
> +	},
> +};
> +
> +#define s5pc1xx_gpio_chips s5pc110_gpio_chips
> +
> +#endif
> +
>  /* FIXME move from irq-gpio.c */
>  extern struct irq_chip s5pc1xx_gpioint;
>  extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
> diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/plat-s5pc1xx/irq-gpio.c
> index f5d8dab..b13308f 100644
> --- a/arch/arm/plat-s5pc1xx/irq-gpio.c
> +++ b/arch/arm/plat-s5pc1xx/irq-gpio.c
> @@ -142,6 +142,116 @@ static int s5pc100_group_end = 21;
>  
>  #endif
>  
> +#ifdef CONFIG_CPU_S5PC110

these follwing functions could have had their info added to an extended
gpio structure, say struct s5p_gpio_chip and had a s3c_gpio_chip embededded in
it, which would make the code simpler,

ie:

struct s5p_gpio_chip {
       struct s3c_gpio_chip chip;
       unsigned int 	    gpio_start;
       unsigned int 	    gpio_groupl
};

and then you could have gone chip->info easily.

> +static int s5pc110_get_start(unsigned int group)
> +{
> +	switch (group) {
> +	case 0: return S5PC110_GPIO_A0_START;
> +	case 1: return S5PC110_GPIO_A1_START;
> +	case 2: return S5PC110_GPIO_B_START;
> +	case 3: return S5PC110_GPIO_C0_START;
> +	case 4: return S5PC110_GPIO_C1_START;
> +	case 5: return S5PC110_GPIO_D0_START;
> +	case 6: return S5PC110_GPIO_D1_START;
> +	case 7: return S5PC110_GPIO_E0_START;
> +	case 8: return S5PC110_GPIO_E1_START;
> +	case 9: return S5PC110_GPIO_F0_START;
> +	case 10: return S5PC110_GPIO_F1_START;
> +	case 11: return S5PC110_GPIO_F2_START;
> +	case 12: return S5PC110_GPIO_F3_START;
> +	case 13: return S5PC110_GPIO_G0_START;
> +	case 14: return S5PC110_GPIO_G1_START;
> +	case 15: return S5PC110_GPIO_G2_START;
> +	case 16: return S5PC110_GPIO_G3_START;
> +	case 17: return S5PC110_GPIO_J0_START;
> +	case 18: return S5PC110_GPIO_J1_START;
> +	case 19: return S5PC110_GPIO_J2_START;
> +	case 20: return S5PC110_GPIO_J3_START;
> +	case 21: return S5PC110_GPIO_J4_START;
> +	case 22: return S5PC110_GPIO_MP0_1_START;
> +	case 23: return S5PC110_GPIO_MP0_2_START;
> +	case 24: return S5PC110_GPIO_MP0_3_START;
> +	case 25: return S5PC110_GPIO_MP0_4_START;
> +	case 26: return S5PC110_GPIO_MP0_5_START;
> +	default:
> +		BUG();
> +	}
> +	return -EINVAL;
> +}
> +
> +static int s5pc110_get_group(unsigned int irq)
> +{
> +	irq -= S3C_IRQ_GPIO(0);
> +
> +	switch (irq) {
> +	case S5PC110_GPIO_A0_START ... S5PC110_GPIO_A1_START - 1:
> +		return 0;
> +	case S5PC110_GPIO_A1_START ... S5PC110_GPIO_B_START - 1:
> +		return 1;
> +	case S5PC110_GPIO_B_START ... S5PC110_GPIO_C0_START - 1:
> +		return 2;
> +	case S5PC110_GPIO_C0_START ... S5PC110_GPIO_C1_START - 1:
> +		return 3;
> +	case S5PC110_GPIO_C1_START ... S5PC110_GPIO_D0_START - 1:
> +		return 4;
> +	case S5PC110_GPIO_D0_START ... S5PC110_GPIO_D1_START - 1:
> +		return 5;
> +	case S5PC110_GPIO_D1_START ... S5PC110_GPIO_E0_START - 1:
> +		return 6;
> +	case S5PC110_GPIO_E0_START ... S5PC110_GPIO_E1_START - 1:
> +		return 7;
> +	case S5PC110_GPIO_E1_START ... S5PC110_GPIO_F0_START - 1:
> +		return 8;
> +	case S5PC110_GPIO_F0_START ... S5PC110_GPIO_F1_START - 1:
> +		return 9;
> +	case S5PC110_GPIO_F1_START ... S5PC110_GPIO_F2_START - 1:
> +		return 10;
> +	case S5PC110_GPIO_F2_START ... S5PC110_GPIO_F3_START - 1:
> +		return 11;
> +	case S5PC110_GPIO_F3_START ... S5PC110_GPIO_G0_START - 1:
> +		return 12;
> +	case S5PC110_GPIO_G0_START ... S5PC110_GPIO_G1_START - 1:
> +		return 13;
> +	case S5PC110_GPIO_G1_START ... S5PC110_GPIO_G2_START - 1:
> +		return 14;
> +	case S5PC110_GPIO_G2_START ... S5PC110_GPIO_G3_START - 1:
> +		return 15;
> +	case S5PC110_GPIO_G3_START ... S5PC110_GPIO_H0_START - 1:
> +		return 16;
> +	case S5PC110_GPIO_J0_START ... S5PC110_GPIO_J1_START - 1:
> +		return 17;
> +	case S5PC110_GPIO_J1_START ... S5PC110_GPIO_J2_START - 1:
> +		return 18;
> +	case S5PC110_GPIO_J2_START ... S5PC110_GPIO_J3_START - 1:
> +		return 19;
> +	case S5PC110_GPIO_J3_START ... S5PC110_GPIO_J4_START - 1:
> +		return 20;
> +	case S5PC110_GPIO_J4_START ... S5PC110_GPIO_MP0_1_START - 1:
> +		return 21;
> +	case S5PC110_GPIO_MP0_1_START ... S5PC110_GPIO_MP0_2_START - 1:
> +		return 22;
> +	case S5PC110_GPIO_MP0_2_START ... S5PC110_GPIO_MP0_3_START - 1:
> +		return 23;
> +	case S5PC110_GPIO_MP0_3_START ... S5PC110_GPIO_MP0_4_START - 1:
> +		return 24;
> +	case S5PC110_GPIO_MP0_4_START ... S5PC110_GPIO_MP0_5_START - 1:
> +		return 25;
> +	case S5PC110_GPIO_MP0_5_START ... S5PC110_GPIO_MP0_6_START - 1:
> +		return 26;
> +	default:
> +		BUG();
> +	}
> +	return -EINVAL;
> +}
> +
> +static int s5pc110_group_end = 27;
> +
> +#define s5pc1xx_get_group s5pc110_get_group
> +#define s5pc1xx_get_start s5pc110_get_start
> +#define s5pc1xx_group_end s5pc110_group_end
> +
> +#endif
> +
>  static int s5pc1xx_get_offset(unsigned int irq)
>  {
>  	struct gpio_chip *chip = get_irq_data(irq);
> -- 
> 1.6.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[Ben Dooks]

On Wed, Nov 18, 2009 at 11:14:52PM +0900, jassi brar wrote:
> On Wed, Nov 18, 2009 at 10:33 PM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
> > From: Kyungmin Park <kyungmin.park@samsung.com>
> >
> > Samsung S5PC110 SoCs have UART that differs a bit from the one known
> > from the previous Samsung SoCs. This patch adds support for this new
> > driver.
> >
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

> Not just about this c110 patch: I think this string comparison thing
> isn't very neat.
> I think we'd better be doing it by indexing into an array of clock
> names(which can be
> defined in some platform specific code).

I don't mind changing to using a table, but the table is probably best
off here, closest to the UART drivers in question.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.

[PATCH 12/19] ARM: S5PC1XX: add support for s5pc110 plls and clocks

[Ben Dooks]

On Wed, Nov 18, 2009 at 02:33:07PM +0100, Marek Szyprowski wrote:
> From: Kyungmin Park <kyungmin.park@samsung.com>
> 
> Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
> on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
> This patch adds clocks and plls definition for S5PC110 SoCs.
> 
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> 
> ---
>  arch/arm/mach-s5pc110/Kconfig                   |    1 +
>  arch/arm/mach-s5pc110/cpu.c                     |    3 +
>  arch/arm/mach-s5pc110/include/plat/regs-clock.h |  347 ++++++
>  arch/arm/plat-s5pc1xx/Kconfig                   |    5 +
>  arch/arm/plat-s5pc1xx/Makefile                  |    1 +
>  arch/arm/plat-s5pc1xx/include/plat/pll.h        |    8 +-
>  arch/arm/plat-s5pc1xx/include/plat/s5pc110.h    |   11 +
>  arch/arm/plat-s5pc1xx/s5pc100-plls.c            |    8 +-
>  arch/arm/plat-s5pc1xx/s5pc110-clocks.c          |  254 +++++
>  arch/arm/plat-s5pc1xx/s5pc110-plls.c            | 1292 +++++++++++++++++++++++

Are these files likely to be shared with other SoCs? If not, then they
would be better off going in arch/arm/mach-s5pc110/ instead of here and
just being compiled if the machine support is enabled.

>  10 files changed, 1924 insertions(+), 6 deletions(-)
>  create mode 100644 arch/arm/mach-s5pc110/include/plat/regs-clock.h
>  create mode 100644 arch/arm/plat-s5pc1xx/s5pc110-clocks.c
>  create mode 100644 arch/arm/plat-s5pc1xx/s5pc110-plls.c
> 
> diff --git a/arch/arm/mach-s5pc110/Kconfig b/arch/arm/mach-s5pc110/Kconfig
> index fb298e2..420b585 100644
> --- a/arch/arm/mach-s5pc110/Kconfig
> +++ b/arch/arm/mach-s5pc110/Kconfig
> @@ -12,6 +12,7 @@ if ARCH_S5PC110
>  config CPU_S5PC110
>  	bool
>  	select CPU_S5PC110_INIT
> +	select CPU_S5PC110_CLOCK
>  	help
>  	  Enable S5PC110 CPU support
>  
> diff --git a/arch/arm/mach-s5pc110/cpu.c b/arch/arm/mach-s5pc110/cpu.c
> index 1a4a5e4..6c9ebcb 100644
> --- a/arch/arm/mach-s5pc110/cpu.c
> +++ b/arch/arm/mach-s5pc110/cpu.c
> @@ -86,6 +86,9 @@ void __init s5pc110_init_clocks(int xtal)
>  {
>  	printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
>  	s3c24xx_register_baseclocks(xtal);
> +	s5pc1xx_register_clocks();
> +	s5pc110_register_clocks();
> +	s5pc110_setup_clocks();
>  }
>  
>  void __init s5pc110_init_irq(void)
> diff --git a/arch/arm/mach-s5pc110/include/plat/regs-clock.h b/arch/arm/mach-s5pc110/include/plat/regs-clock.h
> new file mode 100644
> index 0000000..4305a07
> --- /dev/null
> +++ b/arch/arm/mach-s5pc110/include/plat/regs-clock.h
> @@ -0,0 +1,347 @@
> +/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
> + *
> + * Copyright 2009 Samsung Electronics Co.
> + *	Byungho Min <bhmin@samsung.com>
> + *
> + * S5PC110 clock register definitions
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#ifndef __PLAT_REGS_CLOCK_H
> +#define __PLAT_REGS_CLOCK_H __FILE__
> +
> +#define S5PC1XX_CLKREG(x)		(S5PC1XX_VA_CLK + (x))
> +
> +/* s5pc110 register for clock */
> +#define S5PC110_APLL_LOCK		S5PC1XX_CLKREG(0x00)
> +#define S5PC110_MPLL_LOCK		S5PC1XX_CLKREG(0x08)
> +#define S5PC110_EPLL_LOCK		S5PC1XX_CLKREG(0x10)
> +#define S5PC110_VPLL_LOCK		S5PC1XX_CLKREG(0x20)
> +
> +#define S5PC110_APLL_CON		S5PC1XX_CLKREG(0x100)
> +#define S5PC110_MPLL_CON		S5PC1XX_CLKREG(0x108)
> +#define S5PC110_EPLL_CON		S5PC1XX_CLKREG(0x110)
> +#define S5PC110_VPLL_CON		S5PC1XX_CLKREG(0x120)
> +
> +#define S5PC110_CLKSRC0			S5PC1XX_CLKREG(0x200)
> +#define S5PC110_CLKSRC1			S5PC1XX_CLKREG(0x204)
> +#define S5PC110_CLKSRC2			S5PC1XX_CLKREG(0x208)
> +#define S5PC110_CLKSRC3			S5PC1XX_CLKREG(0x20C)
> +#define S5PC110_CLKSRC4			S5PC1XX_CLKREG(0x210)
> +#define S5PC110_CLKSRC5			S5PC1XX_CLKREG(0x214)
> +#define S5PC110_CLKSRC6			S5PC1XX_CLKREG(0x218)
> +
> +#define S5PC110_CLKSRC_MASK0		S5PC1XX_CLKREG(0x280)
> +#define S5PC110_CLKSRC_MASK1		S5PC1XX_CLKREG(0x284)
> +
> +#define S5PC110_CLKDIV0		S5PC1XX_CLKREG(0x300)
> +#define S5PC110_CLKDIV1		S5PC1XX_CLKREG(0x304)
> +#define S5PC110_CLKDIV2		S5PC1XX_CLKREG(0x308)
> +#define S5PC110_CLKDIV3		S5PC1XX_CLKREG(0x30C)
> +#define S5PC110_CLKDIV4		S5PC1XX_CLKREG(0x310)
> +#define S5PC110_CLKDIV5		S5PC1XX_CLKREG(0x314)
> +#define S5PC110_CLKDIV6		S5PC1XX_CLKREG(0x318)
> +#define S5PC110_CLKDIV7		S5PC1XX_CLKREG(0x31C)
> +
> +#define S5PC110_CLKGATE_IP0		S5PC1XX_CLKREG(0x460)
> +#define S5PC110_CLKGATE_IP1		S5PC1XX_CLKREG(0x464)
> +#define S5PC110_CLKGATE_IP2		S5PC1XX_CLKREG(0x468)
> +#define S5PC110_CLKGATE_IP3		S5PC1XX_CLKREG(0x46C)
> +#define S5PC110_CLKGATE_IP4		S5PC1XX_CLKREG(0x470)
> +#define S5PC110_CLKGATE_BLOCK		S5PC1XX_CLKREG(0x480)
> +#define S5PC110_CLKGATE_BUS0		S5PC1XX_CLKREG(0x484)
> +#define S5PC110_CLKGATE_BUS1		S5PC1XX_CLKREG(0x488)
> +
> +#define S5PC110_CLK_OUT			S5PC1XX_CLKREG(0x500)
> +#define S5PC110_MDNIE_SEL		S5PC1XX_CLKREG(0x7008)
> +
> +#define S5PC110_CLKDIV_STAT0		S5PC1XX_CLKREG(0x1000)
> +#define S5PC110_CLKDIV_STAT1		S5PC1XX_CLKREG(0x1004)
> +
> +#define S5PC110_CLK_MUX_STAT0		S5PC1XX_CLKREG(0x1100)
> +#define S5PC110_CLK_MUX_STAT1		S5PC1XX_CLKREG(0x1104)
> +
> +#define S5PC110_SWRESET		S5PC1XX_CLKREG(0x2000)
> +
> +#define S5PC110_CLKSRC0_APLL_MASK		(0x1<<0)
> +#define S5PC110_CLKSRC0_APLL_SHIFT		(0)
> +#define S5PC110_CLKSRC0_MPLL_MASK		(0x1<<4)
> +#define S5PC110_CLKSRC0_MPLL_SHIFT		(4)
> +#define S5PC110_CLKSRC0_EPLL_MASK		(0x1<<8)
> +#define S5PC110_CLKSRC0_EPLL_SHIFT		(8)
> +#define S5PC110_CLKSRC0_VPLL_MASK		(0x1<<12)
> +#define S5PC110_CLKSRC0_VPLL_SHIFT		(12)
> +#define S5PC110_CLKSRC0_MUX200_MASK		(0x1<<16)
> +#define S5PC110_CLKSRC0_MUX200_SHIFT		(16)
> +#define S5PC110_CLKSRC0_MUX166_MASK		(0x1<<20)
> +#define S5PC110_CLKSRC0_MUX166_SHIFT		(20)
> +#define S5PC110_CLKSRC0_MUX133_MASK		(0x1<<24)
> +#define S5PC110_CLKSRC0_MUX133_SHIFT		(24)
> +#define S5PC110_CLKSRC0_ONENAND_MASK		(0x1<<28)
> +#define S5PC110_CLKSRC0_ONENAND_SHIFT		(28)
> +
> +#define S5PC110_CLKSRC1_HDMI_MASK		(0x1<<0)
> +#define S5PC110_CLKSRC1_HDMI_SHIFT		(0)
> +#define S5PC110_CLKSRC1_MIXER_MASK		(0x7<<1)
> +#define S5PC110_CLKSRC1_MIXER_SHIFT		(1)
> +#define S5PC110_CLKSRC1_DAC_MASK		(0x1<<8)
> +#define S5PC110_CLKSRC1_DAC_SHIFT		(8)
> +#define S5PC110_CLKSRC1_CAM0_MASK		(0xf<<12)
> +#define S5PC110_CLKSRC1_CAM0_SHIFT		(12)
> +#define S5PC110_CLKSRC1_CAM1_MASK		(0xf<<16)
> +#define S5PC110_CLKSRC1_CAM1_SHIFT		(16)
> +#define S5PC110_CLKSRC1_FIMD_MASK		(0xf<<20)
> +#define S5PC110_CLKSRC1_FIMD_SHIFT		(20)
> +#define S5PC110_CLKSRC1_CSIS_MASK		(0xf<<24)
> +#define S5PC110_CLKSRC1_CSIS_SHIFT		(24)
> +#define S5PC110_CLKSRC1_VPLLSRC_MASK		(0x1<<28)
> +#define S5PC110_CLKSRC1_VPLLSRC_SHIFT		(28)
> +
> +#define S5PC110_CLKSRC2_G3D_MASK		(0x3<<0)
> +#define S5PC110_CLKSRC2_G3D_SHIFT		(0)
> +#define S5PC110_CLKSRC2_MFC_MASK		(0x3<<4)
> +#define S5PC110_CLKSRC2_MFC_SHIFT		(4)
> +
> +#define S5PC110_CLKSRC3_MDNIE_MASK		(0xf<<0)
> +#define S5PC110_CLKSRC3_MDNIE_SHIFT		(0)
> +#define S5PC110_CLKSRC3_MDNIE_PWMCLK_MASK	(0xf<<4)
> +#define S5PC110_CLKSRC3_MDNIE_PWMCLK_SHIFT	(4)
> +#define S5PC110_CLKSRC3_FIMC0_LCLK_MASK		(0xf<<12)
> +#define S5PC110_CLKSRC3_FIMC0_LCLK_SHIFT	(12)
> +#define S5PC110_CLKSRC3_FIMC1_LCLK_MASK		(0xf<<16)
> +#define S5PC110_CLKSRC3_FIMC1_LCLK_SHIFT	(16)
> +#define S5PC110_CLKSRC3_FIMC2_LCLK_MASK		(0xf<<20)
> +#define S5PC110_CLKSRC3_FIMC2_LCLK_SHIFT	(20)
> +
> +/* CLKSRC4 */
> +#define S5PC110_CLKSRC4_MMC0_MASK		(0xf<<0)
> +#define S5PC110_CLKSRC4_MMC0_SHIFT		(0)
> +#define S5PC110_CLKSRC4_MMC1_MASK		(0xf<<4)
> +#define S5PC110_CLKSRC4_MMC1_SHIFT		(4)
> +#define S5PC110_CLKSRC4_MMC2_MASK		(0xf<<8)
> +#define S5PC110_CLKSRC4_MMC2_SHIFT		(8)
> +#define S5PC110_CLKSRC4_MMC3_MASK		(0xf<<12)
> +#define S5PC110_CLKSRC4_MMC3_SHIFT		(12)
> +#define S5PC110_CLKSRC4_UART0_MASK		(0xf<<16)
> +#define S5PC110_CLKSRC4_UART0_SHIFT		(16)
> +#define S5PC110_CLKSRC4_UART1_MASK		(0xf<<20)
> +#define S5PC110_CLKSRC4_UART1_SHIFT		(20)
> +#define S5PC110_CLKSRC4_UART2_MASK		(0xf<<24)
> +#define S5PC110_CLKSRC4_UART2_SHIFT		(24)
> +#define S5PC110_CLKSRC4_UART3_MASK		(0xf<<28)
> +#define S5PC110_CLKSRC4_UART3_SHIFT		(28)
> +
> +/* CLKSRC5 */
> +#define S5PC110_CLKSRC5_SPI0_MASK		(0xf<<0)
> +#define S5PC110_CLKSRC5_SPI0_SHIFT		(0)
> +#define S5PC110_CLKSRC5_SPI1_MASK		(0xf<<4)
> +#define S5PC110_CLKSRC5_SPI1_SHIFT		(4)
> +#define S5PC110_CLKSRC5_SPI2_MASK		(0xf<<8)
> +#define S5PC110_CLKSRC5_SPI2_SHIFT		(8)
> +#define S5PC110_CLKSRC5_PWM_MASK		(0xf<<12)
> +#define S5PC110_CLKSRC5_PWM_SHIFT		(12)
> +
> +/* CLKSRC6 */
> +#define S5PC110_CLKSRC6_AUDIO0_MASK		(0xf<<0)
> +#define S5PC110_CLKSRC6_AUDIO0_SHIFT		(0)
> +#define S5PC110_CLKSRC6_AUDIO1_MASK		(0xf<<4)
> +#define S5PC110_CLKSRC6_AUDIO1_SHIFT		(4)
> +#define S5PC110_CLKSRC6_AUDIO2_MASK		(0xf<<8)
> +#define S5PC110_CLKSRC6_AUDIO2_SHIFT		(4)
> +#define S5PC110_CLKSRC6_SPDIF_MASK		(0x3<<12)
> +#define S5PC110_CLKSRC6_SPDIF_SHIFT		(12)
> +#define S5PC110_CLKSRC6_HPM_MASK		(0x1<<16)
> +#define S5PC110_CLKSRC6_HPM_SHIFT		(16)
> +#define S5PC110_CLKSRC6_PWI_MASK		(0xf<<20)
> +#define S5PC110_CLKSRC6_PWI_SHIFT		(20)
> +#define S5PC110_CLKSRC6_ONEDRAM_MASK		(0x3<<24)
> +#define S5PC110_CLKSRC6_ONEDRAM_SHIFT		(24)
> +
> +#define S5PC110_CLKDIV0_APLL_MASK		(0x7<<0)
> +#define S5PC110_CLKDIV0_APLL_SHIFT		(0)
> +#define S5PC110_CLKDIV0_A2M_MASK		(0x7<<4)
> +#define S5PC110_CLKDIV0_A2M_SHIFT		(4)
> +#define S5PC110_CLKDIV0_HCLK_MSYS_MASK		(0x7<<8)
> +#define S5PC110_CLKDIV0_HCLK_MSYS_SHIFT	(8)
> +#define S5PC110_CLKDIV0_PCLK_MSYS_MASK		(0x7<<12)
> +#define S5PC110_CLKDIV0_PCLK_MSYS_SHIFT	(12)
> +#define S5PC110_CLKDIV0_HCLK_DSYS_MASK		(0xf<<16)
> +#define S5PC110_CLKDIV0_HCLK_DSYS_SHIFT	(16)
> +#define S5PC110_CLKDIV0_PCLK_DSYS_MASK		(0x7<<20)
> +#define S5PC110_CLKDIV0_PCLK_DSYS_SHIFT	(20)
> +#define S5PC110_CLKDIV0_HCLK_PSYS_MASK		(0xf<<24)
> +#define S5PC110_CLKDIV0_HCLK_PSYS_SHIFT	(24)
> +#define S5PC110_CLKDIV0_PCLK_PSYS_MASK		(0x7<<28)
> +#define S5PC110_CLKDIV0_PCLK_PSYS_SHIFT	(28)
> +
> +#define S5PC110_CLKDIV1_TBLK_MASK		(0xf<<0)
> +#define S5PC110_CLKDIV1_TBLK_SHIFT		(0)
> +#define S5PC110_CLKDIV1_FIMC_MASK		(0xf<<8)
> +#define S5PC110_CLKDIV1_FIMC_SHIFT		(8)
> +#define S5PC110_CLKDIV1_CAM0_MASK		(0xf<<12)
> +#define S5PC110_CLKDIV1_CAM0_SHIFT		(12)
> +#define S5PC110_CLKDIV1_CAM1_MASK		(0xf<<16)
> +#define S5PC110_CLKDIV1_CAM1_SHIFT		(16)
> +#define S5PC110_CLKDIV1_FIMD_MASK		(0xf<<20)
> +#define S5PC110_CLKDIV1_FIMD_SHIFT		(20)
> +#define S5PC110_CLKDIV1_CSIS_MASK		(0xf<<28)
> +#define S5PC110_CLKDIV1_CSIS_SHIFT		(28)
> +
> +#define S5PC110_CLKDIV2_G3D_MASK		(0xf<<0)
> +#define S5PC110_CLKDIV2_G3D_SHIFT		(0)
> +#define S5PC110_CLKDIV2_MFC_MASK		(0xf<<4)
> +#define S5PC110_CLKDIV2_MFC_SHIFT		(4)
> +
> +#define S5PC110_CLKDIV3_MDNIE_MASK		(0xf<<0)
> +#define S5PC110_CLKDIV3_MDNIE_SHIFT		(0)
> +#define S5PC110_CLKDIV3_MDNIE_PWM_MASK		(0x7f<<4)
> +#define S5PC110_CLKDIV3_MDNIE_PWM_SHIFT	(4)
> +#define S5PC110_CLKDIV3_FIMC0_LCLK_MASK	(0xf<<12)
> +#define S5PC110_CLKDIV3_FIMC0_LCLK_SHIFT	(12)
> +#define S5PC110_CLKDIV3_FIMC1_LCLK_MASK	(0xf<<16)
> +#define S5PC110_CLKDIV3_FIMC1_LCLK_SHIFT	(16)
> +#define S5PC110_CLKDIV3_FIMC2_LCLK_MASK	(0xf<<20)
> +#define S5PC110_CLKDIV3_FIMC2_LCLK_SHIFT	(20)
> +
> +#define S5PC110_CLKDIV4_MMC0_MASK		(0xf<<0)
> +#define S5PC110_CLKDIV4_MMC0_SHIFT		(0)
> +#define S5PC110_CLKDIV4_MMC1_MASK		(0xf<<4)
> +#define S5PC110_CLKDIV4_MMC1_SHIFT		(4)
> +#define S5PC110_CLKDIV4_MMC2_MASK		(0xf<<8)
> +#define S5PC110_CLKDIV4_MMC2_SHIFT		(8)
> +#define S5PC110_CLKDIV4_MMC3_MASK		(0xf<<12)
> +#define S5PC110_CLKDIV4_MMC3_SHIFT		(12)
> +#define S5PC110_CLKDIV4_UART0_MASK		(0xf<<16)
> +#define S5PC110_CLKDIV4_UART0_SHIFT		(16)
> +#define S5PC110_CLKDIV4_UART1_MASK		(0xf<<20)
> +#define S5PC110_CLKDIV4_UART1_SHIFT		(20)
> +#define S5PC110_CLKDIV4_UART2_MASK		(0xf<<24)
> +#define S5PC110_CLKDIV4_UART2_SHIFT		(24)
> +#define S5PC110_CLKDIV4_UART3_MASK		(0xf<<28)
> +#define S5PC110_CLKDIV4_UART3_SHIFT		(28)
> +
> +/* CLK_DIV5 */
> +#define S5PC110_CLKDIV5_SPI0_MASK		(0xf<<0)
> +#define S5PC110_CLKDIV5_SPI0_SHIFT		(0)
> +#define S5PC110_CLKDIV5_SPI1_MASK		(0xf<<4)
> +#define S5PC110_CLKDIV5_SPI1_SHIFT		(4)
> +#define S5PC110_CLKDIV5_SPI2_MASK		(0xf<<8)
> +#define S5PC110_CLKDIV5_SPI2_SHIFT		(8)
> +#define S5PC110_CLKDIV5_PWM_MASK		(0xf<<120)
> +#define S5PC110_CLKDIV5_PWM_SHIFT		(12)
> +
> +/* CLK_DIV6 */
> +#define S5PC110_CLKDIV6_AUDIO0_MASK		(0xf<<0)
> +#define S5PC110_CLKDIV6_AUDIO0_SHIFT		(0)
> +#define S5PC110_CLKDIV6_AUDIO1_MASK		(0xf<<4)
> +#define S5PC110_CLKDIV6_AUDIO1_SHIFT		(4)
> +#define S5PC110_CLKDIV6_AUDIO2_MASK		(0xf<<8)
> +#define S5PC110_CLKDIV6_AUDIO2_SHIFT		(8)
> +#define S5PC110_CLKDIV6_ONENAND_MASK		(0x7<<12)
> +#define S5PC110_CLKDIV6_ONENAND_SHIFT		(12)
> +#define S5PC110_CLKDIV6_COPY_MASK		(0x7<<16)
> +#define S5PC110_CLKDIV6_COPY_SHIFT		(16)
> +#define S5PC110_CLKDIV6_HPM_MASK		(0x7<<20)
> +#define S5PC110_CLKDIV6_HPM_SHIFT		(20)
> +#define S5PC110_CLKDIV6_PWI_MASK		(0xf<<24)
> +#define S5PC110_CLKDIV6_PWI_SHIFT		(24)
> +#define S5PC110_CLKDIV6_ONEDRAM_MASK		(0xf<<28)
> +#define S5PC110_CLKDIV6_ONEDRAM_SHIFT		(28)
> +
> +/* Clock Gate IP0 */
> +#define S5PC110_CLKGATE_IP0_DMC0		(1<<0)
> +#define S5PC110_CLKGATE_IP0_DMC1		(1<<1)
> +#define S5PC110_CLKGATE_IP0_MDMA		(1<<2)
> +#define S5PC110_CLKGATE_IP0_PDMA0		(1<<3)
> +#define S5PC110_CLKGATE_IP0_PDMA1		(1<<4)
> +#define S5PC110_CLKGATE_IP0_IMEM		(1<<5)
> +#define S5PC110_CLKGATE_IP0_G3D			(1<<8)
> +#define S5PC110_CLKGATE_IP0_MFC			(1<<16)
> +#define S5PC110_CLKGATE_IP0_FIMC0		(1<<24)
> +#define S5PC110_CLKGATE_IP0_FIMC1		(1<<25)
> +#define S5PC110_CLKGATE_IP0_FIMC2		(1<<26)
> +#define S5PC110_CLKGATE_IP0_JPEG		(1<<28)
> +#define S5PC110_CLKGATE_IP0_ROTATOR		(1<<29)
> +#define S5PC110_CLKGATE_IP0_IPC			(1<<30)
> +#define S5PC110_CLKGATE_IP0_CSIS		(1<<31)
> +
> +/* Clock Gate IP1 */
> +#define S5PC110_CLKGATE_IP1_FIMD		(1<<0)
> +#define S5PC110_CLKGATE_IP1_MIE			(1<<1)
> +#define S5PC110_CLKGATE_IP1_DSIM		(1<<2)
> +#define S5PC110_CLKGATE_IP1_VP			(1<<8)
> +#define S5PC110_CLKGATE_IP1_MIXER		(1<<9)
> +#define S5PC110_CLKGATE_IP1_TVENC		(1<<10)
> +#define S5PC110_CLKGATE_IP1_HDMI		(1<<11)
> +#define S5PC110_CLKGATE_IP1_USBOTG		(1<<16)
> +#define S5PC110_CLKGATE_IP1_USBHOST		(1<<17)
> +#define S5PC110_CLKGATE_IP1_NANDXL		(1<<24)
> +#define S5PC110_CLKGATE_IP1_CFCON		(1<<25)
> +#define S5PC110_CLKGATE_IP1_SROMC		(1<<26)
> +#define S5PC110_CLKGATE_IP1_NFCON		(1<<28)
> +
> +/* Clock Gate IP2 */
> +#define S5PC110_CLKGATE_IP2_SECSS		(1<<0)
> +#define S5PC110_CLKGATE_IP2_SDM			(1<<1)
> +#define S5PC110_CLKGATE_IP2_CORESIGHT		(1<<8)
> +#define S5PC110_CLKGATE_IP2_MODEM		(1<<9)
> +#define S5PC110_CLKGATE_IP2_HOSTIF		(1<<10)
> +#define S5PC110_CLKGATE_IP2_SECJTAG		(1<<11)
> +#define S5PC110_CLKGATE_IP2_HSMMC0		(1<<16)
> +#define S5PC110_CLKGATE_IP2_HSMMC1		(1<<17)
> +#define S5PC110_CLKGATE_IP2_HSMMC2		(1<<18)
> +#define S5PC110_CLKGATE_IP2_HSMMC3		(1<<19)
> +#define S5PC110_CLKGATE_IP2_TSI			(1<<20)
> +#define S5PC110_CLKGATE_IP2_VIC0		(1<<24)
> +#define S5PC110_CLKGATE_IP2_VIC1		(1<<25)
> +#define S5PC110_CLKGATE_IP2_VIC2		(1<<26)
> +#define S5PC110_CLKGATE_IP2_VIC3		(1<<27)
> +#define S5PC110_CLKGATE_IP2_TZIC0		(1<<28)
> +#define S5PC110_CLKGATE_IP2_TZIC1		(1<<29)
> +#define S5PC110_CLKGATE_IP2_TZIC2		(1<<30)
> +#define S5PC110_CLKGATE_IP2_TZIC3		(1<<31)
> +
> +/* Clock Gate IP3 */
> +#define S5PC110_CLKGATE_IP3_SPDIF		(1<<0)
> +#define S5PC110_CLKGATE_IP3_AC97		(1<<1)
> +#define S5PC110_CLKGATE_IP3_I2S0		(1<<4)
> +#define S5PC110_CLKGATE_IP3_I2S1		(1<<5)
> +#define S5PC110_CLKGATE_IP3_I2S2		(1<<6)
> +#define S5PC110_CLKGATE_IP3_I2C0		(1<<7)
> +#define S5PC110_CLKGATE_IP3_I2C1		(1<<8)
> +#define S5PC110_CLKGATE_IP3_I2C2		(1<<9)
> +#define S5PC110_CLKGATE_IP3_I2C_HDMI_DDC	(1<<10)
> +#define S5PC110_CLKGATE_IP3_I2C_HDMI_PHY	(1<<11)
> +#define S5PC110_CLKGATE_IP3_SPI0		(1<<12)
> +#define S5PC110_CLKGATE_IP3_SPI1		(1<<13)
> +#define S5PC110_CLKGATE_IP3_SPI2		(1<<14)
> +#define S5PC110_CLKGATE_IP3_RTC			(1<<15)
> +#define S5PC110_CLKGATE_IP3_SYSTIMER		(1<<16)
> +#define S5PC110_CLKGATE_IP3_UART0		(1<<17)
> +#define S5PC110_CLKGATE_IP3_UART1		(1<<18)
> +#define S5PC110_CLKGATE_IP3_UART2		(1<<19)
> +#define S5PC110_CLKGATE_IP3_UART3		(1<<20)
> +#define S5PC110_CLKGATE_IP3_KEYIF		(1<<21)
> +#define S5PC110_CLKGATE_IP3_WDT			(1<<22)
> +#define S5PC110_CLKGATE_IP3_PWM			(1<<23)
> +#define S5PC110_CLKGATE_IP3_TSADC		(1<<24)
> +#define S5PC110_CLKGATE_IP3_GPIO		(1<<26)
> +#define S5PC110_CLKGATE_IP3_SYSCON		(1<<27)
> +#define S5PC110_CLKGATE_IP3_PCM0		(1<<28)
> +#define S5PC110_CLKGATE_IP3_PCM1		(1<<29)
> +#define S5PC110_CLKGATE_IP3_PCM2		(1<<30)
> +
> +/* Clock Gate IP4 */
> +#define S5PC110_CLKGATE_IP4_CHIP_ID		(1<<0)
> +#define S5PC110_CLKGATE_IP4_IEM_IEC		(1<<1)
> +#define S5PC110_CLKGATE_IP4_IEM_APC		(1<<2)
> +#define S5PC110_CLKGATE_IP4_SECKEY		(1<<3)
> +#define S5PC110_CLKGATE_IP4_TZPC0		(1<<5)
> +#define S5PC110_CLKGATE_IP4_TZPC1		(1<<6)
> +#define S5PC110_CLKGATE_IP4_TZPC2		(1<<7)
> +#define S5PC110_CLKGATE_IP4_TZPC3		(1<<8)
> +
> +#endif /* _PLAT_REGS_CLOCK_H */
> diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
> index 679e145..898cd82 100644
> --- a/arch/arm/plat-s5pc1xx/Kconfig
> +++ b/arch/arm/plat-s5pc1xx/Kconfig
> @@ -50,6 +50,11 @@ config CPU_S5PC110_INIT
>  	help
>  	  Common initialisation code for the S5PC1XX
>  
> +config CPU_S5PC110_CLOCK
> +	bool
> +	help
> +	  Common clock support code for the S5PC1XX
> +
>  # platform specific device setup
>  
>  endif
> diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
> index 3e8ebf1..b03a983 100644
> --- a/arch/arm/plat-s5pc1xx/Makefile
> +++ b/arch/arm/plat-s5pc1xx/Makefile
> @@ -21,6 +21,7 @@ obj-y				+= gpiolib.o
>  obj-$(CONFIG_CPU_S5PC100_INIT)	+= s5pc100-init.o
>  obj-$(CONFIG_CPU_S5PC100_CLOCK)	+= s5pc100-plls.o s5pc100-clocks.o
>  obj-$(CONFIG_CPU_S5PC110_INIT)	+= s5pc110-init.o
> +obj-$(CONFIG_CPU_S5PC110_CLOCK)	+= s5pc110-plls.o s5pc110-clocks.o
>  
>  # Device setup
>  
> diff --git a/arch/arm/plat-s5pc1xx/include/plat/pll.h b/arch/arm/plat-s5pc1xx/include/plat/pll.h
> index 21afef1..7380d16 100644
> --- a/arch/arm/plat-s5pc1xx/include/plat/pll.h
> +++ b/arch/arm/plat-s5pc1xx/include/plat/pll.h
> @@ -22,7 +22,7 @@
>  #include <asm/div64.h>
>  
>  static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk,
> -					    u32 pllcon)
> +					    u32 pllcon, int sub)
>  {
>  	u32 mdiv, pdiv, sdiv;
>  	u64 fvco = baseclk;
> @@ -32,7 +32,11 @@ static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk,
>  	sdiv = (pllcon >> S5P_PLL_SDIV_SHIFT) & S5P_PLL_SDIV_MASK;
>  
>  	fvco *= mdiv;
> -	do_div(fvco, (pdiv << sdiv));
> +
> +	if (sub)
> +		do_div(fvco, (pdiv << (sdiv - 1)));
> +	else
> +		do_div(fvco, (pdiv << sdiv));
>  
>  	return (unsigned long)fvco;
>  }
> diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h
> index 93c623b..86d4952 100644
> --- a/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h
> +++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h
> @@ -26,6 +26,17 @@ extern void s5pc110_init_irq(void);
>  extern void s5pc110_register_clocks(void);
>  extern void s5pc110_setup_clocks(void);
>  
> +extern struct clk clk_hpll;
> +extern struct clk clk_hd0;
> +extern struct clk clk_pd0;
> +extern struct clk clk_54m;
> +extern struct clk clk_30m;
> +extern int s5pc110_ip0_ctrl(struct clk *clk, int enable);
> +extern int s5pc110_ip1_ctrl(struct clk *clk, int enable);
> +extern int s5pc110_ip2_ctrl(struct clk *clk, int enable);
> +extern int s5pc110_ip3_ctrl(struct clk *clk, int enable);
> +extern int s5pc110_ip4_ctrl(struct clk *clk, int enable);
> +
>  #else
>  
>  #define s5pc110_map_io NULL
> diff --git a/arch/arm/plat-s5pc1xx/s5pc100-plls.c b/arch/arm/plat-s5pc1xx/s5pc100-plls.c
> index 45f073e..b7559f8 100644
> --- a/arch/arm/plat-s5pc1xx/s5pc100-plls.c
> +++ b/arch/arm/plat-s5pc1xx/s5pc100-plls.c
> @@ -1050,10 +1050,10 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
>  
>  	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
>  
> -	apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON));
> -	mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON));
> -	epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON));
> -	hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
> +	apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON), 0);
> +	mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON), 0);
> +	epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON), 0);
> +	hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON), 0);
>  
>  	printk(KERN_INFO "S5PC100: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz"
>  		", Epll=%ld.%03ld Mhz, Hpll=%ld.%03ld Mhz\n",
> diff --git a/arch/arm/plat-s5pc1xx/s5pc110-clocks.c b/arch/arm/plat-s5pc1xx/s5pc110-clocks.c
> new file mode 100644
> index 0000000..456bd5e
> --- /dev/null
> +++ b/arch/arm/plat-s5pc1xx/s5pc110-clocks.c
> @@ -0,0 +1,254 @@
> +/* linux/arch/arm/plat-s5pc1xx/s5pc110-clocks.c
> + *
> + * Copyright 2009 Samsung Electronics Co.
> + *
> + * S5PC110 - Clocks support
> + *
> + * Based on plat-s3c64xx/clock.c
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/interrupt.h>
> +#include <linux/ioport.h>
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +
> +#include <mach/hardware.h>
> +#include <mach/map.h>
> +
> +#include <plat/regs-clock.h>
> +#include <plat/devs.h>
> +#include <plat/clock.h>
> +
> +struct clk clk_27m = {
> +	.name		= "clk_27m",
> +	.id		= -1,
> +	.rate		= 27000000,
> +};
> +
> +struct clk clk_48m = {
> +	.name		= "clk_48m",
> +	.id		= -1,
> +	.rate		= 48000000,
> +};
> +
> +struct clk clk_54m = {
> +	.name		= "clk_54m",
> +	.id		= -1,
> +	.rate		= 54000000,
> +};
> +
> +struct clk clk_30m = {
> +	.name		= "clk_30m",
> +	.id		= -1,
> +	.rate		= 30000000,
> +};
> +
> +static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
> +{
> +	unsigned int ctrlbit = clk->ctrlbit;
> +	u32 con;
> +
> +	con = __raw_readl(reg);
> +	if (enable)
> +		con |= ctrlbit;
> +	else
> +		con &= ~ctrlbit;
> +	__raw_writel(con, reg);
> +
> +	return 0;
> +}
> +
> +int s5pc110_ip0_ctrl(struct clk *clk, int enable)
> +{
> +	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP0, clk, enable);
> +}
> +
> +int s5pc110_ip1_ctrl(struct clk *clk, int enable)
> +{
> +	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP1, clk, enable);
> +}
> +
> +int s5pc110_ip2_ctrl(struct clk *clk, int enable)
> +{
> +	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP2, clk, enable);
> +}
> +
> +int s5pc110_ip3_ctrl(struct clk *clk, int enable)
> +{
> +	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP3, clk, enable);
> +}
> +
> +int s5pc110_ip4_ctrl(struct clk *clk, int enable)
> +{
> +	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP4, clk, enable);
> +}
> +
> +extern struct clk clk_dout_hclkm;
> +extern struct clk clk_dout_hclkd;
> +extern struct clk clk_dout_hclkp;
> +extern struct clk clk_dout_pclkd;
> +extern struct clk clk_dout_pclkp;
> +
> +static struct clk s5pc110_init_clocks_disable[] = {
> +	{
> +		.name		= "keypad",
> +		.id		= -1,
> +		.parent		= &clk_dout_pclkp,
> +		.enable		= s5pc110_ip3_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP3_KEYIF,
> +	},
> +};
> +
> +static struct clk s5pc110_init_clocks[] = {
> +	/* IP0 */
> +	{
> +		.name		= "mfc",
> +		.id		= -1,
> +		.parent		= NULL,
> +		.enable		= s5pc110_ip0_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP0_MFC,
> +	},
> +
> +	/* IP1 */
> +	{
> +		.name		= "lcd",
> +		.id		= -1,
> +		.parent		= &clk_dout_hclkd,
> +		.enable		= s5pc110_ip1_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP1_FIMD,
> +	}, {
> +		.name		= "otg",
> +		.id		= -1,
> +		.parent		= &clk_dout_hclkp,
> +		.enable		= s5pc110_ip1_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP1_USBOTG,
> +	},
> +
> +	/* IP2 */
> +	{
> +		.name		= "hsmmc",
> +		.id		= 0,
> +		.parent		= &clk_dout_hclkp,
> +		.enable		= s5pc110_ip2_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC0,
> +	}, {
> +		.name		= "hsmmc",
> +		.id		= 1,
> +		.parent		= &clk_dout_hclkp,
> +		.enable		= s5pc110_ip2_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC1,
> +	}, {
> +		.name		= "hsmmc",
> +		.id		= 2,
> +		.parent		= &clk_dout_hclkp,
> +		.enable		= s5pc110_ip2_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC2,
> +	}, {
> +		.name		= "hsmmc",
> +		.id		= 3,
> +		.parent		= &clk_dout_hclkp,
> +		.enable		= s5pc110_ip2_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC3,
> +	},
> +	/* IP3 */
> +	{
> +		.name           = "iis",
> +		.id             = 0,
> +		.parent		= &clk_dout_pclkp,
> +		.enable		= s5pc110_ip3_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP3_I2S0,
> +	}, {
> +		.name           = "iis",
> +		.id             = 1,
> +		.parent		= &clk_dout_pclkp,
> +		.enable		= s5pc110_ip3_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP3_I2S1,
> +	}, {
> +		.name           = "iis",
> +		.id             = 2,
> +		.parent		= &clk_dout_pclkp,
> +		.enable		= s5pc110_ip3_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP3_I2S2,
> +	}, {
> +		.name		= "i2c",
> +		.id		= 0,
> +		.parent		= &clk_dout_pclkp,
> +		.enable		= s5pc110_ip3_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP3_I2C0,
> +	}, {
> +		.name		= "i2c",
> +		.id		= 1,
> +		.parent		= &clk_dout_pclkd,
> +		.enable		= s5pc110_ip3_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP3_I2C1,
> +	}, {
> +		.name		= "i2c",
> +		.id		= 2,
> +		.parent		= &clk_dout_pclkp,
> +		.enable		= s5pc110_ip3_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP3_I2C2,
> +	}, {
> +		.name		= "timers",
> +		.id		= -1,
> +		.parent		= &clk_dout_pclkp,
> +		.enable		= s5pc110_ip3_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP3_PWM,
> +	}, {
> +		.name		= "adc",
> +		.id		= -1,
> +		.parent		= &clk_dout_pclkp,
> +		.enable		= s5pc110_ip3_ctrl,
> +		.ctrlbit	= S5PC110_CLKGATE_IP3_TSADC,
> +	},
> +};
> +
> +static struct clk *clks[] __initdata = {
> +	&clk_ext,
> +	&clk_epll,
> +	&clk_27m,
> +	&clk_30m,
> +	&clk_48m,
> +	&clk_54m,
> +};
> +
> +void __init s5pc1xx_register_clocks(void)
> +{
> +	struct clk *clkp;
> +	int ret;
> +	int ptr;
> +	int size;
> +
> +	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
> +
> +	clkp = s5pc110_init_clocks;
> +	size = ARRAY_SIZE(s5pc110_init_clocks);
> +
> +	for (ptr = 0; ptr < size; ptr++, clkp++) {
> +		ret = s3c24xx_register_clock(clkp);
> +		if (ret < 0) {
> +			printk(KERN_ERR "Failed to register clock %s (%d)\n",
> +			       clkp->name, ret);
> +		}
> +	}
> +
> +	clkp = s5pc110_init_clocks_disable;
> +	size = ARRAY_SIZE(s5pc110_init_clocks_disable);
> +
> +	for (ptr = 0; ptr < size; ptr++, clkp++) {
> +		ret = s3c24xx_register_clock(clkp);
> +		if (ret < 0) {
> +			printk(KERN_ERR "Failed to register clock %s (%d)\n",
> +			       clkp->name, ret);
> +		}
> +
> +		(clkp->enable)(clkp, 0);
> +	}
> +
> +	s3c_pwmclk_init();
> +}
> diff --git a/arch/arm/plat-s5pc1xx/s5pc110-plls.c b/arch/arm/plat-s5pc1xx/s5pc110-plls.c
> new file mode 100644
> index 0000000..05ac43c
> --- /dev/null
> +++ b/arch/arm/plat-s5pc1xx/s5pc110-plls.c
> @@ -0,0 +1,1288 @@
> +/*
> + * linux/arch/arm/plat-s5pc1xx/s5pc110-plls.c
> + *
> + * Copyright 2009 Samsung Electronics, Co.
> + * Minkyu Kang <mk7.kang@samsung.com>
> + *
> + * S5PC110 based common clock support
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/errno.h>
> +#include <linux/err.h>
> +#include <linux/clk.h>
> +#include <linux/sysdev.h>
> +#include <linux/io.h>
> +
> +#include <mach/hardware.h>
> +#include <mach/map.h>
> +
> +#include <plat/cpu-freq.h>
> +
> +#include <plat/regs-clock.h>
> +#include <plat/clock.h>
> +#include <plat/cpu.h>
> +#include <plat/pll.h>
> +#include <plat/devs.h>
> +#include <plat/s5pc1xx.h>
> +
> +static struct clk clk_ext_xtal_mux = {
> +	.name		= "ext_xtal",
> +	.id		= -1,
> +};
> +
> +#define clk_fin_apll	clk_ext_xtal_mux
> +#define clk_fin_mpll	clk_ext_xtal_mux
> +#define clk_fin_epll	clk_ext_xtal_mux
> +#define clk_fin_vpll	clk_ext_xtal_mux
> +#define clk_hdmi_phy	clk_ext_xtal_mux
> +
> +#define clk_fout_mpll	clk_mpll
> +#define clk_hdmi_27m	clk_27m
> +#define clk_usbphy0	clk_30m
> +#define clk_usbphy1	clk_48m
> +
> +static struct clk clk_usb_xtal = {
> +	.name		= "usb_xtal",
> +	.id		= -1,
> +};
> +
> +static struct clk clk_pcm_cd0 = {
> +	.name		= "pcm_cdclk0",
> +	.id		= -1,
> +};
> +
> +static struct clk clk_pcm_cd1 = {
> +	.name		= "pcm_cdclk1",
> +	.id		= -1,
> +};
> +
> +static struct clk clk_iis_cd1 = {
> +	.name		= "iis_cdclk1",
> +	.id		= -1,
> +};
> +
> +struct clk_sources {
> +	unsigned int	nr_sources;
> +	struct clk	**sources;
> +};
> +
> +struct clksrc_clk {
> +	struct clk		clk;
> +	unsigned int		mask;
> +	unsigned int		shift;
> +
> +	struct clk_sources	*sources;
> +
> +	unsigned int		divider_shift;
> +	void __iomem		*reg_divider;
> +	void __iomem		*reg_source;
> +};
> +
> +/* APLL */
> +static struct clk clk_fout_apll = {
> +	.name		= "fout_apll",
> +	.id		= -1,
> +};
> +
> +static struct clk *clk_src_apll_list[] = {
> +	[0] = &clk_fin_apll,
> +	[1] = &clk_fout_apll,
> +};
> +
> +static struct clk_sources clk_src_apll = {
> +	.sources	= clk_src_apll_list,
> +	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),
> +};
> +
> +static struct clksrc_clk clk_mout_apll = {
> +	.clk	= {
> +		.name		= "mout_apll",
> +		.id		= -1,
> +	},
> +	.shift		= S5PC110_CLKSRC0_APLL_SHIFT,
> +	.mask		= S5PC110_CLKSRC0_APLL_MASK,
> +	.sources	= &clk_src_apll,
> +	.reg_source	= S5PC110_CLKSRC0,
> +};
> +
> +/* MPLL */
> +static struct clk *clk_src_mpll_list[] = {
> +	[0] = &clk_fin_mpll,
> +	[1] = &clk_fout_mpll,
> +};
> +
> +static struct clk_sources clk_src_mpll = {
> +	.sources	= clk_src_mpll_list,
> +	.nr_sources	= ARRAY_SIZE(clk_src_mpll_list),
> +};
> +
> +static struct clksrc_clk clk_mout_mpll = {
> +	.clk = {
> +		.name		= "mout_mpll",
> +		.id		= -1,
> +	},
> +	.shift		= S5PC110_CLKSRC0_MPLL_SHIFT,
> +	.mask		= S5PC110_CLKSRC0_MPLL_MASK,
> +	.sources	= &clk_src_mpll,
> +	.reg_source	= S5PC110_CLKSRC0,
> +};
> +
> +static int s5pc110_default_enable(struct clk *clk, int enable)
> +{
> +	return 0;
> +}
> +
> +/* EPLL */
> +static struct clk clk_fout_epll = {
> +	.name		= "fout_epll",
> +	.id		= -1,
> +	.enable		= s5pc110_default_enable,
> +};
> +
> +static struct clk *clk_src_epll_list[] = {
> +	[0] = &clk_fin_epll,
> +	[1] = &clk_fout_epll,
> +};
> +
> +static struct clk_sources clk_src_epll = {
> +	.sources	= clk_src_epll_list,
> +	.nr_sources	= ARRAY_SIZE(clk_src_epll_list),
> +};
> +
> +static struct clksrc_clk clk_mout_epll = {
> +	.clk = {
> +		.name		= "mout_epll",
> +		.id		= -1,
> +	},
> +	.shift		= S5PC110_CLKSRC0_EPLL_SHIFT,
> +	.mask		= S5PC110_CLKSRC0_EPLL_MASK,
> +	.sources	= &clk_src_epll,
> +	.reg_source	= S5PC110_CLKSRC0,
> +};
> +
> +/* VPLLSRC */
> +static struct clk *clk_src_vpllsrc_list[] = {
> +	[0] = &clk_fin_vpll,
> +	[1] = &clk_hdmi_27m,
> +};
> +
> +static struct clk_sources clk_src_vpllsrc = {
> +	.sources	= clk_src_vpllsrc_list,
> +	.nr_sources	= ARRAY_SIZE(clk_src_vpllsrc_list),
> +};
> +
> +static struct clksrc_clk clk_mout_vpllsrc = {
> +	.clk = {
> +		.name		= "mout_vpllsrc",
> +		.id		= -1,
> +	},
> +	.shift		= S5PC110_CLKSRC1_VPLLSRC_SHIFT,
> +	.mask		= S5PC110_CLKSRC1_VPLLSRC_MASK,
> +	.sources	= &clk_src_vpllsrc,
> +	.reg_source	= S5PC110_CLKSRC1,
> +};
> +
> +/* VPLL */
> +static struct clk clk_fout_vpll = {
> +	.name		= "fout_vpll",
> +	.id		= -1,
> +};
> +
> +static struct clk *clk_src_vpll_list[] = {
> +	[0] = &clk_mout_vpllsrc.clk,
> +	[1] = &clk_fout_vpll,
> +};
> +
> +static struct clk_sources clk_src_vpll = {
> +	.sources	= clk_src_vpll_list,
> +	.nr_sources	= ARRAY_SIZE(clk_src_vpll_list),
> +};
> +
> +static struct clksrc_clk clk_mout_vpll = {
> +	.clk = {
> +		.name		= "mout_vpll",
> +		.id		= -1,
> +	},
> +	.shift		= S5PC110_CLKSRC0_VPLL_SHIFT,
> +	.mask		= S5PC110_CLKSRC0_VPLL_MASK,
> +	.sources	= &clk_src_vpll,
> +	.reg_source	= S5PC110_CLKSRC0,
> +};
> +
> +/* Dout A2M */
> +static unsigned long s5pc110_clk_dout_a2m_get_rate(struct clk *clk)
> +{
> +	unsigned long rate = clk_get_rate(clk->parent);
> +	unsigned int ratio;
> +
> +	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_A2M_MASK;
> +	ratio >>= S5PC110_CLKDIV0_A2M_SHIFT;
> +
> +	return rate / (ratio + 1);
> +}
> +
> +static struct clk clk_dout_a2m = {
> +	.name		= "dout_a2m",
> +	.id		= -1,
> +	.parent		= &clk_mout_apll.clk,
> +	.get_rate	= s5pc110_clk_dout_a2m_get_rate,
> +};
> +
> +/* HPM */
> +static struct clk *clk_src_hpm_list[] = {
> +	[0] = &clk_mout_apll.clk,
> +	[1] = &clk_mout_mpll.clk,
> +};
> +
> +static struct clk_sources clk_src_hpm = {
> +	.sources	= clk_src_hpm_list,
> +	.nr_sources	= ARRAY_SIZE(clk_src_hpm_list),
> +};
> +
> +static struct clksrc_clk clk_mout_hpm = {
> +	.clk = {
> +		.name		= "mout_hpm",
> +		.id		= -1,
> +	},
> +	.shift		= S5PC110_CLKSRC6_HPM_SHIFT,
> +	.mask		= S5PC110_CLKSRC6_HPM_MASK,
> +	.sources	= &clk_src_hpm,
> +	.reg_source	= S5PC110_CLKSRC6,
> +};
> +
> +/* MSYS */
> +static struct clk *clk_src_msys_list[] = {
> +	[0] = &clk_mout_apll.clk,
> +	[1] = &clk_mout_mpll.clk,
> +};
> +
> +static struct clk_sources clk_src_msys = {
> +	.sources	= clk_src_msys_list,
> +	.nr_sources	= ARRAY_SIZE(clk_src_msys_list),
> +};
> +
> +static struct clksrc_clk clk_mout_msys = {
> +	.clk = {
> +		.name		= "mout_msys",
> +		.id		= -1,
> +	},
> +	.shift		= S5PC110_CLKSRC0_MUX200_SHIFT,
> +	.mask		= S5PC110_CLKSRC0_MUX200_MASK,
> +	.sources	= &clk_src_msys,
> +	.reg_source	= S5PC110_CLKSRC0,
> +};
> +
> +/* DSYS */
> +static struct clk *clk_src_dsys_list[] = {
> +	[0] = &clk_mout_mpll.clk,
> +	[1] = &clk_dout_a2m,
> +};
> +
> +static struct clk_sources clk_src_dsys = {
> +	.sources	= clk_src_dsys_list,
> +	.nr_sources	= ARRAY_SIZE(clk_src_dsys_list),
> +};
> +
> +struct clksrc_clk clk_mout_dsys = {
> +	.clk = {
> +		.name		= "mout_dsys",
> +		.id		= -1,
> +	},
> +	.shift		= S5PC110_CLKSRC0_MUX166_SHIFT,
> +	.mask		= S5PC110_CLKSRC0_MUX166_MASK,
> +	.sources	= &clk_src_dsys,
> +	.reg_source	= S5PC110_CLKSRC0,
> +};
> +
> +/* PSYS */
> +static struct clk *clk_src_psys_list[] = {
> +	[0] = &clk_mout_mpll.clk,
> +	[1] = &clk_dout_a2m,
> +};
> +
> +static struct clk_sources clk_src_psys = {
> +	.sources	= clk_src_psys_list,
> +	.nr_sources	= ARRAY_SIZE(clk_src_psys_list),
> +};
> +
> +static struct clksrc_clk clk_mout_psys = {
> +	.clk = {
> +		.name		= "mout_psys",
> +		.id		= -1,
> +	},
> +	.shift		= S5PC110_CLKSRC0_MUX133_SHIFT,
> +	.mask		= S5PC110_CLKSRC0_MUX133_MASK,
> +	.sources	= &clk_src_psys,
> +	.reg_source	= S5PC110_CLKSRC0,
> +};
> +
> +/* Dout COPY */
> +static unsigned long s5pc110_clk_dout_copy_get_rate(struct clk *clk)
> +{
> +	unsigned long rate = clk_get_rate(clk->parent);
> +	unsigned int ratio;
> +
> +	ratio = __raw_readl(S5PC110_CLKDIV6) & S5PC110_CLKDIV6_COPY_MASK;
> +	ratio >>= S5PC110_CLKDIV6_COPY_SHIFT;
> +
> +	return rate / (ratio + 1);
> +}
> +
> +static struct clk clk_dout_copy = {
> +	.name		= "dout_copy",
> +	.id		= -1,
> +	.parent		= &clk_mout_hpm.clk,
> +	.get_rate	= s5pc110_clk_dout_copy_get_rate,
> +};
> +
> +/* Dout HPM */
> +static unsigned long s5pc110_clk_dout_hpm_get_rate(struct clk *clk)
> +{
> +	unsigned long rate = clk_get_rate(clk->parent);
> +	unsigned int ratio;
> +
> +	ratio = __raw_readl(S5PC110_CLKDIV6) & S5PC110_CLKDIV6_HPM_MASK;
> +	ratio >>= S5PC110_CLKDIV6_HPM_SHIFT;
> +
> +	return rate / (ratio + 1);
> +}
> +
> +static struct clk clk_dout_hpm = {
> +	.name		= "dout_hpm",
> +	.id		= -1,
> +	.parent		= &clk_dout_copy,
> +	.get_rate	= s5pc110_clk_dout_hpm_get_rate,
> +};
> +
> +/* Dout APLL - ARMCLK */
> +static unsigned long s5pc110_clk_dout_apll_get_rate(struct clk *clk)
> +{
> +	unsigned long rate = clk_get_rate(clk->parent);
> +	unsigned int ratio;
> +
> +	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_APLL_MASK;
> +	ratio >>= S5PC110_CLKDIV0_APLL_SHIFT;
> +
> +	return rate / (ratio + 1);
> +}
> +
> +static struct clk clk_dout_apll = {
> +	.name		= "dout_apll",
> +	.id		= -1,
> +	.parent		= &clk_mout_msys.clk,
> +	.get_rate	= s5pc110_clk_dout_apll_get_rate,
> +};
> +
> +/* Dout HCLKM - ACLK200, HCLK_MSYS */
> +static unsigned long s5pc110_clk_dout_hclkm_get_rate(struct clk *clk)
> +{
> +	unsigned long rate = clk_get_rate(clk->parent);
> +	unsigned int ratio;
> +
> +	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_HCLK_MSYS_MASK;
> +	ratio >>= S5PC110_CLKDIV0_HCLK_MSYS_SHIFT;
> +
> +	return rate / (ratio + 1);
> +}
> +
> +struct clk clk_dout_hclkm = {
> +	.name		= "dout_hclkm",
> +	.id		= -1,
> +	.parent		= &clk_dout_apll,
> +	.get_rate	= s5pc110_clk_dout_hclkm_get_rate,
> +};
> +
> +/* Dout PCLKM - PCLK_MSYS */
> +static unsigned long s5pc110_clk_dout_pclkm_get_rate(struct clk *clk)
> +{
> +	unsigned long rate = clk_get_rate(clk->parent);
> +	unsigned int ratio;
> +
> +	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_PCLK_MSYS_MASK;
> +	ratio >>= S5PC110_CLKDIV0_HCLK_PSYS_SHIFT;
> +
> +	return rate / (ratio + 1);
> +}
> +
> +struct clk clk_dout_pclkm = {
> +	.name		= "dout_pclkm",
> +	.id		= -1,
> +	.parent		= &clk_dout_hclkm,
> +	.get_rate	= s5pc110_clk_dout_pclkm_get_rate,
> +};
> +
> +/* Dout IMEM - HCLK100 */
> +static unsigned long s5pc110_clk_dout_imem_get_rate(struct clk *clk)
> +{
> +	unsigned long rate = clk_get_rate(clk->parent);
> +	return rate / 2;
> +}
> +
> +static struct clk clk_dout_imem = {
> +	.name		= "dout_imem",
> +	.id		= -1,
> +	.parent		= &clk_dout_hclkm,
> +	.get_rate	= s5pc110_clk_dout_imem_get_rate,
> +};
> +
> +/* Dout HCLKD - HCLK_DSYS */
> +static unsigned long s5pc110_clk_dout_hclkd_get_rate(struct clk *clk)
> +{
> +	unsigned long rate;
> +	unsigned int ratio;
> +
> +	rate = clk_get_rate(clk->parent);
> +	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_HCLK_DSYS_MASK;
> +	ratio >>= S5PC110_CLKDIV0_HCLK_DSYS_SHIFT;
> +
> +	return rate / (ratio + 1);
> +}
> +
> +struct clk clk_dout_hclkd = {
> +	.name		= "dout_hclkd",
> +	.id		= -1,
> +	.parent		= &clk_mout_dsys.clk,
> +	.get_rate	= s5pc110_clk_dout_hclkd_get_rate,
> +};
> +
> +/* Dout PCLKD - PCLK_DSYS */
> +static unsigned long s5pc110_clk_dout_pclkd_get_rate(struct clk *clk)
> +{
> +	unsigned long rate = clk_get_rate(clk->parent);
> +	unsigned int ratio;
> +
> +	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_PCLK_DSYS_MASK;
> +	ratio >>= S5PC110_CLKDIV0_PCLK_DSYS_SHIFT;
> +
> +	return rate / (ratio + 1);
> +}
> +
> +struct clk clk_dout_pclkd = {
> +	.name		= "dout_pclkd",
> +	.id		= -1,
> +	.parent		= &clk_dout_hclkd,
> +	.get_rate	= s5pc110_clk_dout_pclkd_get_rate,
> +};
> +
> +/* Dout FIMC - SCLK_FIMC */
> +static unsigned long s5pc110_clk_dout_fimc_get_rate(struct clk *clk)
> +{
> +	unsigned long rate = clk_get_rate(clk->parent);
> +	unsigned int ratio;
> +
> +	ratio = __raw_readl(S5PC110_CLKDIV1) & S5PC110_CLKDIV1_FIMC_MASK;
> +	ratio >>= S5PC110_CLKDIV1_FIMC_SHIFT;
> +
> +	return rate / (ratio + 1);
> +}
> +
> +static struct clk clk_dout_fimc = {
> +	.name		= "dout_fimc",
> +	.id		= -1,
> +	.parent		= &clk_mout_dsys.clk,
> +	.get_rate	= s5pc110_clk_dout_fimc_get_rate,
> +};
> +
> +/* Dout HCLKP - ARMATCLK, HCLK_PSYS */
> +static unsigned long s5pc110_clk_dout_hclkp_get_rate(struct clk *clk)
> +{
> +	unsigned long rate = clk_get_rate(clk->parent);
> +	unsigned int ratio;
> +
> +	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_HCLK_PSYS_MASK;
> +	ratio >>= S5PC110_CLKDIV0_HCLK_PSYS_SHIFT;
> +
> +	return rate / (ratio + 1);
> +}
> +
> +struct clk clk_dout_hclkp = {
> +	.name		= "dout_hclkp",
> +	.id		= -1,
> +	.parent		= &clk_mout_psys.clk,
> +	.get_rate	= s5pc110_clk_dout_hclkp_get_rate,
> +};
> +
> +/* Dout PCLKD - PCLK_DSYS */
> +static unsigned long s5pc110_clk_dout_pclkp_get_rate(struct clk *clk)
> +{
> +	unsigned long rate = clk_get_rate(clk->parent);
> +	unsigned int ratio;
> +
> +	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_PCLK_PSYS_MASK;
> +	ratio >>= S5PC110_CLKDIV0_PCLK_PSYS_SHIFT;
> +
> +	return rate / (ratio + 1);
> +}
> +
> +struct clk clk_dout_pclkp = {
> +	.name		= "dout_pclkp",
> +	.id		= -1,
> +	.parent		= &clk_dout_hclkp,
> +	.get_rate	= s5pc110_clk_dout_pclkp_get_rate,
> +};
> +
> +/* FLASH */
> +static struct clk *clk_src_onenand_list[] = {
> +	[0] = &clk_dout_hclkd,
> +	[1] = &clk_dout_hclkp,
> +};
> +
> +static struct clk_sources clk_src_onenand = {
> +	.sources	= clk_src_onenand_list,
> +	.nr_sources	= ARRAY_SIZE(clk_src_onenand_list),
> +};
> +
> +static struct clksrc_clk clk_mout_onenand = {
> +	.clk = {
> +		.name		= "mout_onenand",
> +		.id		= -1,
> +	},
> +	.shift		= S5PC110_CLKSRC0_ONENAND_SHIFT,
> +	.mask		= S5PC110_CLKSRC0_ONENAND_MASK,
> +	.sources	= &clk_src_onenand,
> +	.reg_source	= S5PC110_CLKSRC0,
> +};
> +
> +/* Dout FLASH - SCLK_ONENAND */
> +static unsigned long s5pc110_clk_dout_onenand_get_rate(struct clk *clk)
> +{
> +	unsigned long rate = clk_get_rate(clk->parent);
> +	unsigned int ratio;
> +
> +	ratio = __raw_readl(S5PC110_CLKDIV6) & S5PC110_CLKDIV6_ONENAND_MASK;
> +	ratio >>= S5PC110_CLKDIV6_ONENAND_SHIFT;
> +
> +	return rate / (ratio + 1);
> +}
> +
> +static struct clk clk_dout_onenand = {
> +	.name		= "dout_onenand",
> +	.id		= -1,
> +	.parent		= &clk_mout_onenand.clk,
> +	.get_rate	= s5pc110_clk_dout_onenand_get_rate,
> +};
> +
> +/* Dout FLASH2 - SCLK_ONENAND2 */
> +static unsigned long s5pc110_clk_dout_onenand2_get_rate(struct clk *clk)
> +{
> +	unsigned long rate = clk_get_rate(clk->parent);
> +	return rate / 2;
> +}
> +
> +static struct clk clk_dout_onenand2 = {
> +	.name		= "dout_onenand2",
> +	.id		= -1,
> +	.parent		= &clk_dout_onenand,
> +	.get_rate	= s5pc110_clk_dout_onenand2_get_rate,
> +};
> +
> +/* Peripherals */
> +static inline struct clksrc_clk *to_clksrc(struct clk *clk)
> +{
> +	return container_of(clk, struct clksrc_clk, clk);
> +}
> +
> +static unsigned long s5pc110_getrate_clksrc(struct clk *clk)
> +{
> +	struct clksrc_clk *sclk = to_clksrc(clk);
> +	unsigned long rate = clk_get_rate(clk->parent);
> +	u32 clkdiv = __raw_readl(sclk->reg_divider);
> +
> +	clkdiv >>= sclk->divider_shift;
> +	clkdiv &= 0xf;
> +	clkdiv++;
> +
> +	rate /= clkdiv;
> +	return rate;
> +}
> +
> +static int s5pc110_setrate_clksrc(struct clk *clk, unsigned long rate)
> +{
> +	struct clksrc_clk *sclk = to_clksrc(clk);
> +	void __iomem *reg = sclk->reg_divider;
> +	unsigned int div;
> +	u32 val;
> +
> +	rate = clk_round_rate(clk, rate);
> +	div = clk_get_rate(clk->parent) / rate;
> +	if (div > 16)
> +		return -EINVAL;
> +
> +	val = __raw_readl(reg);
> +	val &= ~(0xf << sclk->divider_shift);
> +	val |= (div - 1) << sclk->divider_shift;
> +	__raw_writel(val, reg);
> +
> +	return 0;
> +}
> +
> +static int s5pc110_setparent_clksrc(struct clk *clk, struct clk *parent)
> +{
> +	struct clksrc_clk *sclk = to_clksrc(clk);
> +	struct clk_sources *srcs = sclk->sources;
> +	u32 clksrc = __raw_readl(sclk->reg_source);
> +	int src_nr = -1;
> +	int ptr;
> +
> +	for (ptr = 0; ptr < srcs->nr_sources; ptr++) {
> +		if (srcs->sources[ptr] == parent) {
> +			src_nr = ptr;
> +			break;
> +		}
> +	}
> +
> +	if (src_nr >= 0) {
> +		clksrc &= ~sclk->mask;
> +		clksrc |= src_nr << sclk->shift;
> +
> +		__raw_writel(clksrc, sclk->reg_source);
> +		return 0;
> +	}
> +
> +	return -EINVAL;
> +}
> +
> +static unsigned long s5pc110_roundrate_clksrc(struct clk *clk,
> +					      unsigned long rate)
> +{
> +	unsigned long parent_rate = clk_get_rate(clk->parent);
> +	int div;
> +
> +	if (rate > parent_rate)
> +		rate = parent_rate;
> +	else {
> +		div = parent_rate / rate;
> +
> +		if (div == 0)
> +			div = 1;
> +		if (div > 16)
> +			div = 16;
> +
> +		rate = parent_rate / div;
> +	}
> +
> +	return rate;
> +}
> +
> +static struct clk *clkset_default_list[] = {
> +	&clk_fin_apll,
> +	&clk_usb_xtal,
> +	&clk_hdmi_27m,
> +	&clk_usbphy0,
> +	&clk_usbphy1,
> +	&clk_hdmi_phy,
> +	&clk_mout_mpll.clk,
> +	&clk_mout_epll.clk,
> +	&clk_mout_vpll.clk,
> +};
> +
> +
> +/* CAM */
> +static struct clk_sources clkset_cam = {
> +	.sources	= clkset_default_list,
> +	.nr_sources	= ARRAY_SIZE(clkset_default_list),
> +};
> +
> +static struct clksrc_clk clk_cam0 = {
> +	.clk	= {
> +		.name		= "cam",
> +		.id		= 0,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC1_CAM0_SHIFT,
> +	.mask		= S5PC110_CLKSRC1_CAM0_MASK,
> +	.sources	= &clkset_cam,
> +	.divider_shift	= S5PC110_CLKDIV1_CAM0_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV1,
> +	.reg_source	= S5PC110_CLKSRC1,
> +};
> +
> +static struct clksrc_clk clk_cam1 = {
> +	.clk	= {
> +		.name		= "cam",
> +		.id		= 1,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC1_CAM1_SHIFT,
> +	.mask		= S5PC110_CLKSRC1_CAM1_MASK,
> +	.sources	= &clkset_cam,
> +	.divider_shift	= S5PC110_CLKDIV1_CAM1_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV1,
> +	.reg_source	= S5PC110_CLKSRC1,
> +};
> +
> +/* FIMD */
> +static struct clk_sources clkset_fimd = {
> +	.sources	= clkset_default_list,
> +	.nr_sources	= ARRAY_SIZE(clkset_default_list),
> +};
> +
> +static struct clksrc_clk clk_fimd = {
> +	.clk	= {
> +		.name		= "fimd",
> +		.id		= -1,
> +		.ctrlbit	= S5PC110_CLKGATE_IP1_FIMD,
> +		.enable		= s5pc110_ip1_ctrl,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC1_FIMD_SHIFT,
> +	.mask		= S5PC110_CLKSRC1_FIMD_MASK,
> +	.sources	= &clkset_fimd,
> +	.divider_shift	= S5PC110_CLKDIV1_FIMD_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV1,
> +	.reg_source	= S5PC110_CLKSRC1,
> +};
> +
> +/* MMC */
> +static struct clk_sources clkset_mmc = {
> +	.sources	= clkset_default_list,
> +	.nr_sources	= ARRAY_SIZE(clkset_default_list),
> +};
> +
> +static struct clksrc_clk clk_mmc0 = {
> +	.clk	= {
> +		.name		= "mmc-bus",
> +		.id		= 0,
> +		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC0,
> +		.enable		= s5pc110_ip2_ctrl,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC4_MMC0_SHIFT,
> +	.mask		= S5PC110_CLKSRC4_MMC0_MASK,
> +	.sources	= &clkset_mmc,
> +	.divider_shift	= S5PC110_CLKDIV4_MMC0_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV4,
> +	.reg_source	= S5PC110_CLKSRC4,
> +};
> +
> +static struct clksrc_clk clk_mmc1 = {
> +	.clk	= {
> +		.name		= "mmc-bus",
> +		.id		= 1,
> +		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC1,
> +		.enable		= s5pc110_ip2_ctrl,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC4_MMC1_SHIFT,
> +	.mask		= S5PC110_CLKSRC4_MMC1_MASK,
> +	.sources	= &clkset_mmc,
> +	.divider_shift	= S5PC110_CLKDIV4_MMC1_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV4,
> +	.reg_source	= S5PC110_CLKSRC4,
> +};
> +
> +static struct clksrc_clk clk_mmc2 = {
> +	.clk	= {
> +		.name		= "mmc-bus",
> +		.id		= 2,
> +		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC2,
> +		.enable		= s5pc110_ip2_ctrl,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC4_MMC2_SHIFT,
> +	.mask		= S5PC110_CLKSRC4_MMC2_MASK,
> +	.sources	= &clkset_mmc,
> +	.divider_shift	= S5PC110_CLKDIV4_MMC2_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV4,
> +	.reg_source	= S5PC110_CLKSRC4,
> +};
> +
> +static struct clksrc_clk clk_mmc3 = {
> +	.clk	= {
> +		.name		= "mmc-bus",
> +		.id		= 3,
> +		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC3,
> +		.enable		= s5pc110_ip2_ctrl,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC4_MMC3_SHIFT,
> +	.mask		= S5PC110_CLKSRC4_MMC3_MASK,
> +	.sources	= &clkset_mmc,
> +	.divider_shift	= S5PC110_CLKDIV4_MMC3_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV4,
> +	.reg_source	= S5PC110_CLKSRC4,
> +};
> +
> +/* AUDIO0 */
> +static struct clk_sources clkset_audio0 = {
> +	.sources	= clkset_default_list,
> +	.nr_sources	= ARRAY_SIZE(clkset_default_list),
> +};
> +
> +static struct clksrc_clk clk_audio0 = {
> +	.clk	= {
> +		.name		= "audio-bus",
> +		.id		= 0,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC6_AUDIO0_SHIFT,
> +	.mask		= S5PC110_CLKSRC6_AUDIO0_MASK,
> +	.sources	= &clkset_audio0,
> +	.divider_shift	= S5PC110_CLKDIV6_AUDIO0_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV6,
> +	.reg_source	= S5PC110_CLKSRC6,
> +};
> +
> +/* AUDIO1 */
> +static struct clk *clkset_audio1_list[] = {
> +	&clk_iis_cd1,
> +	&clk_pcm_cd1,
> +	&clk_hdmi_27m,
> +	&clk_usbphy0,
> +	&clk_usbphy1,
> +	&clk_hdmi_phy,
> +	&clk_mout_mpll.clk,
> +	&clk_mout_epll.clk,
> +	&clk_mout_vpll.clk,
> +};
> +
> +static struct clk_sources clkset_audio1 = {
> +	.sources	= clkset_audio1_list,
> +	.nr_sources	= ARRAY_SIZE(clkset_audio1_list),
> +};
> +
> +static struct clksrc_clk clk_audio1 = {
> +	.clk	= {
> +		.name		= "audio-bus",
> +		.id		= 1,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC6_AUDIO1_SHIFT,
> +	.mask		= S5PC110_CLKSRC6_AUDIO1_MASK,
> +	.sources	= &clkset_audio1,
> +	.divider_shift	= S5PC110_CLKDIV6_AUDIO1_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV6,
> +	.reg_source	= S5PC110_CLKSRC6,
> +};
> +
> +/* AUDIO2 */
> +static struct clk *clkset_audio2_list[] = {
> +	&clk_fin_apll,
> +	&clk_pcm_cd0,
> +	&clk_hdmi_27m,
> +	&clk_usbphy0,
> +	&clk_usbphy1,
> +	&clk_hdmi_phy,
> +	&clk_mout_mpll.clk,
> +	&clk_mout_epll.clk,
> +	&clk_mout_vpll.clk,
> +};
> +
> +static struct clk_sources clkset_audio2 = {
> +	.sources	= clkset_audio2_list,
> +	.nr_sources	= ARRAY_SIZE(clkset_audio2_list),
> +};
> +
> +static struct clksrc_clk clk_audio2 = {
> +	.clk	= {
> +		.name		= "audio-bus",
> +		.id		= 2,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC6_AUDIO2_SHIFT,
> +	.mask		= S5PC110_CLKSRC6_AUDIO2_MASK,
> +	.sources	= &clkset_audio2,
> +	.divider_shift	= S5PC110_CLKDIV6_AUDIO2_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV6,
> +	.reg_source	= S5PC110_CLKSRC6,
> +};
> +
> +/* FIMC */
> +static struct clk_sources clkset_fimc = {
> +	.sources	= clkset_default_list,
> +	.nr_sources	= ARRAY_SIZE(clkset_default_list),
> +};
> +
> +static struct clksrc_clk clk_fimc0 = {
> +	.clk	= {
> +		.name		= "fimc",
> +		.id		= 0,
> +		.ctrlbit	= S5PC110_CLKGATE_IP0_FIMC0,
> +		.enable		= s5pc110_ip0_ctrl,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC3_FIMC0_LCLK_SHIFT,
> +	.mask		= S5PC110_CLKSRC3_FIMC0_LCLK_MASK,
> +	.sources	= &clkset_fimc,
> +	.divider_shift	= S5PC110_CLKDIV3_FIMC0_LCLK_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV3,
> +	.reg_source	= S5PC110_CLKSRC3,
> +};
> +
> +static struct clksrc_clk clk_fimc1 = {
> +	.clk	= {
> +		.name		= "fimc",
> +		.id		= 1,
> +		.ctrlbit	= S5PC110_CLKGATE_IP0_FIMC1,
> +		.enable		= s5pc110_ip0_ctrl,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC3_FIMC1_LCLK_SHIFT,
> +	.mask		= S5PC110_CLKSRC3_FIMC1_LCLK_MASK,
> +	.sources	= &clkset_fimc,
> +	.divider_shift	= S5PC110_CLKDIV3_FIMC1_LCLK_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV3,
> +	.reg_source	= S5PC110_CLKSRC3,
> +};
> +
> +static struct clksrc_clk clk_fimc2 = {
> +	.clk	= {
> +		.name		= "fimc",
> +		.id		= 2,
> +		.ctrlbit	= S5PC110_CLKGATE_IP0_FIMC2,
> +		.enable		= s5pc110_ip0_ctrl,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC3_FIMC2_LCLK_SHIFT,
> +	.mask		= S5PC110_CLKSRC3_FIMC2_LCLK_MASK,
> +	.sources	= &clkset_fimc,
> +	.divider_shift	= S5PC110_CLKDIV3_FIMC2_LCLK_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV3,
> +	.reg_source	= S5PC110_CLKSRC3,
> +};
> +
> +/* UART */
> +static struct clk_sources clkset_uart = {
> +	.sources	= clkset_default_list,
> +	.nr_sources	= ARRAY_SIZE(clkset_default_list),
> +};
> +
> +static struct clksrc_clk clk_uart0 = {
> +	.clk	= {
> +		.name		= "uart",
> +		.id		= 0,
> +		.ctrlbit	= S5PC110_CLKGATE_IP3_UART0,
> +		.enable		= s5pc110_ip3_ctrl,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC4_UART0_SHIFT,
> +	.mask		= S5PC110_CLKSRC4_UART0_MASK,
> +	.sources	= &clkset_uart,
> +	.divider_shift	= S5PC110_CLKDIV4_UART0_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV4,
> +	.reg_source	= S5PC110_CLKSRC4,
> +};
> +
> +static struct clksrc_clk clk_uart1 = {
> +	.clk	= {
> +		.name		= "uart",
> +		.id		= 1,
> +		.ctrlbit	= S5PC110_CLKGATE_IP3_UART1,
> +		.enable		= s5pc110_ip3_ctrl,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC4_UART1_SHIFT,
> +	.mask		= S5PC110_CLKSRC4_UART1_MASK,
> +	.sources	= &clkset_uart,
> +	.divider_shift	= S5PC110_CLKDIV4_UART1_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV4,
> +	.reg_source	= S5PC110_CLKSRC4,
> +};
> +
> +static struct clksrc_clk clk_uart2 = {
> +	.clk	= {
> +		.name		= "uart",
> +		.id		= 2,
> +		.ctrlbit	= S5PC110_CLKGATE_IP3_UART2,
> +		.enable		= s5pc110_ip3_ctrl,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC4_UART2_SHIFT,
> +	.mask		= S5PC110_CLKSRC4_UART2_MASK,
> +	.sources	= &clkset_uart,
> +	.divider_shift	= S5PC110_CLKDIV4_UART2_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV4,
> +	.reg_source	= S5PC110_CLKSRC4,
> +};
> +
> +static struct clksrc_clk clk_uart3 = {
> +	.clk	= {
> +		.name		= "uart",
> +		.id		= 3,
> +		.ctrlbit	= S5PC110_CLKGATE_IP3_UART3,
> +		.enable		= s5pc110_ip3_ctrl,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC4_UART3_SHIFT,
> +	.mask		= S5PC110_CLKSRC4_UART3_MASK,
> +	.sources	= &clkset_uart,
> +	.divider_shift	= S5PC110_CLKDIV4_UART3_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV4,
> +	.reg_source	= S5PC110_CLKSRC4,
> +};
> +
> +/* PWM */
> +static struct clk_sources clkset_pwm = {
> +	.sources	= clkset_default_list,
> +	.nr_sources	= ARRAY_SIZE(clkset_default_list),
> +};
> +
> +static struct clksrc_clk clk_pwm = {
> +	.clk	= {
> +		.name		= "pwm",
> +		.id		= -1,
> +		.ctrlbit	= S5PC110_CLKGATE_IP3_PWM,
> +		.enable		= s5pc110_ip3_ctrl,
> +		.set_parent	= s5pc110_setparent_clksrc,
> +		.get_rate	= s5pc110_getrate_clksrc,
> +		.set_rate	= s5pc110_setrate_clksrc,
> +		.round_rate	= s5pc110_roundrate_clksrc,
> +	},
> +	.shift		= S5PC110_CLKSRC5_PWM_SHIFT,
> +	.mask		= S5PC110_CLKSRC5_PWM_MASK,
> +	.sources	= &clkset_pwm,
> +	.divider_shift	= S5PC110_CLKDIV5_PWM_SHIFT,
> +	.reg_divider	= S5PC110_CLKDIV5,
> +	.reg_source	= S5PC110_CLKSRC5,
> +};
> +
> +/* Clock initialisation code */
> +static struct clksrc_clk *init_parents[] = {
> +	&clk_mout_apll,
> +	&clk_mout_mpll,
> +	&clk_mout_epll,
> +	&clk_mout_vpllsrc,
> +	&clk_mout_vpll,
> +	&clk_mout_hpm,
> +	&clk_mout_msys,
> +	&clk_mout_dsys,
> +	&clk_mout_psys,
> +	&clk_mout_onenand,
> +	&clk_cam0,
> +	&clk_cam1,
> +	&clk_fimd,
> +	&clk_mmc0,
> +	&clk_mmc1,
> +	&clk_mmc2,
> +	&clk_mmc3,
> +	&clk_audio0,
> +	&clk_audio1,
> +	&clk_audio2,
> +	&clk_fimc0,
> +	&clk_fimc1,
> +	&clk_fimc2,
> +	&clk_uart0,
> +	&clk_uart1,
> +	&clk_uart2,
> +	&clk_uart3,
> +	&clk_pwm,
> +};
> +
> +static void __init_or_cpufreq s5pc110_set_clksrc(struct clksrc_clk *clk)
> +{
> +	struct clk_sources *srcs = clk->sources;
> +	u32 clksrc = __raw_readl(clk->reg_source);
> +
> +	clksrc &= clk->mask;
> +	clksrc >>= clk->shift;
> +
> +	if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
> +		printk(KERN_ERR "%s: bad source %d\n",
> +		       clk->clk.name, clksrc);
> +		return;
> +	}
> +
> +	clk->clk.parent = srcs->sources[clksrc];
> +
> +	printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n",
> +		clk->clk.name, clk->clk.parent->name, clksrc,
> +		print_mhz(clk_get_rate(&clk->clk)));
> +}
> +
> +#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
> +
> +void __init_or_cpufreq s5pc110_setup_clocks(void)
> +{
> +	struct clk *xtal_clk;
> +	unsigned long xtal;
> +	unsigned long armclk;
> +	unsigned long hclk_msys, hclk_dsys, hclk_psys;
> +	unsigned long pclk_msys, pclk_dsys, pclk_psys;
> +	unsigned long apll, mpll, epll, vpll;
> +	unsigned int clkdiv0;
> +	unsigned int ptr;
> +
> +	printk(KERN_DEBUG "%s: registering clocks\n", __func__);
> +
> +	clkdiv0 = __raw_readl(S5PC110_CLKDIV0);
> +
> +	printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
> +
> +	xtal_clk = clk_get(NULL, "xtal");
> +	BUG_ON(IS_ERR(xtal_clk));
> +
> +	xtal = clk_get_rate(xtal_clk);
> +	clk_put(xtal_clk);
> +
> +	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
> +
> +	apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC110_APLL_CON), 1);
> +	mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC110_MPLL_CON), 0);
> +	epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC110_EPLL_CON), 0);
> +	vpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC110_VPLL_CON), 0);
> +
> +	printk(KERN_INFO "S5PC110: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz"
> +		", Epll=%ld.%03ld Mhz, Vpll=%ld.%03ld Mhz\n",
> +		print_mhz(apll), print_mhz(mpll),
> +		print_mhz(epll), print_mhz(vpll));
> +
> +	armclk = apll / GET_DIV(clkdiv0, S5PC110_CLKDIV0_APLL);
> +	hclk_msys = armclk / GET_DIV(clkdiv0, S5PC110_CLKDIV0_HCLK_MSYS);
> +	hclk_dsys = mpll / GET_DIV(clkdiv0, S5PC110_CLKDIV0_HCLK_DSYS);
> +	hclk_psys = mpll / GET_DIV(clkdiv0, S5PC110_CLKDIV0_HCLK_PSYS);
> +	pclk_msys = hclk_msys / GET_DIV(clkdiv0, S5PC110_CLKDIV0_PCLK_MSYS);
> +	pclk_dsys = hclk_dsys / GET_DIV(clkdiv0, S5PC110_CLKDIV0_PCLK_DSYS);
> +	pclk_psys = hclk_psys / GET_DIV(clkdiv0, S5PC110_CLKDIV0_PCLK_PSYS);
> +
> +	printk(KERN_INFO "S5PC110: ARMCLK=%ld.%03ld MHz\n"
> +		"HCLK: Msys %ld.%03ld MHz, Dsys %ld.%03ld MHz, Psys %ld.%03ld MHz\n"
> +		"PCLK: Msys %ld.%03ld MHz, Dsys %ld.%03ld MHz, Psys %ld.%03ld MHz\n",
> +		print_mhz(armclk),
> +		print_mhz(hclk_msys), print_mhz(hclk_dsys), print_mhz(hclk_psys),
> +		print_mhz(pclk_msys), print_mhz(pclk_dsys), print_mhz(pclk_psys));
> +
> +	clk_ext_xtal_mux.rate = xtal;
> +	clk_fout_apll.rate = apll;
> +	clk_fout_mpll.rate = mpll;
> +	clk_fout_epll.rate = epll;
> +	clk_fout_vpll.rate = vpll;
> +
> +	clk_dout_hclkm.rate = hclk_msys;
> +	clk_dout_hclkd.rate = hclk_dsys;
> +	clk_dout_hclkp.rate = hclk_psys;
> +	clk_dout_pclkm.rate = pclk_msys;
> +	clk_dout_pclkd.rate = pclk_dsys;
> +	clk_dout_pclkp.rate = pclk_psys;
> +
> +	clk_h.rate = hclk_psys;
> +	clk_p.rate = pclk_psys;
> +	clk_f.rate = armclk;
> +
> +	for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
> +		s5pc110_set_clksrc(init_parents[ptr]);
> +}
> +
> +static struct clk *clks[] __initdata = {
> +	&clk_ext_xtal_mux,
> +	&clk_usb_xtal,
> +	&clk_pcm_cd0,
> +	&clk_pcm_cd1,
> +	&clk_iis_cd1,
> +	&clk_mout_apll.clk,
> +	&clk_mout_mpll.clk,
> +	&clk_mout_epll.clk,
> +	&clk_mout_vpllsrc.clk,
> +	&clk_mout_vpll.clk,
> +	&clk_dout_a2m,
> +	&clk_mout_hpm.clk,
> +	&clk_mout_msys.clk,
> +	&clk_mout_dsys.clk,
> +	&clk_mout_psys.clk,
> +	&clk_dout_copy,
> +	&clk_dout_hpm,
> +	&clk_dout_apll,
> +	&clk_dout_hclkm,
> +	&clk_dout_pclkm,
> +	&clk_dout_hclkd,
> +	&clk_dout_pclkd,
> +	&clk_dout_hclkp,
> +	&clk_dout_pclkp,
> +	&clk_dout_fimc,
> +	&clk_dout_imem,
> +	&clk_mout_onenand.clk,
> +	&clk_dout_onenand,
> +	&clk_dout_onenand2,
> +	&clk_cam0.clk,
> +	&clk_cam1.clk,
> +	&clk_fimd.clk,
> +	&clk_mmc0.clk,
> +	&clk_mmc1.clk,
> +	&clk_mmc2.clk,
> +	&clk_mmc3.clk,
> +	&clk_audio0.clk,
> +	&clk_audio1.clk,
> +	&clk_audio2.clk,
> +	&clk_fimc0.clk,
> +	&clk_fimc1.clk,
> +	&clk_fimc2.clk,
> +	&clk_uart0.clk,
> +	&clk_uart1.clk,
> +	&clk_uart2.clk,
> +	&clk_uart3.clk,
> +	&clk_pwm.clk,
> +};
> +
> +void __init s5pc110_register_clocks(void)
> +{
> +	struct clk *clkp;
> +	int ret;
> +	int ptr;
> +
> +	for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
> +		clkp = clks[ptr];
> +		ret = s3c24xx_register_clock(clkp);
> +		if (ret < 0) {
> +			printk(KERN_ERR "Failed to register clock %s (%d)\n",
> +			       clkp->name, ret);
> +		}
> +	}
> +}
> -- 
> 1.6.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.

[PATCH] Add Samsung S5PC110 SoC support

[Ben Dooks]

On Wed, Nov 18, 2009 at 02:32:55PM +0100, Marek Szyprowski wrote:
> Hello,
> 
> This preliminary patch series adds support for Samsung S5PC110 SoC.
> S5PC110 belongs to S5PC1XX family (CortexA8 ARM core), but differs in
> many places from the S5PC100 SoC: new memory map, different clock
> hierarchy, new gpio banks and much more powerful integrated peripherals.
> Such differences cannot be easily handled in the current Samsung
> machine&platform framework. To avoid duplication of code and adding yet
> another plat-* directory, we decided to introduce sub-platforms in
> the current s5pc1xx platform.
> 
> First 8 patches prepare s5pc1xx platform code for introduction of the
> new sub-platform approach. Then in the next 11 patches all core
> functions and drivers are subsequently added, so S5PC110 sub-platform
> gets similar level of support as S5PC100.
> 
> This patch series has been prepared against latest ARM Kernel tree from
> http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm.git/
> 
> I know that Ben is working hard on new Samsung SoC platform framework,
> but stabilizing it and porting all the existing Samsung platforms would
> take time. This sub-platform solution is already prepared and until the
> new framework will be available and merged, we would like to use our
> approach.

running these through checkpatch first would have been a good idea:

fyi, these need fixing:

WARNING: externs should be avoided in .c files
#666: FILE: arch/arm/plat-s5pc1xx/s5pc110-clocks.c:92:
+extern struct clk clk_dout_hclkm;

WARNING: externs should be avoided in .c files
#667: FILE: arch/arm/plat-s5pc1xx/s5pc110-clocks.c:93:
+extern struct clk clk_dout_hclkd;

WARNING: externs should be avoided in .c files
#668: FILE: arch/arm/plat-s5pc1xx/s5pc110-clocks.c:94:
+extern struct clk clk_dout_hclkp;

WARNING: externs should be avoided in .c files
#669: FILE: arch/arm/plat-s5pc1xx/s5pc110-clocks.c:95:
+extern struct clk clk_dout_pclkd;

WARNING: externs should be avoided in .c files
#670: FILE: arch/arm/plat-s5pc1xx/s5pc110-clocks.c:96:
+extern struct clk clk_dout_pclkp;

#348: FILE: arch/arm/mach-s5pc110/include/plat/irqs.h:197:
+#define IRQ_EINT_BIT(x)		(x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0))

could this be made an inline, or@least have x encased in brackets to
avoid any problems with macro expansion?

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[jassi brar]

On Thu, Nov 19, 2009 at 7:13 AM, Ben Dooks <ben-linux@fluff.org> wrote:
> On Wed, Nov 18, 2009 at 11:14:52PM +0900, jassi brar wrote:
>> On Wed, Nov 18, 2009 at 10:33 PM, Marek Szyprowski
>> <m.szyprowski@samsung.com> wrote:
>> > From: Kyungmin Park <kyungmin.park@samsung.com>
>> >
>> > Samsung S5PC110 SoCs have UART that differs a bit from the one known
>> > from the previous Samsung SoCs. This patch adds support for this new
>> > driver.
>> >
>> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>
>> Not just about this c110 patch: I think this string comparison thing
>> isn't very neat.
>> I think we'd better be doing it by indexing into an array of clock
>> names(which can be
>> defined in some platform specific code).
>
> I don't mind changing to using a table, but the table is probably best
> off here, closest to the UART drivers in question.
well as per current implementation of drivers/serial/samsung.c we can't
do much about it.

Ideally, each SoC(if not yet, maybe in future) can have different
number/names of possible source clocks for signal generation. Let us
not depend upon even defaults(fclk, pclk etc)
Let each platform code(SoC specific) define names of all possible
source clocks and let the board init code pass on the potential source
clocks by some bit-mask(or some other mechanism) while setting the
platform data.
The samsung.c could then simply go thru the array of source clock
names and the bit-mask, in platform_data, while selecting the best possible
 source for the baud rate under consideration.

[PATCH 10/19] ARM: S5PC1XX: add S5PC110 memory map

[Kyungmin Park]

Hi,

On Thu, Nov 19, 2009 at 5:00 AM, Ben Dooks <ben-linux@fluff.org> wrote:
> There's stuff in here from 'Byungho Min <bhmin@samsung.com>'
> but no mention of an ack or signoff from this person.

Mr. Min also works together with me. He knows that this changes since
we use the same git.

Thank you,
Kyungmin Park

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[Mark Brown]

On Thu, Nov 19, 2009 at 11:44:14AM +0900, jassi brar wrote:

> Let each platform code(SoC specific) define names of all possible
> source clocks and let the board init code pass on the potential source
> clocks by some bit-mask(or some other mechanism) while setting the
> platform data.

This is going to set off warnings from a clock API point of view -
passing clock names around in platform data is usually a sign that
something is very wrong.  Keeping the mapping inside the clock API
(still controlled by the board driver but by telling the clock API that
device X should use clock Y).

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[jassi brar]

On Thu, Nov 19, 2009 at 7:33 PM, Mark Brown
<broonie@opensource.wolfsonmicro.com> wrote:
> On Thu, Nov 19, 2009 at 11:44:14AM +0900, jassi brar wrote:
>
>> Let each platform code(SoC specific) define names of all possible
>> source clocks and let the board init code pass on the potential source
>> clocks by some bit-mask(or some other mechanism) while setting the
>> platform data.
>
> This is going to set off warnings from a clock API point of view -
> passing clock names around in platform data is usually a sign that
> something is very wrong. ?Keeping the mapping inside the clock API
> (still controlled by the board driver but by telling the clock API that
> device X should use clock Y).
no clock pointer needs to be passed, just a pointer to an array of _strings_
There is no need to even include any clock header in platform code
for the purpose.

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[Mark Brown]

On Thu, Nov 19, 2009 at 08:05:29PM +0900, jassi brar wrote:
> On Thu, Nov 19, 2009 at 7:33 PM, Mark Brown

> > This is going to set off warnings from a clock API point of view -
> > passing clock names around in platform data is usually a sign that
> > something is very wrong. ?Keeping the mapping inside the clock API
> > (still controlled by the board driver but by telling the clock API that
> > device X should use clock Y).

> no clock pointer needs to be passed, just a pointer to an array of _strings_
> There is no need to even include any clock header in platform code
> for the purpose.

Yes, that's what I was commenting on - like I say, passing clock names
tends to set off the same alarm bells as passing a struct clk.  Like I
say, the general model for this has been that the fixups will be done by
having the machine code talk to the clock API ratehr than bouncing the
data about the clock to use through the driver.

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[jassi brar]

On Thu, Nov 19, 2009 at 8:08 PM, Mark Brown
<broonie@opensource.wolfsonmicro.com> wrote:
> On Thu, Nov 19, 2009 at 08:05:29PM +0900, jassi brar wrote:
>> On Thu, Nov 19, 2009 at 7:33 PM, Mark Brown
>
>> > This is going to set off warnings from a clock API point of view -
>> > passing clock names around in platform data is usually a sign that
>> > something is very wrong. ?Keeping the mapping inside the clock API
>> > (still controlled by the board driver but by telling the clock API that
>> > device X should use clock Y).
>
>> no clock pointer needs to be passed, just a pointer to an array of _strings_
>> There is no need to even include any clock header in platform code
>> for the purpose.
>
> Yes, that's what I was commenting on - like I say, passing clock names
> tends to set off the same alarm bells as passing a struct clk. ?Like I
> say, the general model for this has been that the fixups will be done by
> having the machine code talk to the clock API ratehr than bouncing the
> data about the clock to use through the driver.
The case here is that UART controller can source from various platform clocks
to generate the UART clocks. The drivers/serial/samsung.c chooses a source
clock that can result in closest match to the requested rate.
How could we do that from machine code(except for writing callbacks for each
machine using the SoC)?

Or maybe i cud understand better looking at some example.
Cud u suggest some please?

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[Mark Brown]

On Thu, Nov 19, 2009 at 08:26:34PM +0900, jassi brar wrote:

> The case here is that UART controller can source from various platform clocks
> to generate the UART clocks. The drivers/serial/samsung.c chooses a source
> clock that can result in closest match to the requested rate.
> How could we do that from machine code(except for writing callbacks for each
> machine using the SoC)?

> Or maybe i cud understand better looking at some example.
> Cud u suggest some please?

I can't think off the top of my head of anything which does this
dynamically (rather than just choosing a clock at startup time).  OMAP
might have something since they seem to have the most advanced of the
current implementations.

Off the top of my head it sounds like the muxing ought to be pushed into
the clock API completely - the problem of picking the best match for the
current use case isn't unique to the serial driver by any stretch of the
imagination.  The serial driver would then end up just seeing the output
of the mux it uses, with the clock API dealing with working out which of
the sources can deliver the best match.

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[Russell King - ARM Linux]

On Thu, Nov 19, 2009 at 11:08:27AM +0000, Mark Brown wrote:
> On Thu, Nov 19, 2009 at 08:05:29PM +0900, jassi brar wrote:
> > On Thu, Nov 19, 2009 at 7:33 PM, Mark Brown
> 
> > > This is going to set off warnings from a clock API point of view -
> > > passing clock names around in platform data is usually a sign that
> > > something is very wrong. ?Keeping the mapping inside the clock API
> > > (still controlled by the board driver but by telling the clock API that
> > > device X should use clock Y).
> 
> > no clock pointer needs to be passed, just a pointer to an array of _strings_
> > There is no need to even include any clock header in platform code
> > for the purpose.
> 
> Yes, that's what I was commenting on - like I say, passing clock names
> tends to set off the same alarm bells as passing a struct clk.  Like I
> say, the general model for this has been that the fixups will be done by
> having the machine code talk to the clock API ratehr than bouncing the
> data about the clock to use through the driver.

I'm not sure what you're commenting on precisely, but the Samsung code as
a whole doesn't use the clk API very well, and I suspect that is starting
to cause people to have to pass clock names around.

I've tried to persuade Ben to tidy this up and convert over to clkdev
before it becomes too big a problem, but I've had little success.  I
suspect it's now grown too big to be tackled sanely.

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[Mark Brown]

On Thu, Nov 19, 2009 at 11:38:41AM +0000, Russell King - ARM Linux wrote:

> I'm not sure what you're commenting on precisely, but the Samsung code as
> a whole doesn't use the clk API very well, and I suspect that is starting
> to cause people to have to pass clock names around.

That's what I'd thought originally but it's not quite the problem here.
The issue is that Samsung serial port clock is chosen from a mux and the
logic to select which of the inputs to that mux should be used is in the
serial driver.  This means that if the set of parent clocks changes then
the serial driver needs to be told what they are.

My suggestion was to push this logic down into the clock API so the
serial driver just requests a rate and then clock API picks the best
option from the mux.  As well as being nicer from the clock API point of
view this would also allow other drivers to use the same logic since
these muxes are a standard idiom for Samsung SoCs.

> I've tried to persuade Ben to tidy this up and convert over to clkdev
> before it becomes too big a problem, but I've had little success.  I
> suspect it's now grown too big to be tackled sanely.

clkdev would be nice but I don't think it'd deal with the issue here.

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[Russell King - ARM Linux]

On Thu, Nov 19, 2009 at 11:48:33AM +0000, Mark Brown wrote:
> On Thu, Nov 19, 2009 at 11:38:41AM +0000, Russell King - ARM Linux wrote:
> 
> > I'm not sure what you're commenting on precisely, but the Samsung code as
> > a whole doesn't use the clk API very well, and I suspect that is starting
> > to cause people to have to pass clock names around.
> 
> That's what I'd thought originally but it's not quite the problem here.
> The issue is that Samsung serial port clock is chosen from a mux and the
> logic to select which of the inputs to that mux should be used is in the
> serial driver.  This means that if the set of parent clocks changes then
> the serial driver needs to be told what they are.
> 
> My suggestion was to push this logic down into the clock API so the
> serial driver just requests a rate and then clock API picks the best
> option from the mux.  As well as being nicer from the clock API point of
> view this would also allow other drivers to use the same logic since
> these muxes are a standard idiom for Samsung SoCs.

Yes, I agree with that approach.

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[jassi brar]

On Thu, Nov 19, 2009 at 8:48 PM, Mark Brown
<broonie@opensource.wolfsonmicro.com> wrote:
> On Thu, Nov 19, 2009 at 11:38:41AM +0000, Russell King - ARM Linux wrote:
>
>> I'm not sure what you're commenting on precisely, but the Samsung code as
>> a whole doesn't use the clk API very well, and I suspect that is starting
>> to cause people to have to pass clock names around.
>
> That's what I'd thought originally but it's not quite the problem here.
> The issue is that Samsung serial port clock is chosen from a mux and the
> logic to select which of the inputs to that mux should be used is in the
> serial driver. ?This means that if the set of parent clocks changes then
> the serial driver needs to be told what they are.
just to add to the info: unlike system clocks and mux'es which are controlled
by registers of a dedicated clock/system controller, this uart mux is
managed by bits of some register of the UART controller.

> My suggestion was to push this logic down into the clock API so the
> serial driver just requests a rate and then clock API picks the best
> option from the mux. ?As well as being nicer from the clock API point of
> view this would also allow other drivers to use the same logic since
> these muxes are a standard idiom for Samsung SoCs.
how transparently could we add this 'uart-mux' into the clock API, provided
that the register space ioremap'ing is done in the uart driver, is to be seen.

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[Marek Szyprowski]

Hello,

On Thursday, November 19, 2009 12:49 PM Mark Brown wrote:

> On Thu, Nov 19, 2009 at 11:38:41AM +0000, Russell King - ARM Linux wrote:
> 
> > I'm not sure what you're commenting on precisely, but the Samsung code as
> > a whole doesn't use the clk API very well, and I suspect that is starting
> > to cause people to have to pass clock names around.
> 
> That's what I'd thought originally but it's not quite the problem here.
> The issue is that Samsung serial port clock is chosen from a mux and the
> logic to select which of the inputs to that mux should be used is in the
> serial driver.  This means that if the set of parent clocks changes then
> the serial driver needs to be told what they are.
> 
> My suggestion was to push this logic down into the clock API so the
> serial driver just requests a rate and then clock API picks the best
> option from the mux.  As well as being nicer from the clock API point of
> view this would also allow other drivers to use the same logic since
> these muxes are a standard idiom for Samsung SoCs.

What if a device does not operate properly when clocked from one of the
available clock sources (lets say machine specific problem)? There must
be a way of setting which clock(s) should not be considered when calculating
best choice for particular device.

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[Mark Brown]

On Thu, Nov 19, 2009 at 01:09:23PM +0100, Marek Szyprowski wrote:
> On Thursday, November 19, 2009 12:49 PM Mark Brown wrote:

> > My suggestion was to push this logic down into the clock API so the
> > serial driver just requests a rate and then clock API picks the best
> > option from the mux.  As well as being nicer from the clock API point of

> What if a device does not operate properly when clocked from one of the
> available clock sources (lets say machine specific problem)? There must
> be a way of setting which clock(s) should not be considered when calculating
> best choice for particular device.

Have the machine driver tell the clock API about this - that's what I
was suggesting originally before I realised there was the mux managment
logic in there.

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[jassi brar]

On Thu, Nov 19, 2009 at 9:09 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Hello,
>
> On Thursday, November 19, 2009 12:49 PM Mark Brown wrote:
>
>> On Thu, Nov 19, 2009 at 11:38:41AM +0000, Russell King - ARM Linux wrote:
>>
>> > I'm not sure what you're commenting on precisely, but the Samsung code as
>> > a whole doesn't use the clk API very well, and I suspect that is starting
>> > to cause people to have to pass clock names around.
>>
>> That's what I'd thought originally but it's not quite the problem here.
>> The issue is that Samsung serial port clock is chosen from a mux and the
>> logic to select which of the inputs to that mux should be used is in the
>> serial driver. ?This means that if the set of parent clocks changes then
>> the serial driver needs to be told what they are.
>>
>> My suggestion was to push this logic down into the clock API so the
>> serial driver just requests a rate and then clock API picks the best
>> option from the mux. ?As well as being nicer from the clock API point of
>> view this would also allow other drivers to use the same logic since
>> these muxes are a standard idiom for Samsung SoCs.
>
> What if a device does not operate properly when clocked from one of the
> available clock sources (lets say machine specific problem)? There must
> be a way of setting which clock(s) should not be considered when calculating
> best choice for particular device.
That shudn't be a concern. for example, if some machine doesn't provide clock
at some PAD, which could be used as a source, then the clock API wud read the
clock as 0 and the calculations wudn't pick that source up. Likewise, any such
'unusable' clock in the machine wud be marked by having invalid(0) rates.
The problem is moving this uart-mux into the the Clock API.

[PATCH 14/19] ARM: S5PC1XX: add support for s5pc110 gpio

[Marek Szyprowski]

Hello,

On Wednesday, November 18, 2009 11:06 PM Ben Dooks wrote:

> On Wed, Nov 18, 2009 at 02:33:09PM +0100, Marek Szyprowski wrote:
> > From: Kyungmin Park <kyungmin.park@samsung.com>
> >
> > Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
> > on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
> > This patch adds gpiolib support for S5PC110 sub-platform.
> 
> Hmm, another file with Byungho Min <bhmin@samsung.com> in and no signoff
> from this person.

Ok, we will handle this better next time.

> [...]

> > diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c
> > index 60bf31d..2cd095c 100644
> > --- a/arch/arm/plat-s5pc1xx/gpiolib.c
> > +++ b/arch/arm/plat-s5pc1xx/gpiolib.c
> > @@ -453,6 +453,272 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
> >  #define s5pc1xx_gpio_chips s5pc100_gpio_chips
> >
> >  #endif
> > +
> > +#ifdef CONFIG_CPU_S5PC110
> 
> this amount of #ifdef screams seperate file.
> 

> [...]

> > +	}, {
> > +		.base	= S5PC110_MP0_5_BASE,
> > +		.config	= &gpio_cfg,
> > +		.chip	= {
> > +			.base	= S5PC110_MP0_5(0),
> > +			.ngpio	= S5PC110_GPIO_MP0_5_NR,
> > +			.label	= "MP0_5",
> > +		},
> > +	},
> > +};
> > +
> > +#define s5pc1xx_gpio_chips s5pc110_gpio_chips
> > +
> > +#endif
> > +
> >  /* FIXME move from irq-gpio.c */
> >  extern struct irq_chip s5pc1xx_gpioint;
> >  extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
> > diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/plat-s5pc1xx/irq-gpio.c
> > index f5d8dab..b13308f 100644
> > --- a/arch/arm/plat-s5pc1xx/irq-gpio.c
> > +++ b/arch/arm/plat-s5pc1xx/irq-gpio.c
> > @@ -142,6 +142,116 @@ static int s5pc100_group_end = 21;
> >
> >  #endif
> >
> > +#ifdef CONFIG_CPU_S5PC110
> 
> these follwing functions could have had their info added to an extended
> gpio structure, say struct s5p_gpio_chip and had a s3c_gpio_chip embededded in
> it, which would make the code simpler,
> 
> ie:
> 
> struct s5p_gpio_chip {
>        struct s3c_gpio_chip chip;
>        unsigned int 	    gpio_start;
>        unsigned int 	    gpio_groupl
> };
> 
> and then you could have gone chip->info easily.
 
Thanks for suggestion! I will rewrite this and split gpio lib support into
separate files for each sub-platform and send new patches soon.

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center

[PATCH v2] Add Samsung S5PC110 SoC support

[Marek Szyprowski]

Hello,

This preliminary patch series adds support for Samsung S5PC110 SoC.
S5PC110 belongs to S5PC1XX family (CortexA8 ARM core), but differs in
many places from the S5PC100 SoC: new memory map, different clock
hierarchy, new gpio banks and much more powerful integrated peripherals.
Such differences cannot be easily handled in the current Samsung
machine&platform framework. To avoid duplication of code and adding yet
another plat-* directory, we decided to introduce sub-platforms in
the current s5pc1xx platform.

First 8 patches prepare s5pc1xx platform code for introduction of the
new sub-platform approach. Then in the next 11 patches all core
functions and drivers are subsequently added, so S5PC110 sub-platform
gets similar level of support as S5PC100. The last patch updated
MAINTAINERS information.

This patch series has been prepared against latest ARM Kernel tree from
http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm.git/

This is the second version of this patch series. The following issues
reported by Ben have been fixed: gpiolib support has been rewriten, more
SoC specific files have been moved to mach-s5pc* directories (gpio chip,
plls and clocks definitions). Also author/sender issues are resolved.

The clock issue in S5PC110 driver has not been addressed. The driver
uses clock API in the same way as it is handled in other Samsung UART
drivers. This clock issue should be resolved in a separate patch which
would fix all Samsung drivers at once. Until then we would like to use
the current approach.

This patch series includes:

[PATCH 01/20] ARM: S5PC100: use 0x30008000 as memory base
[PATCH 02/20] ARM: S5PC1XX: create sub-platform for S5PC100 SoCs
[PATCH 03/20] ARM: S5PC1XX: prepare common cpu&clocks code for S5PC110 sub-platform
[PATCH 04/20] ARM: S5PC1XX: prepare common gpiolib code for S5PC110 sub-platform
[PATCH 05/20] ARM: S5PC1XX: move common s5pc1xx mach/* includes to plat-s5pc1xx/include/mach
[PATCH 06/20] ARM: S5PC1XX: cleanup of s5pc1xx common code
[PATCH 07/20] ARM: S5PC1XX: move s5pc100 specific device helpers to mach-s5pc100 dir
[PATCH 08/20] ARM: S5PC1XX: move common s5pc1xx s3c-fb regs to platform directory
[PATCH 09/20] drivers: serial: add support for Samsung S5PC110 SoC uart
[PATCH 10/20] ARM: S5PC1XX: add S5PC110 memory map
[PATCH 11/20] ARM: S5PC1XX: add S5PC110 cpu initialization code
[PATCH 12/20] ARM: S5PC1XX: add support for s5pc110 plls and clocks
[PATCH 13/20] ARM: S5PC1XX: add support for s5pc110 irqs
[PATCH 14/20] ARM: S5PC1XX: add support for s5pc110 gpio
[PATCH 15/20] ARM: S5PC1XX: add i2c platform helpers on s5pc110 sub-platform
[PATCH 16/20] ARM: S5PC1XX: enable S5PC110 sub-platform
[PATCH 17/20] ARM: S5PC1XX: add sdhci platform helpers for s5pc110 sub-platform
[PATCH 18/20] ARM: S5PC1XX: add framebuffer platform helpers for s5pc110 sub-platform
[PATCH 19/20] ARM: S5PC1XX: add support for SMDKC110 board
[PATCH 20/20] MAINTAINERS: add ARM/S5PC100 and ARM/S5PC110 architectures

[PATCH 01/20] ARM: S5PC100: use 0x30008000 as memory base

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

We decided to use 0x3000'0000 as base memory address on S5PC1XX SoCs
(s5pc100 and s5pc110).
A patch to u-boot that configures SMDKC100 board and sets base memory
as 0x3000'0000 has been already posted.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/mach-s5pc100/Makefile.boot         |    4 ++--
 arch/arm/mach-s5pc100/include/mach/map.h    |    2 +-
 arch/arm/mach-s5pc100/include/mach/memory.h |    2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-s5pc100/Makefile.boot b/arch/arm/mach-s5pc100/Makefile.boot
index ff90aa1..b0909e3 100644
--- a/arch/arm/mach-s5pc100/Makefile.boot
+++ b/arch/arm/mach-s5pc100/Makefile.boot
@@ -1,2 +1,2 @@
-   zreladdr-y	:= 0x20008000
-params_phys-y	:= 0x20000100
+   zreladdr-y	:= 0x30008000
+params_phys-y	:= 0x30000100
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 4681ebe..f90c033 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -113,7 +113,7 @@
 #define S5PC100_PA_TSADC	(0xF3000000)
 
 /* ETC */
-#define S5PC100_PA_SDRAM	(0x20000000)
+#define S5PC100_PA_SDRAM	(0x30000000)
 #define S5PC1XX_PA_SDRAM	S5PC100_PA_SDRAM
 
 /* compatibility defines. */
diff --git a/arch/arm/mach-s5pc100/include/mach/memory.h b/arch/arm/mach-s5pc100/include/mach/memory.h
index 4b60d18..21cc182 100644
--- a/arch/arm/mach-s5pc100/include/mach/memory.h
+++ b/arch/arm/mach-s5pc100/include/mach/memory.h
@@ -13,6 +13,6 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
 
-#define PHYS_OFFSET     	UL(0x20000000)
+#define PHYS_OFFSET     	UL(0x30000000)
 
 #endif
-- 
1.6.4

[PATCH 02/20] ARM: S5PC1XX: create sub-platform for S5PC100 SoCs

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC100 and S5PC110 SoCs differs a lot in register map and other
core platform definitions, so it is not possible to have both SoCs in
the current platform framework without runtime hacks. To address this
issue a sub-platform has been introduced, so each SoC in sub-platform
can have its own set of include files (register map, irq&gpio
definitions, etc)

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/Makefile             |    2 +-
 arch/arm/mach-s5pc100/Kconfig |    4 ++++
 arch/arm/plat-s5pc1xx/Kconfig |   10 ++++++++++
 3 files changed, 15 insertions(+), 1 deletions(-)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a73caaf..daea150 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -160,7 +160,7 @@ machine-$(CONFIG_ARCH_RPC)		:= rpc
 machine-$(CONFIG_ARCH_S3C2410)		:= s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
 machine-$(CONFIG_ARCH_S3C24A0)		:= s3c24a0
 machine-$(CONFIG_ARCH_S3C64XX)		:= s3c6400 s3c6410
-machine-$(CONFIG_ARCH_S5PC1XX)		:= s5pc100
+machine-$(CONFIG_ARCH_S5PC100)		:= s5pc100
 machine-$(CONFIG_ARCH_SA1100)		:= sa1100
 machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_STMP378X)		:= stmp378x
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 0dd2b8c..d72f881 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -5,6 +5,8 @@
 #
 # Licensed under GPLv2
 
+if ARCH_S5PC100
+
 # Configuration options for the S5PC100 CPU
 
 config CPU_S5PC100
@@ -34,3 +36,5 @@ config MACH_SMDKC100
 	select S5PC100_SETUP_SDHCI
 	help
 	  Machine support for the Samsung SMDKC100
+
+endif
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index 1608e62..eee2abb 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -23,6 +23,16 @@ config PLAT_S5PC1XX
 
 if PLAT_S5PC1XX
 
+choice
+	prompt "S5PC1xx SoC Type"
+	default ARCH_S5PC100
+
+config ARCH_S5PC100
+	bool "S5PC100"
+
+endchoice
+
+
 # Configuration options shared by all S3C64XX implementations
 
 config CPU_S5PC100_INIT
-- 
1.6.4

[PATCH 03/20] ARM: S5PC1XX: prepare common cpu&clocks code for S5PC110 sub-platform

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

CLK_OTHER register block is specific for S5PC100 SoC, so move the
definition to mach-s5pc100/cpu.c. Size of CLK and PWR register block is
different on S5PC100 and S5PC110, thus new defines are introduced.

Clock and pll hierarchy is completely different between S5PC100 and
S5PC110 SoCs, so move related includes to new sub-platform and rename
plat-s5pc1xx/clocks.c and plat-s5pc1xx/s5pc100-clock.c to
s5pc100-clocks.c (periperal clocks definition) and s5pc100-plls.c (core
pll hierarchy definition).

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/mach-s5pc100/Kconfig                      |    2 --
 arch/arm/mach-s5pc100/Makefile                     |    3 +++
 .../clock.c => mach-s5pc100/clocks.c}              |    4 ++--
 arch/arm/mach-s5pc100/cpu.c                        |    6 ++++++
 arch/arm/mach-s5pc100/include/mach/map.h           |    2 ++
 .../include/plat/regs-clock.h                      |    2 +-
 .../include/plat/regs-power.h                      |    2 +-
 .../s5pc100-clock.c => mach-s5pc100/plls.c}        |    2 +-
 .../s5pc100-init.c => mach-s5pc100/uarts.c}        |    2 +-
 arch/arm/plat-s5pc1xx/Kconfig                      |   12 +-----------
 arch/arm/plat-s5pc1xx/Makefile                     |    4 ----
 arch/arm/plat-s5pc1xx/cpu.c                        |   18 ++++++------------
 12 files changed, 24 insertions(+), 35 deletions(-)
 rename arch/arm/{plat-s5pc1xx/clock.c => mach-s5pc100/clocks.c} (99%)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/include/plat/regs-clock.h (99%)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/include/plat/regs-power.h (98%)
 rename arch/arm/{plat-s5pc1xx/s5pc100-clock.c => mach-s5pc100/plls.c} (99%)
 rename arch/arm/{plat-s5pc1xx/s5pc100-init.c => mach-s5pc100/uarts.c} (94%)

diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index d72f881..1dbb5f1 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -11,8 +11,6 @@ if ARCH_S5PC100
 
 config CPU_S5PC100
 	bool
-	select CPU_S5PC100_INIT
-	select CPU_S5PC100_CLOCK
 	help
 	  Enable S5PC100 CPU support
 
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 809ff10..dc6b0ff 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -12,6 +12,9 @@ obj-				:=
 # Core support for S5PC100 system
 
 obj-$(CONFIG_CPU_S5PC100)	+= cpu.o
+obj-$(CONFIG_CPU_S5PC100)	+= clocks.o
+obj-$(CONFIG_CPU_S5PC100)	+= plls.o
+obj-$(CONFIG_CPU_S5PC100)	+= uarts.o
 
 # Helper and device support
 
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/mach-s5pc100/clocks.c
similarity index 99%
rename from arch/arm/plat-s5pc1xx/clock.c
rename to arch/arm/mach-s5pc100/clocks.c
index 26c21d8..a191beb 100644
--- a/arch/arm/plat-s5pc1xx/clock.c
+++ b/arch/arm/mach-s5pc100/clocks.c
@@ -1,8 +1,8 @@
-/* linux/arch/arm/plat-s5pc1xx/clock.c
+/* linux/arch/arm/mach-s5pc100/clocks.c
  *
  * Copyright 2009 Samsung Electronics Co.
  *
- * S5PC1XX Base clock support
+ * S5PC100 - Clocks support
  *
  * Based on plat-s3c64xx/clock.c
  *
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index d79e757..41fdecf 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -46,6 +46,12 @@
 /* Initial IO mappings */
 
 static struct map_desc s5pc100_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5PC1XX_VA_CLK_OTHER,
+		.pfn		= __phys_to_pfn(S5PC1XX_PA_CLK_OTHER),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}
 };
 
 static void s5pc100_idle(void)
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index f90c033..88f267a 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -46,6 +46,8 @@
 #define S5PC1XX_VA_CLK		(S3C_VA_SYS + 0x10000)
 #define S5PC1XX_VA_PWR		(S3C_VA_SYS + 0x20000)
 #define S5PC1XX_VA_CLK_OTHER	(S3C_VA_SYS + 0x30000)
+#define S5PC1XX_SZ_CLK		SZ_4K
+#define S5PC1XX_SZ_PWR		SZ_4K
 
 /* GPIO */
 #define S5PC100_PA_GPIO		(0xE0300000)
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/mach-s5pc100/include/plat/regs-clock.h
similarity index 99%
rename from arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
rename to arch/arm/mach-s5pc100/include/plat/regs-clock.h
index c5cc86e..f0a007b 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+++ b/arch/arm/mach-s5pc100/include/plat/regs-clock.h
@@ -3,7 +3,7 @@
  * Copyright 2009 Samsung Electronics Co.
  *	Byungho Min <bhmin@samsung.com>
  *
- * S5PC1XX clock register definitions
+ * S5PC100 clock register definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h b/arch/arm/mach-s5pc100/include/plat/regs-power.h
similarity index 98%
rename from arch/arm/plat-s5pc1xx/include/plat/regs-power.h
rename to arch/arm/mach-s5pc100/include/plat/regs-power.h
index 02ffa49..50a9679 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h
+++ b/arch/arm/mach-s5pc100/include/plat/regs-power.h
@@ -3,7 +3,7 @@
  * Copyright 2009 Samsung Electronics Co.
  *	Jongse Won <jongse.won@samsung.com>
  *
- * S5PC1XX clock register definitions
+ * S5PC100 power controll register definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/mach-s5pc100/plls.c
similarity index 99%
rename from arch/arm/plat-s5pc1xx/s5pc100-clock.c
rename to arch/arm/mach-s5pc100/plls.c
index b436d44..cd3f6a7 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+++ b/arch/arm/mach-s5pc100/plls.c
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+/* linux/arch/arm/mach-s5pc100/s5pc100-plls.c
  *
  * Copyright 2009 Samsung Electronics, Co.
  *	Byungho Min <bhmin@samsung.com>
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-init.c b/arch/arm/mach-s5pc100/uarts.c
similarity index 94%
rename from arch/arm/plat-s5pc1xx/s5pc100-init.c
rename to arch/arm/mach-s5pc100/uarts.c
index c587108..32972f2 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-init.c
+++ b/arch/arm/mach-s5pc100/uarts.c
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5pc1xx/s5pc100-init.c
+/* linux/arch/arm/mach-s5pc100/uarts.c
  *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index eee2abb..7131ce9 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -33,17 +33,7 @@ config ARCH_S5PC100
 endchoice
 
 
-# Configuration options shared by all S3C64XX implementations
-
-config CPU_S5PC100_INIT
-	bool
-	help
-	  Common initialisation code for the S5PC1XX
-
-config CPU_S5PC100_CLOCK
-	bool
-	help
-	  Common clock support code for the S5PC1XX
+# configuration options shared by all S5PC1XX implementations
 
 # platform specific device setup
 
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
index 278f268..39dd0a1 100644
--- a/arch/arm/plat-s5pc1xx/Makefile
+++ b/arch/arm/plat-s5pc1xx/Makefile
@@ -14,14 +14,10 @@ obj-				:=
 obj-y				+= dev-uart.o
 obj-y				+= cpu.o
 obj-y				+= irq.o irq-gpio.o irq-eint.o
-obj-y				+= clock.o
 obj-y				+= gpiolib.o
 
 # CPU support
 
-obj-$(CONFIG_CPU_S5PC100_INIT)	+= s5pc100-init.o
-obj-$(CONFIG_CPU_S5PC100_CLOCK)	+= s5pc100-clock.o
-
 # Device setup
 
 obj-$(CONFIG_S5P_GPIO_CFG_S5PC1XX) += gpio-config.o
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c
index 02baeaa..ecd6d38 100644
--- a/arch/arm/plat-s5pc1xx/cpu.c
+++ b/arch/arm/plat-s5pc1xx/cpu.c
@@ -50,18 +50,11 @@ static struct cpu_table cpu_ids[] __initdata = {
 };
 /* minimal IO mapping */
 
-/* see notes on uart map in arch/arm/mach-s5pc100/include/mach/debug-macro.S */
-#define UART_OFFS (S3C_PA_UART & 0xffff)
 
 static struct map_desc s5pc1xx_iodesc[] __initdata = {
 	{
-		.virtual	= (unsigned long)S5PC1XX_VA_CLK_OTHER,
-		.pfn		= __phys_to_pfn(S5PC1XX_PA_CLK_OTHER),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE,
-	}, {
 		.virtual	= (unsigned long)S5PC1XX_VA_GPIO,
-		.pfn		= __phys_to_pfn(S5PC100_PA_GPIO),
+		.pfn		= __phys_to_pfn(S5PC1XX_PA_GPIO),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
 	}, {
@@ -72,15 +65,15 @@ static struct map_desc s5pc1xx_iodesc[] __initdata = {
 	}, {
 		.virtual	= (unsigned long)S5PC1XX_VA_CLK,
 		.pfn		= __phys_to_pfn(S5PC1XX_PA_CLK),
-		.length		= SZ_4K,
+		.length		= S5PC1XX_SZ_CLK,
 		.type		= MT_DEVICE,
 	}, {
 		.virtual	= (unsigned long)S5PC1XX_VA_PWR,
 		.pfn		= __phys_to_pfn(S5PC1XX_PA_PWR),
-		.length		= SZ_4K,
+		.length		= S5PC1XX_SZ_PWR,
 		.type		= MT_DEVICE,
 	}, {
-		.virtual	= (unsigned long)(S5PC1XX_VA_UART),
+		.virtual	= (unsigned long)S5PC1XX_VA_UART,
 		.pfn		= __phys_to_pfn(S5PC1XX_PA_UART),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
@@ -115,8 +108,9 @@ void __init s5pc1xx_init_io(struct map_desc *mach_desc, int size)
 
 	/* initialise the io descriptors we need for initialisation */
 	iotable_init(s5pc1xx_iodesc, ARRAY_SIZE(s5pc1xx_iodesc));
-	iotable_init(mach_desc, size);
 
 	idcode = __raw_readl(S5PC1XX_VA_CHIPID);
 	s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
+
+	iotable_init(mach_desc, size);
 }
-- 
1.6.4

[PATCH 04/20] ARM: S5PC1XX: prepare common gpiolib code for S5PC110 sub-platform

[Marek Szyprowski]

S5PC100 GPIOlib support has been rewriten to make it possible to reuse
most of the common code in the upcoming S5PC110 sub-platform.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-s5pc100/Makefile                     |    1 +
 arch/arm/mach-s5pc100/gpio-chips.c                 |  106 ++++++
 arch/arm/mach-s5pc100/include/mach/gpio.h          |   46 +++
 .../include/plat/irqs.h                            |    2 +-
 .../include/plat/regs-gpio.h                       |    2 +-
 arch/arm/plat-s5pc1xx/gpiolib.c                    |  374 ++------------------
 arch/arm/plat-s5pc1xx/include/plat/gpio-s5pc1xx.h  |   79 ++++
 arch/arm/plat-s5pc1xx/irq-eint.c                   |   13 +-
 arch/arm/plat-s5pc1xx/irq-gpio.c                   |  105 +-----
 9 files changed, 292 insertions(+), 436 deletions(-)
 create mode 100644 arch/arm/mach-s5pc100/gpio-chips.c
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/include/plat/irqs.h (99%)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/include/plat/regs-gpio.h (98%)
 create mode 100644 arch/arm/plat-s5pc1xx/include/plat/gpio-s5pc1xx.h

diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index dc6b0ff..8d29ea1 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -13,6 +13,7 @@ obj-				:=
 
 obj-$(CONFIG_CPU_S5PC100)	+= cpu.o
 obj-$(CONFIG_CPU_S5PC100)	+= clocks.o
+obj-$(CONFIG_CPU_S5PC100)	+= gpio-chips.o
 obj-$(CONFIG_CPU_S5PC100)	+= plls.o
 obj-$(CONFIG_CPU_S5PC100)	+= uarts.o
 
diff --git a/arch/arm/mach-s5pc100/gpio-chips.c b/arch/arm/mach-s5pc100/gpio-chips.c
new file mode 100644
index 0000000..f8fa8d7
--- /dev/null
+++ b/arch/arm/mach-s5pc100/gpio-chips.c
@@ -0,0 +1,106 @@
+/*
+ * linux/arch/arm/mach-s5pc100/gpio-chips.c
+ *
+ *  Copyright 2009 Samsung Electronics Co
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *  Marek Szyprowski <m.szyprowski@samsung.com>
+ *
+ * S5PC100 - GPIOlib chip definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+#include <mach/gpio-core.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+#include <plat/gpio-s5pc1xx.h>
+#include <plat/regs-gpio.h>
+
+/* S5PC100 GPIO bank summary:
+ *
+ * Bank	GPIOs	Style	INT Type
+ * A0	8	4Bit	GPIO_INT0
+ * A1	5	4Bit	GPIO_INT1
+ * B	8	4Bit	GPIO_INT2
+ * C	5	4Bit	GPIO_INT3
+ * D	7	4Bit	GPIO_INT4
+ * E0	8	4Bit	GPIO_INT5
+ * E1	6	4Bit	GPIO_INT6
+ * F0	8	4Bit	GPIO_INT7
+ * F1	8	4Bit	GPIO_INT8
+ * F2	8	4Bit	GPIO_INT9
+ * F3	4	4Bit	GPIO_INT10
+ * G0	8	4Bit	GPIO_INT11
+ * G1	3	4Bit	GPIO_INT12
+ * G2	7	4Bit	GPIO_INT13
+ * G3	7	4Bit	GPIO_INT14
+ * H0	8	4Bit	WKUP_INT
+ * H1	8	4Bit	WKUP_INT
+ * H2	8	4Bit	WKUP_INT
+ * H3	8	4Bit	WKUP_INT
+ * I	8	4Bit	GPIO_INT15
+ * J0	8	4Bit	GPIO_INT16
+ * J1	5	4Bit	GPIO_INT17
+ * J2	8	4Bit	GPIO_INT18
+ * J3	8	4Bit	GPIO_INT19
+ * J4	4	4Bit	GPIO_INT20
+ * K0	8	4Bit	None
+ * K1	6	4Bit	None
+ * K2	8	4Bit	None
+ * K3	8	4Bit	None
+ * L0	8	4Bit	None
+ * L1	8	4Bit	None
+ * L2	8	4Bit	None
+ * L3	8	4Bit	None
+ */
+
+static struct s5pc1xx_gpio_chip s5pc100_gpio_chips[] = {
+	S5PC1XX_INT_CHIP_DEF(S5PC100, A0),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, A1),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, B),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, C),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, D),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, E0),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, E1),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, F0),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, F1),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, F2),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, F3),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, G0),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, G1),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, G2),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, G3),
+	S5PC1XX_EINT_CHIP_DEF(S5PC100, H0),
+	S5PC1XX_EINT_CHIP_DEF(S5PC100, H1),
+	S5PC1XX_EINT_CHIP_DEF(S5PC100, H2),
+	S5PC1XX_EINT_CHIP_DEF(S5PC100, H3),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, I),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, J0),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, J1),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, J2),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, J3),
+	S5PC1XX_INT_CHIP_DEF(S5PC100, J4),
+	S5PC1XX_NOINT_CHIP_DEF(S5PC100, K0),
+	S5PC1XX_NOINT_CHIP_DEF(S5PC100, K1),
+	S5PC1XX_NOINT_CHIP_DEF(S5PC100, K2),
+	S5PC1XX_NOINT_CHIP_DEF(S5PC100, K3),
+	S5PC1XX_NOINT_CHIP_DEF(S5PC100, L0),
+	S5PC1XX_NOINT_CHIP_DEF(S5PC100, L1),
+	S5PC1XX_NOINT_CHIP_DEF(S5PC100, L2),
+	S5PC1XX_NOINT_CHIP_DEF(S5PC100, L3),
+	S5PC1XX_NOINT_CHIP_DEF(S5PC100, L4),
+};
+
+struct s5pc1xx_gpio s5pc1xx_gpio_chips = {
+	.chips = s5pc100_gpio_chips,
+	.count = ARRAY_SIZE(s5pc100_gpio_chips),
+};
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index 2c4cbe8..3142c40 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -159,4 +159,50 @@ enum s3c_gpio_number {
 /* define the number of gpios we need to the one after the MP04() range */
 #define ARCH_NR_GPIOS		(S5PC100_GPIO_END + 1)
 
+/* Offset of the bank in the interrupt group registers */
+#define S5PC100_GPIO_A0_INT_GROUP	(0)
+#define S5PC100_GPIO_A1_INT_GROUP	(1)
+#define S5PC100_GPIO_B_INT_GROUP	(2)
+#define S5PC100_GPIO_C_INT_GROUP	(3)
+#define S5PC100_GPIO_D_INT_GROUP	(4)
+#define S5PC100_GPIO_E0_INT_GROUP	(5)
+#define S5PC100_GPIO_E1_INT_GROUP	(6)
+#define S5PC100_GPIO_F0_INT_GROUP	(7)
+#define S5PC100_GPIO_F1_INT_GROUP	(8)
+#define S5PC100_GPIO_F2_INT_GROUP	(9)
+#define S5PC100_GPIO_F3_INT_GROUP	(10)
+#define S5PC100_GPIO_G0_INT_GROUP	(11)
+#define S5PC100_GPIO_G1_INT_GROUP	(12)
+#define S5PC100_GPIO_G2_INT_GROUP	(13)
+#define S5PC100_GPIO_G3_INT_GROUP	(14)
+#define S5PC100_GPIO_I_INT_GROUP	(15)
+#define S5PC100_GPIO_J0_INT_GROUP	(16)
+#define S5PC100_GPIO_J1_INT_GROUP	(17)
+#define S5PC100_GPIO_J2_INT_GROUP	(18)
+#define S5PC100_GPIO_J3_INT_GROUP	(19)
+#define S5PC100_GPIO_J4_INT_GROUP	(20)
+#define S5PC100_GPIO_H0_INT_GROUP	(-1)
+#define S5PC100_GPIO_H1_INT_GROUP	(-1)
+#define S5PC100_GPIO_H2_INT_GROUP	(-1)
+#define S5PC100_GPIO_H3_INT_GROUP	(-1)
+#define S5PC100_GPIO_K0_INT_GROUP	(-1)
+#define S5PC100_GPIO_K1_INT_GROUP	(-1)
+#define S5PC100_GPIO_K2_INT_GROUP	(-1)
+#define S5PC100_GPIO_K3_INT_GROUP	(-1)
+#define S5PC100_GPIO_L0_INT_GROUP	(-1)
+#define S5PC100_GPIO_L1_INT_GROUP	(-1)
+#define S5PC100_GPIO_L2_INT_GROUP	(-1)
+#define S5PC100_GPIO_L3_INT_GROUP	(-1)
+#define S5PC100_GPIO_L4_INT_GROUP	(-1)
+
+#define S5PC100_GPIO_INT_GROUP_END	(S5PC100_GPIO_J4_INT_GROUP + 1)
+
+/* Common compatibility defines */
+#define S5PC1XX_GPIO_EINT_SFN	S3C_GPIO_SFN(0x2)
+#define S5PC1XX_GPH0(n)		S5PC100_GPH0(n)
+#define S5PC1XX_GPH1(n)		S5PC100_GPH1(n)
+#define S5PC1XX_GPH2(n)		S5PC100_GPH2(n)
+#define S5PC1XX_GPH3(n)		S5PC100_GPH3(n)
+#define S5PC1XX_GPIO_INT_GROUP_END	S5PC100_GPIO_INT_GROUP_END
+
 #include <asm-generic/gpio.h>
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/mach-s5pc100/include/plat/irqs.h
similarity index 99%
rename from arch/arm/plat-s5pc1xx/include/plat/irqs.h
rename to arch/arm/mach-s5pc100/include/plat/irqs.h
index ef87363..e34e2ef 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h
+++ b/arch/arm/mach-s5pc100/include/plat/irqs.h
@@ -3,7 +3,7 @@
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
- * S5PC1XX - Common IRQ support
+ * S5PC100 - Common IRQ support
  *
  * Based on plat-s3c64xx/include/plat/irqs.h
  */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h b/arch/arm/mach-s5pc100/include/plat/regs-gpio.h
similarity index 98%
rename from arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
rename to arch/arm/mach-s5pc100/include/plat/regs-gpio.h
index 43c7bc8..87e1884 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
+++ b/arch/arm/mach-s5pc100/include/plat/regs-gpio.h
@@ -3,7 +3,7 @@
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
- * S5PC1XX - GPIO register definitions
+ * S5PC100 - GPIO register definitions
  */
 
 #ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H
diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c
index facb410..e0eb8e3 100644
--- a/arch/arm/plat-s5pc1xx/gpiolib.c
+++ b/arch/arm/plat-s5pc1xx/gpiolib.c
@@ -3,6 +3,7 @@
  *
  *  Copyright 2009 Samsung Electronics Co
  *  Kyungmin Park <kyungmin.park@samsung.com>
+ *  Marek Szyprowski <m.szyprowski@samsung.com>
  *
  * S5PC1XX - GPIOlib support
  *
@@ -21,46 +22,9 @@
 
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
+#include <plat/gpio-s5pc1xx.h>
 #include <plat/regs-gpio.h>
 
-/* S5PC100 GPIO bank summary:
- *
- * Bank	GPIOs	Style	INT Type
- * A0	8	4Bit	GPIO_INT0
- * A1	5	4Bit	GPIO_INT1
- * B	8	4Bit	GPIO_INT2
- * C	5	4Bit	GPIO_INT3
- * D	7	4Bit	GPIO_INT4
- * E0	8	4Bit	GPIO_INT5
- * E1	6	4Bit	GPIO_INT6
- * F0	8	4Bit	GPIO_INT7
- * F1	8	4Bit	GPIO_INT8
- * F2	8	4Bit	GPIO_INT9
- * F3	4	4Bit	GPIO_INT10
- * G0	8	4Bit	GPIO_INT11
- * G1	3	4Bit	GPIO_INT12
- * G2	7	4Bit	GPIO_INT13
- * G3	7	4Bit	GPIO_INT14
- * H0	8	4Bit	WKUP_INT
- * H1	8	4Bit	WKUP_INT
- * H2	8	4Bit	WKUP_INT
- * H3	8	4Bit	WKUP_INT
- * I	8	4Bit	GPIO_INT15
- * J0	8	4Bit	GPIO_INT16
- * J1	5	4Bit	GPIO_INT17
- * J2	8	4Bit	GPIO_INT18
- * J3	8	4Bit	GPIO_INT19
- * J4	4	4Bit	GPIO_INT20
- * K0	8	4Bit	None
- * K1	6	4Bit	None
- * K2	8	4Bit	None
- * K3	8	4Bit	None
- * L0	8	4Bit	None
- * L1	8	4Bit	None
- * L2	8	4Bit	None
- * L3	8	4Bit	None
- */
-
 #define OFF_GPCON	(0x00)
 #define OFF_GPDAT	(0x04)
 
@@ -138,328 +102,50 @@ static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
 {
 	int base;
 
-	base = chip->base - S5PC100_GPH0(0);
+	base = chip->base - S5PC1XX_GPH0(0);
 	if (base == 0)
 		return IRQ_EINT(offset);
-	base = chip->base - S5PC100_GPH1(0);
+	base = chip->base - S5PC1XX_GPH1(0);
 	if (base == 0)
 		return IRQ_EINT(8 + offset);
-	base = chip->base - S5PC100_GPH2(0);
+	base = chip->base - S5PC1XX_GPH2(0);
 	if (base == 0)
 		return IRQ_EINT(16 + offset);
-	base = chip->base - S5PC100_GPH3(0);
+	base = chip->base - S5PC1XX_GPH3(0);
 	if (base == 0)
 		return IRQ_EINT(24 + offset);
+
 	return -EINVAL;
 }
 
-static struct s3c_gpio_cfg gpio_cfg = {
+struct s3c_gpio_cfg s5pc1xx_gpio_cfg = {
 	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
 	.set_pull	= s3c_gpio_setpull_updown,
 	.get_pull	= s3c_gpio_getpull_updown,
 };
 
-static struct s3c_gpio_cfg gpio_cfg_eint = {
+struct s3c_gpio_cfg s5pc1xx_gpio_cfg_eint = {
 	.cfg_eint	= 0xf,
 	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
 	.set_pull	= s3c_gpio_setpull_updown,
 	.get_pull	= s3c_gpio_getpull_updown,
 };
 
-static struct s3c_gpio_cfg gpio_cfg_noint = {
+struct s3c_gpio_cfg s5pc1xx_gpio_cfg_noint = {
 	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
 	.set_pull	= s3c_gpio_setpull_updown,
 	.get_pull	= s3c_gpio_getpull_updown,
 };
 
-static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
-	{
-		.base	= S5PC100_GPA0_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPA0(0),
-			.ngpio	= S5PC100_GPIO_A0_NR,
-			.label	= "GPA0",
-		},
-	}, {
-		.base	= S5PC100_GPA1_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPA1(0),
-			.ngpio	= S5PC100_GPIO_A1_NR,
-			.label	= "GPA1",
-		},
-	}, {
-		.base	= S5PC100_GPB_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPB(0),
-			.ngpio	= S5PC100_GPIO_B_NR,
-			.label	= "GPB",
-		},
-	}, {
-		.base	= S5PC100_GPC_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPC(0),
-			.ngpio	= S5PC100_GPIO_C_NR,
-			.label	= "GPC",
-		},
-	}, {
-		.base	= S5PC100_GPD_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPD(0),
-			.ngpio	= S5PC100_GPIO_D_NR,
-			.label	= "GPD",
-		},
-	}, {
-		.base	= S5PC100_GPE0_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPE0(0),
-			.ngpio	= S5PC100_GPIO_E0_NR,
-			.label	= "GPE0",
-		},
-	}, {
-		.base	= S5PC100_GPE1_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPE1(0),
-			.ngpio	= S5PC100_GPIO_E1_NR,
-			.label	= "GPE1",
-		},
-	}, {
-		.base	= S5PC100_GPF0_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPF0(0),
-			.ngpio	= S5PC100_GPIO_F0_NR,
-			.label	= "GPF0",
-		},
-	}, {
-		.base	= S5PC100_GPF1_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPF1(0),
-			.ngpio	= S5PC100_GPIO_F1_NR,
-			.label	= "GPF1",
-		},
-	}, {
-		.base	= S5PC100_GPF2_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPF2(0),
-			.ngpio	= S5PC100_GPIO_F2_NR,
-			.label	= "GPF2",
-		},
-	}, {
-		.base	= S5PC100_GPF3_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPF3(0),
-			.ngpio	= S5PC100_GPIO_F3_NR,
-			.label	= "GPF3",
-		},
-	}, {
-		.base	= S5PC100_GPG0_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPG0(0),
-			.ngpio	= S5PC100_GPIO_G0_NR,
-			.label	= "GPG0",
-		},
-	}, {
-		.base	= S5PC100_GPG1_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPG1(0),
-			.ngpio	= S5PC100_GPIO_G1_NR,
-			.label	= "GPG1",
-		},
-	}, {
-		.base	= S5PC100_GPG2_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPG2(0),
-			.ngpio	= S5PC100_GPIO_G2_NR,
-			.label	= "GPG2",
-		},
-	}, {
-		.base	= S5PC100_GPG3_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPG3(0),
-			.ngpio	= S5PC100_GPIO_G3_NR,
-			.label	= "GPG3",
-		},
-	}, {
-		.base	= S5PC100_GPH0_BASE,
-		.config	= &gpio_cfg_eint,
-		.chip	= {
-			.base	= S5PC100_GPH0(0),
-			.ngpio	= S5PC100_GPIO_H0_NR,
-			.label	= "GPH0",
-		},
-	}, {
-		.base	= S5PC100_GPH1_BASE,
-		.config	= &gpio_cfg_eint,
-		.chip	= {
-			.base	= S5PC100_GPH1(0),
-			.ngpio	= S5PC100_GPIO_H1_NR,
-			.label	= "GPH1",
-		},
-	}, {
-		.base	= S5PC100_GPH2_BASE,
-		.config	= &gpio_cfg_eint,
-		.chip	= {
-			.base	= S5PC100_GPH2(0),
-			.ngpio	= S5PC100_GPIO_H2_NR,
-			.label	= "GPH2",
-		},
-	}, {
-		.base	= S5PC100_GPH3_BASE,
-		.config	= &gpio_cfg_eint,
-		.chip	= {
-			.base	= S5PC100_GPH3(0),
-			.ngpio	= S5PC100_GPIO_H3_NR,
-			.label	= "GPH3",
-		},
-	}, {
-		.base	= S5PC100_GPI_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPI(0),
-			.ngpio	= S5PC100_GPIO_I_NR,
-			.label	= "GPI",
-		},
-	}, {
-		.base	= S5PC100_GPJ0_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPJ0(0),
-			.ngpio	= S5PC100_GPIO_J0_NR,
-			.label	= "GPJ0",
-		},
-	}, {
-		.base	= S5PC100_GPJ1_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPJ1(0),
-			.ngpio	= S5PC100_GPIO_J1_NR,
-			.label	= "GPJ1",
-		},
-	}, {
-		.base	= S5PC100_GPJ2_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPJ2(0),
-			.ngpio	= S5PC100_GPIO_J2_NR,
-			.label	= "GPJ2",
-		},
-	}, {
-		.base	= S5PC100_GPJ3_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPJ3(0),
-			.ngpio	= S5PC100_GPIO_J3_NR,
-			.label	= "GPJ3",
-		},
-	}, {
-		.base	= S5PC100_GPJ4_BASE,
-		.config	= &gpio_cfg,
-		.chip	= {
-			.base	= S5PC100_GPJ4(0),
-			.ngpio	= S5PC100_GPIO_J4_NR,
-			.label	= "GPJ4",
-		},
-	}, {
-		.base	= S5PC100_GPK0_BASE,
-		.config	= &gpio_cfg_noint,
-		.chip	= {
-			.base	= S5PC100_GPK0(0),
-			.ngpio	= S5PC100_GPIO_K0_NR,
-			.label	= "GPK0",
-		},
-	}, {
-		.base	= S5PC100_GPK1_BASE,
-		.config	= &gpio_cfg_noint,
-		.chip	= {
-			.base	= S5PC100_GPK1(0),
-			.ngpio	= S5PC100_GPIO_K1_NR,
-			.label	= "GPK1",
-		},
-	}, {
-		.base	= S5PC100_GPK2_BASE,
-		.config	= &gpio_cfg_noint,
-		.chip	= {
-			.base	= S5PC100_GPK2(0),
-			.ngpio	= S5PC100_GPIO_K2_NR,
-			.label	= "GPK2",
-		},
-	}, {
-		.base	= S5PC100_GPK3_BASE,
-		.config	= &gpio_cfg_noint,
-		.chip	= {
-			.base	= S5PC100_GPK3(0),
-			.ngpio	= S5PC100_GPIO_K3_NR,
-			.label	= "GPK3",
-		},
-	}, {
-		.base	= S5PC100_GPL0_BASE,
-		.config	= &gpio_cfg_noint,
-		.chip	= {
-			.base	= S5PC100_GPL0(0),
-			.ngpio	= S5PC100_GPIO_L0_NR,
-			.label	= "GPL0",
-		},
-	}, {
-		.base	= S5PC100_GPL1_BASE,
-		.config	= &gpio_cfg_noint,
-		.chip	= {
-			.base	= S5PC100_GPL1(0),
-			.ngpio	= S5PC100_GPIO_L1_NR,
-			.label	= "GPL1",
-		},
-	}, {
-		.base	= S5PC100_GPL2_BASE,
-		.config	= &gpio_cfg_noint,
-		.chip	= {
-			.base	= S5PC100_GPL2(0),
-			.ngpio	= S5PC100_GPIO_L2_NR,
-			.label	= "GPL2",
-		},
-	}, {
-		.base	= S5PC100_GPL3_BASE,
-		.config	= &gpio_cfg_noint,
-		.chip	= {
-			.base	= S5PC100_GPL3(0),
-			.ngpio	= S5PC100_GPIO_L3_NR,
-			.label	= "GPL3",
-		},
-	}, {
-		.base	= S5PC100_GPL4_BASE,
-		.config	= &gpio_cfg_noint,
-		.chip	= {
-			.base	= S5PC100_GPL4(0),
-			.ngpio	= S5PC100_GPIO_L4_NR,
-			.label	= "GPL4",
-		},
-	},
-};
-
-/* FIXME move from irq-gpio.c */
-extern struct irq_chip s5pc1xx_gpioint;
-extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
-
-static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip)
+static __init void s5pc1xx_gpiolib_link(struct s5pc1xx_gpio_chip *s5pc1xx_chip)
 {
+	struct s3c_gpio_chip *chip = &s5pc1xx_chip->chip;
 	chip->chip.direction_input = s5pc1xx_gpiolib_input;
 	chip->chip.direction_output = s5pc1xx_gpiolib_output;
 	chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
 
 	/* Interrupt */
-	if (chip->config == &gpio_cfg) {
+	if (chip->config == &s5pc1xx_gpio_cfg) {
 		int i, irq;
 
 		chip->chip.to_irq = s5pc1xx_gpiolib_to_irq;
@@ -471,31 +157,37 @@ static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip)
 			set_irq_handler(irq, handle_level_irq);
 			set_irq_flags(irq, IRQF_VALID);
 		}
-	} else if (chip->config == &gpio_cfg_eint)
+
+		if (s5pc1xx_chip->gpio_group >= 0 &&
+		    s5pc1xx_chip->gpio_group < S5PC1XX_GPIO_INT_GROUP_END)
+			s5pc1xx_gpioint_group_map[s5pc1xx_chip->gpio_group] =
+				s5pc1xx_chip->gpio_start;
+
+	} else if (chip->config == &s5pc1xx_gpio_cfg_eint)
 		chip->chip.to_irq = s5pc1xx_gpiolib_to_eint;
 }
 
-static __init void s5pc1xx_gpiolib_add(struct s3c_gpio_chip *chips,
-				       int nr_chips,
-				       void (*fn)(struct s3c_gpio_chip *))
+static __init void s5pc1xx_gpiolib_add(struct s5pc1xx_gpio *chips)
 {
-	for (; nr_chips > 0; nr_chips--, chips++) {
-		if (fn)
-			(fn)(chips);
-		s3c_gpiolib_add(chips);
+	struct s5pc1xx_gpio_chip *chip;
+	int i;
+
+	for (chip = chips->chips; i < chips->count; i++, chip++) {
+		s5pc1xx_gpiolib_link(chip);
+		s3c_gpiolib_add(&chip->chip);
 	}
 }
 
 static __init int s5pc1xx_gpiolib_init(void)
 {
-	struct s3c_gpio_chip *chips;
-	int nr_chips;
+	int i;
 
-		chips = s5pc100_gpio_chips;
-		nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
+	for (i = 0; i < S5PC1XX_GPIO_INT_GROUP_END; i++)
+		s5pc1xx_gpioint_group_map[i] = -1;
 
-	s5pc1xx_gpiolib_add(chips, nr_chips, s5pc1xx_gpiolib_link);
-	/* Interrupt */
+	s5pc1xx_gpiolib_add(&s5pc1xx_gpio_chips);
+
+	/* register gpio interrupt handler */
 	set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler);
 
 	return 0;
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-s5pc1xx.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-s5pc1xx.h
new file mode 100644
index 0000000..ad7c174
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/gpio-s5pc1xx.h
@@ -0,0 +1,79 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-s5pc1xx.h
+ *
+ *  Copyright 2009 Samsung Electronics Co
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *  Marek Szyprowski <m.szyprowski@samsung.com>
+ *
+ * GPIOlib support for S5PC1XX
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __GPIO_S5PC1XX_H
+#define __GPIO_S5PC1XX_H __FILE__
+
+struct s5pc1xx_gpio_chip {
+       struct s3c_gpio_chip chip;
+       unsigned int gpio_group;
+       unsigned int gpio_start;
+};
+
+extern struct irq_chip s5pc1xx_gpioint;
+extern int s5pc1xx_gpioint_group_map[S5PC1XX_GPIO_INT_GROUP_END];
+extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
+
+#define S5PC1XX_CHIP_DEF(plat, bank, cfg) \
+	{ \
+		.base	= plat ## _GP ## bank ## _BASE, \
+		.config	= &cfg, \
+		.chip	= { \
+			.base	= plat ## _GP ## bank(0), \
+			.ngpio	= plat ## _GPIO_ ## bank ## _NR, \
+			.label	= "GP" # bank, \
+		}, \
+	}
+
+#define S5PC1XX_INT_CHIP_DEF(plat, bank) \
+	{ \
+		.chip = S5PC1XX_CHIP_DEF(plat, bank, s5pc1xx_gpio_cfg), \
+		.gpio_start = plat ## _GPIO_## bank ## _START, \
+		.gpio_group = plat ## _GPIO_## bank ## _INT_GROUP, \
+	}
+
+#define S5PC1XX_EINT_CHIP_DEF(plat, bank) \
+	{ \
+		.chip = S5PC1XX_CHIP_DEF(plat, bank, s5pc1xx_gpio_cfg_eint), \
+	}
+
+#define S5PC1XX_NOINT_CHIP_DEF(plat, bank) \
+	{ \
+		.chip = S5PC1XX_CHIP_DEF(plat, bank, s5pc1xx_gpio_cfg_noint), \
+	}
+
+#define S5PC1XX_MP_CHIP_DEF(plat, bank) \
+	{ \
+		.chip = { \
+			.base	= plat ## _ ## bank ## _BASE, \
+			.config	= &s5pc1xx_gpio_cfg_noint, \
+			.chip	= { \
+				.base	= plat ## _ ## bank(0), \
+				.ngpio	= plat ## _GPIO_ ## bank ## _NR, \
+				.label	= "" # bank, \
+			}, \
+		}, \
+	}
+
+extern struct s3c_gpio_cfg s5pc1xx_gpio_cfg;
+extern struct s3c_gpio_cfg s5pc1xx_gpio_cfg_eint;
+extern struct s3c_gpio_cfg s5pc1xx_gpio_cfg_noint;
+
+struct s5pc1xx_gpio {
+	struct s5pc1xx_gpio_chip *chips;
+	int count;
+};
+
+extern struct s5pc1xx_gpio s5pc1xx_gpio_chips;
+
+#endif /* __GPIO_S5PC1XX_H */
diff --git a/arch/arm/plat-s5pc1xx/irq-eint.c b/arch/arm/plat-s5pc1xx/irq-eint.c
index 373122f..9e8bc12 100644
--- a/arch/arm/plat-s5pc1xx/irq-eint.c
+++ b/arch/arm/plat-s5pc1xx/irq-eint.c
@@ -105,7 +105,7 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
 {
 	u32 bank = s3c_get_bank(irq);
 	int real = s3c_get_eint(irq);
-	int gpio, shift, sfn;
+	int gpio, shift;
 	u32 ctrl, con = 0;
 
 	switch (type) {
@@ -148,23 +148,22 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
 
 	switch (real) {
 	case 0 ... 7:
-			gpio = S5PC100_GPH0(gpio);
+		gpio = S5PC1XX_GPH0(gpio);
 		break;
 	case 8 ... 15:
-			gpio = S5PC100_GPH1(gpio);
+		gpio = S5PC1XX_GPH1(gpio);
 		break;
 	case 16 ... 23:
-			gpio = S5PC100_GPH2(gpio);
+		gpio = S5PC1XX_GPH2(gpio);
 		break;
 	case 24 ... 31:
-			gpio = S5PC100_GPH3(gpio);
+		gpio = S5PC1XX_GPH3(gpio);
 		break;
 	default:
 		return -EINVAL;
 	}
 
-	sfn = S3C_GPIO_SFN(0x2);
-	s3c_gpio_cfgpin(gpio, sfn);
+	s3c_gpio_cfgpin(gpio, S5PC1XX_GPIO_EINT_SFN);
 
 	return 0;
 }
diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/plat-s5pc1xx/irq-gpio.c
index fecca7a..117cb8d 100644
--- a/arch/arm/plat-s5pc1xx/irq-gpio.c
+++ b/arch/arm/plat-s5pc1xx/irq-gpio.c
@@ -17,7 +17,9 @@
 #include <linux/gpio.h>
 
 #include <mach/map.h>
+#include <mach/gpio-core.h>
 #include <plat/gpio-cfg.h>
+#include <plat/gpio-s5pc1xx.h>
 
 #define S5PC1XX_GPIOREG(x)		(S5PC1XX_VA_GPIO + (x))
 
@@ -49,88 +51,19 @@ static int group_to_pend_offset(int group)
 	return group << 2;
 }
 
-static int s5pc1xx_get_start(unsigned int group)
-{
-	switch (group) {
-	case 0: return S5PC100_GPIO_A0_START;
-	case 1: return S5PC100_GPIO_A1_START;
-	case 2: return S5PC100_GPIO_B_START;
-	case 3: return S5PC100_GPIO_C_START;
-	case 4: return S5PC100_GPIO_D_START;
-	case 5: return S5PC100_GPIO_E0_START;
-	case 6: return S5PC100_GPIO_E1_START;
-	case 7: return S5PC100_GPIO_F0_START;
-	case 8: return S5PC100_GPIO_F1_START;
-	case 9: return S5PC100_GPIO_F2_START;
-	case 10: return S5PC100_GPIO_F3_START;
-	case 11: return S5PC100_GPIO_G0_START;
-	case 12: return S5PC100_GPIO_G1_START;
-	case 13: return S5PC100_GPIO_G2_START;
-	case 14: return S5PC100_GPIO_G3_START;
-	case 15: return S5PC100_GPIO_I_START;
-	case 16: return S5PC100_GPIO_J0_START;
-	case 17: return S5PC100_GPIO_J1_START;
-	case 18: return S5PC100_GPIO_J2_START;
-	case 19: return S5PC100_GPIO_J3_START;
-	case 20: return S5PC100_GPIO_J4_START;
-	default:
-		BUG();
-	}
-
-	return -EINVAL;
-}
-
 static int s5pc1xx_get_group(unsigned int irq)
 {
-	irq -= S3C_IRQ_GPIO(0);
-
-	switch (irq) {
-	case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1:
-		return 0;
-	case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1:
-		return 1;
-	case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1:
-		return 2;
-	case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1:
-		return 3;
-	case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1:
-		return 4;
-	case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1:
-		return 5;
-	case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1:
-		return 6;
-	case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1:
-		return 7;
-	case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1:
-		return 8;
-	case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1:
-		return 9;
-	case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1:
-		return 10;
-	case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1:
-		return 11;
-	case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1:
-		return 12;
-	case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1:
-		return 13;
-	case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1:
-		return 14;
-	case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1:
-		return 15;
-	case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1:
-		return 16;
-	case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1:
-		return 17;
-	case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1:
-		return 18;
-	case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1:
-		return 19;
-	case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1:
-		return 20;
-	default:
-		BUG();
-	}
-
+	struct gpio_chip *chip = get_irq_data(irq);
+	struct s3c_gpio_chip *s3c_chip = container_of(chip,
+					 struct s3c_gpio_chip, chip);
+	struct s5pc1xx_gpio_chip *s5pc1xx_chip = container_of(s3c_chip,
+						 struct s5pc1xx_gpio_chip,
+						 chip);
+
+	if (s5pc1xx_chip->gpio_group >= 0 &&
+	    s5pc1xx_chip->gpio_group < S5PC1XX_GPIO_INT_GROUP_END)
+		return s5pc1xx_chip->gpio_group;
+	BUG();
 	return -EINVAL;
 }
 
@@ -220,7 +153,6 @@ static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type)
 		BUG();
 	}
 
-
 	value = __raw_readl(S5PC1XX_GPIOREG(CON_OFFSET) + con_offset);
 	value &= ~(0xf << (offset * 0x4));
 	value |= (type << (offset * 0x4));
@@ -238,15 +170,15 @@ struct irq_chip s5pc1xx_gpioint = {
 	.set_type	= s5pc1xx_gpioint_set_type,
 };
 
+int s5pc1xx_gpioint_group_map[S5PC1XX_GPIO_INT_GROUP_END];
+
 void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
 {
 	int group, offset, pend_offset, mask_offset;
-	int real_irq, group_end;
+	int real_irq;
 	unsigned int pend, mask;
 
-	group_end = 21;
-
-	for (group = 0; group < group_end; group++) {
+	for (group = 0; group < S5PC1XX_GPIO_INT_GROUP_END; group++) {
 		pend_offset = group_to_pend_offset(group);
 		pend = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
 		if (!pend)
@@ -258,7 +190,8 @@ void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
 
 		for (offset = 0; offset < 8; offset++) {
 			if (pend & (1 << offset)) {
-				real_irq = s5pc1xx_get_start(group) + offset;
+				real_irq = s5pc1xx_gpioint_group_map[group] +
+					   offset;
 				generic_handle_irq(S3C_IRQ_GPIO(real_irq));
 			}
 		}
-- 
1.6.4

[PATCH 05/20] ARM: S5PC1XX: move common s5pc1xx mach/* includes to plat-s5pc1xx/include/mach

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

All includes that are common for S5PC100 and S5PC110 are moved to
plat-s5pc1xx/include/mach, so they can be used by both sub-platforms.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 .../include/mach/gpio-core.h                       |    2 +-
 .../include/mach/hardware.h                        |    2 +-
 .../include/mach/irqs.h                            |    2 +-
 .../include/mach/memory.h                          |    2 +-
 .../include/mach/pwm-clock.h                       |    2 +-
 .../include/mach/tick.h                            |    2 +-
 .../include/mach/uncompress.h                      |    2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)
 rename arch/arm/{mach-s5pc100 => plat-s5pc1xx}/include/mach/gpio-core.h (91%)
 rename arch/arm/{mach-s5pc100 => plat-s5pc1xx}/include/mach/hardware.h (83%)
 rename arch/arm/{mach-s5pc100 => plat-s5pc1xx}/include/mach/irqs.h (87%)
 rename arch/arm/{mach-s5pc100 => plat-s5pc1xx}/include/mach/memory.h (89%)
 rename arch/arm/{mach-s5pc100 => plat-s5pc1xx}/include/mach/pwm-clock.h (96%)
 rename arch/arm/{mach-s5pc100 => plat-s5pc1xx}/include/mach/tick.h (93%)
 rename arch/arm/{mach-s5pc100 => plat-s5pc1xx}/include/mach/uncompress.h (92%)

diff --git a/arch/arm/mach-s5pc100/include/mach/gpio-core.h b/arch/arm/plat-s5pc1xx/include/mach/gpio-core.h
similarity index 91%
rename from arch/arm/mach-s5pc100/include/mach/gpio-core.h
rename to arch/arm/plat-s5pc1xx/include/mach/gpio-core.h
index ad28d8e..6364800 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio-core.h
+++ b/arch/arm/plat-s5pc1xx/include/mach/gpio-core.h
@@ -1,4 +1,4 @@
-/* arch/arm/mach-s5pc100/include/mach/gpio-core.h
+/* arch/arm/plat-s5pc1xx/include/mach/gpio-core.h
  *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
diff --git a/arch/arm/mach-s5pc100/include/mach/hardware.h b/arch/arm/plat-s5pc1xx/include/mach/hardware.h
similarity index 83%
rename from arch/arm/mach-s5pc100/include/mach/hardware.h
rename to arch/arm/plat-s5pc1xx/include/mach/hardware.h
index 6b38618..c47affb 100644
--- a/arch/arm/mach-s5pc100/include/mach/hardware.h
+++ b/arch/arm/plat-s5pc1xx/include/mach/hardware.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/hardware.h
+/* linux/arch/arm/plat-s5pc1xx/include/mach/hardware.h
  *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/plat-s5pc1xx/include/mach/irqs.h
similarity index 87%
rename from arch/arm/mach-s5pc100/include/mach/irqs.h
rename to arch/arm/plat-s5pc1xx/include/mach/irqs.h
index b53fa48..198cff8 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/plat-s5pc1xx/include/mach/irqs.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/irqs.h
+/* linux/arch/arm/plat-s5pc1xx/include/mach/irqs.h
  *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
diff --git a/arch/arm/mach-s5pc100/include/mach/memory.h b/arch/arm/plat-s5pc1xx/include/mach/memory.h
similarity index 89%
rename from arch/arm/mach-s5pc100/include/mach/memory.h
rename to arch/arm/plat-s5pc1xx/include/mach/memory.h
index 21cc182..d378f45 100644
--- a/arch/arm/mach-s5pc100/include/mach/memory.h
+++ b/arch/arm/plat-s5pc1xx/include/mach/memory.h
@@ -1,4 +1,4 @@
-/* arch/arm/mach-s5pc100/include/mach/memory.h
+/* linux/arch/arm/plat-s5pc1xx/include/mach/memory.h
  *
  * Copyright 2008 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
diff --git a/arch/arm/mach-s5pc100/include/mach/pwm-clock.h b/arch/arm/plat-s5pc1xx/include/mach/pwm-clock.h
similarity index 96%
rename from arch/arm/mach-s5pc100/include/mach/pwm-clock.h
rename to arch/arm/plat-s5pc1xx/include/mach/pwm-clock.h
index b34d2f7..09a2834 100644
--- a/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
+++ b/arch/arm/plat-s5pc1xx/include/mach/pwm-clock.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
+/* linux/arch/arm/plat-s5pc1xx/include/mach/pwm-clock.h
  *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/plat-s5pc1xx/include/mach/tick.h
similarity index 93%
rename from arch/arm/mach-s5pc100/include/mach/tick.h
rename to arch/arm/plat-s5pc1xx/include/mach/tick.h
index d3de0f3..e43d1fd 100644
--- a/arch/arm/mach-s5pc100/include/mach/tick.h
+++ b/arch/arm/plat-s5pc1xx/include/mach/tick.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/tick.h
+/* linux/arch/arm/plat-s5pc1xx/include/mach/tick.h
  *
  * Copyright 2009 Samsung Electronics Co.
  *	Byungho Min <bhmin@samsung.com>
diff --git a/arch/arm/mach-s5pc100/include/mach/uncompress.h b/arch/arm/plat-s5pc1xx/include/mach/uncompress.h
similarity index 92%
rename from arch/arm/mach-s5pc100/include/mach/uncompress.h
rename to arch/arm/plat-s5pc1xx/include/mach/uncompress.h
index 01ccf53..e9ee0be 100644
--- a/arch/arm/mach-s5pc100/include/mach/uncompress.h
+++ b/arch/arm/plat-s5pc1xx/include/mach/uncompress.h
@@ -1,4 +1,4 @@
-/* arch/arm/mach-s5pc100/include/mach/uncompress.h
+/* linux/arch/arm/plat-s5pc1xx/include/mach/uncompress.h
  *
  * Copyright 2009 Samsung Electronics Co.
  *	Byungho Min <bhmin@samsung.com>
-- 
1.6.4

[PATCH 06/20] ARM: S5PC1XX: cleanup of s5pc1xx common code

[Marek Szyprowski]

This patch removes all useless definitions from plat/s5pc100.h and
introduces new common plat/s5pc1xx.h include.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-s5pc100/cpu.c                     |    2 +-
 arch/arm/mach-s5pc100/include/plat/regs-clock.h |    8 ++--
 arch/arm/mach-s5pc100/mach-smdkc100.c           |    2 +-
 arch/arm/mach-s5pc100/plls.c                    |    2 +-
 arch/arm/mach-s5pc100/uarts.c                   |    5 +-
 arch/arm/plat-s5pc1xx/cpu.c                     |    2 +-
 arch/arm/plat-s5pc1xx/include/plat/s5pc100.h    |   51 ++++++-----------------
 arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h    |   21 +++++++++
 8 files changed, 45 insertions(+), 48 deletions(-)
 create mode 100644 arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h

diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index 41fdecf..f383e33 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -41,7 +41,7 @@
 #include <plat/clock.h>
 #include <plat/sdhci.h>
 #include <plat/iic-core.h>
-#include <plat/s5pc100.h>
+#include <plat/s5pc1xx.h>
 
 /* Initial IO mappings */
 
diff --git a/arch/arm/mach-s5pc100/include/plat/regs-clock.h b/arch/arm/mach-s5pc100/include/plat/regs-clock.h
index f0a007b..637ff71 100644
--- a/arch/arm/mach-s5pc100/include/plat/regs-clock.h
+++ b/arch/arm/mach-s5pc100/include/plat/regs-clock.h
@@ -341,10 +341,10 @@
 #define S5PC100_HDMI_PHY_CON0	S5PC100_CLKREG_OTHER(0x420)
 
 #define S5PC100_SWRESET_RESETVAL	0xc100
-#define S5PC100_OTHER_SYS_INT	24
-#define S5PC100_OTHER_STA_TYPE	23
-#define STA_TYPE_EXPON		0
-#define STA_TYPE_SFR		1
+#define S5PC100_OTHERS_PMU_INT_DISALBE		(1 << 24)
+#define S5PC100_OTHERS_STABLE_COUNTER_TYPE_MASK	(1 << 23)
+#define S5PC100_OTHERS_STABLE_COUNTER_TYPE_SFR	(1 << 23)
+#define S5PC100_OTHERS_STABLE_COUNTER_TYPE_EXP	(0 << 23)
 
 #define S5PC100_SLEEP_CFG_OSC_EN	0
 
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index ae3c52c..29b95f1 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -40,7 +40,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/s5pc100.h>
+#include <plat/s5pc1xx.h>
 #include <plat/fb.h>
 #include <plat/iic.h>
 
diff --git a/arch/arm/mach-s5pc100/plls.c b/arch/arm/mach-s5pc100/plls.c
index cd3f6a7..970f49d 100644
--- a/arch/arm/mach-s5pc100/plls.c
+++ b/arch/arm/mach-s5pc100/plls.c
@@ -32,7 +32,7 @@
 #include <plat/cpu.h>
 #include <plat/pll.h>
 #include <plat/devs.h>
-#include <plat/s5pc100.h>
+#include <plat/s5pc1xx.h>
 
 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
  * ext_xtal_mux for want of an actual name from the manual.
diff --git a/arch/arm/mach-s5pc100/uarts.c b/arch/arm/mach-s5pc100/uarts.c
index 32972f2..6bab6d2 100644
--- a/arch/arm/mach-s5pc100/uarts.c
+++ b/arch/arm/mach-s5pc100/uarts.c
@@ -13,14 +13,15 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/init.h>
+#include <linux/clk.h>
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/s5pc100.h>
+#include <plat/s5pc1xx.h>
 
 /* uart registration process */
 
-void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
 	/* The driver name is s3c6400-uart to reuse s3c6400_serial_drv  */
 	s3c24xx_init_uartdevs("s3c6400-uart", s5pc1xx_uart_resources, cfg, no);
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c
index ecd6d38..d30998d 100644
--- a/arch/arm/plat-s5pc1xx/cpu.c
+++ b/arch/arm/plat-s5pc1xx/cpu.c
@@ -31,7 +31,7 @@
 #include <plat/devs.h>
 #include <plat/clock.h>
 
-#include <plat/s5pc100.h>
+#include <plat/s5pc1xx.h>
 
 /* table of supported CPUs */
 
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
index 2531f34..32eb6e7 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
@@ -13,52 +13,27 @@
 */
 
 /* Common init code for S5PC100 related SoCs */
+
+#ifdef CONFIG_CPU_S5PC100
+
 extern  int s5pc100_init(void);
 extern void s5pc100_map_io(void);
 extern void s5pc100_init_clocks(int xtal);
 extern  int s5pc100_register_baseclocks(unsigned long xtal);
 extern void s5pc100_init_irq(void);
 extern void s5pc100_init_io(struct map_desc *mach_desc, int size);
-extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s5pc100_register_clocks(void);
 extern void s5pc100_setup_clocks(void);
-extern struct sysdev_class s5pc100_sysclass;
-
-#define s5pc100_init_uarts s5pc100_common_init_uarts
-
-/* Some day, belows will be moved to plat-s5pc/include/plat/cpu.h */
-extern void s5pc1xx_init_irq(u32 *vic_valid, int num);
-extern void s5pc1xx_init_io(struct map_desc *mach_desc, int size);
-
-/* Some day, belows will be moved to plat-s5pc/include/plat/clock.h */
-extern struct clk clk_hpll;
-extern struct clk clk_hd0;
-extern struct clk clk_pd0;
+extern  int s5pc100_sclk0_ctrl(struct clk *clk, int enable);
+extern  int s5pc100_sclk1_ctrl(struct clk *clk, int enable);
 extern struct clk clk_54m;
-extern void s5pc1xx_register_clocks(void);
-extern int s5pc100_sclk0_ctrl(struct clk *clk, int enable);
-extern int s5pc100_sclk1_ctrl(struct clk *clk, int enable);
 
-/* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */
-extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
-extern struct platform_device s3c_device_g2d;
-extern struct platform_device s3c_device_g3d;
-extern struct platform_device s3c_device_vpp;
-extern struct platform_device s3c_device_tvenc;
-extern struct platform_device s3c_device_tvscaler;
-extern struct platform_device s3c_device_rotator;
-extern struct platform_device s3c_device_jpeg;
-extern struct platform_device s3c_device_onenand;
-extern struct platform_device s3c_device_usb_otghcd;
-extern struct platform_device s3c_device_keypad;
-extern struct platform_device s3c_device_ts;
-extern struct platform_device s3c_device_g3d;
-extern struct platform_device s3c_device_smc911x;
-extern struct platform_device s3c_device_fimc0;
-extern struct platform_device s3c_device_fimc1;
-extern struct platform_device s3c_device_mfc;
-extern struct platform_device s3c_device_ac97;
-extern struct platform_device s3c_device_fimc0;
-extern struct platform_device s3c_device_fimc1;
-extern struct platform_device s3c_device_fimc2;
+#else
+
+#define s5pc100_map_io NULL
+#define s5pc100_init_clocks NULL
+#define s5pc100_init_uarts NULL
+#define s5pc100_init NULL
 
+#endif
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h
new file mode 100644
index 0000000..398251f
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h
@@ -0,0 +1,21 @@
+/* arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Marek Szyprowski <m.szyprowski@samsung.com>
+ *
+ * Header file for s5pc1xx cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for S5PC1XX related SoCs */
+
+extern void s5pc1xx_init_irq(u32 *vic_valid, int num);
+extern void s5pc1xx_init_io(struct map_desc *mach_desc, int size);
+extern void s5pc1xx_register_clocks(void);
+
+extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
+
+#include <plat/s5pc100.h>
-- 
1.6.4

[PATCH 07/20] ARM: S5PC1XX: move s5pc100 specific device helpers to mach-s5pc100 dir

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

All device helpers that are defined in plat-s5pc1xx are S5PC100
specific. This patch moves them to mach-s5pc100 directory to make use of
newly created sub-platform support.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/mach-s5pc100/Kconfig                      |   32 +++++++++++++++++--
 arch/arm/mach-s5pc100/Makefile                     |    4 ++
 .../setup-fb-24bpp.c                               |    0
 .../{plat-s5pc1xx => mach-s5pc100}/setup-i2c0.c    |    0
 .../{plat-s5pc1xx => mach-s5pc100}/setup-i2c1.c    |    0
 .../setup-sdhci-gpio.c                             |    0
 arch/arm/plat-s5pc1xx/Kconfig                      |   24 ---------------
 arch/arm/plat-s5pc1xx/Makefile                     |    4 --
 8 files changed, 32 insertions(+), 32 deletions(-)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/setup-fb-24bpp.c (100%)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/setup-i2c0.c (100%)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/setup-i2c1.c (100%)
 rename arch/arm/{plat-s5pc1xx => mach-s5pc100}/setup-sdhci-gpio.c (100%)

diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 1dbb5f1..6749d5e 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -14,12 +14,36 @@ config CPU_S5PC100
 	help
 	  Enable S5PC100 CPU support
 
+config S5PC100_SETUP_FB_24BPP
+	bool
+	help
+          Common setup code for S5PC1XX with an 24bpp RGB display helper.
+
+config S5PC100_SETUP_I2C0
+	bool
+	default y
+	help
+	  Common setup code for i2c bus 0.
+
+	  Note, currently since i2c0 is always compiled, this setup helper
+	  is always compiled with it.
+
+config S5PC100_SETUP_I2C1
+	bool
+	help
+	  Common setup code for i2c bus 1.
+
 config S5PC100_SETUP_SDHCI
         bool
-        select S5PC1XX_SETUP_SDHCI_GPIO
+        select S5PC100_SETUP_SDHCI_GPIO
         help
           Internal helper functions for S5PC100 based SDHCI systems
 
+config S5PC100_SETUP_SDHCI_GPIO
+	bool
+	help
+	  Common setup code for SDHCI gpio.
+
 config MACH_SMDKC100
 	bool "SMDKC100"
 	select CPU_S5PC100
@@ -28,9 +52,9 @@ config MACH_SMDKC100
 	select S3C_DEV_HSMMC
 	select S3C_DEV_HSMMC1
 	select S3C_DEV_HSMMC2
-	select S5PC1XX_SETUP_I2C0
-	select S5PC1XX_SETUP_I2C1
-	select S5PC1XX_SETUP_FB_24BPP
+	select S5PC100_SETUP_I2C0
+	select S5PC100_SETUP_I2C1
+	select S5PC100_SETUP_FB_24BPP
 	select S5PC100_SETUP_SDHCI
 	help
 	  Machine support for the Samsung SMDKC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 8d29ea1..b0664ce 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -19,7 +19,11 @@ obj-$(CONFIG_CPU_S5PC100)	+= uarts.o
 
 # Helper and device support
 
+obj-$(CONFIG_S5PC100_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
+obj-$(CONFIG_S5PC100_SETUP_I2C0)	+= setup-i2c0.o
+obj-$(CONFIG_S5PC100_SETUP_I2C1)	+= setup-i2c1.o
 obj-$(CONFIG_S5PC100_SETUP_SDHCI)       += setup-sdhci.o
+obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
 
 # machine support
 obj-$(CONFIG_MACH_SMDKC100)	+= mach-smdkc100.o
diff --git a/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
similarity index 100%
rename from arch/arm/plat-s5pc1xx/setup-fb-24bpp.c
rename to arch/arm/mach-s5pc100/setup-fb-24bpp.c
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c
similarity index 100%
rename from arch/arm/plat-s5pc1xx/setup-i2c0.c
rename to arch/arm/mach-s5pc100/setup-i2c0.c
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c
similarity index 100%
rename from arch/arm/plat-s5pc1xx/setup-i2c1.c
rename to arch/arm/mach-s5pc100/setup-i2c1.c
diff --git a/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
similarity index 100%
rename from arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
rename to arch/arm/mach-s5pc100/setup-sdhci-gpio.c
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index 7131ce9..4a3347d 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -37,28 +37,4 @@ endchoice
 
 # platform specific device setup
 
-config S5PC1XX_SETUP_FB_24BPP
-	bool
-	help
-          Common setup code for S5PC1XX with an 24bpp RGB display helper.
-
-config S5PC1XX_SETUP_I2C0
-	bool
-	default y
-	help
-	  Common setup code for i2c bus 0.
-
-	  Note, currently since i2c0 is always compiled, this setup helper
-	  is always compiled with it.
-
-config S5PC1XX_SETUP_I2C1
-	bool
-	help
-	  Common setup code for i2c bus 1.
-
-config S5PC1XX_SETUP_SDHCI_GPIO
-	bool
-	help
-	  Common setup code for SDHCI gpio.
-
 endif
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
index 39dd0a1..ad187b2 100644
--- a/arch/arm/plat-s5pc1xx/Makefile
+++ b/arch/arm/plat-s5pc1xx/Makefile
@@ -21,7 +21,3 @@ obj-y				+= gpiolib.o
 # Device setup
 
 obj-$(CONFIG_S5P_GPIO_CFG_S5PC1XX) += gpio-config.o
-obj-$(CONFIG_S5PC1XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
-obj-$(CONFIG_S5PC1XX_SETUP_I2C0) += setup-i2c0.o
-obj-$(CONFIG_S5PC1XX_SETUP_I2C1) += setup-i2c1.o
-obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
-- 
1.6.4

[PATCH 08/20] ARM: S5PC1XX: move common s5pc1xx s3c-fb regs to platform directory

[Marek Szyprowski]

From: Pawel Osciak <p.osciak@samsung.com>

Framebuffer register blocks on S5PC100 and S5PC110 differ only slightly.
This patch moves all register definitions that are common for S5PC100
and S5PC110 to plat-s3c/plat/regs-fb-v5.h.

Signed-off-by: Pawel Osciak <p.osciak@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/mach-s5pc100/include/mach/regs-fb.h       |  133 ++------------------
 .../include/plat/regs-fb-v5.h}                     |   15 +--
 2 files changed, 15 insertions(+), 133 deletions(-)
 copy arch/arm/{mach-s5pc100/include/mach/regs-fb.h => plat-s3c/include/plat/regs-fb-v5.h} (93%)

diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
index 1732cd2..49764cb 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-fb.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
@@ -1,139 +1,22 @@
-/* arch/arm/mach-s5pc100/include/mach/regs-fb.h
- *
+/*
  * Copyright 2009 Samsung Electronics Co.
  *   Pawel Osciak <p.osciak@samsung.com>
  *
- * Framebuffer register definitions for Samsung S5PC100.
+ * Machine-specific framebuffer definitions for Samsung S5PC100.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_FB_H
-#define __ASM_ARCH_REGS_FB_H __FILE__
-
-#include <plat/regs-fb-v4.h>
-
-/* VP1 interface timing control */
-#define VP1CON0						(0x118)
-#define VP1_RATECON_EN					(1 << 31)
-#define VP1_CLKRATE_MASK				(0xff)
-
-#define VP1CON1						(0x11c)
-#define VP1_VTREGCON_EN					(1 << 31)
-#define VP1_VBPD_MASK					(0xfff)
-#define VP1_VBPD_SHIFT					(16)
-
-
-#define WPALCON_H					(0x19c)
-#define WPALCON_L					(0x1a0)
-
-/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but
- * different for WPAL2-4
- */
-/* In WPALCON_L (aka WPALCON) */
-#define WPALCON_W1PAL_32BPP_A888			(0x7 << 3)
-#define WPALCON_W0PAL_32BPP_A888			(0x7 << 0)
-
-/* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H,
- * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]).
- */
-#define WPALCON_L_WxPAL_L_MASK				(0x1)
-#define WPALCON_L_W2PAL_L_SHIFT				(6)
-#define WPALCON_L_W3PAL_L_SHIFT				(7)
-#define WPALCON_L_W4PAL_L_SHIFT				(8)
-
-#define WPALCON_L_WxPAL_H_MASK				(0x3)
-#define WPALCON_H_W2PAL_H_SHIFT				(9)
-#define WPALCON_H_W3PAL_H_SHIFT				(13)
-#define WPALCON_H_W4PAL_H_SHIFT				(17)
-
-/* Per-window alpha value registers */
-/* For window 0 8-bit alpha values are in VIDW0ALPHAx,
- * for windows 1-4 alpha values consist of two parts, the 4 low bits are
- * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC,
- * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0])
- */
-#define VIDWxALPHA0(_win)				(0x200 + (_win * 8))
-#define VIDWxALPHA1(_win)				(0x204 + (_win * 8))
-
-/* Only for window 0 in VIDW0ALPHAx. */
-#define VIDW0ALPHAx_R(_x)				((_x) << 16)
-#define VIDW0ALPHAx_R_MASK				(0xff << 16)
-#define VIDW0ALPHAx_R_SHIFT				(16)
-#define VIDW0ALPHAx_G(_x)				((_x) << 8)
-#define VIDW0ALPHAx_G_MASK				(0xff << 8)
-#define VIDW0ALPHAx_G_SHIFT				(8)
-#define VIDW0ALPHAx_B(_x)				((_x) << 0)
-#define VIDW0ALPHAx_B_MASK				(0xff << 0)
-#define VIDW0ALPHAx_B_SHIFT				(0)
-
-/* Low 4 bits of alpha0-1 for windows 1-4 */
-#define VIDW14ALPHAx_R_L(_x)				((_x) << 16)
-#define VIDW14ALPHAx_R_L_MASK				(0xf << 16)
-#define VIDW14ALPHAx_R_L_SHIFT				(16)
-#define VIDW14ALPHAx_G_L(_x)				((_x) << 8)
-#define VIDW14ALPHAx_G_L_MASK				(0xf << 8)
-#define VIDW14ALPHAx_G_L_SHIFT				(8)
-#define VIDW14ALPHAx_B_L(_x)				((_x) << 0)
-#define VIDW14ALPHAx_B_L_MASK				(0xf << 0)
-#define VIDW14ALPHAx_B_L_SHIFT				(0)
-
-
-/* Per-window blending equation control registers */
-#define BLENDEQx(_win)					(0x244 + ((_win) * 4))
-#define BLENDEQ1					(0x244)
-#define BLENDEQ2					(0x248)
-#define BLENDEQ3					(0x24c)
-#define BLENDEQ4					(0x250)
-
-#define BLENDEQx_Q_FUNC(_x)				((_x) << 18)
-#define BLENDEQx_Q_FUNC_MASK				(0xf << 18)
-#define BLENDEQx_P_FUNC(_x)				((_x) << 12)
-#define BLENDEQx_P_FUNC_MASK				(0xf << 12)
-#define BLENDEQx_B_FUNC(_x)				((_x) << 6)
-#define BLENDEQx_B_FUNC_MASK				(0xf << 6)
-#define BLENDEQx_A_FUNC(_x)				((_x) << 0)
-#define BLENDEQx_A_FUNC_MASK				(0xf << 0)
-
-#define BLENDCON					(0x260)
-#define BLENDCON_8BIT_ALPHA				(1 << 0)
-
-/* Per-window palette base addresses (start of palette memory).
- * Each window palette area consists of 256 32-bit entries.
- * START is the first address (entry 0th), END is the address of 255th entry.
  */
-#define WIN0_PAL_BASE					(0x2400)
-#define WIN0_PAL_END					(0x27fc)
-#define WIN1_PAL_BASE					(0x2800)
-#define WIN1_PAL_END					(0x2bfc)
-#define WIN2_PAL_BASE					(0x2c00)
-#define WIN2_PAL_END					(0x2ffc)
-#define WIN3_PAL_BASE					(0x3000)
-#define WIN3_PAL_END					(0x33fc)
-#define WIN4_PAL_BASE					(0x3400)
-#define WIN4_PAL_END					(0x37fc)
 
-#define WIN0_PAL(_entry)			(WIN0_PAL_BASE + ((_entry) * 4))
-#define WIN1_PAL(_entry)			(WIN1_PAL_BASE + ((_entry) * 4))
-#define WIN2_PAL(_entry)			(WIN2_PAL_BASE + ((_entry) * 4))
-#define WIN3_PAL(_entry)			(WIN3_PAL_BASE + ((_entry) * 4))
-#define WIN4_PAL(_entry)			(WIN4_PAL_BASE + ((_entry) * 4))
+#ifndef __ASM_ARCH_MACH_REGS_FB_H
+#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
 
-static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
-{
-	switch (window) {
-	case 0: return WIN0_PAL(reg);
-	case 1: return WIN1_PAL(reg);
-	case 2: return WIN2_PAL(reg);
-	case 3: return WIN3_PAL(reg);
-	case 4: return WIN4_PAL(reg);
-	}
+#include <plat/regs-fb-v5.h>
 
-	BUG();
-}
+#define PRTCON						(0xc)
+#define PRTCON_PROTECT					(1 << 11)
 
 
-#endif /* __ASM_ARCH_REGS_FB_H */
+#endif /* __ASM_ARCH_MACH_REGS_FB_H */
 
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/plat-s3c/include/plat/regs-fb-v5.h
similarity index 93%
copy from arch/arm/mach-s5pc100/include/mach/regs-fb.h
copy to arch/arm/plat-s3c/include/plat/regs-fb-v5.h
index 1732cd2..0e0686d 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-fb.h
+++ b/arch/arm/plat-s3c/include/plat/regs-fb-v5.h
@@ -1,17 +1,16 @@
-/* arch/arm/mach-s5pc100/include/mach/regs-fb.h
- *
+/*
  * Copyright 2009 Samsung Electronics Co.
  *   Pawel Osciak <p.osciak@samsung.com>
  *
- * Framebuffer register definitions for Samsung S5PC100.
+ * Common framebuffer register definitions for Samsung S5PC1xx family.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
-*/
+ */
 
-#ifndef __ASM_ARCH_REGS_FB_H
-#define __ASM_ARCH_REGS_FB_H __FILE__
+#ifndef __ASM_ARCH_REGS_FB_V5_H
+#define __ASM_ARCH_REGS_FB_V5_H __FILE__
 
 #include <plat/regs-fb-v4.h>
 
@@ -36,7 +35,7 @@
 #define WPALCON_W1PAL_32BPP_A888			(0x7 << 3)
 #define WPALCON_W0PAL_32BPP_A888			(0x7 << 0)
 
-/* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H,
+/* W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H,
  * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]).
  */
 #define WPALCON_L_WxPAL_L_MASK				(0x1)
@@ -135,5 +134,5 @@ static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
 }
 
 
-#endif /* __ASM_ARCH_REGS_FB_H */
+#endif /* __ASM_ARCH_REGS_FB_V5_H */
 
-- 
1.6.4

[PATCH 09/20] drivers: serial: add support for Samsung S5PC110 SoC uart

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoCs have UART that differs a bit from the one known
from the previous Samsung SoCs. This patch adds support for this new
driver.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/plat-s3c/include/plat/regs-serial.h |   31 ++++++
 drivers/serial/Kconfig                       |    7 ++
 drivers/serial/Makefile                      |    1 +
 drivers/serial/s5pc110.c                     |  143 ++++++++++++++++++++++++++
 4 files changed, 182 insertions(+), 0 deletions(-)
 create mode 100644 drivers/serial/s5pc110.c

diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h
index 66af75a..910cfba 100644
--- a/arch/arm/plat-s3c/include/plat/regs-serial.h
+++ b/arch/arm/plat-s3c/include/plat/regs-serial.h
@@ -194,6 +194,37 @@
 #define S3C64XX_UINTSP		0x34
 #define S3C64XX_UINTM		0x38
 
+/* S5PC110 UCON */
+#define S5PC110_UCON_CLKMASK	(1<<10)
+#define S5PC110_UCON_PCLK	(0<<10)
+#define S5PC110_UCON_SCLK_UART	(1<<10)
+
+/* S5PC110 FIFO trigger levels */
+#define S5PC110_UFCON_RXTRIG1	(0<<4)
+#define S5PC110_UFCON_RXTRIG4	(1<<4)
+#define S5PC110_UFCON_RXTRIG8	(2<<4)
+#define S5PC110_UFCON_RXTRIG16	(3<<4)
+#define S5PC110_UFCON_RXTRIG32	(4<<4)
+#define S5PC110_UFCON_RXTRIG64	(5<<4)
+#define S5PC110_UFCON_RXTRIG128	(6<<4)
+#define S5PC110_UFCON_RXTRIG256	(7<<4)
+
+#define S5PC110_UFCON_TXTRIG1	(0<<8)
+#define S5PC110_UFCON_TXTRIG4	(1<<8)
+#define S5PC110_UFCON_TXTRIG8	(2<<8)
+#define S5PC110_UFCON_TXTRIG16	(3<<8)
+#define S5PC110_UFCON_TXTRIG32	(4<<8)
+#define S5PC110_UFCON_TXTRIG64	(5<<8)
+#define S5PC110_UFCON_TXTRIG128	(6<<8)
+#define S5PC110_UFCON_TXTRIG256	(7<<8)
+
+#define S5PC110_UFSTAT_TXFULL	(1<<24)
+#define S5PC110_UFSTAT_RXFULL	(1<<8)
+#define S5PC110_UFSTAT_TXSHIFT	(16)
+#define S5PC110_UFSTAT_RXSHIFT	(0)
+#define S5PC110_UFSTAT_TXMASK	(255<<16)
+#define S5PC110_UFSTAT_RXMASK	(255)
+
 #ifndef __ASSEMBLY__
 
 /* struct s3c24xx_uart_clksrc
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index e522572..d119cac 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -540,6 +540,13 @@ config SERIAL_S5PC100
 	help
 	  Serial port support for the Samsung S5PC100 SoCs
 
+config SERIAL_S5PC110
+	tristate "Samsung S5PC110 Serial port support"
+	depends on SERIAL_SAMSUNG && CPU_S5PC110
+	default y
+	help
+	  Serial port support for the Samsung S5PC110 SoCs
+
 config SERIAL_MAX3100
 	tristate "MAX3100 support"
 	depends on SPI
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index d21d5dd..43d6123 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
 obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
 obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
 obj-$(CONFIG_SERIAL_S5PC100) += s3c6400.o
+obj-$(CONFIG_SERIAL_S5PC110) += s5pc110.o
 obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
 obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
 obj-$(CONFIG_SERIAL_MUX) += mux.o
diff --git a/drivers/serial/s5pc110.c b/drivers/serial/s5pc110.c
new file mode 100644
index 0000000..1e1e229
--- /dev/null
+++ b/drivers/serial/s5pc110.c
@@ -0,0 +1,143 @@
+/*
+ * linux/drivers/serial/s5pc110.c
+ *
+ * Driver for Samsung S5PC110 SoC onboard UARTs.
+ *
+ *  Copyright 2009 Samsung Electronics
+ *  Kyungin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+
+#include <asm/irq.h>
+#include <mach/hardware.h>
+
+#include <plat/regs-serial.h>
+
+#include "samsung.h"
+
+static int s5pc110_serial_setsource(struct uart_port *port,
+				    struct s3c24xx_uart_clksrc *clk)
+{
+	unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+	if (strcmp(clk->name, "uclk0") == 0)
+		ucon |= S5PC110_UCON_SCLK_UART;
+	else if (strcmp(clk->name, "pclk") == 0)
+		/* See notes about transitioning from UCLK to PCLK */
+		ucon &= ~S5PC110_UCON_SCLK_UART;
+	else {
+		printk(KERN_ERR "unknown clock source %s\n", clk->name);
+		return -EINVAL;
+	}
+
+	wr_regl(port, S3C2410_UCON, ucon);
+	return 0;
+}
+
+static int s5pc110_serial_getsource(struct uart_port *port,
+				    struct s3c24xx_uart_clksrc *clk)
+{
+	u32 ucon = rd_regl(port, S3C2410_UCON);
+
+	clk->divisor = 1;
+
+	switch (ucon & S5PC110_UCON_CLKMASK) {
+	case S5PC110_UCON_SCLK_UART:
+		clk->name = "uclk0";
+		break;
+
+	case S5PC110_UCON_PCLK:
+		clk->name = "pclk";
+		break;
+	}
+
+	return 0;
+}
+
+static int s5pc110_serial_resetport(struct uart_port *port,
+				    struct s3c2410_uartcfg *cfg)
+{
+	unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+	dbg("s5pc110_serial_resetport: port=%p (%08lx), cfg=%p\n",
+	    port, port->mapbase, cfg);
+
+	/* ensure we don't change the clock settings... */
+
+	ucon &= S5PC110_UCON_CLKMASK;
+
+	wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
+	wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+	/* reset both fifos */
+
+	wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+	wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+	return 0;
+}
+
+static struct s3c24xx_uart_info s5pc110_uart_inf = {
+	.name		= "Samsung S5PC110 UART",
+	.type		= PORT_S3C6400,
+	.fifosize	= 16,
+	.has_divslot	= 1,
+	.rx_fifomask	= S5PC110_UFSTAT_RXMASK,
+	.rx_fifoshift	= S5PC110_UFSTAT_RXSHIFT,
+	.rx_fifofull	= S5PC110_UFSTAT_RXFULL,
+	.tx_fifofull	= S5PC110_UFSTAT_TXFULL,
+	.tx_fifomask	= S5PC110_UFSTAT_TXMASK,
+	.tx_fifoshift	= S5PC110_UFSTAT_TXSHIFT,
+	.get_clksrc	= s5pc110_serial_getsource,
+	.set_clksrc	= s5pc110_serial_setsource,
+	.reset_port	= s5pc110_serial_resetport,
+};
+
+/* device management */
+
+static int s5pc110_serial_probe(struct platform_device *dev)
+{
+	dbg("s5pc110_serial_probe: dev=%p\n", dev);
+
+	return s3c24xx_serial_probe(dev, &s5pc110_uart_inf);
+}
+
+static struct platform_driver s5pc110_serial_driver = {
+	.probe		= s5pc110_serial_probe,
+	.remove		= __devexit_p(s3c24xx_serial_remove),
+	.driver		= {
+		.name	= "s5pc110-uart",
+		.owner	= THIS_MODULE,
+	},
+};
+
+s3c24xx_console_init(&s5pc110_serial_driver, &s5pc110_uart_inf);
+
+static int __init s5pc110_serial_init(void)
+{
+	return s3c24xx_serial_init(&s5pc110_serial_driver, &s5pc110_uart_inf);
+}
+
+static void __exit s5pc110_serial_exit(void)
+{
+	platform_driver_unregister(&s5pc110_serial_driver);
+}
+
+module_init(s5pc110_serial_init);
+module_exit(s5pc110_serial_exit);
+
+MODULE_DESCRIPTION("Samsung S5PC110 SoC Serial port driver");
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:s5pc110-uart");
-- 
1.6.4

[PATCH 10/20] ARM: S5PC1XX: add S5PC110 memory map

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds register map for S5PC110 sub-platform.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Byungho Min <bhmin@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/mach-s5pc110/include/mach/map.h |  154 ++++++++++++++++++++++++++++++
 1 files changed, 154 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/include/mach/map.h

diff --git a/arch/arm/mach-s5pc110/include/mach/map.h b/arch/arm/mach-s5pc110/include/mach/map.h
new file mode 100644
index 0000000..af9ce84
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/mach/map.h
@@ -0,0 +1,154 @@
+/* linux/arch/arm/mach-s5pc110/include/mach/map.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Based on mach-s3c6400/include/mach/map.h
+ *
+ * S5PC110 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H __FILE__
+
+#include <plat/map-base.h>
+
+/*
+ * map-base.h has already defined virtual memory address
+ * S3C_VA_IRQ		S3C_ADDR(0x00000000)	irq controller(s)
+ * S3C_VA_SYS		S3C_ADDR(0x00100000)	system control
+ * S3C_VA_MEM		S3C_ADDR(0x00200000)	system control (not used)
+ * S3C_VA_TIMER		S3C_ADDR(0x00300000)	timer block
+ * S3C_VA_WATCHDOG	S3C_ADDR(0x00400000)	watchdog
+ * S3C_VA_UART		S3C_ADDR(0x01000000)	UART
+ *
+ * S5PC110 specific virtual memory address can be defined here
+ * S5PC1XX_VA_GPIO	S3C_ADDR(0x00500000)	GPIO
+ *
+ */
+
+/* Chip ID */
+#define S5PC110_PA_CHIPID	(0xE0000000)
+#define S5PC1XX_PA_CHIPID	S5PC110_PA_CHIPID
+#define S5PC1XX_VA_CHIPID	S3C_VA_SYS
+
+/* System */
+#define S5PC110_PA_CLK		(0xE0100000)
+#define S5PC110_PA_PWR		(0xE010C000)
+#define S5PC1XX_PA_CLK		S5PC110_PA_CLK
+#define S5PC1XX_PA_PWR		S5PC110_PA_PWR
+#define S5PC1XX_VA_CLK		(S3C_VA_SYS + 0x10000)
+#define S5PC1XX_VA_PWR		(S3C_VA_SYS + 0x20000)
+#define S5PC1XX_SZ_CLK		SZ_32K
+#define S5PC1XX_SZ_PWR		SZ_16K
+
+/* GPIO */
+#define S5PC110_PA_GPIO		(0xE0200000)
+#define S5PC1XX_PA_GPIO		S5PC110_PA_GPIO
+#define S5PC1XX_VA_GPIO		S3C_ADDR(0x00500000)
+
+/* Interrupt */
+#define S5PC110_PA_VIC		(0xF2000000)
+#define S5PC110_PA_VIC_OFFSET	0x100000
+#define S5PC1XX_PA_VIC(x)	(S5PC110_PA_VIC + ((x) * S5PC110_PA_VIC_OFFSET))
+#define S5PC110_VA_VIC		S3C_VA_IRQ
+#define S5PC110_VA_VIC_OFFSET	0x10000
+#define S5PC1XX_VA_VIC(x)	(S5PC110_VA_VIC + ((x) * S5PC110_VA_VIC_OFFSET))
+
+/* DMA */
+#define S5PC110_PA_MDMA		(0xFA200000)
+#define S5PC110_PA_PDMA0	(0xE0900000)
+#define S5PC110_PA_PDMA1	(0xE0A00000)
+
+/* Timer */
+#define S5PC110_PA_TIMER	(0xE2500000)
+#define S5PC1XX_PA_TIMER	S5PC110_PA_TIMER
+#define S5PC1XX_VA_TIMER	S3C_VA_TIMER
+
+/* RTC */
+#define S5PC110_PA_RTC		(0xE2800000)
+#define S5PC1XX_PA_RTC		S5PC110_PA_RTC
+
+/* UART */
+#define S5PC110_PA_UART		(0xE2900000)
+#define S5PC1XX_PA_UART		S5PC110_PA_UART
+#define S5PC110_PA_UART0	(S5PC110_PA_UART + 0x0)
+#define S5PC110_PA_UART1	(S5PC110_PA_UART + 0x400)
+#define S5PC110_PA_UART2	(S5PC110_PA_UART + 0x800)
+#define S5PC110_PA_UART3	(S5PC110_PA_UART + 0xC00)
+#define S5PC1XX_VA_UART		S3C_VA_UART
+
+/* I2C */
+#define S5PC110_PA_I2C		(0xE1800000)
+#define S5PC110_PA_I2C1		(0xFAB00000)
+#define S5PC110_PA_I2C2		(0xE1A00000)
+
+/* USB HS OTG */
+#define S5PC110_PA_USB_HSOTG	(0xEC000000)
+#define S5PC110_PA_USB_HSPHY	(0xEC100000)
+
+/* SD/MMC */
+#define S5PC110_PA_HSMMC(x)	(0xEB000000 + ((x) * 0x100000))
+#define S5PC110_PA_HSMMC0	S5PC110_PA_HSMMC(0)
+#define S5PC110_PA_HSMMC1	S5PC110_PA_HSMMC(1)
+#define S5PC110_PA_HSMMC2	S5PC110_PA_HSMMC(2)
+#define S5PC110_PA_HSMMC3	S5PC110_PA_HSMMC(2)
+
+/* LCD */
+#define S5PC110_PA_FB		(0xF8000000)
+
+/* Multimedia */
+#define S5PC110_PA_MFC		(0xF1700000)
+#define S5PC110_SZ_MFC		(0x0000FFFF)
+
+/* I2S */
+#define S5PC110_PA_I2S0		(0xEEE30000)
+#define S5PC110_PA_I2S1		(0xE2100000)
+#define S5PC110_PA_I2S2		(0xE2A00000)
+
+/* KEYPAD */
+#define S5PC110_PA_KEYPAD	(0xE1600000)
+
+/* ADC & TouchScreen */
+#define S5PC110_PA_TSADC	(0xE1700000)
+
+/* ETC */
+#define S5PC110_PA_SDRAM	(0x30000000)
+#define S5PC1XX_PA_SDRAM	S5PC110_PA_SDRAM
+
+/* compatibility defines. */
+#define S3C_PA_RTC		S5PC1XX_PA_RTC
+#define S3C_PA_UART		S5PC1XX_PA_UART
+#define S3C_PA_UART0		S5PC110_PA_UART0
+#define S3C_PA_UART1		S5PC110_PA_UART1
+#define S3C_PA_UART2		S5PC110_PA_UART2
+#define S3C_PA_UART3		S5PC110_PA_UART3
+
+#define S3C_VA_UART0		(S3C_VA_UART + 0x0)
+#define S3C_VA_UART1		(S3C_VA_UART + 0x400)
+#define S3C_VA_UART2		(S3C_VA_UART + 0x800)
+#define S3C_VA_UART3		(S3C_VA_UART + 0xC00)
+#define S3C_UART_OFFSET		0x400
+#define S3C_VA_UARTx(x)		(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+
+#define S3C_PA_FB		S5PC110_PA_FB
+#define S3C_VA_VIC0		(S3C_VA_IRQ + 0x0)
+#define S3C_VA_VIC1		(S3C_VA_IRQ + 0x10000)
+#define S3C_VA_VIC2		(S3C_VA_IRQ + 0x20000)
+#define S3C_VA_VIC3		(S3C_VA_IRQ + 0x30000)
+#define S3C_PA_IIC		S5PC110_PA_I2C
+#define S3C_PA_IIC1		S5PC110_PA_I2C1
+#define S3C_PA_IIC2		S5PC110_PA_I2C2
+#define S3C_PA_USB_HSOTG	S5PC110_PA_USB_HSOTG
+#define S3C_PA_USB_HSPHY	S5PC110_PA_USB_HSPHY
+#define S3C_PA_HSMMC0		S5PC110_PA_HSMMC0
+#define S3C_PA_HSMMC1		S5PC110_PA_HSMMC1
+#define S3C_PA_HSMMC2		S5PC110_PA_HSMMC2
+#define S3C_PA_KEYPAD		S5PC110_PA_KEYPAD
+#define S3C_PA_TSADC		S5PC110_PA_TSADC
+
+#endif /* __ASM_ARCH_C100_MAP_H */
-- 
1.6.4

[PATCH 11/20] ARM: S5PC1XX: add S5PC110 cpu initialization code

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds CPU initialization code for S5PC110 sub-platform.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Byungho Min <bhmin@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/mach-s5pc110/Kconfig                    |   17 +++
 arch/arm/mach-s5pc110/Makefile                   |   18 ++++
 arch/arm/mach-s5pc110/Makefile.boot              |    2 +
 arch/arm/mach-s5pc110/cpu.c                      |  117 ++++++++++++++++++++++
 arch/arm/mach-s5pc110/include/mach/debug-macro.S |   54 ++++++++++
 arch/arm/mach-s5pc110/include/mach/entry-macro.S |   56 ++++++++++
 arch/arm/mach-s5pc110/include/mach/system.h      |   31 ++++++
 arch/arm/mach-s5pc110/include/plat/regs-power.h  |   79 +++++++++++++++
 arch/arm/mach-s5pc110/uarts.c                    |   28 +++++
 arch/arm/plat-s5pc1xx/cpu.c                      |    9 ++
 arch/arm/plat-s5pc1xx/include/plat/s5pc110.h     |   36 +++++++
 arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h     |    1 +
 12 files changed, 448 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/Kconfig
 create mode 100644 arch/arm/mach-s5pc110/Makefile
 create mode 100644 arch/arm/mach-s5pc110/Makefile.boot
 create mode 100644 arch/arm/mach-s5pc110/cpu.c
 create mode 100644 arch/arm/mach-s5pc110/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-s5pc110/include/mach/entry-macro.S
 create mode 100644 arch/arm/mach-s5pc110/include/mach/system.h
 create mode 100644 arch/arm/mach-s5pc110/include/plat/regs-power.h
 create mode 100644 arch/arm/mach-s5pc110/uarts.c
 create mode 100644 arch/arm/plat-s5pc1xx/include/plat/s5pc110.h

diff --git a/arch/arm/mach-s5pc110/Kconfig b/arch/arm/mach-s5pc110/Kconfig
new file mode 100644
index 0000000..4257b96
--- /dev/null
+++ b/arch/arm/mach-s5pc110/Kconfig
@@ -0,0 +1,17 @@
+# arch/arm/mach-s5pc110/Kconfig
+#
+#  Copyright 2009 Samsung Electronics Co.
+#  Kyungmin Park <kyungmin.park@samsung.com>
+#
+# Licensed under GPLv2
+
+if ARCH_S5PC110
+
+# Configuration options for the S5PC110 CPU
+
+config CPU_S5PC110
+	bool
+	help
+	  Enable S5PC110 CPU support
+
+endif
diff --git a/arch/arm/mach-s5pc110/Makefile b/arch/arm/mach-s5pc110/Makefile
new file mode 100644
index 0000000..d9fecf0
--- /dev/null
+++ b/arch/arm/mach-s5pc110/Makefile
@@ -0,0 +1,18 @@
+# arch/arm/mach-s5pc100/Makefile
+#
+# Copyright 2009 Samsung Electronics Co.
+#
+# Licensed under GPLv2
+
+obj-y                           :=
+obj-m                           :=
+obj-n                           :=
+obj-                            :=
+
+# Core support for S5PC110 system
+
+obj-$(CONFIG_CPU_S5PC110)	+= cpu.o
+
+# Helper and device support
+
+# machine support
diff --git a/arch/arm/mach-s5pc110/Makefile.boot b/arch/arm/mach-s5pc110/Makefile.boot
new file mode 100644
index 0000000..b0909e3
--- /dev/null
+++ b/arch/arm/mach-s5pc110/Makefile.boot
@@ -0,0 +1,2 @@
+   zreladdr-y	:= 0x30008000
+params_phys-y	:= 0x30000100
diff --git a/arch/arm/mach-s5pc110/cpu.c b/arch/arm/mach-s5pc110/cpu.c
new file mode 100644
index 0000000..1a4a5e4
--- /dev/null
+++ b/arch/arm/mach-s5pc110/cpu.c
@@ -0,0 +1,117 @@
+/* linux/arch/arm/mach-s5pc110/cpu.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Based on mach-s3c6410/cpu.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+
+#include <asm/proc-fns.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/regs-serial.h>
+#include <plat/regs-power.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/sdhci.h>
+#include <plat/iic-core.h>
+#include <plat/s5pc1xx.h>
+
+/* Initial IO mappings */
+
+static struct map_desc s5pc110_iodesc[] __initdata = {
+};
+
+static void s5pc110_idle(void)
+{
+	unsigned long tmp;
+
+	tmp = __raw_readl(S5PC110_IDLE_CFG);
+	tmp &= ~(S5PC110_IDLECFG_TOP_LOGIC_MASK |
+			S5PC110_IDLECFG_TOP_MEMORY_MASK |
+			S5PC110_IDLECFG_OSC_EN);
+	tmp |= S5PC110_IDLECFG_TOP_LOGIC_ON |
+		S5PC110_IDLECFG_TOP_MEMORY_ON;
+	__raw_writel(tmp, S5PC110_IDLE_CFG);
+
+	tmp = __raw_readl(S5PC110_PWR_CFG);
+	tmp &= ~S5PC110_PWRCFG_CFG_WFI_MASK;
+	/* S5pc110 EVT0 chip bug */
+	/* tmp |= S5PC110_PWRCFG_CFG_WFI_IDLE; */
+	__raw_writel(tmp, S5PC110_PWR_CFG);
+
+	tmp = __raw_readl(S5PC110_OTHERS);
+	tmp |= S5PC110_SYSCON_INT_DISABLE;
+	__raw_writel(tmp, S5PC110_OTHERS);
+
+	cpu_do_idle();
+}
+
+/* s5pc110_map_io
+ *
+ * register the standard cpu IO areas
+*/
+
+void __init s5pc110_map_io(void)
+{
+	iotable_init(s5pc110_iodesc, ARRAY_SIZE(s5pc110_iodesc));
+
+	/* initialise device information early */
+}
+
+void __init s5pc110_init_clocks(int xtal)
+{
+	printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
+	s3c24xx_register_baseclocks(xtal);
+}
+
+void __init s5pc110_init_irq(void)
+{
+}
+
+struct sysdev_class s5pc110_sysclass = {
+	.name	= "s5pc110-core",
+};
+
+static struct sys_device s5pc110_sysdev = {
+	.cls	= &s5pc110_sysclass,
+};
+
+static int __init s5pc110_core_init(void)
+{
+	return sysdev_class_register(&s5pc110_sysclass);
+}
+
+core_initcall(s5pc110_core_init);
+
+int __init s5pc110_init(void)
+{
+	printk(KERN_DEBUG "S5PC110: Initialising architecture\n");
+
+	s5pc1xx_idle = s5pc110_idle;
+
+	return sysdev_register(&s5pc110_sysdev);
+}
diff --git a/arch/arm/mach-s5pc110/include/mach/debug-macro.S b/arch/arm/mach-s5pc110/include/mach/debug-macro.S
new file mode 100644
index 0000000..1f75af5
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/mach/debug-macro.S
@@ -0,0 +1,54 @@
+/* arch/arm/mach-s5pc110/include/mach/debug-macro.S
+ *
+ *  Copyright (C) 2009 Samsung Electronics Co.
+ *  Byungho Min <bhmin@samsung.com>
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Based on mach-s3c6400/include/mach/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* pull in the relevant register and map files. */
+
+#include <mach/map.h>
+#include <plat/regs-serial.h>
+
+	/* note, for the boot process to work we have to keep the UART
+	 * virtual address aligned to an 1MiB boundary for the L1
+	 * mapping the head code makes. We keep the UART virtual address
+	 * aligned and add in the offset when we load the value here.
+	 */
+
+	.macro addruart, rx
+		mrc	p15, 0, \rx, c1, c0
+		tst	\rx, #1
+		ldreq	\rx, = S3C_PA_UART
+		ldrne	\rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
+		add	\rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
+	.endm
+
+	/*
+	 * S5PC110 has different TXMASK & TXFULL
+	 */
+        .macro fifo_level_s5pc110 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                and     \rd, \rd, #S5PC110_UFSTAT_TXMASK
+        .endm
+
+	.macro  fifo_full_s5pc110 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                tst     \rd, #S5PC110_UFSTAT_TXFULL
+        .endm
+
+#define fifo_level	fifo_level_s5pc110
+#define fifo_full	fifo_full_s5pc110
+
+/* include the reset of the code which will do the work, we're only
+ * compiling for a single cpu processor type so the default of s3c2440
+ * will be fine with us.
+ */
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5pc110/include/mach/entry-macro.S b/arch/arm/mach-s5pc110/include/mach/entry-macro.S
new file mode 100644
index 0000000..7695b9d
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/mach/entry-macro.S
@@ -0,0 +1,56 @@
+/* arch/arm/mach-s5pc110/include/mach/entry-macro.S
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Based on mach-s3c6400/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for the Samsung S5PC110 series
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+#include <asm/hardware/vic.h>
+#include <mach/map.h>
+#include <plat/irqs.h>
+
+	.macro	disable_fiq
+	.endm
+
+	.macro	get_irqnr_preamble, base, tmp
+	ldr	\base, =S3C_VA_VIC0
+	.endm
+
+	.macro	arch_ret_to_user, tmp1, tmp2
+	.endm
+
+	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+	@ check the vic0
+	mov	\irqnr, # S3C_IRQ_OFFSET + 31
+	ldr	\irqstat, [ \base, # VIC_IRQ_STATUS ]
+	teq	\irqstat, #0
+
+	@ otherwise try vic1
+	addeq	\tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0)
+	addeq	\irqnr, \irqnr, #32
+	ldreq	\irqstat, [ \tmp, # VIC_IRQ_STATUS ]
+	teqeq	\irqstat, #0
+
+	@ otherwise try vic2
+	addeq	\tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0)
+	addeq	\irqnr, \irqnr, #32
+	ldreq	\irqstat, [ \tmp, # VIC_IRQ_STATUS ]
+	teqeq	\irqstat, #0
+
+	@ otherwise try vic3
+	addeq	\tmp, \base, #(S3C_VA_VIC3 - S3C_VA_VIC0)
+	addeq	\irqnr, \irqnr, #32
+	ldreq	\irqstat, [ \tmp, # VIC_IRQ_STATUS ]
+	teqeq	\irqstat, #0
+
+	clzne	\irqstat, \irqstat
+	subne	\irqnr, \irqnr, \irqstat
+	.endm
diff --git a/arch/arm/mach-s5pc110/include/mach/system.h b/arch/arm/mach-s5pc110/include/mach/system.h
new file mode 100644
index 0000000..be40aa6
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/mach/system.h
@@ -0,0 +1,31 @@
+/* linux/arch/arm/mach-s5pc110/include/mach/system.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC110 - system implementation
+ *
+ * Based on mach-s3c6400/include/mach/system.h
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H __FILE__
+
+#include <linux/io.h>
+#include <mach/map.h>
+#include <plat/regs-clock.h>
+
+void (*s5pc1xx_idle)(void);
+
+static void arch_idle(void)
+{
+	if (s5pc1xx_idle)
+		s5pc1xx_idle();
+}
+
+static void arch_reset(char mode, const char *cmd)
+{
+	__raw_writel(0x1, S5PC110_SWRESET);
+	return;
+}
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pc110/include/plat/regs-power.h b/arch/arm/mach-s5pc110/include/plat/regs-power.h
new file mode 100644
index 0000000..db0880a
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/plat/regs-power.h
@@ -0,0 +1,79 @@
+/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *
+ * S5PC110 power control register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARM_REGS_PWR
+#define __ASM_ARM_REGS_PWR __FILE__
+
+#define S5PC1XX_PWRREG(x)			(S5PC1XX_VA_PWR + (x))
+
+/* s5pc110 (0xE010C000) register for power management */
+#define S5PC110_PWR_CFG				S5PC1XX_PWRREG(0x0)
+#define S5PC110_EINT_WAKEUP_MASK		S5PC1XX_PWRREG(0x4)
+#define S5PC110_WAKEUP_MASK			S5PC1XX_PWRREG(0x8)
+#define S5PC110_NORMAL_CFG			S5PC1XX_PWRREG(0x10)
+#define S5PC110_IDLE_CFG			S5PC1XX_PWRREG(0x20)
+#define S5PC110_STOP_CFG			S5PC1XX_PWRREG(0x30)
+#define S5PC110_STOP_MEM_CFG			S5PC1XX_PWRREG(0x34)
+#define S5PC110_SLEEP_CFG			S5PC1XX_PWRREG(0x40)
+#define S5PC110_OSC_FREQ			S5PC1XX_PWRREG(0x100)
+#define S5PC110_OSC_STABLE			S5PC1XX_PWRREG(0x104)
+#define S5PC110_PWR_STABLE			S5PC1XX_PWRREG(0x108)
+#define S5PC110_MTC_STABLE			S5PC1XX_PWRREG(0x110)
+#define S5PC110_CLAMP_STABLE			S5PC1XX_PWRREG(0x114)
+#define S5PC110_WAKEUP_STAT			S5PC1XX_PWRREG(0x200)
+#define S5PC110_BLK_PWR_STAT			S5PC1XX_PWRREG(0x204)
+#define S5PC110_BODY_BIAS_CON			S5PC1XX_PWRREG(0x300)
+#define S5PC110_ION_SKEW_CON			S5PC1XX_PWRREG(0x310)
+#define S5PC110_ION_SKEW_MON			S5PC1XX_PWRREG(0x314)
+#define S5PC110_IOFF_SKEW_CON			S5PC1XX_PWRREG(0x320)
+#define S5PC110_IOFF_SKEW_MON			S5PC1XX_PWRREG(0x324)
+#define S5PC110_OTHERS				S5PC1XX_PWRREG(0x2000)
+#define S5PC110_OM_STAT				S5PC1XX_PWRREG(0x2100)
+#define S5PC110_MIE_CONTROL			S5PC1XX_PWRREG(0x2800)
+#define S5PC110_HDMI_CONTROL			S5PC1XX_PWRREG(0x2804)
+#define S5PC110_USB_PHY_CONTROL			S5PC1XX_PWRREG(0x280C)
+#define S5PC110_DAC_CONTROL			S5PC1XX_PWRREG(0x2810)
+#define S5PC110_MIPI_DPHY_CONTROL		S5PC1XX_PWRREG(0x2814)
+#define S5PC110_ADC_CONTROL			S5PC1XX_PWRREG(0x2818)
+#define S5PC110_PS_HOLD_CONTROL			S5PC1XX_PWRREG(0x281C)
+#define S5PC110_INFORM0				S5PC1XX_PWRREG(0x3000)
+#define S5PC110_INFORM1				S5PC1XX_PWRREG(0x3004)
+#define S5PC110_INFORM2				S5PC1XX_PWRREG(0x3008)
+#define S5PC110_INFORM3				S5PC1XX_PWRREG(0x300C)
+#define S5PC110_INFORM4				S5PC1XX_PWRREG(0x3010)
+#define S5PC110_INFORM5				S5PC1XX_PWRREG(0x3014)
+#define S5PC110_INFORM6				S5PC1XX_PWRREG(0x3018)
+#define S5PC110_INFORM7				S5PC1XX_PWRREG(0x301C)
+
+/* PWR_CFG */
+#define S5PC110_PWRCFG_CFG_WFI_MASK		(3 << 8)
+#define S5PC110_PWRCFG_CFG_WFI_IGNORE		(0 << 8)
+#define S5PC110_PWRCFG_CFG_WFI_IDLE		(1 << 8)
+#define S5PC110_PWRCFG_CFG_WFI_STOP		(2 << 8)
+#define S5PC110_PWRCFG_CFG_WFI_SLEEP		(3 << 8)
+
+/* IDLE_CFG */
+#define S5PC110_IDLECFG_TOP_LOGIC_MASK		(3 << 30)
+#define S5PC110_IDLECFG_TOP_LOGIC_RET		(1 << 30)
+#define S5PC110_IDLECFG_TOP_LOGIC_ON		(2 << 30)
+#define S5PC110_IDLECFG_TOP_MEMORY_MASK		(3 << 28)
+#define S5PC110_IDLECFG_TOP_MEMORY_RET		(1 << 28)
+#define S5PC110_IDLECFG_TOP_MEMORY_ON		(2 << 28)
+#define S5PC110_IDLECFG_OSC_EN			(1 << 0)
+
+/* SLEEP_CFG */
+#define S5PC110_SLEEP_OSCUSB_EN			(1 << 1)
+#define S5PC110_SLEEP_OSC_EN			(1 << 0)
+
+/* OTHERS */
+#define S5PC110_SYSCON_INT_DISABLE		(1 << 0)
+
+#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/mach-s5pc110/uarts.c b/arch/arm/mach-s5pc110/uarts.c
new file mode 100644
index 0000000..7e63f77
--- /dev/null
+++ b/arch/arm/mach-s5pc110/uarts.c
@@ -0,0 +1,28 @@
+/*
+ * linux/arch/arm/mach-s5pc110/uarts.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *
+ * S5PC110 - CPU initialisation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/s5pc1xx.h>
+
+/* uart registration process */
+
+void __init s5pc110_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+	/* The driver name is s5pc1xx-uart to reuse s5pc1xx_serial_drv  */
+	s3c24xx_init_uartdevs("s5pc110-uart", s5pc1xx_uart_resources, cfg, no);
+}
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c
index d30998d..893d433 100644
--- a/arch/arm/plat-s5pc1xx/cpu.c
+++ b/arch/arm/plat-s5pc1xx/cpu.c
@@ -36,6 +36,7 @@
 /* table of supported CPUs */
 
 static const char name_s5pc100[] = "S5PC100";
+static const char name_s5pc110[] = "S5PC110";
 
 static struct cpu_table cpu_ids[] __initdata = {
 	{
@@ -46,6 +47,14 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.init_uarts	= s5pc100_init_uarts,
 		.init		= s5pc100_init,
 		.name		= name_s5pc100,
+	}, {
+		.idcode		= 0x43110000,
+		.idmask		= 0xfffff000,
+		.map_io		= s5pc110_map_io,
+		.init_clocks	= s5pc110_init_clocks,
+		.init_uarts	= s5pc110_init_uarts,
+		.init		= s5pc110_init,
+		.name		= name_s5pc110,
 	},
 };
 /* minimal IO mapping */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h
new file mode 100644
index 0000000..93c623b
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h
@@ -0,0 +1,36 @@
+/* arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Header file for s5pc100 cpu support
+ *
+ * Based on plat-s3c64xx/include/plat/s3c6400.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for S5PC110 related SoCs */
+
+#ifdef CONFIG_CPU_S5PC110
+
+extern void s5pc110_map_io(void);
+extern void s5pc110_init_clocks(int xtal);
+extern void s5pc110_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern  int s5pc110_init(void);
+
+extern void s5pc110_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s5pc110_init_irq(void);
+extern void s5pc110_register_clocks(void);
+extern void s5pc110_setup_clocks(void);
+
+#else
+
+#define s5pc110_map_io NULL
+#define s5pc110_init_clocks NULL
+#define s5pc110_init_uarts NULL
+#define s5pc110_init NULL
+
+#endif
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h
index 398251f..d8d7a43 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc1xx.h
@@ -19,3 +19,4 @@ extern void s5pc1xx_register_clocks(void);
 extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
 
 #include <plat/s5pc100.h>
+#include <plat/s5pc110.h>
-- 
1.6.4

[PATCH 12/20] ARM: S5PC1XX: add support for s5pc110 plls and clocks

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds clocks and plls definition for S5PC110 SoCs.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Byungho Min <bhmin@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/mach-s5pc100/plls.c                    |    8 +-
 arch/arm/mach-s5pc110/Makefile                  |    3 +
 arch/arm/mach-s5pc110/clocks.c                  |  249 +++++
 arch/arm/mach-s5pc110/cpu.c                     |    3 +
 arch/arm/mach-s5pc110/include/plat/regs-clock.h |  347 ++++++
 arch/arm/mach-s5pc110/plls.c                    | 1287 +++++++++++++++++++++++
 arch/arm/plat-s5pc1xx/include/plat/pll.h        |    8 +-
 arch/arm/plat-s5pc1xx/include/plat/s5pc110.h    |   19 +
 8 files changed, 1918 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/clocks.c
 create mode 100644 arch/arm/mach-s5pc110/include/plat/regs-clock.h
 create mode 100644 arch/arm/mach-s5pc110/plls.c

diff --git a/arch/arm/mach-s5pc100/plls.c b/arch/arm/mach-s5pc100/plls.c
index 970f49d..595c007 100644
--- a/arch/arm/mach-s5pc100/plls.c
+++ b/arch/arm/mach-s5pc100/plls.c
@@ -1050,10 +1050,10 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
 
 	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 
-	apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON));
-	mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON));
-	epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON));
-	hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
+	apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON), 0);
+	mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON), 0);
+	epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON), 0);
+	hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON), 0);
 
 	printk(KERN_INFO "S5PC100: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz"
 		", Epll=%ld.%03ld Mhz, Hpll=%ld.%03ld Mhz\n",
diff --git a/arch/arm/mach-s5pc110/Makefile b/arch/arm/mach-s5pc110/Makefile
index d9fecf0..4dfb306 100644
--- a/arch/arm/mach-s5pc110/Makefile
+++ b/arch/arm/mach-s5pc110/Makefile
@@ -12,6 +12,9 @@ obj-                            :=
 # Core support for S5PC110 system
 
 obj-$(CONFIG_CPU_S5PC110)	+= cpu.o
+obj-$(CONFIG_CPU_S5PC110)	+= clocks.o
+obj-$(CONFIG_CPU_S5PC110)	+= plls.o
+obj-$(CONFIG_CPU_S5PC110)	+= uarts.o
 
 # Helper and device support
 
diff --git a/arch/arm/mach-s5pc110/clocks.c b/arch/arm/mach-s5pc110/clocks.c
new file mode 100644
index 0000000..75cf28e
--- /dev/null
+++ b/arch/arm/mach-s5pc110/clocks.c
@@ -0,0 +1,249 @@
+/* linux/arch/arm/mach-s5pc110/clocks.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *
+ * S5PC110 - Clocks support
+ *
+ * Based on plat-s3c64xx/clock.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/regs-clock.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/s5pc110.h>
+
+struct clk clk_27m = {
+	.name		= "clk_27m",
+	.id		= -1,
+	.rate		= 27000000,
+};
+
+struct clk clk_48m = {
+	.name		= "clk_48m",
+	.id		= -1,
+	.rate		= 48000000,
+};
+
+struct clk clk_54m = {
+	.name		= "clk_54m",
+	.id		= -1,
+	.rate		= 54000000,
+};
+
+struct clk clk_30m = {
+	.name		= "clk_30m",
+	.id		= -1,
+	.rate		= 30000000,
+};
+
+static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
+{
+	unsigned int ctrlbit = clk->ctrlbit;
+	u32 con;
+
+	con = __raw_readl(reg);
+	if (enable)
+		con |= ctrlbit;
+	else
+		con &= ~ctrlbit;
+	__raw_writel(con, reg);
+
+	return 0;
+}
+
+int s5pc110_ip0_ctrl(struct clk *clk, int enable)
+{
+	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP0, clk, enable);
+}
+
+int s5pc110_ip1_ctrl(struct clk *clk, int enable)
+{
+	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP1, clk, enable);
+}
+
+int s5pc110_ip2_ctrl(struct clk *clk, int enable)
+{
+	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP2, clk, enable);
+}
+
+int s5pc110_ip3_ctrl(struct clk *clk, int enable)
+{
+	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP3, clk, enable);
+}
+
+int s5pc110_ip4_ctrl(struct clk *clk, int enable)
+{
+	return s5pc1xx_clk_gate(S5PC110_CLKGATE_IP4, clk, enable);
+}
+
+static struct clk s5pc110_soc_init_clocks_disable[] = {
+	{
+		.name		= "keypad",
+		.id		= -1,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_KEYIF,
+	},
+};
+
+static struct clk s5pc110_soc_init_clocks[] = {
+	/* IP0 */
+	{
+		.name		= "mfc",
+		.id		= -1,
+		.parent		= NULL,
+		.enable		= s5pc110_ip0_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP0_MFC,
+	},
+
+	/* IP1 */
+	{
+		.name		= "lcd",
+		.id		= -1,
+		.parent		= &clk_dout_hclkd,
+		.enable		= s5pc110_ip1_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP1_FIMD,
+	}, {
+		.name		= "otg",
+		.id		= -1,
+		.parent		= &clk_dout_hclkp,
+		.enable		= s5pc110_ip1_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP1_USBOTG,
+	},
+
+	/* IP2 */
+	{
+		.name		= "hsmmc",
+		.id		= 0,
+		.parent		= &clk_dout_hclkp,
+		.enable		= s5pc110_ip2_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC0,
+	}, {
+		.name		= "hsmmc",
+		.id		= 1,
+		.parent		= &clk_dout_hclkp,
+		.enable		= s5pc110_ip2_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC1,
+	}, {
+		.name		= "hsmmc",
+		.id		= 2,
+		.parent		= &clk_dout_hclkp,
+		.enable		= s5pc110_ip2_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC2,
+	}, {
+		.name		= "hsmmc",
+		.id		= 3,
+		.parent		= &clk_dout_hclkp,
+		.enable		= s5pc110_ip2_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC3,
+	},
+	/* IP3 */
+	{
+		.name           = "iis",
+		.id             = 0,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_I2S0,
+	}, {
+		.name           = "iis",
+		.id             = 1,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_I2S1,
+	}, {
+		.name           = "iis",
+		.id             = 2,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_I2S2,
+	}, {
+		.name		= "i2c",
+		.id		= 0,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_I2C0,
+	}, {
+		.name		= "i2c",
+		.id		= 1,
+		.parent		= &clk_dout_pclkd,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_I2C1,
+	}, {
+		.name		= "i2c",
+		.id		= 2,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_I2C2,
+	}, {
+		.name		= "timers",
+		.id		= -1,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_PWM,
+	}, {
+		.name		= "adc",
+		.id		= -1,
+		.parent		= &clk_dout_pclkp,
+		.enable		= s5pc110_ip3_ctrl,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_TSADC,
+	},
+};
+
+static struct clk *clks[] __initdata = {
+	&clk_ext,
+	&clk_epll,
+	&clk_27m,
+	&clk_30m,
+	&clk_48m,
+	&clk_54m,
+};
+
+void __init s5pc1xx_register_clocks(void)
+{
+	struct clk *clkp;
+	int ret;
+	int ptr;
+	int size;
+
+	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+
+	clkp = s5pc110_soc_init_clocks;
+	size = ARRAY_SIZE(s5pc110_soc_init_clocks);
+
+	for (ptr = 0; ptr < size; ptr++, clkp++) {
+		ret = s3c24xx_register_clock(clkp);
+		if (ret < 0) {
+			printk(KERN_ERR "Failed to register clock %s (%d)\n",
+			       clkp->name, ret);
+		}
+	}
+
+	clkp = s5pc110_soc_init_clocks_disable;
+	size = ARRAY_SIZE(s5pc110_soc_init_clocks_disable);
+
+	for (ptr = 0; ptr < size; ptr++, clkp++) {
+		ret = s3c24xx_register_clock(clkp);
+		if (ret < 0) {
+			printk(KERN_ERR "Failed to register clock %s (%d)\n",
+			       clkp->name, ret);
+		}
+
+		(clkp->enable)(clkp, 0);
+	}
+
+	s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-s5pc110/cpu.c b/arch/arm/mach-s5pc110/cpu.c
index 1a4a5e4..6c9ebcb 100644
--- a/arch/arm/mach-s5pc110/cpu.c
+++ b/arch/arm/mach-s5pc110/cpu.c
@@ -86,6 +86,9 @@ void __init s5pc110_init_clocks(int xtal)
 {
 	printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
 	s3c24xx_register_baseclocks(xtal);
+	s5pc1xx_register_clocks();
+	s5pc110_register_clocks();
+	s5pc110_setup_clocks();
 }
 
 void __init s5pc110_init_irq(void)
diff --git a/arch/arm/mach-s5pc110/include/plat/regs-clock.h b/arch/arm/mach-s5pc110/include/plat/regs-clock.h
new file mode 100644
index 0000000..4305a07
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/plat/regs-clock.h
@@ -0,0 +1,347 @@
+/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC110 clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_CLOCK_H
+#define __PLAT_REGS_CLOCK_H __FILE__
+
+#define S5PC1XX_CLKREG(x)		(S5PC1XX_VA_CLK + (x))
+
+/* s5pc110 register for clock */
+#define S5PC110_APLL_LOCK		S5PC1XX_CLKREG(0x00)
+#define S5PC110_MPLL_LOCK		S5PC1XX_CLKREG(0x08)
+#define S5PC110_EPLL_LOCK		S5PC1XX_CLKREG(0x10)
+#define S5PC110_VPLL_LOCK		S5PC1XX_CLKREG(0x20)
+
+#define S5PC110_APLL_CON		S5PC1XX_CLKREG(0x100)
+#define S5PC110_MPLL_CON		S5PC1XX_CLKREG(0x108)
+#define S5PC110_EPLL_CON		S5PC1XX_CLKREG(0x110)
+#define S5PC110_VPLL_CON		S5PC1XX_CLKREG(0x120)
+
+#define S5PC110_CLKSRC0			S5PC1XX_CLKREG(0x200)
+#define S5PC110_CLKSRC1			S5PC1XX_CLKREG(0x204)
+#define S5PC110_CLKSRC2			S5PC1XX_CLKREG(0x208)
+#define S5PC110_CLKSRC3			S5PC1XX_CLKREG(0x20C)
+#define S5PC110_CLKSRC4			S5PC1XX_CLKREG(0x210)
+#define S5PC110_CLKSRC5			S5PC1XX_CLKREG(0x214)
+#define S5PC110_CLKSRC6			S5PC1XX_CLKREG(0x218)
+
+#define S5PC110_CLKSRC_MASK0		S5PC1XX_CLKREG(0x280)
+#define S5PC110_CLKSRC_MASK1		S5PC1XX_CLKREG(0x284)
+
+#define S5PC110_CLKDIV0		S5PC1XX_CLKREG(0x300)
+#define S5PC110_CLKDIV1		S5PC1XX_CLKREG(0x304)
+#define S5PC110_CLKDIV2		S5PC1XX_CLKREG(0x308)
+#define S5PC110_CLKDIV3		S5PC1XX_CLKREG(0x30C)
+#define S5PC110_CLKDIV4		S5PC1XX_CLKREG(0x310)
+#define S5PC110_CLKDIV5		S5PC1XX_CLKREG(0x314)
+#define S5PC110_CLKDIV6		S5PC1XX_CLKREG(0x318)
+#define S5PC110_CLKDIV7		S5PC1XX_CLKREG(0x31C)
+
+#define S5PC110_CLKGATE_IP0		S5PC1XX_CLKREG(0x460)
+#define S5PC110_CLKGATE_IP1		S5PC1XX_CLKREG(0x464)
+#define S5PC110_CLKGATE_IP2		S5PC1XX_CLKREG(0x468)
+#define S5PC110_CLKGATE_IP3		S5PC1XX_CLKREG(0x46C)
+#define S5PC110_CLKGATE_IP4		S5PC1XX_CLKREG(0x470)
+#define S5PC110_CLKGATE_BLOCK		S5PC1XX_CLKREG(0x480)
+#define S5PC110_CLKGATE_BUS0		S5PC1XX_CLKREG(0x484)
+#define S5PC110_CLKGATE_BUS1		S5PC1XX_CLKREG(0x488)
+
+#define S5PC110_CLK_OUT			S5PC1XX_CLKREG(0x500)
+#define S5PC110_MDNIE_SEL		S5PC1XX_CLKREG(0x7008)
+
+#define S5PC110_CLKDIV_STAT0		S5PC1XX_CLKREG(0x1000)
+#define S5PC110_CLKDIV_STAT1		S5PC1XX_CLKREG(0x1004)
+
+#define S5PC110_CLK_MUX_STAT0		S5PC1XX_CLKREG(0x1100)
+#define S5PC110_CLK_MUX_STAT1		S5PC1XX_CLKREG(0x1104)
+
+#define S5PC110_SWRESET		S5PC1XX_CLKREG(0x2000)
+
+#define S5PC110_CLKSRC0_APLL_MASK		(0x1<<0)
+#define S5PC110_CLKSRC0_APLL_SHIFT		(0)
+#define S5PC110_CLKSRC0_MPLL_MASK		(0x1<<4)
+#define S5PC110_CLKSRC0_MPLL_SHIFT		(4)
+#define S5PC110_CLKSRC0_EPLL_MASK		(0x1<<8)
+#define S5PC110_CLKSRC0_EPLL_SHIFT		(8)
+#define S5PC110_CLKSRC0_VPLL_MASK		(0x1<<12)
+#define S5PC110_CLKSRC0_VPLL_SHIFT		(12)
+#define S5PC110_CLKSRC0_MUX200_MASK		(0x1<<16)
+#define S5PC110_CLKSRC0_MUX200_SHIFT		(16)
+#define S5PC110_CLKSRC0_MUX166_MASK		(0x1<<20)
+#define S5PC110_CLKSRC0_MUX166_SHIFT		(20)
+#define S5PC110_CLKSRC0_MUX133_MASK		(0x1<<24)
+#define S5PC110_CLKSRC0_MUX133_SHIFT		(24)
+#define S5PC110_CLKSRC0_ONENAND_MASK		(0x1<<28)
+#define S5PC110_CLKSRC0_ONENAND_SHIFT		(28)
+
+#define S5PC110_CLKSRC1_HDMI_MASK		(0x1<<0)
+#define S5PC110_CLKSRC1_HDMI_SHIFT		(0)
+#define S5PC110_CLKSRC1_MIXER_MASK		(0x7<<1)
+#define S5PC110_CLKSRC1_MIXER_SHIFT		(1)
+#define S5PC110_CLKSRC1_DAC_MASK		(0x1<<8)
+#define S5PC110_CLKSRC1_DAC_SHIFT		(8)
+#define S5PC110_CLKSRC1_CAM0_MASK		(0xf<<12)
+#define S5PC110_CLKSRC1_CAM0_SHIFT		(12)
+#define S5PC110_CLKSRC1_CAM1_MASK		(0xf<<16)
+#define S5PC110_CLKSRC1_CAM1_SHIFT		(16)
+#define S5PC110_CLKSRC1_FIMD_MASK		(0xf<<20)
+#define S5PC110_CLKSRC1_FIMD_SHIFT		(20)
+#define S5PC110_CLKSRC1_CSIS_MASK		(0xf<<24)
+#define S5PC110_CLKSRC1_CSIS_SHIFT		(24)
+#define S5PC110_CLKSRC1_VPLLSRC_MASK		(0x1<<28)
+#define S5PC110_CLKSRC1_VPLLSRC_SHIFT		(28)
+
+#define S5PC110_CLKSRC2_G3D_MASK		(0x3<<0)
+#define S5PC110_CLKSRC2_G3D_SHIFT		(0)
+#define S5PC110_CLKSRC2_MFC_MASK		(0x3<<4)
+#define S5PC110_CLKSRC2_MFC_SHIFT		(4)
+
+#define S5PC110_CLKSRC3_MDNIE_MASK		(0xf<<0)
+#define S5PC110_CLKSRC3_MDNIE_SHIFT		(0)
+#define S5PC110_CLKSRC3_MDNIE_PWMCLK_MASK	(0xf<<4)
+#define S5PC110_CLKSRC3_MDNIE_PWMCLK_SHIFT	(4)
+#define S5PC110_CLKSRC3_FIMC0_LCLK_MASK		(0xf<<12)
+#define S5PC110_CLKSRC3_FIMC0_LCLK_SHIFT	(12)
+#define S5PC110_CLKSRC3_FIMC1_LCLK_MASK		(0xf<<16)
+#define S5PC110_CLKSRC3_FIMC1_LCLK_SHIFT	(16)
+#define S5PC110_CLKSRC3_FIMC2_LCLK_MASK		(0xf<<20)
+#define S5PC110_CLKSRC3_FIMC2_LCLK_SHIFT	(20)
+
+/* CLKSRC4 */
+#define S5PC110_CLKSRC4_MMC0_MASK		(0xf<<0)
+#define S5PC110_CLKSRC4_MMC0_SHIFT		(0)
+#define S5PC110_CLKSRC4_MMC1_MASK		(0xf<<4)
+#define S5PC110_CLKSRC4_MMC1_SHIFT		(4)
+#define S5PC110_CLKSRC4_MMC2_MASK		(0xf<<8)
+#define S5PC110_CLKSRC4_MMC2_SHIFT		(8)
+#define S5PC110_CLKSRC4_MMC3_MASK		(0xf<<12)
+#define S5PC110_CLKSRC4_MMC3_SHIFT		(12)
+#define S5PC110_CLKSRC4_UART0_MASK		(0xf<<16)
+#define S5PC110_CLKSRC4_UART0_SHIFT		(16)
+#define S5PC110_CLKSRC4_UART1_MASK		(0xf<<20)
+#define S5PC110_CLKSRC4_UART1_SHIFT		(20)
+#define S5PC110_CLKSRC4_UART2_MASK		(0xf<<24)
+#define S5PC110_CLKSRC4_UART2_SHIFT		(24)
+#define S5PC110_CLKSRC4_UART3_MASK		(0xf<<28)
+#define S5PC110_CLKSRC4_UART3_SHIFT		(28)
+
+/* CLKSRC5 */
+#define S5PC110_CLKSRC5_SPI0_MASK		(0xf<<0)
+#define S5PC110_CLKSRC5_SPI0_SHIFT		(0)
+#define S5PC110_CLKSRC5_SPI1_MASK		(0xf<<4)
+#define S5PC110_CLKSRC5_SPI1_SHIFT		(4)
+#define S5PC110_CLKSRC5_SPI2_MASK		(0xf<<8)
+#define S5PC110_CLKSRC5_SPI2_SHIFT		(8)
+#define S5PC110_CLKSRC5_PWM_MASK		(0xf<<12)
+#define S5PC110_CLKSRC5_PWM_SHIFT		(12)
+
+/* CLKSRC6 */
+#define S5PC110_CLKSRC6_AUDIO0_MASK		(0xf<<0)
+#define S5PC110_CLKSRC6_AUDIO0_SHIFT		(0)
+#define S5PC110_CLKSRC6_AUDIO1_MASK		(0xf<<4)
+#define S5PC110_CLKSRC6_AUDIO1_SHIFT		(4)
+#define S5PC110_CLKSRC6_AUDIO2_MASK		(0xf<<8)
+#define S5PC110_CLKSRC6_AUDIO2_SHIFT		(4)
+#define S5PC110_CLKSRC6_SPDIF_MASK		(0x3<<12)
+#define S5PC110_CLKSRC6_SPDIF_SHIFT		(12)
+#define S5PC110_CLKSRC6_HPM_MASK		(0x1<<16)
+#define S5PC110_CLKSRC6_HPM_SHIFT		(16)
+#define S5PC110_CLKSRC6_PWI_MASK		(0xf<<20)
+#define S5PC110_CLKSRC6_PWI_SHIFT		(20)
+#define S5PC110_CLKSRC6_ONEDRAM_MASK		(0x3<<24)
+#define S5PC110_CLKSRC6_ONEDRAM_SHIFT		(24)
+
+#define S5PC110_CLKDIV0_APLL_MASK		(0x7<<0)
+#define S5PC110_CLKDIV0_APLL_SHIFT		(0)
+#define S5PC110_CLKDIV0_A2M_MASK		(0x7<<4)
+#define S5PC110_CLKDIV0_A2M_SHIFT		(4)
+#define S5PC110_CLKDIV0_HCLK_MSYS_MASK		(0x7<<8)
+#define S5PC110_CLKDIV0_HCLK_MSYS_SHIFT	(8)
+#define S5PC110_CLKDIV0_PCLK_MSYS_MASK		(0x7<<12)
+#define S5PC110_CLKDIV0_PCLK_MSYS_SHIFT	(12)
+#define S5PC110_CLKDIV0_HCLK_DSYS_MASK		(0xf<<16)
+#define S5PC110_CLKDIV0_HCLK_DSYS_SHIFT	(16)
+#define S5PC110_CLKDIV0_PCLK_DSYS_MASK		(0x7<<20)
+#define S5PC110_CLKDIV0_PCLK_DSYS_SHIFT	(20)
+#define S5PC110_CLKDIV0_HCLK_PSYS_MASK		(0xf<<24)
+#define S5PC110_CLKDIV0_HCLK_PSYS_SHIFT	(24)
+#define S5PC110_CLKDIV0_PCLK_PSYS_MASK		(0x7<<28)
+#define S5PC110_CLKDIV0_PCLK_PSYS_SHIFT	(28)
+
+#define S5PC110_CLKDIV1_TBLK_MASK		(0xf<<0)
+#define S5PC110_CLKDIV1_TBLK_SHIFT		(0)
+#define S5PC110_CLKDIV1_FIMC_MASK		(0xf<<8)
+#define S5PC110_CLKDIV1_FIMC_SHIFT		(8)
+#define S5PC110_CLKDIV1_CAM0_MASK		(0xf<<12)
+#define S5PC110_CLKDIV1_CAM0_SHIFT		(12)
+#define S5PC110_CLKDIV1_CAM1_MASK		(0xf<<16)
+#define S5PC110_CLKDIV1_CAM1_SHIFT		(16)
+#define S5PC110_CLKDIV1_FIMD_MASK		(0xf<<20)
+#define S5PC110_CLKDIV1_FIMD_SHIFT		(20)
+#define S5PC110_CLKDIV1_CSIS_MASK		(0xf<<28)
+#define S5PC110_CLKDIV1_CSIS_SHIFT		(28)
+
+#define S5PC110_CLKDIV2_G3D_MASK		(0xf<<0)
+#define S5PC110_CLKDIV2_G3D_SHIFT		(0)
+#define S5PC110_CLKDIV2_MFC_MASK		(0xf<<4)
+#define S5PC110_CLKDIV2_MFC_SHIFT		(4)
+
+#define S5PC110_CLKDIV3_MDNIE_MASK		(0xf<<0)
+#define S5PC110_CLKDIV3_MDNIE_SHIFT		(0)
+#define S5PC110_CLKDIV3_MDNIE_PWM_MASK		(0x7f<<4)
+#define S5PC110_CLKDIV3_MDNIE_PWM_SHIFT	(4)
+#define S5PC110_CLKDIV3_FIMC0_LCLK_MASK	(0xf<<12)
+#define S5PC110_CLKDIV3_FIMC0_LCLK_SHIFT	(12)
+#define S5PC110_CLKDIV3_FIMC1_LCLK_MASK	(0xf<<16)
+#define S5PC110_CLKDIV3_FIMC1_LCLK_SHIFT	(16)
+#define S5PC110_CLKDIV3_FIMC2_LCLK_MASK	(0xf<<20)
+#define S5PC110_CLKDIV3_FIMC2_LCLK_SHIFT	(20)
+
+#define S5PC110_CLKDIV4_MMC0_MASK		(0xf<<0)
+#define S5PC110_CLKDIV4_MMC0_SHIFT		(0)
+#define S5PC110_CLKDIV4_MMC1_MASK		(0xf<<4)
+#define S5PC110_CLKDIV4_MMC1_SHIFT		(4)
+#define S5PC110_CLKDIV4_MMC2_MASK		(0xf<<8)
+#define S5PC110_CLKDIV4_MMC2_SHIFT		(8)
+#define S5PC110_CLKDIV4_MMC3_MASK		(0xf<<12)
+#define S5PC110_CLKDIV4_MMC3_SHIFT		(12)
+#define S5PC110_CLKDIV4_UART0_MASK		(0xf<<16)
+#define S5PC110_CLKDIV4_UART0_SHIFT		(16)
+#define S5PC110_CLKDIV4_UART1_MASK		(0xf<<20)
+#define S5PC110_CLKDIV4_UART1_SHIFT		(20)
+#define S5PC110_CLKDIV4_UART2_MASK		(0xf<<24)
+#define S5PC110_CLKDIV4_UART2_SHIFT		(24)
+#define S5PC110_CLKDIV4_UART3_MASK		(0xf<<28)
+#define S5PC110_CLKDIV4_UART3_SHIFT		(28)
+
+/* CLK_DIV5 */
+#define S5PC110_CLKDIV5_SPI0_MASK		(0xf<<0)
+#define S5PC110_CLKDIV5_SPI0_SHIFT		(0)
+#define S5PC110_CLKDIV5_SPI1_MASK		(0xf<<4)
+#define S5PC110_CLKDIV5_SPI1_SHIFT		(4)
+#define S5PC110_CLKDIV5_SPI2_MASK		(0xf<<8)
+#define S5PC110_CLKDIV5_SPI2_SHIFT		(8)
+#define S5PC110_CLKDIV5_PWM_MASK		(0xf<<120)
+#define S5PC110_CLKDIV5_PWM_SHIFT		(12)
+
+/* CLK_DIV6 */
+#define S5PC110_CLKDIV6_AUDIO0_MASK		(0xf<<0)
+#define S5PC110_CLKDIV6_AUDIO0_SHIFT		(0)
+#define S5PC110_CLKDIV6_AUDIO1_MASK		(0xf<<4)
+#define S5PC110_CLKDIV6_AUDIO1_SHIFT		(4)
+#define S5PC110_CLKDIV6_AUDIO2_MASK		(0xf<<8)
+#define S5PC110_CLKDIV6_AUDIO2_SHIFT		(8)
+#define S5PC110_CLKDIV6_ONENAND_MASK		(0x7<<12)
+#define S5PC110_CLKDIV6_ONENAND_SHIFT		(12)
+#define S5PC110_CLKDIV6_COPY_MASK		(0x7<<16)
+#define S5PC110_CLKDIV6_COPY_SHIFT		(16)
+#define S5PC110_CLKDIV6_HPM_MASK		(0x7<<20)
+#define S5PC110_CLKDIV6_HPM_SHIFT		(20)
+#define S5PC110_CLKDIV6_PWI_MASK		(0xf<<24)
+#define S5PC110_CLKDIV6_PWI_SHIFT		(24)
+#define S5PC110_CLKDIV6_ONEDRAM_MASK		(0xf<<28)
+#define S5PC110_CLKDIV6_ONEDRAM_SHIFT		(28)
+
+/* Clock Gate IP0 */
+#define S5PC110_CLKGATE_IP0_DMC0		(1<<0)
+#define S5PC110_CLKGATE_IP0_DMC1		(1<<1)
+#define S5PC110_CLKGATE_IP0_MDMA		(1<<2)
+#define S5PC110_CLKGATE_IP0_PDMA0		(1<<3)
+#define S5PC110_CLKGATE_IP0_PDMA1		(1<<4)
+#define S5PC110_CLKGATE_IP0_IMEM		(1<<5)
+#define S5PC110_CLKGATE_IP0_G3D			(1<<8)
+#define S5PC110_CLKGATE_IP0_MFC			(1<<16)
+#define S5PC110_CLKGATE_IP0_FIMC0		(1<<24)
+#define S5PC110_CLKGATE_IP0_FIMC1		(1<<25)
+#define S5PC110_CLKGATE_IP0_FIMC2		(1<<26)
+#define S5PC110_CLKGATE_IP0_JPEG		(1<<28)
+#define S5PC110_CLKGATE_IP0_ROTATOR		(1<<29)
+#define S5PC110_CLKGATE_IP0_IPC			(1<<30)
+#define S5PC110_CLKGATE_IP0_CSIS		(1<<31)
+
+/* Clock Gate IP1 */
+#define S5PC110_CLKGATE_IP1_FIMD		(1<<0)
+#define S5PC110_CLKGATE_IP1_MIE			(1<<1)
+#define S5PC110_CLKGATE_IP1_DSIM		(1<<2)
+#define S5PC110_CLKGATE_IP1_VP			(1<<8)
+#define S5PC110_CLKGATE_IP1_MIXER		(1<<9)
+#define S5PC110_CLKGATE_IP1_TVENC		(1<<10)
+#define S5PC110_CLKGATE_IP1_HDMI		(1<<11)
+#define S5PC110_CLKGATE_IP1_USBOTG		(1<<16)
+#define S5PC110_CLKGATE_IP1_USBHOST		(1<<17)
+#define S5PC110_CLKGATE_IP1_NANDXL		(1<<24)
+#define S5PC110_CLKGATE_IP1_CFCON		(1<<25)
+#define S5PC110_CLKGATE_IP1_SROMC		(1<<26)
+#define S5PC110_CLKGATE_IP1_NFCON		(1<<28)
+
+/* Clock Gate IP2 */
+#define S5PC110_CLKGATE_IP2_SECSS		(1<<0)
+#define S5PC110_CLKGATE_IP2_SDM			(1<<1)
+#define S5PC110_CLKGATE_IP2_CORESIGHT		(1<<8)
+#define S5PC110_CLKGATE_IP2_MODEM		(1<<9)
+#define S5PC110_CLKGATE_IP2_HOSTIF		(1<<10)
+#define S5PC110_CLKGATE_IP2_SECJTAG		(1<<11)
+#define S5PC110_CLKGATE_IP2_HSMMC0		(1<<16)
+#define S5PC110_CLKGATE_IP2_HSMMC1		(1<<17)
+#define S5PC110_CLKGATE_IP2_HSMMC2		(1<<18)
+#define S5PC110_CLKGATE_IP2_HSMMC3		(1<<19)
+#define S5PC110_CLKGATE_IP2_TSI			(1<<20)
+#define S5PC110_CLKGATE_IP2_VIC0		(1<<24)
+#define S5PC110_CLKGATE_IP2_VIC1		(1<<25)
+#define S5PC110_CLKGATE_IP2_VIC2		(1<<26)
+#define S5PC110_CLKGATE_IP2_VIC3		(1<<27)
+#define S5PC110_CLKGATE_IP2_TZIC0		(1<<28)
+#define S5PC110_CLKGATE_IP2_TZIC1		(1<<29)
+#define S5PC110_CLKGATE_IP2_TZIC2		(1<<30)
+#define S5PC110_CLKGATE_IP2_TZIC3		(1<<31)
+
+/* Clock Gate IP3 */
+#define S5PC110_CLKGATE_IP3_SPDIF		(1<<0)
+#define S5PC110_CLKGATE_IP3_AC97		(1<<1)
+#define S5PC110_CLKGATE_IP3_I2S0		(1<<4)
+#define S5PC110_CLKGATE_IP3_I2S1		(1<<5)
+#define S5PC110_CLKGATE_IP3_I2S2		(1<<6)
+#define S5PC110_CLKGATE_IP3_I2C0		(1<<7)
+#define S5PC110_CLKGATE_IP3_I2C1		(1<<8)
+#define S5PC110_CLKGATE_IP3_I2C2		(1<<9)
+#define S5PC110_CLKGATE_IP3_I2C_HDMI_DDC	(1<<10)
+#define S5PC110_CLKGATE_IP3_I2C_HDMI_PHY	(1<<11)
+#define S5PC110_CLKGATE_IP3_SPI0		(1<<12)
+#define S5PC110_CLKGATE_IP3_SPI1		(1<<13)
+#define S5PC110_CLKGATE_IP3_SPI2		(1<<14)
+#define S5PC110_CLKGATE_IP3_RTC			(1<<15)
+#define S5PC110_CLKGATE_IP3_SYSTIMER		(1<<16)
+#define S5PC110_CLKGATE_IP3_UART0		(1<<17)
+#define S5PC110_CLKGATE_IP3_UART1		(1<<18)
+#define S5PC110_CLKGATE_IP3_UART2		(1<<19)
+#define S5PC110_CLKGATE_IP3_UART3		(1<<20)
+#define S5PC110_CLKGATE_IP3_KEYIF		(1<<21)
+#define S5PC110_CLKGATE_IP3_WDT			(1<<22)
+#define S5PC110_CLKGATE_IP3_PWM			(1<<23)
+#define S5PC110_CLKGATE_IP3_TSADC		(1<<24)
+#define S5PC110_CLKGATE_IP3_GPIO		(1<<26)
+#define S5PC110_CLKGATE_IP3_SYSCON		(1<<27)
+#define S5PC110_CLKGATE_IP3_PCM0		(1<<28)
+#define S5PC110_CLKGATE_IP3_PCM1		(1<<29)
+#define S5PC110_CLKGATE_IP3_PCM2		(1<<30)
+
+/* Clock Gate IP4 */
+#define S5PC110_CLKGATE_IP4_CHIP_ID		(1<<0)
+#define S5PC110_CLKGATE_IP4_IEM_IEC		(1<<1)
+#define S5PC110_CLKGATE_IP4_IEM_APC		(1<<2)
+#define S5PC110_CLKGATE_IP4_SECKEY		(1<<3)
+#define S5PC110_CLKGATE_IP4_TZPC0		(1<<5)
+#define S5PC110_CLKGATE_IP4_TZPC1		(1<<6)
+#define S5PC110_CLKGATE_IP4_TZPC2		(1<<7)
+#define S5PC110_CLKGATE_IP4_TZPC3		(1<<8)
+
+#endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pc110/plls.c b/arch/arm/mach-s5pc110/plls.c
new file mode 100644
index 0000000..1799975
--- /dev/null
+++ b/arch/arm/mach-s5pc110/plls.c
@@ -0,0 +1,1287 @@
+/*
+ * linux/arch/arm/mach-s5pc110/plls.c
+ *
+ * Copyright 2009 Samsung Electronics, Co.
+ *
+ * S5PC110 based common clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/cpu-freq.h>
+
+#include <plat/regs-clock.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/devs.h>
+#include <plat/s5pc1xx.h>
+
+static struct clk clk_ext_xtal_mux = {
+	.name		= "ext_xtal",
+	.id		= -1,
+};
+
+#define clk_fin_apll	clk_ext_xtal_mux
+#define clk_fin_mpll	clk_ext_xtal_mux
+#define clk_fin_epll	clk_ext_xtal_mux
+#define clk_fin_vpll	clk_ext_xtal_mux
+#define clk_hdmi_phy	clk_ext_xtal_mux
+
+#define clk_fout_mpll	clk_mpll
+#define clk_hdmi_27m	clk_27m
+#define clk_usbphy0	clk_30m
+#define clk_usbphy1	clk_48m
+
+static struct clk clk_usb_xtal = {
+	.name		= "usb_xtal",
+	.id		= -1,
+};
+
+static struct clk clk_pcm_cd0 = {
+	.name		= "pcm_cdclk0",
+	.id		= -1,
+};
+
+static struct clk clk_pcm_cd1 = {
+	.name		= "pcm_cdclk1",
+	.id		= -1,
+};
+
+static struct clk clk_iis_cd1 = {
+	.name		= "iis_cdclk1",
+	.id		= -1,
+};
+
+struct clk_sources {
+	unsigned int	nr_sources;
+	struct clk	**sources;
+};
+
+struct clksrc_clk {
+	struct clk		clk;
+	unsigned int		mask;
+	unsigned int		shift;
+
+	struct clk_sources	*sources;
+
+	unsigned int		divider_shift;
+	void __iomem		*reg_divider;
+	void __iomem		*reg_source;
+};
+
+/* APLL */
+static struct clk clk_fout_apll = {
+	.name		= "fout_apll",
+	.id		= -1,
+};
+
+static struct clk *clk_src_apll_list[] = {
+	[0] = &clk_fin_apll,
+	[1] = &clk_fout_apll,
+};
+
+static struct clk_sources clk_src_apll = {
+	.sources	= clk_src_apll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),
+};
+
+static struct clksrc_clk clk_mout_apll = {
+	.clk	= {
+		.name		= "mout_apll",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_APLL_SHIFT,
+	.mask		= S5PC110_CLKSRC0_APLL_MASK,
+	.sources	= &clk_src_apll,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+/* MPLL */
+static struct clk *clk_src_mpll_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &clk_fout_mpll,
+};
+
+static struct clk_sources clk_src_mpll = {
+	.sources	= clk_src_mpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_mpll_list),
+};
+
+static struct clksrc_clk clk_mout_mpll = {
+	.clk = {
+		.name		= "mout_mpll",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_MPLL_SHIFT,
+	.mask		= S5PC110_CLKSRC0_MPLL_MASK,
+	.sources	= &clk_src_mpll,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+static int s5pc110_default_enable(struct clk *clk, int enable)
+{
+	return 0;
+}
+
+/* EPLL */
+static struct clk clk_fout_epll = {
+	.name		= "fout_epll",
+	.id		= -1,
+	.enable		= s5pc110_default_enable,
+};
+
+static struct clk *clk_src_epll_list[] = {
+	[0] = &clk_fin_epll,
+	[1] = &clk_fout_epll,
+};
+
+static struct clk_sources clk_src_epll = {
+	.sources	= clk_src_epll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_epll_list),
+};
+
+static struct clksrc_clk clk_mout_epll = {
+	.clk = {
+		.name		= "mout_epll",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_EPLL_SHIFT,
+	.mask		= S5PC110_CLKSRC0_EPLL_MASK,
+	.sources	= &clk_src_epll,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+/* VPLLSRC */
+static struct clk *clk_src_vpllsrc_list[] = {
+	[0] = &clk_fin_vpll,
+	[1] = &clk_hdmi_27m,
+};
+
+static struct clk_sources clk_src_vpllsrc = {
+	.sources	= clk_src_vpllsrc_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_vpllsrc_list),
+};
+
+static struct clksrc_clk clk_mout_vpllsrc = {
+	.clk = {
+		.name		= "mout_vpllsrc",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC1_VPLLSRC_SHIFT,
+	.mask		= S5PC110_CLKSRC1_VPLLSRC_MASK,
+	.sources	= &clk_src_vpllsrc,
+	.reg_source	= S5PC110_CLKSRC1,
+};
+
+/* VPLL */
+static struct clk clk_fout_vpll = {
+	.name		= "fout_vpll",
+	.id		= -1,
+};
+
+static struct clk *clk_src_vpll_list[] = {
+	[0] = &clk_mout_vpllsrc.clk,
+	[1] = &clk_fout_vpll,
+};
+
+static struct clk_sources clk_src_vpll = {
+	.sources	= clk_src_vpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_vpll_list),
+};
+
+static struct clksrc_clk clk_mout_vpll = {
+	.clk = {
+		.name		= "mout_vpll",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_VPLL_SHIFT,
+	.mask		= S5PC110_CLKSRC0_VPLL_MASK,
+	.sources	= &clk_src_vpll,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+/* Dout A2M */
+static unsigned long s5pc110_clk_dout_a2m_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_A2M_MASK;
+	ratio >>= S5PC110_CLKDIV0_A2M_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+static struct clk clk_dout_a2m = {
+	.name		= "dout_a2m",
+	.id		= -1,
+	.parent		= &clk_mout_apll.clk,
+	.get_rate	= s5pc110_clk_dout_a2m_get_rate,
+};
+
+/* HPM */
+static struct clk *clk_src_hpm_list[] = {
+	[0] = &clk_mout_apll.clk,
+	[1] = &clk_mout_mpll.clk,
+};
+
+static struct clk_sources clk_src_hpm = {
+	.sources	= clk_src_hpm_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_hpm_list),
+};
+
+static struct clksrc_clk clk_mout_hpm = {
+	.clk = {
+		.name		= "mout_hpm",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC6_HPM_SHIFT,
+	.mask		= S5PC110_CLKSRC6_HPM_MASK,
+	.sources	= &clk_src_hpm,
+	.reg_source	= S5PC110_CLKSRC6,
+};
+
+/* MSYS */
+static struct clk *clk_src_msys_list[] = {
+	[0] = &clk_mout_apll.clk,
+	[1] = &clk_mout_mpll.clk,
+};
+
+static struct clk_sources clk_src_msys = {
+	.sources	= clk_src_msys_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_msys_list),
+};
+
+static struct clksrc_clk clk_mout_msys = {
+	.clk = {
+		.name		= "mout_msys",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_MUX200_SHIFT,
+	.mask		= S5PC110_CLKSRC0_MUX200_MASK,
+	.sources	= &clk_src_msys,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+/* DSYS */
+static struct clk *clk_src_dsys_list[] = {
+	[0] = &clk_mout_mpll.clk,
+	[1] = &clk_dout_a2m,
+};
+
+static struct clk_sources clk_src_dsys = {
+	.sources	= clk_src_dsys_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_dsys_list),
+};
+
+struct clksrc_clk clk_mout_dsys = {
+	.clk = {
+		.name		= "mout_dsys",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_MUX166_SHIFT,
+	.mask		= S5PC110_CLKSRC0_MUX166_MASK,
+	.sources	= &clk_src_dsys,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+/* PSYS */
+static struct clk *clk_src_psys_list[] = {
+	[0] = &clk_mout_mpll.clk,
+	[1] = &clk_dout_a2m,
+};
+
+static struct clk_sources clk_src_psys = {
+	.sources	= clk_src_psys_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_psys_list),
+};
+
+static struct clksrc_clk clk_mout_psys = {
+	.clk = {
+		.name		= "mout_psys",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_MUX133_SHIFT,
+	.mask		= S5PC110_CLKSRC0_MUX133_MASK,
+	.sources	= &clk_src_psys,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+/* Dout COPY */
+static unsigned long s5pc110_clk_dout_copy_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV6) & S5PC110_CLKDIV6_COPY_MASK;
+	ratio >>= S5PC110_CLKDIV6_COPY_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+static struct clk clk_dout_copy = {
+	.name		= "dout_copy",
+	.id		= -1,
+	.parent		= &clk_mout_hpm.clk,
+	.get_rate	= s5pc110_clk_dout_copy_get_rate,
+};
+
+/* Dout HPM */
+static unsigned long s5pc110_clk_dout_hpm_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV6) & S5PC110_CLKDIV6_HPM_MASK;
+	ratio >>= S5PC110_CLKDIV6_HPM_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+static struct clk clk_dout_hpm = {
+	.name		= "dout_hpm",
+	.id		= -1,
+	.parent		= &clk_dout_copy,
+	.get_rate	= s5pc110_clk_dout_hpm_get_rate,
+};
+
+/* Dout APLL - ARMCLK */
+static unsigned long s5pc110_clk_dout_apll_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_APLL_MASK;
+	ratio >>= S5PC110_CLKDIV0_APLL_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+static struct clk clk_dout_apll = {
+	.name		= "dout_apll",
+	.id		= -1,
+	.parent		= &clk_mout_msys.clk,
+	.get_rate	= s5pc110_clk_dout_apll_get_rate,
+};
+
+/* Dout HCLKM - ACLK200, HCLK_MSYS */
+static unsigned long s5pc110_clk_dout_hclkm_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_HCLK_MSYS_MASK;
+	ratio >>= S5PC110_CLKDIV0_HCLK_MSYS_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+struct clk clk_dout_hclkm = {
+	.name		= "dout_hclkm",
+	.id		= -1,
+	.parent		= &clk_dout_apll,
+	.get_rate	= s5pc110_clk_dout_hclkm_get_rate,
+};
+
+/* Dout PCLKM - PCLK_MSYS */
+static unsigned long s5pc110_clk_dout_pclkm_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_PCLK_MSYS_MASK;
+	ratio >>= S5PC110_CLKDIV0_HCLK_PSYS_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+struct clk clk_dout_pclkm = {
+	.name		= "dout_pclkm",
+	.id		= -1,
+	.parent		= &clk_dout_hclkm,
+	.get_rate	= s5pc110_clk_dout_pclkm_get_rate,
+};
+
+/* Dout IMEM - HCLK100 */
+static unsigned long s5pc110_clk_dout_imem_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	return rate / 2;
+}
+
+static struct clk clk_dout_imem = {
+	.name		= "dout_imem",
+	.id		= -1,
+	.parent		= &clk_dout_hclkm,
+	.get_rate	= s5pc110_clk_dout_imem_get_rate,
+};
+
+/* Dout HCLKD - HCLK_DSYS */
+static unsigned long s5pc110_clk_dout_hclkd_get_rate(struct clk *clk)
+{
+	unsigned long rate;
+	unsigned int ratio;
+
+	rate = clk_get_rate(clk->parent);
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_HCLK_DSYS_MASK;
+	ratio >>= S5PC110_CLKDIV0_HCLK_DSYS_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+struct clk clk_dout_hclkd = {
+	.name		= "dout_hclkd",
+	.id		= -1,
+	.parent		= &clk_mout_dsys.clk,
+	.get_rate	= s5pc110_clk_dout_hclkd_get_rate,
+};
+
+/* Dout PCLKD - PCLK_DSYS */
+static unsigned long s5pc110_clk_dout_pclkd_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_PCLK_DSYS_MASK;
+	ratio >>= S5PC110_CLKDIV0_PCLK_DSYS_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+struct clk clk_dout_pclkd = {
+	.name		= "dout_pclkd",
+	.id		= -1,
+	.parent		= &clk_dout_hclkd,
+	.get_rate	= s5pc110_clk_dout_pclkd_get_rate,
+};
+
+/* Dout FIMC - SCLK_FIMC */
+static unsigned long s5pc110_clk_dout_fimc_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV1) & S5PC110_CLKDIV1_FIMC_MASK;
+	ratio >>= S5PC110_CLKDIV1_FIMC_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+static struct clk clk_dout_fimc = {
+	.name		= "dout_fimc",
+	.id		= -1,
+	.parent		= &clk_mout_dsys.clk,
+	.get_rate	= s5pc110_clk_dout_fimc_get_rate,
+};
+
+/* Dout HCLKP - ARMATCLK, HCLK_PSYS */
+static unsigned long s5pc110_clk_dout_hclkp_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_HCLK_PSYS_MASK;
+	ratio >>= S5PC110_CLKDIV0_HCLK_PSYS_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+struct clk clk_dout_hclkp = {
+	.name		= "dout_hclkp",
+	.id		= -1,
+	.parent		= &clk_mout_psys.clk,
+	.get_rate	= s5pc110_clk_dout_hclkp_get_rate,
+};
+
+/* Dout PCLKD - PCLK_DSYS */
+static unsigned long s5pc110_clk_dout_pclkp_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV0) & S5PC110_CLKDIV0_PCLK_PSYS_MASK;
+	ratio >>= S5PC110_CLKDIV0_PCLK_PSYS_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+struct clk clk_dout_pclkp = {
+	.name		= "dout_pclkp",
+	.id		= -1,
+	.parent		= &clk_dout_hclkp,
+	.get_rate	= s5pc110_clk_dout_pclkp_get_rate,
+};
+
+/* FLASH */
+static struct clk *clk_src_onenand_list[] = {
+	[0] = &clk_dout_hclkd,
+	[1] = &clk_dout_hclkp,
+};
+
+static struct clk_sources clk_src_onenand = {
+	.sources	= clk_src_onenand_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_onenand_list),
+};
+
+static struct clksrc_clk clk_mout_onenand = {
+	.clk = {
+		.name		= "mout_onenand",
+		.id		= -1,
+	},
+	.shift		= S5PC110_CLKSRC0_ONENAND_SHIFT,
+	.mask		= S5PC110_CLKSRC0_ONENAND_MASK,
+	.sources	= &clk_src_onenand,
+	.reg_source	= S5PC110_CLKSRC0,
+};
+
+/* Dout FLASH - SCLK_ONENAND */
+static unsigned long s5pc110_clk_dout_onenand_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned int ratio;
+
+	ratio = __raw_readl(S5PC110_CLKDIV6) & S5PC110_CLKDIV6_ONENAND_MASK;
+	ratio >>= S5PC110_CLKDIV6_ONENAND_SHIFT;
+
+	return rate / (ratio + 1);
+}
+
+static struct clk clk_dout_onenand = {
+	.name		= "dout_onenand",
+	.id		= -1,
+	.parent		= &clk_mout_onenand.clk,
+	.get_rate	= s5pc110_clk_dout_onenand_get_rate,
+};
+
+/* Dout FLASH2 - SCLK_ONENAND2 */
+static unsigned long s5pc110_clk_dout_onenand2_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	return rate / 2;
+}
+
+static struct clk clk_dout_onenand2 = {
+	.name		= "dout_onenand2",
+	.id		= -1,
+	.parent		= &clk_dout_onenand,
+	.get_rate	= s5pc110_clk_dout_onenand2_get_rate,
+};
+
+/* Peripherals */
+static inline struct clksrc_clk *to_clksrc(struct clk *clk)
+{
+	return container_of(clk, struct clksrc_clk, clk);
+}
+
+static unsigned long s5pc110_getrate_clksrc(struct clk *clk)
+{
+	struct clksrc_clk *sclk = to_clksrc(clk);
+	unsigned long rate = clk_get_rate(clk->parent);
+	u32 clkdiv = __raw_readl(sclk->reg_divider);
+
+	clkdiv >>= sclk->divider_shift;
+	clkdiv &= 0xf;
+	clkdiv++;
+
+	rate /= clkdiv;
+	return rate;
+}
+
+static int s5pc110_setrate_clksrc(struct clk *clk, unsigned long rate)
+{
+	struct clksrc_clk *sclk = to_clksrc(clk);
+	void __iomem *reg = sclk->reg_divider;
+	unsigned int div;
+	u32 val;
+
+	rate = clk_round_rate(clk, rate);
+	div = clk_get_rate(clk->parent) / rate;
+	if (div > 16)
+		return -EINVAL;
+
+	val = __raw_readl(reg);
+	val &= ~(0xf << sclk->divider_shift);
+	val |= (div - 1) << sclk->divider_shift;
+	__raw_writel(val, reg);
+
+	return 0;
+}
+
+static int s5pc110_setparent_clksrc(struct clk *clk, struct clk *parent)
+{
+	struct clksrc_clk *sclk = to_clksrc(clk);
+	struct clk_sources *srcs = sclk->sources;
+	u32 clksrc = __raw_readl(sclk->reg_source);
+	int src_nr = -1;
+	int ptr;
+
+	for (ptr = 0; ptr < srcs->nr_sources; ptr++) {
+		if (srcs->sources[ptr] == parent) {
+			src_nr = ptr;
+			break;
+		}
+	}
+
+	if (src_nr >= 0) {
+		clksrc &= ~sclk->mask;
+		clksrc |= src_nr << sclk->shift;
+
+		__raw_writel(clksrc, sclk->reg_source);
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+static unsigned long s5pc110_roundrate_clksrc(struct clk *clk,
+					      unsigned long rate)
+{
+	unsigned long parent_rate = clk_get_rate(clk->parent);
+	int div;
+
+	if (rate > parent_rate)
+		rate = parent_rate;
+	else {
+		div = parent_rate / rate;
+
+		if (div == 0)
+			div = 1;
+		if (div > 16)
+			div = 16;
+
+		rate = parent_rate / div;
+	}
+
+	return rate;
+}
+
+static struct clk *clkset_default_list[] = {
+	&clk_fin_apll,
+	&clk_usb_xtal,
+	&clk_hdmi_27m,
+	&clk_usbphy0,
+	&clk_usbphy1,
+	&clk_hdmi_phy,
+	&clk_mout_mpll.clk,
+	&clk_mout_epll.clk,
+	&clk_mout_vpll.clk,
+};
+
+
+/* CAM */
+static struct clk_sources clkset_cam = {
+	.sources	= clkset_default_list,
+	.nr_sources	= ARRAY_SIZE(clkset_default_list),
+};
+
+static struct clksrc_clk clk_cam0 = {
+	.clk	= {
+		.name		= "cam",
+		.id		= 0,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC1_CAM0_SHIFT,
+	.mask		= S5PC110_CLKSRC1_CAM0_MASK,
+	.sources	= &clkset_cam,
+	.divider_shift	= S5PC110_CLKDIV1_CAM0_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV1,
+	.reg_source	= S5PC110_CLKSRC1,
+};
+
+static struct clksrc_clk clk_cam1 = {
+	.clk	= {
+		.name		= "cam",
+		.id		= 1,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC1_CAM1_SHIFT,
+	.mask		= S5PC110_CLKSRC1_CAM1_MASK,
+	.sources	= &clkset_cam,
+	.divider_shift	= S5PC110_CLKDIV1_CAM1_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV1,
+	.reg_source	= S5PC110_CLKSRC1,
+};
+
+/* FIMD */
+static struct clk_sources clkset_fimd = {
+	.sources	= clkset_default_list,
+	.nr_sources	= ARRAY_SIZE(clkset_default_list),
+};
+
+static struct clksrc_clk clk_fimd = {
+	.clk	= {
+		.name		= "fimd",
+		.id		= -1,
+		.ctrlbit	= S5PC110_CLKGATE_IP1_FIMD,
+		.enable		= s5pc110_ip1_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC1_FIMD_SHIFT,
+	.mask		= S5PC110_CLKSRC1_FIMD_MASK,
+	.sources	= &clkset_fimd,
+	.divider_shift	= S5PC110_CLKDIV1_FIMD_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV1,
+	.reg_source	= S5PC110_CLKSRC1,
+};
+
+/* MMC */
+static struct clk_sources clkset_mmc = {
+	.sources	= clkset_default_list,
+	.nr_sources	= ARRAY_SIZE(clkset_default_list),
+};
+
+static struct clksrc_clk clk_mmc0 = {
+	.clk	= {
+		.name		= "mmc-bus",
+		.id		= 0,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC0,
+		.enable		= s5pc110_ip2_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_MMC0_SHIFT,
+	.mask		= S5PC110_CLKSRC4_MMC0_MASK,
+	.sources	= &clkset_mmc,
+	.divider_shift	= S5PC110_CLKDIV4_MMC0_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+static struct clksrc_clk clk_mmc1 = {
+	.clk	= {
+		.name		= "mmc-bus",
+		.id		= 1,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC1,
+		.enable		= s5pc110_ip2_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_MMC1_SHIFT,
+	.mask		= S5PC110_CLKSRC4_MMC1_MASK,
+	.sources	= &clkset_mmc,
+	.divider_shift	= S5PC110_CLKDIV4_MMC1_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+static struct clksrc_clk clk_mmc2 = {
+	.clk	= {
+		.name		= "mmc-bus",
+		.id		= 2,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC2,
+		.enable		= s5pc110_ip2_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_MMC2_SHIFT,
+	.mask		= S5PC110_CLKSRC4_MMC2_MASK,
+	.sources	= &clkset_mmc,
+	.divider_shift	= S5PC110_CLKDIV4_MMC2_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+static struct clksrc_clk clk_mmc3 = {
+	.clk	= {
+		.name		= "mmc-bus",
+		.id		= 3,
+		.ctrlbit	= S5PC110_CLKGATE_IP2_HSMMC3,
+		.enable		= s5pc110_ip2_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_MMC3_SHIFT,
+	.mask		= S5PC110_CLKSRC4_MMC3_MASK,
+	.sources	= &clkset_mmc,
+	.divider_shift	= S5PC110_CLKDIV4_MMC3_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+/* AUDIO0 */
+static struct clk_sources clkset_audio0 = {
+	.sources	= clkset_default_list,
+	.nr_sources	= ARRAY_SIZE(clkset_default_list),
+};
+
+static struct clksrc_clk clk_audio0 = {
+	.clk	= {
+		.name		= "audio-bus",
+		.id		= 0,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC6_AUDIO0_SHIFT,
+	.mask		= S5PC110_CLKSRC6_AUDIO0_MASK,
+	.sources	= &clkset_audio0,
+	.divider_shift	= S5PC110_CLKDIV6_AUDIO0_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV6,
+	.reg_source	= S5PC110_CLKSRC6,
+};
+
+/* AUDIO1 */
+static struct clk *clkset_audio1_list[] = {
+	&clk_iis_cd1,
+	&clk_pcm_cd1,
+	&clk_hdmi_27m,
+	&clk_usbphy0,
+	&clk_usbphy1,
+	&clk_hdmi_phy,
+	&clk_mout_mpll.clk,
+	&clk_mout_epll.clk,
+	&clk_mout_vpll.clk,
+};
+
+static struct clk_sources clkset_audio1 = {
+	.sources	= clkset_audio1_list,
+	.nr_sources	= ARRAY_SIZE(clkset_audio1_list),
+};
+
+static struct clksrc_clk clk_audio1 = {
+	.clk	= {
+		.name		= "audio-bus",
+		.id		= 1,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC6_AUDIO1_SHIFT,
+	.mask		= S5PC110_CLKSRC6_AUDIO1_MASK,
+	.sources	= &clkset_audio1,
+	.divider_shift	= S5PC110_CLKDIV6_AUDIO1_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV6,
+	.reg_source	= S5PC110_CLKSRC6,
+};
+
+/* AUDIO2 */
+static struct clk *clkset_audio2_list[] = {
+	&clk_fin_apll,
+	&clk_pcm_cd0,
+	&clk_hdmi_27m,
+	&clk_usbphy0,
+	&clk_usbphy1,
+	&clk_hdmi_phy,
+	&clk_mout_mpll.clk,
+	&clk_mout_epll.clk,
+	&clk_mout_vpll.clk,
+};
+
+static struct clk_sources clkset_audio2 = {
+	.sources	= clkset_audio2_list,
+	.nr_sources	= ARRAY_SIZE(clkset_audio2_list),
+};
+
+static struct clksrc_clk clk_audio2 = {
+	.clk	= {
+		.name		= "audio-bus",
+		.id		= 2,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC6_AUDIO2_SHIFT,
+	.mask		= S5PC110_CLKSRC6_AUDIO2_MASK,
+	.sources	= &clkset_audio2,
+	.divider_shift	= S5PC110_CLKDIV6_AUDIO2_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV6,
+	.reg_source	= S5PC110_CLKSRC6,
+};
+
+/* FIMC */
+static struct clk_sources clkset_fimc = {
+	.sources	= clkset_default_list,
+	.nr_sources	= ARRAY_SIZE(clkset_default_list),
+};
+
+static struct clksrc_clk clk_fimc0 = {
+	.clk	= {
+		.name		= "fimc",
+		.id		= 0,
+		.ctrlbit	= S5PC110_CLKGATE_IP0_FIMC0,
+		.enable		= s5pc110_ip0_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC3_FIMC0_LCLK_SHIFT,
+	.mask		= S5PC110_CLKSRC3_FIMC0_LCLK_MASK,
+	.sources	= &clkset_fimc,
+	.divider_shift	= S5PC110_CLKDIV3_FIMC0_LCLK_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV3,
+	.reg_source	= S5PC110_CLKSRC3,
+};
+
+static struct clksrc_clk clk_fimc1 = {
+	.clk	= {
+		.name		= "fimc",
+		.id		= 1,
+		.ctrlbit	= S5PC110_CLKGATE_IP0_FIMC1,
+		.enable		= s5pc110_ip0_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC3_FIMC1_LCLK_SHIFT,
+	.mask		= S5PC110_CLKSRC3_FIMC1_LCLK_MASK,
+	.sources	= &clkset_fimc,
+	.divider_shift	= S5PC110_CLKDIV3_FIMC1_LCLK_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV3,
+	.reg_source	= S5PC110_CLKSRC3,
+};
+
+static struct clksrc_clk clk_fimc2 = {
+	.clk	= {
+		.name		= "fimc",
+		.id		= 2,
+		.ctrlbit	= S5PC110_CLKGATE_IP0_FIMC2,
+		.enable		= s5pc110_ip0_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC3_FIMC2_LCLK_SHIFT,
+	.mask		= S5PC110_CLKSRC3_FIMC2_LCLK_MASK,
+	.sources	= &clkset_fimc,
+	.divider_shift	= S5PC110_CLKDIV3_FIMC2_LCLK_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV3,
+	.reg_source	= S5PC110_CLKSRC3,
+};
+
+/* UART */
+static struct clk_sources clkset_uart = {
+	.sources	= clkset_default_list,
+	.nr_sources	= ARRAY_SIZE(clkset_default_list),
+};
+
+static struct clksrc_clk clk_uart0 = {
+	.clk	= {
+		.name		= "uart",
+		.id		= 0,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_UART0,
+		.enable		= s5pc110_ip3_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_UART0_SHIFT,
+	.mask		= S5PC110_CLKSRC4_UART0_MASK,
+	.sources	= &clkset_uart,
+	.divider_shift	= S5PC110_CLKDIV4_UART0_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+static struct clksrc_clk clk_uart1 = {
+	.clk	= {
+		.name		= "uart",
+		.id		= 1,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_UART1,
+		.enable		= s5pc110_ip3_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_UART1_SHIFT,
+	.mask		= S5PC110_CLKSRC4_UART1_MASK,
+	.sources	= &clkset_uart,
+	.divider_shift	= S5PC110_CLKDIV4_UART1_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+static struct clksrc_clk clk_uart2 = {
+	.clk	= {
+		.name		= "uart",
+		.id		= 2,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_UART2,
+		.enable		= s5pc110_ip3_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_UART2_SHIFT,
+	.mask		= S5PC110_CLKSRC4_UART2_MASK,
+	.sources	= &clkset_uart,
+	.divider_shift	= S5PC110_CLKDIV4_UART2_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+static struct clksrc_clk clk_uart3 = {
+	.clk	= {
+		.name		= "uart",
+		.id		= 3,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_UART3,
+		.enable		= s5pc110_ip3_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC4_UART3_SHIFT,
+	.mask		= S5PC110_CLKSRC4_UART3_MASK,
+	.sources	= &clkset_uart,
+	.divider_shift	= S5PC110_CLKDIV4_UART3_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV4,
+	.reg_source	= S5PC110_CLKSRC4,
+};
+
+/* PWM */
+static struct clk_sources clkset_pwm = {
+	.sources	= clkset_default_list,
+	.nr_sources	= ARRAY_SIZE(clkset_default_list),
+};
+
+static struct clksrc_clk clk_pwm = {
+	.clk	= {
+		.name		= "pwm",
+		.id		= -1,
+		.ctrlbit	= S5PC110_CLKGATE_IP3_PWM,
+		.enable		= s5pc110_ip3_ctrl,
+		.set_parent	= s5pc110_setparent_clksrc,
+		.get_rate	= s5pc110_getrate_clksrc,
+		.set_rate	= s5pc110_setrate_clksrc,
+		.round_rate	= s5pc110_roundrate_clksrc,
+	},
+	.shift		= S5PC110_CLKSRC5_PWM_SHIFT,
+	.mask		= S5PC110_CLKSRC5_PWM_MASK,
+	.sources	= &clkset_pwm,
+	.divider_shift	= S5PC110_CLKDIV5_PWM_SHIFT,
+	.reg_divider	= S5PC110_CLKDIV5,
+	.reg_source	= S5PC110_CLKSRC5,
+};
+
+/* Clock initialisation code */
+static struct clksrc_clk *init_parents[] = {
+	&clk_mout_apll,
+	&clk_mout_mpll,
+	&clk_mout_epll,
+	&clk_mout_vpllsrc,
+	&clk_mout_vpll,
+	&clk_mout_hpm,
+	&clk_mout_msys,
+	&clk_mout_dsys,
+	&clk_mout_psys,
+	&clk_mout_onenand,
+	&clk_cam0,
+	&clk_cam1,
+	&clk_fimd,
+	&clk_mmc0,
+	&clk_mmc1,
+	&clk_mmc2,
+	&clk_mmc3,
+	&clk_audio0,
+	&clk_audio1,
+	&clk_audio2,
+	&clk_fimc0,
+	&clk_fimc1,
+	&clk_fimc2,
+	&clk_uart0,
+	&clk_uart1,
+	&clk_uart2,
+	&clk_uart3,
+	&clk_pwm,
+};
+
+static void __init_or_cpufreq s5pc110_set_clksrc(struct clksrc_clk *clk)
+{
+	struct clk_sources *srcs = clk->sources;
+	u32 clksrc = __raw_readl(clk->reg_source);
+
+	clksrc &= clk->mask;
+	clksrc >>= clk->shift;
+
+	if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
+		printk(KERN_ERR "%s: bad source %d\n",
+		       clk->clk.name, clksrc);
+		return;
+	}
+
+	clk->clk.parent = srcs->sources[clksrc];
+
+	printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n",
+		clk->clk.name, clk->clk.parent->name, clksrc,
+		print_mhz(clk_get_rate(&clk->clk)));
+}
+
+#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
+
+void __init_or_cpufreq s5pc110_setup_clocks(void)
+{
+	struct clk *xtal_clk;
+	unsigned long xtal;
+	unsigned long armclk;
+	unsigned long hclk_msys, hclk_dsys, hclk_psys;
+	unsigned long pclk_msys, pclk_dsys, pclk_psys;
+	unsigned long apll, mpll, epll, vpll;
+	unsigned int clkdiv0;
+	unsigned int ptr;
+
+	printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+	clkdiv0 = __raw_readl(S5PC110_CLKDIV0);
+
+	printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
+
+	xtal_clk = clk_get(NULL, "xtal");
+	BUG_ON(IS_ERR(xtal_clk));
+
+	xtal = clk_get_rate(xtal_clk);
+	clk_put(xtal_clk);
+
+	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+	apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC110_APLL_CON), 1);
+	mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC110_MPLL_CON), 0);
+	epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC110_EPLL_CON), 0);
+	vpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC110_VPLL_CON), 0);
+
+	printk(KERN_INFO "S5PC110: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz"
+		", Epll=%ld.%03ld Mhz, Vpll=%ld.%03ld Mhz\n",
+		print_mhz(apll), print_mhz(mpll),
+		print_mhz(epll), print_mhz(vpll));
+
+	armclk = apll / GET_DIV(clkdiv0, S5PC110_CLKDIV0_APLL);
+	hclk_msys = armclk / GET_DIV(clkdiv0, S5PC110_CLKDIV0_HCLK_MSYS);
+	hclk_dsys = mpll / GET_DIV(clkdiv0, S5PC110_CLKDIV0_HCLK_DSYS);
+	hclk_psys = mpll / GET_DIV(clkdiv0, S5PC110_CLKDIV0_HCLK_PSYS);
+	pclk_msys = hclk_msys / GET_DIV(clkdiv0, S5PC110_CLKDIV0_PCLK_MSYS);
+	pclk_dsys = hclk_dsys / GET_DIV(clkdiv0, S5PC110_CLKDIV0_PCLK_DSYS);
+	pclk_psys = hclk_psys / GET_DIV(clkdiv0, S5PC110_CLKDIV0_PCLK_PSYS);
+
+	printk(KERN_INFO "S5PC110: ARMCLK=%ld.%03ld MHz\n"
+		"HCLK: Msys %ld.%03ld MHz, Dsys %ld.%03ld MHz, Psys %ld.%03ld MHz\n"
+		"PCLK: Msys %ld.%03ld MHz, Dsys %ld.%03ld MHz, Psys %ld.%03ld MHz\n",
+		print_mhz(armclk),
+		print_mhz(hclk_msys), print_mhz(hclk_dsys), print_mhz(hclk_psys),
+		print_mhz(pclk_msys), print_mhz(pclk_dsys), print_mhz(pclk_psys));
+
+	clk_ext_xtal_mux.rate = xtal;
+	clk_fout_apll.rate = apll;
+	clk_fout_mpll.rate = mpll;
+	clk_fout_epll.rate = epll;
+	clk_fout_vpll.rate = vpll;
+
+	clk_dout_hclkm.rate = hclk_msys;
+	clk_dout_hclkd.rate = hclk_dsys;
+	clk_dout_hclkp.rate = hclk_psys;
+	clk_dout_pclkm.rate = pclk_msys;
+	clk_dout_pclkd.rate = pclk_dsys;
+	clk_dout_pclkp.rate = pclk_psys;
+
+	clk_h.rate = hclk_psys;
+	clk_p.rate = pclk_psys;
+	clk_f.rate = armclk;
+
+	for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
+		s5pc110_set_clksrc(init_parents[ptr]);
+}
+
+static struct clk *clks[] __initdata = {
+	&clk_ext_xtal_mux,
+	&clk_usb_xtal,
+	&clk_pcm_cd0,
+	&clk_pcm_cd1,
+	&clk_iis_cd1,
+	&clk_mout_apll.clk,
+	&clk_mout_mpll.clk,
+	&clk_mout_epll.clk,
+	&clk_mout_vpllsrc.clk,
+	&clk_mout_vpll.clk,
+	&clk_dout_a2m,
+	&clk_mout_hpm.clk,
+	&clk_mout_msys.clk,
+	&clk_mout_dsys.clk,
+	&clk_mout_psys.clk,
+	&clk_dout_copy,
+	&clk_dout_hpm,
+	&clk_dout_apll,
+	&clk_dout_hclkm,
+	&clk_dout_pclkm,
+	&clk_dout_hclkd,
+	&clk_dout_pclkd,
+	&clk_dout_hclkp,
+	&clk_dout_pclkp,
+	&clk_dout_fimc,
+	&clk_dout_imem,
+	&clk_mout_onenand.clk,
+	&clk_dout_onenand,
+	&clk_dout_onenand2,
+	&clk_cam0.clk,
+	&clk_cam1.clk,
+	&clk_fimd.clk,
+	&clk_mmc0.clk,
+	&clk_mmc1.clk,
+	&clk_mmc2.clk,
+	&clk_mmc3.clk,
+	&clk_audio0.clk,
+	&clk_audio1.clk,
+	&clk_audio2.clk,
+	&clk_fimc0.clk,
+	&clk_fimc1.clk,
+	&clk_fimc2.clk,
+	&clk_uart0.clk,
+	&clk_uart1.clk,
+	&clk_uart2.clk,
+	&clk_uart3.clk,
+	&clk_pwm.clk,
+};
+
+void __init s5pc110_register_clocks(void)
+{
+	struct clk *clkp;
+	int ret;
+	int ptr;
+
+	for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
+		clkp = clks[ptr];
+		ret = s3c24xx_register_clock(clkp);
+		if (ret < 0) {
+			printk(KERN_ERR "Failed to register clock %s (%d)\n",
+			       clkp->name, ret);
+		}
+	}
+}
diff --git a/arch/arm/plat-s5pc1xx/include/plat/pll.h b/arch/arm/plat-s5pc1xx/include/plat/pll.h
index 21afef1..7380d16 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/pll.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/pll.h
@@ -22,7 +22,7 @@
 #include <asm/div64.h>
 
 static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk,
-					    u32 pllcon)
+					    u32 pllcon, int sub)
 {
 	u32 mdiv, pdiv, sdiv;
 	u64 fvco = baseclk;
@@ -32,7 +32,11 @@ static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk,
 	sdiv = (pllcon >> S5P_PLL_SDIV_SHIFT) & S5P_PLL_SDIV_MASK;
 
 	fvco *= mdiv;
-	do_div(fvco, (pdiv << sdiv));
+
+	if (sub)
+		do_div(fvco, (pdiv << (sdiv - 1)));
+	else
+		do_div(fvco, (pdiv << sdiv));
 
 	return (unsigned long)fvco;
 }
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h
index 93c623b..3ac4ce0 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc110.h
@@ -16,6 +16,8 @@
 
 #ifdef CONFIG_CPU_S5PC110
 
+struct s3c2410_uartcfg;
+
 extern void s5pc110_map_io(void);
 extern void s5pc110_init_clocks(int xtal);
 extern void s5pc110_init_uarts(struct s3c2410_uartcfg *cfg, int no);
@@ -26,6 +28,23 @@ extern void s5pc110_init_irq(void);
 extern void s5pc110_register_clocks(void);
 extern void s5pc110_setup_clocks(void);
 
+extern struct clk clk_hpll;
+extern struct clk clk_hd0;
+extern struct clk clk_pd0;
+extern struct clk clk_54m;
+extern struct clk clk_30m;
+extern struct clk clk_dout_hclkm;
+extern struct clk clk_dout_hclkd;
+extern struct clk clk_dout_hclkp;
+extern struct clk clk_dout_pclkd;
+extern struct clk clk_dout_pclkp;
+
+extern int s5pc110_ip0_ctrl(struct clk *clk, int enable);
+extern int s5pc110_ip1_ctrl(struct clk *clk, int enable);
+extern int s5pc110_ip2_ctrl(struct clk *clk, int enable);
+extern int s5pc110_ip3_ctrl(struct clk *clk, int enable);
+extern int s5pc110_ip4_ctrl(struct clk *clk, int enable);
+
 #else
 
 #define s5pc110_map_io NULL
-- 
1.6.4

[PATCH 13/20] ARM: S5PC1XX: add support for s5pc110 irqs

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds interrupt support on S5PC110 SoCs. Unlike S5PC100,
S5PC110 has 4 VICs, so the S5PC110 specifi virtual memory area is
extended to cover VIC3 register block.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Byungho Min <bhmin@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/mach-s5pc110/cpu.c                   |   10 ++
 arch/arm/mach-s5pc110/include/mach/regs-irq.h |   25 +++
 arch/arm/mach-s5pc110/include/plat/irqs.h     |  209 +++++++++++++++++++++++++
 3 files changed, 244 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/include/mach/regs-irq.h
 create mode 100644 arch/arm/mach-s5pc110/include/plat/irqs.h

diff --git a/arch/arm/mach-s5pc110/cpu.c b/arch/arm/mach-s5pc110/cpu.c
index 6c9ebcb..3ea26ff 100644
--- a/arch/arm/mach-s5pc110/cpu.c
+++ b/arch/arm/mach-s5pc110/cpu.c
@@ -43,6 +43,12 @@
 /* Initial IO mappings */
 
 static struct map_desc s5pc110_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5PC1XX_VA_VIC(3),
+		.pfn		= __phys_to_pfn(S5PC1XX_PA_VIC(3)),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
 };
 
 static void s5pc110_idle(void)
@@ -93,6 +99,10 @@ void __init s5pc110_init_clocks(int xtal)
 
 void __init s5pc110_init_irq(void)
 {
+	u32 vic_valid[] = {~0, ~0, ~0, ~0};
+
+	/* VIC0, VIC1, VIC2, and VIC3 are fully populated. */
+	s5pc1xx_init_irq(vic_valid, ARRAY_SIZE(vic_valid));
 }
 
 struct sysdev_class s5pc110_sysclass = {
diff --git a/arch/arm/mach-s5pc110/include/mach/regs-irq.h b/arch/arm/mach-s5pc110/include/mach/regs-irq.h
new file mode 100644
index 0000000..b467e3b
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/mach/regs-irq.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s5pc110/include/mach/regs-irq.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC110 - IRQ register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_IRQ_H
+#define __ASM_ARCH_REGS_IRQ_H __FILE__
+
+#include <mach/map.h>
+#include <asm/hardware/vic.h>
+
+/* interrupt controller */
+#define S5PC1XX_VIC0REG(x)          		((x) + S5PC1XX_VA_VIC(0))
+#define S5PC1XX_VIC1REG(x)          		((x) + S5PC1XX_VA_VIC(1))
+#define S5PC1XX_VIC2REG(x)         		((x) + S5PC1XX_VA_VIC(2))
+#define S5PC1XX_VIC3REG(x)         		((x) + S5PC1XX_VA_VIC(3))
+
+#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pc110/include/plat/irqs.h b/arch/arm/mach-s5pc110/include/plat/irqs.h
new file mode 100644
index 0000000..d1a2a21
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/plat/irqs.h
@@ -0,0 +1,209 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/irqs.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC110 - Common IRQ support
+ *
+ * Based on plat-s3c64xx/include/plat/irqs.h
+ */
+
+#ifndef __ASM_PLAT_S5PC110_IRQS_H
+#define __ASM_PLAT_S5PC110_IRQS_H __FILE__
+
+/* we keep the first set of CPU IRQs out of the range of
+ * the ISA space, so that the PC104 has them to itself
+ * and we don't end up having to do horrible things to the
+ * standard ISA drivers....
+ *
+ * note, since we're using the VICs, our start must be a
+ * mulitple of 32 to allow the common code to work
+ */
+
+#define S3C_IRQ_OFFSET		(32)
+
+#define S3C_IRQ(x)		((x) + S3C_IRQ_OFFSET)
+
+#define S3C_VIC0_BASE		S3C_IRQ(0)
+#define S3C_VIC1_BASE		S3C_IRQ(32)
+#define S3C_VIC2_BASE		S3C_IRQ(64)
+#define S3C_VIC3_BASE		S3C_IRQ(96)
+
+/* UART interrupts, each UART has 4 interupts per channel so
+ * use the space between the ISA and S3C main interrupts. Note, these
+ * are not in the same order as the S3C24XX series! */
+
+#define IRQ_S3CUART_BASE0	(16)
+#define IRQ_S3CUART_BASE1	(20)
+#define IRQ_S3CUART_BASE2	(24)
+#define IRQ_S3CUART_BASE3	(28)
+
+#define UART_IRQ_RXD		(0)
+#define UART_IRQ_ERR		(1)
+#define UART_IRQ_TXD		(2)
+#define UART_IRQ_MODEM		(3)
+
+#define IRQ_S3CUART_RX0		(IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX0		(IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR0	(IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX1		(IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX1		(IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR1	(IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX2		(IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX2		(IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR2	(IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX3		(IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX3		(IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR3	(IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
+
+/* VIC based IRQs */
+
+#define S5PC1XX_IRQ_VIC0(x)	(S3C_VIC0_BASE + (x))
+#define S5PC1XX_IRQ_VIC1(x)	(S3C_VIC1_BASE + (x))
+#define S5PC1XX_IRQ_VIC2(x)	(S3C_VIC2_BASE + (x))
+#define S5PC110_IRQ_VIC3(x)	(S3C_VIC3_BASE + (x))
+
+/*
+ * VIC0: system, DMA, timer
+ */
+#define IRQ_EINT0		S5PC1XX_IRQ_VIC0(0)
+#define IRQ_EINT1		S5PC1XX_IRQ_VIC0(1)
+#define IRQ_EINT2		S5PC1XX_IRQ_VIC0(2)
+#define IRQ_EINT3		S5PC1XX_IRQ_VIC0(3)
+#define IRQ_EINT4		S5PC1XX_IRQ_VIC0(4)
+#define IRQ_EINT5		S5PC1XX_IRQ_VIC0(5)
+#define IRQ_EINT6		S5PC1XX_IRQ_VIC0(6)
+#define IRQ_EINT7		S5PC1XX_IRQ_VIC0(7)
+#define IRQ_EINT8		S5PC1XX_IRQ_VIC0(8)
+#define IRQ_EINT9		S5PC1XX_IRQ_VIC0(9)
+#define IRQ_EINT10		S5PC1XX_IRQ_VIC0(10)
+#define IRQ_EINT11		S5PC1XX_IRQ_VIC0(11)
+#define IRQ_EINT12		S5PC1XX_IRQ_VIC0(12)
+#define IRQ_EINT13		S5PC1XX_IRQ_VIC0(13)
+#define IRQ_EINT14		S5PC1XX_IRQ_VIC0(14)
+#define IRQ_EINT15		S5PC1XX_IRQ_VIC0(15)
+#define IRQ_EINT16_31		S5PC1XX_IRQ_VIC0(16)
+#define IRQ_BATF		S5PC1XX_IRQ_VIC0(17)
+#define IRQ_MDMA		S5PC1XX_IRQ_VIC0(18)
+#define IRQ_PDMA0		S5PC1XX_IRQ_VIC0(19)
+#define IRQ_PDMA1		S5PC1XX_IRQ_VIC0(20)
+#define IRQ_TIMER0		S5PC1XX_IRQ_VIC0(21)
+#define IRQ_TIMER1		S5PC1XX_IRQ_VIC0(22)
+#define IRQ_TIMER2		S5PC1XX_IRQ_VIC0(23)
+#define IRQ_TIMER3		S5PC1XX_IRQ_VIC0(24)
+#define IRQ_TIMER4		S5PC1XX_IRQ_VIC0(25)
+#define IRQ_SYSTIMER		S5PC1XX_IRQ_VIC0(26)
+#define IRQ_WDT			S5PC1XX_IRQ_VIC0(27)
+#define IRQ_RTC_ALARM		S5PC1XX_IRQ_VIC0(28)
+#define IRQ_RTC			IRQ_RTC_ALARM
+#define IRQ_RTC_TIC		S5PC1XX_IRQ_VIC0(29)
+#define IRQ_TICK		IRQ_RTC_TIC
+#define IRQ_GPIOINT		S5PC1XX_IRQ_VIC0(30)
+#define IRQ_FIMC3		S5PC1XX_IRQ_VIC0(31)
+
+/*
+ * VIC1: ARM, power, memory, connectivity
+ */
+#define IRQ_CORTEX0		S5PC1XX_IRQ_VIC1(0)
+#define IRQ_CORTEX1		S5PC1XX_IRQ_VIC1(1)
+#define IRQ_CORTEX2		S5PC1XX_IRQ_VIC1(2)
+#define IRQ_CORTEX3		S5PC1XX_IRQ_VIC1(3)
+#define IRQ_CORTEX4		S5PC1XX_IRQ_VIC1(4)
+#define IRQ_IEMAPC		S5PC1XX_IRQ_VIC1(5)
+#define IRQ_IEMIEC		S5PC1XX_IRQ_VIC1(6)
+#define IRQ_NFC			S5PC1XX_IRQ_VIC1(8)
+#define IRQ_CFC			S5PC1XX_IRQ_VIC1(9)
+#define IRQ_UART0		S5PC1XX_IRQ_VIC1(10)
+#define IRQ_UART1		S5PC1XX_IRQ_VIC1(11)
+#define IRQ_UART2		S5PC1XX_IRQ_VIC1(12)
+#define IRQ_UART3		S5PC1XX_IRQ_VIC1(13)
+#define IRQ_IIC			S5PC1XX_IRQ_VIC1(14)
+#define IRQ_SPI0		S5PC1XX_IRQ_VIC1(15)
+#define IRQ_SPI1		S5PC1XX_IRQ_VIC1(16)
+#define IRQ_SPI2		S5PC1XX_IRQ_VIC1(17)
+#define IRQ_IRDA		S5PC1XX_IRQ_VIC1(18)
+#define IRQ_I2C_PMIC_LINK	S5PC1XX_IRQ_VIC1(19)
+#define IRQ_I2C_HDMI_PHY	S5PC1XX_IRQ_VIC1(20)
+#define IRQ_HSIRX		S5PC1XX_IRQ_VIC1(21)
+#define IRQ_HSITX		S5PC1XX_IRQ_VIC1(22)
+#define IRQ_UHOST		S5PC1XX_IRQ_VIC1(23)
+#define IRQ_OTG			S5PC1XX_IRQ_VIC1(24)
+#define IRQ_MSM			S5PC1XX_IRQ_VIC1(25)
+#define IRQ_HSMMC0		S5PC1XX_IRQ_VIC1(26)
+#define IRQ_HSMMC1		S5PC1XX_IRQ_VIC1(27)
+#define IRQ_HSMMC2		S5PC1XX_IRQ_VIC1(28)
+#define IRQ_MIPICSI		S5PC1XX_IRQ_VIC1(29)
+#define IRQ_MIPIDSI		S5PC1XX_IRQ_VIC1(30)
+#define IRQ_ONENAND_AUDI	S5PC1XX_IRQ_VIC1(31)
+
+/*
+ * VIC2: multimedia, audio, security
+ */
+#define IRQ_LCD0		S5PC1XX_IRQ_VIC2(0)
+#define IRQ_LCD1		S5PC1XX_IRQ_VIC2(1)
+#define IRQ_LCD2		S5PC1XX_IRQ_VIC2(2)
+#define IRQ_LCD3		S5PC1XX_IRQ_VIC2(3)
+#define IRQ_ROTATOR		S5PC1XX_IRQ_VIC2(4)
+#define IRQ_FIMC0		S5PC1XX_IRQ_VIC2(5)
+#define IRQ_FIMC1		S5PC1XX_IRQ_VIC2(6)
+#define IRQ_FIMC2		S5PC1XX_IRQ_VIC2(7)
+#define IRQ_JPEG		S5PC1XX_IRQ_VIC2(8)
+#define IRQ_2D			S5PC1XX_IRQ_VIC2(9)
+#define IRQ_3D			S5PC1XX_IRQ_VIC2(10)
+#define IRQ_MIXER		S5PC1XX_IRQ_VIC2(11)
+#define IRQ_HDMI		S5PC1XX_IRQ_VIC2(12)
+#define IRQ_IIC1		S5PC1XX_IRQ_VIC2(13)
+#define IRQ_HDMI_I2C		S5PC1XX_IRQ_VIC2(13)
+#define IRQ_MFC			S5PC1XX_IRQ_VIC2(14)
+#define IRQ_TVENC		S5PC1XX_IRQ_VIC2(15)
+#define IRQ_I2S0		S5PC1XX_IRQ_VIC2(16)
+#define IRQ_I2S1		S5PC1XX_IRQ_VIC2(17)
+#define IRQ_AC97		S5PC1XX_IRQ_VIC2(19)
+#define IRQ_PCM0		S5PC1XX_IRQ_VIC2(20)
+#define IRQ_PCM1		S5PC1XX_IRQ_VIC2(21)
+#define IRQ_SPDIF		S5PC1XX_IRQ_VIC2(22)
+#define IRQ_ADC			S5PC1XX_IRQ_VIC2(23)
+#define IRQ_PENDN		S5PC1XX_IRQ_VIC2(24)
+#define IRQ_TC			IRQ_PENDN
+#define IRQ_KEYPAD		S5PC1XX_IRQ_VIC2(25)
+#define IRQ_CG			S5PC1XX_IRQ_VIC2(26)
+#define IRQ_SEC			S5PC1XX_IRQ_VIC2(27)
+#define IRQ_SECRX		S5PC1XX_IRQ_VIC2(28)
+#define IRQ_SECTX		S5PC1XX_IRQ_VIC2(29)
+#define IRQ_SDMIRQ		S5PC1XX_IRQ_VIC2(30)
+#define IRQ_SDMFIQ		S5PC1XX_IRQ_VIC2(31)
+
+/* VIC3 used at S5PC110 */
+#define IRQ_IPC			S5PC110_IRQ_VIC3(0)
+#define IRQ_HOSTIF		S5PC110_IRQ_VIC3(1)
+#define IRQ_MMC3		S5PC110_IRQ_VIC3(2)
+#define IRQ_CEC			S5PC110_IRQ_VIC3(3)
+#define IRQ_TSI			S5PC110_IRQ_VIC3(4)
+#define IRQ_MDNIE0		S5PC110_IRQ_VIC3(5)
+#define IRQ_MDNIE1		S5PC110_IRQ_VIC3(6)
+#define IRQ_MDNIE2		S5PC110_IRQ_VIC3(7)
+#define IRQ_MDNIE3		S5PC110_IRQ_VIC3(8)
+#define IRQ_ADC1		S5PC110_IRQ_VIC3(9)
+#define IRQ_PENDN1		S5PC110_IRQ_VIC3(10)
+
+/* External interrupt */
+#define S3C_IRQ_EINT_BASE	(S5PC110_IRQ_VIC3(31) + 1)
+
+#define S3C_EINT(x)		(S3C_IRQ_EINT_BASE + ((x) - 16))
+#define IRQ_EINT(x)		((x) < 16 ? IRQ_EINT0 + (x) : S3C_EINT(x))
+#define IRQ_EINT_BIT(x)	((x) < IRQ_EINT16_31 ? (x) - IRQ_EINT0 : (x) - S3C_EINT(0))
+
+/* GPIO interrupt */
+#define S3C_IRQ_GPIO_BASE	(IRQ_EINT(31) + 1)
+#define S3C_IRQ_GPIO(x)		(S3C_IRQ_GPIO_BASE + (x))
+
+/*
+ * Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs
+ */
+#define NR_IRQS			(S3C_IRQ_GPIO(320) + 1)
+
+#endif /* __ASM_PLAT_S5PC1XX_IRQS_H */
+
-- 
1.6.4

[PATCH 14/20] ARM: S5PC1XX: add support for s5pc110 gpio

[Marek Szyprowski]

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds gpiolib support for S5PC110 sub-platform.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Byungho Min <bhmin@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-s5pc110/Makefile                 |    1 +
 arch/arm/mach-s5pc110/gpio-chips.c             |   66 +++++++++
 arch/arm/mach-s5pc110/include/mach/gpio.h      |  187 ++++++++++++++++++++++++
 arch/arm/mach-s5pc110/include/plat/regs-gpio.h |   65 ++++++++
 4 files changed, 319 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/gpio-chips.c
 create mode 100644 arch/arm/mach-s5pc110/include/mach/gpio.h
 create mode 100644 arch/arm/mach-s5pc110/include/plat/regs-gpio.h

diff --git a/arch/arm/mach-s5pc110/Makefile b/arch/arm/mach-s5pc110/Makefile
index 4dfb306..3849e27 100644
--- a/arch/arm/mach-s5pc110/Makefile
+++ b/arch/arm/mach-s5pc110/Makefile
@@ -13,6 +13,7 @@ obj-                            :=
 
 obj-$(CONFIG_CPU_S5PC110)	+= cpu.o
 obj-$(CONFIG_CPU_S5PC110)	+= clocks.o
+obj-$(CONFIG_CPU_S5PC110)	+= gpio-chips.o
 obj-$(CONFIG_CPU_S5PC110)	+= plls.o
 obj-$(CONFIG_CPU_S5PC110)	+= uarts.o
 
diff --git a/arch/arm/mach-s5pc110/gpio-chips.c b/arch/arm/mach-s5pc110/gpio-chips.c
new file mode 100644
index 0000000..4f1e591
--- /dev/null
+++ b/arch/arm/mach-s5pc110/gpio-chips.c
@@ -0,0 +1,66 @@
+/*
+ * linux/arch/arm/mach-s5pc110/gpio-chips.c
+ *
+ *  Copyright 2009 Samsung Electronics Co
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *  Marek Szyprowski <m.szyprowski@samsung.com>
+ *
+ * S5PC110 - GPIOlib chip definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+#include <mach/gpio-core.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+#include <plat/gpio-s5pc1xx.h>
+#include <plat/regs-gpio.h>
+
+static struct s5pc1xx_gpio_chip s5pc110_gpio_chips[] = {
+	S5PC1XX_INT_CHIP_DEF(S5PC110, A0),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, A1),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, B),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, C0),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, C1),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, D0),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, D1),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, E0),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, E1),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, F0),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, F1),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, F2),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, F3),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, G0),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, G1),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, G2),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, G3),
+	S5PC1XX_EINT_CHIP_DEF(S5PC110, H0),
+	S5PC1XX_EINT_CHIP_DEF(S5PC110, H1),
+	S5PC1XX_EINT_CHIP_DEF(S5PC110, H2),
+	S5PC1XX_EINT_CHIP_DEF(S5PC110, H3),
+	S5PC1XX_NOINT_CHIP_DEF(S5PC110, I),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, J0),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, J1),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, J2),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, J3),
+	S5PC1XX_INT_CHIP_DEF(S5PC110, J4),
+	S5PC1XX_MP_CHIP_DEF(S5PC110, MP0_1),
+	S5PC1XX_MP_CHIP_DEF(S5PC110, MP0_2),
+	S5PC1XX_MP_CHIP_DEF(S5PC110, MP0_3),
+	S5PC1XX_MP_CHIP_DEF(S5PC110, MP0_4),
+	S5PC1XX_MP_CHIP_DEF(S5PC110, MP0_5),
+};
+
+struct s5pc1xx_gpio s5pc1xx_gpio_chips = {
+	.chips = s5pc110_gpio_chips,
+	.count = ARRAY_SIZE(s5pc110_gpio_chips),
+};
diff --git a/arch/arm/mach-s5pc110/include/mach/gpio.h b/arch/arm/mach-s5pc110/include/mach/gpio.h
new file mode 100644
index 0000000..ae36f1e
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/mach/gpio.h
@@ -0,0 +1,187 @@
+/* arch/arm/mach-s5pc110/include/mach/gpio.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC110 - GPIO lib support
+ *
+ * Base on mach-s3c6400/include/mach/gpio.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define gpio_get_value	__gpio_get_value
+#define gpio_set_value	__gpio_set_value
+#define gpio_cansleep	__gpio_cansleep
+#define gpio_to_irq	__gpio_to_irq
+
+/* GPIO bank sizes */
+#define S5PC110_GPIO_A0_NR	(8)
+#define S5PC110_GPIO_A1_NR	(8)
+#define S5PC110_GPIO_B_NR	(8)
+#define S5PC110_GPIO_C0_NR	(8)
+#define S5PC110_GPIO_C1_NR	(8)
+#define S5PC110_GPIO_D0_NR	(8)
+#define S5PC110_GPIO_D1_NR	(8)
+#define S5PC110_GPIO_E0_NR	(8)
+#define S5PC110_GPIO_E1_NR	(8)
+#define S5PC110_GPIO_F0_NR	(8)
+#define S5PC110_GPIO_F1_NR	(8)
+#define S5PC110_GPIO_F2_NR	(8)
+#define S5PC110_GPIO_F3_NR	(8)
+#define S5PC110_GPIO_G0_NR	(8)
+#define S5PC110_GPIO_G1_NR	(8)
+#define S5PC110_GPIO_G2_NR	(8)
+#define S5PC110_GPIO_G3_NR	(8)
+#define S5PC110_GPIO_H0_NR	(8)
+#define S5PC110_GPIO_H1_NR	(8)
+#define S5PC110_GPIO_H2_NR	(8)
+#define S5PC110_GPIO_H3_NR	(8)
+#define S5PC110_GPIO_I_NR	(8)
+#define S5PC110_GPIO_J0_NR	(8)
+#define S5PC110_GPIO_J1_NR	(8)
+#define S5PC110_GPIO_J2_NR	(8)
+#define S5PC110_GPIO_J3_NR	(8)
+#define S5PC110_GPIO_J4_NR	(8)
+#define S5PC110_GPIO_MP0_1_NR	(8)
+#define S5PC110_GPIO_MP0_2_NR	(8)
+#define S5PC110_GPIO_MP0_3_NR	(8)
+#define S5PC110_GPIO_MP0_4_NR	(8)
+#define S5PC110_GPIO_MP0_5_NR	(8)
+#define S5PC110_GPIO_MP0_6_NR	(8)
+
+/* GPIO bank numbes */
+
+/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
+ * space for debugging purposes so that any accidental
+ * change from one gpio bank to another can be caught.
+*/
+
+#define S5PC1XX_GPIO_NEXT(__gpio) \
+	((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+enum s5pc110_gpio_number {
+	S5PC110_GPIO_A0_START	= 0,
+	S5PC110_GPIO_A1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_A0),
+	S5PC110_GPIO_B_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_A1),
+	S5PC110_GPIO_C0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_B),
+	S5PC110_GPIO_C1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_C0),
+	S5PC110_GPIO_D0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_C1),
+	S5PC110_GPIO_D1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_D0),
+	S5PC110_GPIO_E0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_D1),
+	S5PC110_GPIO_E1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_E0),
+	S5PC110_GPIO_F0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_E1),
+	S5PC110_GPIO_F1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_F0),
+	S5PC110_GPIO_F2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_F1),
+	S5PC110_GPIO_F3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_F2),
+	S5PC110_GPIO_G0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_F3),
+	S5PC110_GPIO_G1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_G0),
+	S5PC110_GPIO_G2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_G1),
+	S5PC110_GPIO_G3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_G2),
+	S5PC110_GPIO_H0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_G3),
+	S5PC110_GPIO_H1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_H0),
+	S5PC110_GPIO_H2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_H1),
+	S5PC110_GPIO_H3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_H2),
+	S5PC110_GPIO_I_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_H3),
+	S5PC110_GPIO_J0_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_I),
+	S5PC110_GPIO_J1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J0),
+	S5PC110_GPIO_J2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J1),
+	S5PC110_GPIO_J3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J2),
+	S5PC110_GPIO_J4_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J3),
+	S5PC110_GPIO_MP0_1_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_J4),
+	S5PC110_GPIO_MP0_2_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_1),
+	S5PC110_GPIO_MP0_3_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_2),
+	S5PC110_GPIO_MP0_4_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_3),
+	S5PC110_GPIO_MP0_5_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_4),
+	S5PC110_GPIO_MP0_6_START	= S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_5),
+	S5PC110_GPIO_END        = S5PC1XX_GPIO_NEXT(S5PC110_GPIO_MP0_6),
+};
+
+#define S5PC110_GPA0(_nr)	(S5PC110_GPIO_A0_START + (_nr))
+#define S5PC110_GPA1(_nr)	(S5PC110_GPIO_A1_START + (_nr))
+#define S5PC110_GPB(_nr)	(S5PC110_GPIO_B_START + (_nr))
+#define S5PC110_GPC0(_nr)	(S5PC110_GPIO_C0_START + (_nr))
+#define S5PC110_GPC1(_nr)	(S5PC110_GPIO_C1_START + (_nr))
+#define S5PC110_GPD0(_nr)	(S5PC110_GPIO_D0_START + (_nr))
+#define S5PC110_GPD1(_nr)	(S5PC110_GPIO_D1_START + (_nr))
+#define S5PC110_GPE0(_nr)	(S5PC110_GPIO_E0_START + (_nr))
+#define S5PC110_GPE1(_nr)	(S5PC110_GPIO_E1_START + (_nr))
+#define S5PC110_GPF0(_nr)	(S5PC110_GPIO_F0_START + (_nr))
+#define S5PC110_GPF1(_nr)	(S5PC110_GPIO_F1_START + (_nr))
+#define S5PC110_GPF2(_nr)	(S5PC110_GPIO_F2_START + (_nr))
+#define S5PC110_GPF3(_nr)	(S5PC110_GPIO_F3_START + (_nr))
+#define S5PC110_GPG0(_nr)	(S5PC110_GPIO_G0_START + (_nr))
+#define S5PC110_GPG1(_nr)	(S5PC110_GPIO_G1_START + (_nr))
+#define S5PC110_GPG2(_nr)	(S5PC110_GPIO_G2_START + (_nr))
+#define S5PC110_GPG3(_nr)	(S5PC110_GPIO_G3_START + (_nr))
+#define S5PC110_GPH0(_nr)	(S5PC110_GPIO_H0_START + (_nr))
+#define S5PC110_GPH1(_nr)	(S5PC110_GPIO_H1_START + (_nr))
+#define S5PC110_GPH2(_nr)	(S5PC110_GPIO_H2_START + (_nr))
+#define S5PC110_GPH3(_nr)	(S5PC110_GPIO_H3_START + (_nr))
+#define S5PC110_GPI(_nr)	(S5PC110_GPIO_I_START + (_nr))
+#define S5PC110_GPJ0(_nr)	(S5PC110_GPIO_J0_START + (_nr))
+#define S5PC110_GPJ1(_nr)	(S5PC110_GPIO_J1_START + (_nr))
+#define S5PC110_GPJ2(_nr)	(S5PC110_GPIO_J2_START + (_nr))
+#define S5PC110_GPJ3(_nr)	(S5PC110_GPIO_J3_START + (_nr))
+#define S5PC110_GPJ4(_nr)	(S5PC110_GPIO_J4_START + (_nr))
+#define S5PC110_MP0_1(_nr)	(S5PC110_GPIO_MP0_1_START + (_nr))
+#define S5PC110_MP0_2(_nr)	(S5PC110_GPIO_MP0_2_START + (_nr))
+#define S5PC110_MP0_3(_nr)	(S5PC110_GPIO_MP0_3_START + (_nr))
+#define S5PC110_MP0_4(_nr)	(S5PC110_GPIO_MP0_4_START + (_nr))
+#define S5PC110_MP0_5(_nr)	(S5PC110_GPIO_MP0_5_START + (_nr))
+#define S5PC110_MP0_6(_nr)	(S5PC110_GPIO_MP0_6_START + (_nr))
+
+/* It used the end of the S5PC100 gpios */
+#define S3C_GPIO_END		S5PC110_GPIO_END
+
+/* define the number of gpios we need to the one after the MP05() range */
+#define ARCH_NR_GPIOS		(S5PC110_GPIO_END + 1)
+
+/* Offset of the bank in the interrupt group registers */
+#define S5PC110_GPIO_A0_INT_GROUP	(0)
+#define S5PC110_GPIO_A1_INT_GROUP	(1)
+#define S5PC110_GPIO_B_INT_GROUP	(2)
+#define S5PC110_GPIO_C0_INT_GROUP	(3)
+#define S5PC110_GPIO_C1_INT_GROUP	(4)
+#define S5PC110_GPIO_D0_INT_GROUP	(5)
+#define S5PC110_GPIO_D1_INT_GROUP	(6)
+#define S5PC110_GPIO_E0_INT_GROUP	(7)
+#define S5PC110_GPIO_E1_INT_GROUP	(8)
+#define S5PC110_GPIO_F0_INT_GROUP	(9)
+#define S5PC110_GPIO_F1_INT_GROUP	(10)
+#define S5PC110_GPIO_F2_INT_GROUP	(11)
+#define S5PC110_GPIO_F3_INT_GROUP	(12)
+#define S5PC110_GPIO_G0_INT_GROUP	(13)
+#define S5PC110_GPIO_G1_INT_GROUP	(14)
+#define S5PC110_GPIO_G2_INT_GROUP	(15)
+#define S5PC110_GPIO_G3_INT_GROUP	(16)
+#define S5PC110_GPIO_J0_INT_GROUP	(17)
+#define S5PC110_GPIO_J1_INT_GROUP	(18)
+#define S5PC110_GPIO_J2_INT_GROUP	(19)
+#define S5PC110_GPIO_J3_INT_GROUP	(20)
+#define S5PC110_GPIO_J4_INT_GROUP	(21)
+#define S5PC110_GPIO_H0_INT_GROUP	(-1)
+#define S5PC110_GPIO_H1_INT_GROUP	(-1)
+#define S5PC110_GPIO_H2_INT_GROUP	(-1)
+#define S5PC110_GPIO_H3_INT_GROUP	(-1)
+#define S5PC110_GPIO_I_INT_GROUP	(-1)
+#define S5PC110_GPIO_MP0_1_INT_GROUP	(-1)
+#define S5PC110_GPIO_MP0_2_INT_GROUP	(-1)
+#define S5PC110_GPIO_MP0_3_INT_GROUP	(-1)
+#define S5PC110_GPIO_MP0_4_INT_GROUP	(-1)
+#define S5PC110_GPIO_MP0_5_INT_GROUP	(-1)
+#define S5PC110_GPIO_MP0_6_INT_GROUP	(-1)
+
+#define S5PC110_GPIO_INT_GROUP_END	(S5PC110_GPIO_J4_INT_GROUP + 1)
+
+/* Common compatibility defines */
+#define S5PC1XX_GPIO_EINT_SFN	S3C_GPIO_SFN(0xf)
+#define S5PC1XX_GPH0(n)		S5PC110_GPH0(n)
+#define S5PC1XX_GPH1(n)		S5PC110_GPH1(n)
+#define S5PC1XX_GPH2(n)		S5PC110_GPH2(n)
+#define S5PC1XX_GPH3(n)		S5PC110_GPH3(n)
+#define S5PC1XX_GPIO_INT_GROUP_END	S5PC110_GPIO_INT_GROUP_END
+
+#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s5pc110/include/plat/regs-gpio.h b/arch/arm/mach-s5pc110/include/plat/regs-gpio.h
new file mode 100644
index 0000000..24663b8
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/plat/regs-gpio.h
@@ -0,0 +1,65 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC110 - GPIO register definitions
+ */
+
+#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H
+#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__
+
+#include <mach/map.h>
+
+/* S5PC110 */
+#define S5PC110_GPIO_BASE	S5PC1XX_VA_GPIO
+#define S5PC110_GPA0_BASE	(S5PC110_GPIO_BASE + 0x0000)
+#define S5PC110_GPA1_BASE	(S5PC110_GPIO_BASE + 0x0020)
+#define S5PC110_GPB_BASE	(S5PC110_GPIO_BASE + 0x0040)
+#define S5PC110_GPC0_BASE	(S5PC110_GPIO_BASE + 0x0060)
+#define S5PC110_GPC1_BASE	(S5PC110_GPIO_BASE + 0x0080)
+#define S5PC110_GPD0_BASE	(S5PC110_GPIO_BASE + 0x00A0)
+#define S5PC110_GPD1_BASE	(S5PC110_GPIO_BASE + 0x00C0)
+#define S5PC110_GPE0_BASE	(S5PC110_GPIO_BASE + 0x00E0)
+#define S5PC110_GPE1_BASE	(S5PC110_GPIO_BASE + 0x0100)
+#define S5PC110_GPF0_BASE	(S5PC110_GPIO_BASE + 0x0120)
+#define S5PC110_GPF1_BASE	(S5PC110_GPIO_BASE + 0x0140)
+#define S5PC110_GPF2_BASE	(S5PC110_GPIO_BASE + 0x0160)
+#define S5PC110_GPF3_BASE	(S5PC110_GPIO_BASE + 0x0180)
+#define S5PC110_GPG0_BASE	(S5PC110_GPIO_BASE + 0x01A0)
+#define S5PC110_GPG1_BASE	(S5PC110_GPIO_BASE + 0x01C0)
+#define S5PC110_GPG2_BASE	(S5PC110_GPIO_BASE + 0x01E0)
+#define S5PC110_GPG3_BASE	(S5PC110_GPIO_BASE + 0x0200)
+#define S5PC110_GPH0_BASE	(S5PC110_GPIO_BASE + 0x0C00)
+#define S5PC110_GPH1_BASE	(S5PC110_GPIO_BASE + 0x0C20)
+#define S5PC110_GPH2_BASE	(S5PC110_GPIO_BASE + 0x0C40)
+#define S5PC110_GPH3_BASE	(S5PC110_GPIO_BASE + 0x0C60)
+#define S5PC110_GPI_BASE	(S5PC110_GPIO_BASE + 0x0220)
+#define S5PC110_GPJ0_BASE	(S5PC110_GPIO_BASE + 0x0240)
+#define S5PC110_GPJ1_BASE	(S5PC110_GPIO_BASE + 0x0260)
+#define S5PC110_GPJ2_BASE	(S5PC110_GPIO_BASE + 0x0280)
+#define S5PC110_GPJ3_BASE	(S5PC110_GPIO_BASE + 0x02A0)
+#define S5PC110_GPJ4_BASE	(S5PC110_GPIO_BASE + 0x02C0)
+#define S5PC110_MP0_1_BASE	(S5PC110_GPIO_BASE + 0x02E0)
+#define S5PC110_MP0_2_BASE	(S5PC110_GPIO_BASE + 0x0300)
+#define S5PC110_MP0_3_BASE	(S5PC110_GPIO_BASE + 0x0320)
+#define S5PC110_MP0_4_BASE	(S5PC110_GPIO_BASE + 0x0340)
+#define S5PC110_MP0_5_BASE	(S5PC110_GPIO_BASE + 0x0360)
+#define S5PC110_EXT_INT_BASE	(S5PC110_GPIO_BASE + 0x0E00)
+#define S5PC110_PDNEN		(S5PC110_GPIO_BASE + 0x0F80)
+#define S5PC100_PDNEN_NORMAL	(0 << 0)
+
+#define S5PC110_PDNEN_CFG_PDNEN	(1 << 1)
+#define S5PC110_PDNEN_CFG_AUTO	(0 << 1)
+#define S5PC110_PDNEN_POWERDOWN	(1 << 0)
+#define S5PC110_PDNEN_NORMAL	(0 << 0)
+
+/* Common part */
+#define S5PC1XX_EINT_BASE	(S5PC110_EXT_INT_BASE)
+
+#define S5PC1XX_GPx_INPUT(__gpio)	(0x0 << ((__gpio) * 4))
+#define S5PC1XX_GPx_OUTPUT(__gpio)	(0x1 << ((__gpio) * 4))
+#define S5PC1XX_GPx_CONMASK(__gpio)	(0xf << ((__gpio) * 4))
+
+#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */
+
-- 
1.6.4

[PATCH 15/20] ARM: S5PC1XX: add i2c platform helpers on s5pc110 sub-platform

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds required I2C platform helpers. S5PC110 SoCs has 3 I2C
controllers.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Byungho Min <bhmin@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/mach-s5pc110/Kconfig        |   18 +++++++++
 arch/arm/mach-s5pc110/Makefile       |    3 +
 arch/arm/mach-s5pc110/cpu.c          |    3 +
 arch/arm/mach-s5pc110/setup-i2c0.c   |   31 +++++++++++++++
 arch/arm/mach-s5pc110/setup-i2c1.c   |   31 +++++++++++++++
 arch/arm/mach-s5pc110/setup-i2c2.c   |   32 ++++++++++++++++
 arch/arm/plat-s3c/Kconfig            |    5 ++
 arch/arm/plat-s3c/Makefile           |    1 +
 arch/arm/plat-s3c/dev-i2c2.c         |   69 ++++++++++++++++++++++++++++++++++
 arch/arm/plat-s3c/include/plat/iic.h |    2 +
 10 files changed, 195 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/setup-i2c0.c
 create mode 100644 arch/arm/mach-s5pc110/setup-i2c1.c
 create mode 100644 arch/arm/mach-s5pc110/setup-i2c2.c
 create mode 100644 arch/arm/plat-s3c/dev-i2c2.c

diff --git a/arch/arm/mach-s5pc110/Kconfig b/arch/arm/mach-s5pc110/Kconfig
index 4257b96..6b4d977 100644
--- a/arch/arm/mach-s5pc110/Kconfig
+++ b/arch/arm/mach-s5pc110/Kconfig
@@ -14,4 +14,22 @@ config CPU_S5PC110
 	help
 	  Enable S5PC110 CPU support
 
+config S5PC110_SETUP_I2C0
+	bool
+	default y
+	help
+	  Common setup code for i2c bus 0.
+
+	  Note, currently since i2c0 is always compiled, this setup helper
+	  is always compiled with it.
+
+config S5PC110_SETUP_I2C1
+	bool
+	help
+	  Common setup code for i2c bus 1.
+
+config S5PC110_SETUP_I2C2
+	bool
+	help
+	  Common setup code for i2c bus 2.
 endif
diff --git a/arch/arm/mach-s5pc110/Makefile b/arch/arm/mach-s5pc110/Makefile
index 3849e27..93311b3 100644
--- a/arch/arm/mach-s5pc110/Makefile
+++ b/arch/arm/mach-s5pc110/Makefile
@@ -18,5 +18,8 @@ obj-$(CONFIG_CPU_S5PC110)	+= plls.o
 obj-$(CONFIG_CPU_S5PC110)	+= uarts.o
 
 # Helper and device support
+obj-$(CONFIG_S5PC110_SETUP_I2C0)	+= setup-i2c0.o
+obj-$(CONFIG_S5PC110_SETUP_I2C1)	+= setup-i2c1.o
+obj-$(CONFIG_S5PC110_SETUP_I2C2)	+= setup-i2c2.o
 
 # machine support
diff --git a/arch/arm/mach-s5pc110/cpu.c b/arch/arm/mach-s5pc110/cpu.c
index 3ea26ff..d16ba68 100644
--- a/arch/arm/mach-s5pc110/cpu.c
+++ b/arch/arm/mach-s5pc110/cpu.c
@@ -86,6 +86,9 @@ void __init s5pc110_map_io(void)
 	iotable_init(s5pc110_iodesc, ARRAY_SIZE(s5pc110_iodesc));
 
 	/* initialise device information early */
+	/* the i2c devices are directly compatible with s3c2440 */
+	s3c_i2c0_setname("s3c2440-i2c");
+	s3c_i2c1_setname("s3c2440-i2c");
 }
 
 void __init s5pc110_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5pc110/setup-i2c0.c b/arch/arm/mach-s5pc110/setup-i2c0.c
new file mode 100644
index 0000000..596b139
--- /dev/null
+++ b/arch/arm/mach-s5pc110/setup-i2c0.c
@@ -0,0 +1,31 @@
+/*
+ * linux/arch/arm/mach-s5pc110/setup-i2c2.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Base S5PC110 I2C bus 0 gpio configuration
+ *
+ * Based on plat-s3c64xx/setup-i2c0.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <mach/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c0_cfg_gpio(struct platform_device *dev)
+{
+	s3c_gpio_cfgpin(S5PC110_GPD1(0), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC110_GPD1(0), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC110_GPD1(1), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC110_GPD1(1), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pc110/setup-i2c1.c b/arch/arm/mach-s5pc110/setup-i2c1.c
new file mode 100644
index 0000000..cd9649b
--- /dev/null
+++ b/arch/arm/mach-s5pc110/setup-i2c1.c
@@ -0,0 +1,31 @@
+/*
+ * linux/arch/arm/mach-s5pc110/setup-i2c1.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Base S5PC110 I2C bus 1 gpio configuration
+ *
+ * Based on plat-s3c64xx/setup-i2c1.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <mach/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c1_cfg_gpio(struct platform_device *dev)
+{
+	s3c_gpio_cfgpin(S5PC110_GPD1(2), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC110_GPD1(2), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC110_GPD1(3), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC110_GPD1(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pc110/setup-i2c2.c b/arch/arm/mach-s5pc110/setup-i2c2.c
new file mode 100644
index 0000000..aa20628
--- /dev/null
+++ b/arch/arm/mach-s5pc110/setup-i2c2.c
@@ -0,0 +1,32 @@
+/*
+ * linux/arch/arm/mach-s5pc110/setup-i2c2.c
+ *
+ * Copyright (C) 2009 Samsung Electronics Co.Ltd
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Base S5PC110 I2C bus 2 gpio configuration
+ *
+ * Based on plat-s3c64xx/setup-i2c1.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <mach/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c2_cfg_gpio(struct platform_device *dev)
+{
+	s3c_gpio_cfgpin(S5PC110_GPD1(4), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC110_GPD1(4), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC110_GPD1(5), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC110_GPD1(5), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig
index e139a72..afdfca2 100644
--- a/arch/arm/plat-s3c/Kconfig
+++ b/arch/arm/plat-s3c/Kconfig
@@ -194,6 +194,11 @@ config S3C_DEV_I2C1
 	help
 	  Compile in platform device definitions for I2C channel 1
 
+config S3C_DEV_I2C2
+	bool
+	help
+	  Compile in platform device definitions for I2C channel 2
+
 config S3C_DEV_FB
 	bool
 	help
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index 50444da..c40e312 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_S3C_DEV_HSMMC1)	+= dev-hsmmc1.o
 obj-$(CONFIG_S3C_DEV_HSMMC2)	+= dev-hsmmc2.o
 obj-y				+= dev-i2c0.o
 obj-$(CONFIG_S3C_DEV_I2C1)	+= dev-i2c1.o
+obj-$(CONFIG_S3C_DEV_I2C2)	+= dev-i2c2.o
 obj-$(CONFIG_S3C_DEV_FB)	+= dev-fb.o
 obj-$(CONFIG_S3C_DEV_USB_HOST)	+= dev-usb.o
 obj-$(CONFIG_S3C_DEV_USB_HSOTG)	+= dev-usb-hsotg.o
diff --git a/arch/arm/plat-s3c/dev-i2c2.c b/arch/arm/plat-s3c/dev-i2c2.c
new file mode 100644
index 0000000..49ec279
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-i2c2.c
@@ -0,0 +1,69 @@
+/*
+ * linux/arch/arm/plat-s3c/dev-i2c2.c
+ *
+ * Copyright (C) 2009 Samsung Electronics Co.Ltd
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * S3C series device definition for i2c device 2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/cpu.h>
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+
+static struct resource s3c_i2c_resource[] = {
+	[0] = {
+		.start = S3C_PA_IIC2,
+		.end   = S3C_PA_IIC2 + SZ_4K - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_I2C_PMIC_LINK,
+		.end   = IRQ_I2C_PMIC_LINK,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device s3c_device_i2c2 = {
+	.name		  = "s3c2440-i2c",
+	.id		  = 2,
+	.num_resources	  = ARRAY_SIZE(s3c_i2c_resource),
+	.resource	  = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data2 __initdata = {
+	.flags		= 0,
+	.bus_num	= 2,
+	.slave_addr	= 0x10,
+	.frequency	= 400*1000,
+	.sda_delay	= 100,
+};
+
+void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+	struct s3c2410_platform_i2c *npd;
+
+	if (!pd)
+		pd = &default_i2c_data2;
+
+	npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+	if (!npd)
+		printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+	else if (!npd->cfg_gpio)
+		npd->cfg_gpio = s3c_i2c2_cfg_gpio;
+
+	s3c_device_i2c2.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-s3c/include/plat/iic.h b/arch/arm/plat-s3c/include/plat/iic.h
index 67450f1..9f22675 100644
--- a/arch/arm/plat-s3c/include/plat/iic.h
+++ b/arch/arm/plat-s3c/include/plat/iic.h
@@ -54,9 +54,11 @@ struct s3c2410_platform_i2c {
  */
 extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
 extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *i2c);
 
 /* defined by architecture to configure gpio */
 extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
 extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c2_cfg_gpio(struct platform_device *dev);
 
 #endif /* __ASM_ARCH_IIC_H */
-- 
1.6.4

[PATCH 16/20] ARM: S5PC1XX: enable S5PC110 sub-platform

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch enables S5PC110 sub-platform.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/Kconfig              |    1 +
 arch/arm/Makefile             |    1 +
 arch/arm/plat-s5pc1xx/Kconfig |    3 +++
 3 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1c4119c..280c38e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -770,6 +770,7 @@ source "arch/arm/plat-stmp3xxx/Kconfig"
 
 if ARCH_S5PC1XX
 source "arch/arm/mach-s5pc100/Kconfig"
+source "arch/arm/mach-s5pc110/Kconfig"
 endif
 
 source "arch/arm/mach-lh7a40x/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index daea150..d9daa45 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -161,6 +161,7 @@ machine-$(CONFIG_ARCH_S3C2410)		:= s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c24
 machine-$(CONFIG_ARCH_S3C24A0)		:= s3c24a0
 machine-$(CONFIG_ARCH_S3C64XX)		:= s3c6400 s3c6410
 machine-$(CONFIG_ARCH_S5PC100)		:= s5pc100
+machine-$(CONFIG_ARCH_S5PC110)		:= s5pc110
 machine-$(CONFIG_ARCH_SA1100)		:= sa1100
 machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_STMP378X)		:= stmp378x
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index 4a3347d..b310314 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -30,6 +30,9 @@ choice
 config ARCH_S5PC100
 	bool "S5PC100"
 
+config ARCH_S5PC110
+	bool "S5PC110"
+
 endchoice
 
 
-- 
1.6.4

[PATCH 17/20] ARM: S5PC1XX: add sdhci platform helpers for s5pc110 sub-platform

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds common SDHCI platform helper for S5PC110 sub-platform.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/mach-s5pc110/Kconfig            |   12 +++
 arch/arm/mach-s5pc110/Makefile           |    2 +
 arch/arm/mach-s5pc110/cpu.c              |    5 +
 arch/arm/mach-s5pc110/setup-sdhci-gpio.c |  123 ++++++++++++++++++++++++++++++
 arch/arm/mach-s5pc110/setup-sdhci.c      |   59 ++++++++++++++
 arch/arm/plat-s3c/include/plat/sdhci.h   |   64 +++++++++++++++
 6 files changed, 265 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/setup-sdhci-gpio.c
 create mode 100644 arch/arm/mach-s5pc110/setup-sdhci.c

diff --git a/arch/arm/mach-s5pc110/Kconfig b/arch/arm/mach-s5pc110/Kconfig
index 6b4d977..0e13f54 100644
--- a/arch/arm/mach-s5pc110/Kconfig
+++ b/arch/arm/mach-s5pc110/Kconfig
@@ -32,4 +32,16 @@ config S5PC110_SETUP_I2C2
 	bool
 	help
 	  Common setup code for i2c bus 2.
+
+config S5PC110_SETUP_SDHCI
+        bool
+        select S5PC110_SETUP_SDHCI_GPIO
+        help
+          Internal helper functions for S5PC110 based SDHCI systems
+
+config S5PC110_SETUP_SDHCI_GPIO
+	bool
+	help
+	  Common setup code for SDHCI gpio.
+
 endif
diff --git a/arch/arm/mach-s5pc110/Makefile b/arch/arm/mach-s5pc110/Makefile
index 93311b3..cf8f4ef 100644
--- a/arch/arm/mach-s5pc110/Makefile
+++ b/arch/arm/mach-s5pc110/Makefile
@@ -21,5 +21,7 @@ obj-$(CONFIG_CPU_S5PC110)	+= uarts.o
 obj-$(CONFIG_S5PC110_SETUP_I2C0)	+= setup-i2c0.o
 obj-$(CONFIG_S5PC110_SETUP_I2C1)	+= setup-i2c1.o
 obj-$(CONFIG_S5PC110_SETUP_I2C2)	+= setup-i2c2.o
+obj-$(CONFIG_S5PC110_SETUP_SDHCI)       += setup-sdhci.o
+obj-$(CONFIG_S5PC110_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
 
 # machine support
diff --git a/arch/arm/mach-s5pc110/cpu.c b/arch/arm/mach-s5pc110/cpu.c
index d16ba68..e72582f 100644
--- a/arch/arm/mach-s5pc110/cpu.c
+++ b/arch/arm/mach-s5pc110/cpu.c
@@ -86,6 +86,11 @@ void __init s5pc110_map_io(void)
 	iotable_init(s5pc110_iodesc, ARRAY_SIZE(s5pc110_iodesc));
 
 	/* initialise device information early */
+	s5pc110_default_sdhci0();
+	s5pc110_default_sdhci1();
+	s5pc110_default_sdhci2();
+	s5pc110_default_sdhci3();
+
 	/* the i2c devices are directly compatible with s3c2440 */
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
diff --git a/arch/arm/mach-s5pc110/setup-sdhci-gpio.c b/arch/arm/mach-s5pc110/setup-sdhci-gpio.c
new file mode 100644
index 0000000..49db2a0
--- /dev/null
+++ b/arch/arm/mach-s5pc110/setup-sdhci-gpio.c
@@ -0,0 +1,123 @@
+/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
+ *
+ * Copyright 2009 Samsung Eletronics
+ *
+ * S5PC110 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-sdhci.h>
+
+void s5pc110_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+
+	/* Set all the necessary GPG0/GPG1 pins to special-function 2 */
+	for (gpio = S5PC110_GPG0(0); gpio < S5PC110_GPG0(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+	switch (width) {
+	case 8:
+		/* GPG1[3:6] special-funtion 3 */
+		for (gpio = S5PC110_GPG1(3); gpio <= S5PC110_GPG1(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		}
+	case 4:
+		/* GPG0[3:6] special-funtion 2 */
+		for (gpio = S5PC110_GPG0(3); gpio <= S5PC110_GPG0(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		}
+	default:
+		break;
+	}
+
+	s3c_gpio_setpull(S5PC110_GPG0(2), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC110_GPG0(2), S3C_GPIO_SFN(2));
+}
+
+void s5pc110_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+
+	/* Set all the necessary GPG1[0:1] pins to special-function 2 */
+	for (gpio = S5PC110_GPG1(0); gpio < S5PC110_GPG1(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	/* Data pin GPG1[3:6] to special-function 2 */
+	for (gpio = S5PC110_GPG1(3); gpio <= S5PC110_GPG1(6); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	s3c_gpio_setpull(S5PC110_GPG1(2), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC110_GPG1(2), S3C_GPIO_SFN(2));
+}
+
+void s5pc110_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+
+	/* Set all the necessary GPG2[0:1] pins to special-function 2 */
+	for (gpio = S5PC110_GPG2(0); gpio < S5PC110_GPG2(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	switch (width) {
+	case 8:
+		/* Data pin GPG3[3:6] to special-function 3 */
+		for (gpio = S5PC110_GPG3(3); gpio <= S5PC110_GPG3(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		}
+	case 4:
+		/* Data pin GPG2[3:6] to special-function 2 */
+		for (gpio = S5PC110_GPG2(3); gpio <= S5PC110_GPG2(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		}
+	default:
+		break;
+	}
+
+	s3c_gpio_setpull(S5PC110_GPG2(2), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC110_GPG2(2), S3C_GPIO_SFN(2));
+}
+
+void s5pc110_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+
+	/* Set all the necessary GPG3[0:1] pins to special-function 2 */
+	for (gpio = S5PC110_GPG3(0); gpio < S5PC110_GPG3(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	/* Data pin GPG3[3:6] to special-function 2 */
+	for (gpio = S5PC110_GPG3(3); gpio <= S5PC110_GPG3(6); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	s3c_gpio_setpull(S5PC110_GPG3(2), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC110_GPG3(2), S3C_GPIO_SFN(2));
+}
diff --git a/arch/arm/mach-s5pc110/setup-sdhci.c b/arch/arm/mach-s5pc110/setup-sdhci.c
new file mode 100644
index 0000000..c368bb5
--- /dev/null
+++ b/arch/arm/mach-s5pc110/setup-sdhci.c
@@ -0,0 +1,59 @@
+/* linux/arch/arm/mach-s5pc100/setup-sdhci.c
+ *
+ * Copyright 2008 Samsung Electronics
+ *
+ * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+
+char *s5pc110_hsmmc_clksrcs[4] = {
+	[0] = "mmc-bus",
+};
+
+void s5pc110_setup_sdhci_cfg_card(struct platform_device *dev,
+				    void __iomem *r,
+				    struct mmc_ios *ios,
+				    struct mmc_card *card)
+{
+	u32 ctrl2, ctrl3;
+
+	/* don't need to alter anything acording to card-type */
+
+	writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
+
+	ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
+	ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+	ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
+		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
+		  S3C_SDHCI_CTRL2_ENFBCLKRX |
+		  S3C_SDHCI_CTRL2_DFCNT_NONE |
+		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+
+	if (ios->clock < 25 * 1000000)
+		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
+			 S3C_SDHCI_CTRL3_FCSEL2 |
+			 S3C_SDHCI_CTRL3_FCSEL1 |
+			 S3C_SDHCI_CTRL3_FCSEL0);
+	else
+		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
+
+	writel(ctrl2, r + S3C_SDHCI_CONTROL2);
+	writel(ctrl3, r + S3C_SDHCI_CONTROL3);
+}
diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-s3c/include/plat/sdhci.h
index c71d078..cf71b93 100644
--- a/arch/arm/plat-s3c/include/plat/sdhci.h
+++ b/arch/arm/plat-s3c/include/plat/sdhci.h
@@ -74,6 +74,10 @@ extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s5pc110_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s5pc110_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5pc110_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s5pc110_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
 
 /* S3C6400 SDHCI setup */
 
@@ -200,4 +204,64 @@ static inline void s5pc100_default_sdhci1(void) { }
 static inline void s5pc100_default_sdhci2(void) { }
 #endif /* CONFIG_S5PC100_SETUP_SDHCI */
 
+/* S5PC110 SDHCI setup */
+#ifdef CONFIG_S5PC110_SETUP_SDHCI
+extern char *s5pc110_hsmmc_clksrcs[4];
+
+extern void s5pc110_setup_sdhci_cfg_card(struct platform_device *dev,
+					   void __iomem *r,
+					   struct mmc_ios *ios,
+					   struct mmc_card *card);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static inline void s5pc110_default_sdhci0(void)
+{
+	s3c_hsmmc0_def_platdata.clocks = s5pc110_hsmmc_clksrcs;
+	s3c_hsmmc0_def_platdata.cfg_gpio = s5pc110_setup_sdhci0_cfg_gpio;
+	s3c_hsmmc0_def_platdata.cfg_card = s5pc110_setup_sdhci_cfg_card;
+}
+#else
+static inline void s5pc100_default_sdhci0(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC */
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static inline void s5pc110_default_sdhci1(void)
+{
+	s3c_hsmmc1_def_platdata.clocks = s5pc110_hsmmc_clksrcs;
+	s3c_hsmmc1_def_platdata.cfg_gpio = s5pc110_setup_sdhci1_cfg_gpio;
+	s3c_hsmmc1_def_platdata.cfg_card = s5pc110_setup_sdhci_cfg_card;
+}
+#else
+static inline void s5pc110_default_sdhci1(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static inline void s5pc110_default_sdhci2(void)
+{
+	s3c_hsmmc2_def_platdata.clocks = s5pc110_hsmmc_clksrcs;
+	s3c_hsmmc2_def_platdata.cfg_gpio = s5pc110_setup_sdhci2_cfg_gpio;
+	s3c_hsmmc2_def_platdata.cfg_card = s5pc110_setup_sdhci_cfg_card;
+}
+#else
+static inline void s5pc110_default_sdhci2(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC2 */
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+static inline void s5pc110_default_sdhci3(void)
+{
+	s3c_hsmmc3_def_platdata.clocks = s5pc110_hsmmc_clksrcs;
+	s3c_hsmmc3_def_platdata.cfg_gpio = s5pc110_setup_sdhci3_cfg_gpio;
+	s3c_hsmmc3_def_platdata.cfg_card = s5pc110_setup_sdhci_cfg_card;
+}
+#else
+static inline void s5pc110_default_sdhci3(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC3 */
+
+#else
+static inline void s5pc110_default_sdhci0(void) { }
+static inline void s5pc110_default_sdhci1(void) { }
+static inline void s5pc110_default_sdhci2(void) { }
+static inline void s5pc110_default_sdhci3(void) { }
+#endif /* CONFIG_S5PC100_SETUP_SDHCI */
+
 #endif /* __PLAT_S3C_SDHCI_H */
-- 
1.6.4

[PATCH 18/20] ARM: S5PC1XX: add framebuffer platform helpers for s5pc110 sub-platform

[Marek Szyprowski]

From: Pawel Osciak <p.osciak@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds common framebuffer device helpers and register defines
for S5PC110 sub-platform.

Signed-off-by: Pawel Osciak <p.osciak@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/mach-s5pc110/Kconfig                |    5 ++
 arch/arm/mach-s5pc110/Makefile               |    1 +
 arch/arm/mach-s5pc110/include/mach/regs-fb.h |   91 ++++++++++++++++++++++++++
 arch/arm/mach-s5pc110/setup-fb-24bpp.c       |   67 +++++++++++++++++++
 arch/arm/plat-s3c/include/plat/fb.h          |    7 ++
 5 files changed, 171 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/include/mach/regs-fb.h
 create mode 100644 arch/arm/mach-s5pc110/setup-fb-24bpp.c

diff --git a/arch/arm/mach-s5pc110/Kconfig b/arch/arm/mach-s5pc110/Kconfig
index 0e13f54..ef2f940 100644
--- a/arch/arm/mach-s5pc110/Kconfig
+++ b/arch/arm/mach-s5pc110/Kconfig
@@ -14,6 +14,11 @@ config CPU_S5PC110
 	help
 	  Enable S5PC110 CPU support
 
+config S5PC110_SETUP_FB_24BPP
+	bool
+	help
+          Common setup code for S5PC110 with an 24bpp RGB display helper.
+
 config S5PC110_SETUP_I2C0
 	bool
 	default y
diff --git a/arch/arm/mach-s5pc110/Makefile b/arch/arm/mach-s5pc110/Makefile
index cf8f4ef..d7e03b6 100644
--- a/arch/arm/mach-s5pc110/Makefile
+++ b/arch/arm/mach-s5pc110/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_CPU_S5PC110)	+= plls.o
 obj-$(CONFIG_CPU_S5PC110)	+= uarts.o
 
 # Helper and device support
+obj-$(CONFIG_S5PC110_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
 obj-$(CONFIG_S5PC110_SETUP_I2C0)	+= setup-i2c0.o
 obj-$(CONFIG_S5PC110_SETUP_I2C1)	+= setup-i2c1.o
 obj-$(CONFIG_S5PC110_SETUP_I2C2)	+= setup-i2c2.o
diff --git a/arch/arm/mach-s5pc110/include/mach/regs-fb.h b/arch/arm/mach-s5pc110/include/mach/regs-fb.h
new file mode 100644
index 0000000..27fa497
--- /dev/null
+++ b/arch/arm/mach-s5pc110/include/mach/regs-fb.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2009 Samsung Electronics Co.
+ *   Pawel Osciak <p.osciak@samsung.com>
+ *
+ * Machine-specific framebuffer definitions for Samsung S5PC110.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MACH_REGS_FB_H
+#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
+
+#include <plat/regs-fb-v5.h>
+
+/* WINCONx */
+#define WINCONx_BUFSTATUS_H				(1 << 31)
+#define WINCONx_BUFSEL_H				(1 << 30)
+#define WINCONx_LIMIT_ON				(1 << 29)
+#define WINCONx_EQ709					(1 << 28)
+
+
+/* VIDCON3 */
+#define VIDCON3						(0x0c)
+#define VIDCON3_VE_ON					(1 << 20)
+#define VIDCON3_CG_ON					(1 << 18)
+#define VIDCON3_GM_ON					(1 << 16)
+#define VIDCON3_HU_CSC_F_NARROW				(1 << 14)
+#define VIDCON3_HU_CSC_F_EQ709				(1 << 13)
+#define VIDCON3_HU_CSC_F_EN				(1 << 12)
+#define VIDCON3_HU_CSC_B_NARROW				(1 << 10)
+#define VIDCON3_HU_CSC_B_EQ709				(1 << 9)
+#define VIDCON3_HU_CSC_B_EN				(1 << 8)
+#define VIDCON3_HUE_EN					(1 << 7)
+#define VIDCON3_PC_DIR_NEG				(1 << 1)
+#define VIDCON3_PC_EN					(1 << 0)
+
+
+/* VIDTCON3 */
+#define VIDTCON3					(0x1c)
+#define VIDTCON3_VSYNC_EN				(1 << 31)
+#define VIDTCON3_FRM_EN					(1 << 29)
+#define VIDTCON3_INVFRM_LOW				(1 << 28)
+#define VIDTCON3_FRMVRATE_MASK				0xf
+#define VIDTCON3_FRMVRATE_SHIFT				(24)
+#define VIDTCON3_FRMVFPD_MASK				0xff
+#define VIDTCON3_FRMVFPD_SHIFT				(8)
+#define VIDTCON3_FRMVSPW_MASK				0xff
+#define VIDTCON3_FRMVSPW_SHIFT				(0)
+
+
+#define SHADOWCON					(0x34)
+/* Set to disable window 4-0 shadow registers' update */
+#define SHADOWCON_W4_PROTECT				(1 << 14)
+#define SHADOWCON_W3_PROTECT				(1 << 13)
+#define SHADOWCON_W2_PROTECT				(1 << 12)
+#define SHADOWCON_W1_PROTECT				(1 << 11)
+#define SHADOWCON_W0_PROTECT				(1 << 10)
+
+
+/* Video buffer address shadow registers (read-only) */
+#define VIDW_BUF_START_SHADOW(_buf)			(0x20a0 + ((_buf) * 8))
+#define VIDW_BUF_END_SHADOW(_buf)			(0x20d0 + ((_buf) * 8))
+
+/* For windows 1-4 */
+#define WxKEY_ALPHA(_win)				(0x160 + ((_win) * 4))
+
+#define COLORGAINCON					(0x1c0)
+#define VESFRCON0					(0x1c4)
+#define VESFRCON1					(0x1c8)
+#define VESFRCON2					(0x1cc)
+
+/* Hue matrix coefficients */
+#define HUECOEF00					(0x1ec)
+#define HUECOEF01					(0x1f0)
+#define HUECOEF10					(0x1f4)
+#define HUECOEF11					(0x1f8)
+#define HUEOFFSET					(0x1fc)
+
+/* RTQOS control for windows 0-4*/
+#define WxRTQOSCON(_win)				(0x264 + ((_win) * 4))
+
+/* Gamma LUT data for index I1 and I0, where
+ * I0 = _index, I1 = _index + 1.
+ */
+#define GAMMALUT_BASE					(0x37c)
+#define GAMMALUT_I1I0(_index)			(GAMMALUT_BASE + ((_index) * 4))
+
+#endif /* __ASM_ARCH_MACH_REGS_FB_H */
+
diff --git a/arch/arm/mach-s5pc110/setup-fb-24bpp.c b/arch/arm/mach-s5pc110/setup-fb-24bpp.c
new file mode 100644
index 0000000..993504e
--- /dev/null
+++ b/arch/arm/mach-s5pc110/setup-fb-24bpp.c
@@ -0,0 +1,67 @@
+/*
+ * linux/arch/arm/plat-s5pc100/setup-fb-24bpp.c
+ *
+ * Copyright 2009 Samsung Electronics
+ *
+ * Base S5PC110 setup information for 24bpp LCD framebuffer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/fb.h>
+
+#include <mach/regs-fb.h>
+#include <mach/gpio.h>
+#include <mach/map.h>
+#include <plat/fb.h>
+#include <plat/regs-clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-s5pc1xx.h>
+
+void s5pc110_fb_gpio_setup_24bpp(void)
+{
+	unsigned int gpio = 0;
+
+	for (gpio = S5PC110_GPF0(0); gpio <= S5PC110_GPF0(7); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, gpio-S5PC110_GPF0(0),
+				    S5P_GPIO_DRVSTR_LV4);
+	}
+
+	for (gpio = S5PC110_GPF1(0); gpio <= S5PC110_GPF1(7); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, gpio-S5PC110_GPF1(0),
+				    S5P_GPIO_DRVSTR_LV4);
+	}
+
+	for (gpio = S5PC110_GPF2(0); gpio <= S5PC110_GPF2(7); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, gpio-S5PC110_GPF2(0),
+				    S5P_GPIO_DRVSTR_LV4);
+	}
+
+	for (gpio = S5PC110_GPF3(0); gpio <= S5PC110_GPF3(3); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, gpio-S5PC110_GPF3(0),
+				    S5P_GPIO_DRVSTR_LV4);
+	}
+
+	/* Set DISPLAY_CONTROL register for Display path selection.
+	 *
+	 * ouput   |   RGB   |   I80   |   ITU
+	 * -----------------------------------
+	 *  00     |   MIE   |  FIMD   |  FIMD
+	 *  01     | MDNIE   | MDNIE   |  FIMD
+	 *  10     |  FIMD   |  FIMD   |  FIMD
+	 *  11     |  FIMD   |  FIMD   |  FIMD
+	 */
+	writel(0x2, S5PC110_MDNIE_SEL);
+}
diff --git a/arch/arm/plat-s3c/include/plat/fb.h b/arch/arm/plat-s3c/include/plat/fb.h
index f8db879..ee5cdd0 100644
--- a/arch/arm/plat-s3c/include/plat/fb.h
+++ b/arch/arm/plat-s3c/include/plat/fb.h
@@ -77,4 +77,11 @@ extern void s3c64xx_fb_gpio_setup_24bpp(void);
  */
 extern void s5pc100_fb_gpio_setup_24bpp(void);
 
+/**
+ * s5pc110_fb_gpio_setup_24bpp() - S5PC110 setup function for 24bpp LCD
+ *
+ * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
+ */
+extern void s5pc110_fb_gpio_setup_24bpp(void);
+
 #endif /* __PLAT_S3C_FB_H */
-- 
1.6.4

[PATCH 19/20] ARM: S5PC1XX: add support for SMDKC110 board

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds support for SMDKC110 evaluation board. The board can be
obtained from Meritech (http://www.meritech.co.kr).

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/mach-s5pc110/Kconfig         |    6 ++
 arch/arm/mach-s5pc110/Makefile        |    1 +
 arch/arm/mach-s5pc110/mach-smdkc110.c |  102 +++++++++++++++++++++++++++++++++
 3 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc110/mach-smdkc110.c

diff --git a/arch/arm/mach-s5pc110/Kconfig b/arch/arm/mach-s5pc110/Kconfig
index ef2f940..b2374fd 100644
--- a/arch/arm/mach-s5pc110/Kconfig
+++ b/arch/arm/mach-s5pc110/Kconfig
@@ -49,4 +49,10 @@ config S5PC110_SETUP_SDHCI_GPIO
 	help
 	  Common setup code for SDHCI gpio.
 
+config MACH_SMDKC110
+	bool "SMDKC110"
+	select CPU_S5PC110
+	help
+	  Machine support for the SMDKC110 board
+
 endif
diff --git a/arch/arm/mach-s5pc110/Makefile b/arch/arm/mach-s5pc110/Makefile
index d7e03b6..3017ddd 100644
--- a/arch/arm/mach-s5pc110/Makefile
+++ b/arch/arm/mach-s5pc110/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_S5PC110_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_S5PC110_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
 
 # machine support
+obj-$(CONFIG_MACH_SMDKC110)	+= mach-smdkc110.o
diff --git a/arch/arm/mach-s5pc110/mach-smdkc110.c b/arch/arm/mach-s5pc110/mach-smdkc110.c
new file mode 100644
index 0000000..2d39dfb
--- /dev/null
+++ b/arch/arm/mach-s5pc110/mach-smdkc110.c
@@ -0,0 +1,102 @@
+/*
+ * linux/arch/arm/mach-s5pc110/mach-smdkc110.c
+ *
+ *  Copyright (C) 2009 Samsung Electronics Co.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/map.h>
+
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/s5pc1xx.h>
+
+#define UCON	(S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
+#define ULCON	(S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
+#define UFCON	(S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+
+static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport	     = 0,
+		.flags	     = 0,
+		.ucon	     = 0x3c5,
+		.ulcon	     = 0x03,
+		.ufcon	     = 0x51,
+	},
+	[1] = {
+		.hwport	     = 1,
+		.flags	     = 0,
+		.ucon	     = 0x3c5,
+		.ulcon	     = 0x03,
+		.ufcon	     = 0x51,
+	},
+	[2] = {
+		.hwport	     = 2,
+		.flags	     = 0,
+		.ucon	     = 0x3c5,
+		.ulcon	     = 0x03,
+		.ufcon	     = 0x51,
+	},
+	[3] = {
+		.hwport	     = 3,
+		.flags	     = 0,
+		.ucon	     = 0x3c5,
+		.ulcon	     = 0x03,
+		.ufcon	     = 0x51,
+	},
+};
+
+static struct platform_device *universal_devices[] __initdata = {
+};
+
+static struct map_desc universal_iodesc[] = {};
+
+static void __init universal_map_io(void)
+{
+	s5pc1xx_init_io(universal_iodesc, ARRAY_SIZE(universal_iodesc));
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
+}
+
+static void __init universal_machine_init(void)
+{
+	platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
+}
+
+MACHINE_START(SMDKC110, "SMDKC110")
+	/* Maintainer: Samsung Electronics */
+	.phys_io	= S5PC110_PA_UART & 0xfff00000,
+	.io_pg_offst	= (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc,
+	.boot_params	= S5PC110_PA_SDRAM + 0x100,
+	.init_irq	= s5pc110_init_irq,
+	.map_io		= universal_map_io,
+	.init_machine	= universal_machine_init,
+	.timer		= &s3c24xx_timer,
+MACHINE_END
-- 
1.6.4

[PATCH 20/20] MAINTAINERS: add ARM/S5PC100 and ARM/S5PC110 architectures

[Marek Szyprowski]

From: Kyungmin Park <kyungmin.park@samsung.com>

Add entries for the ARM S5PC100 and ARM S5PC110 architectures that are
currently being maintained by ourself.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 MAINTAINERS |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 81d68d5..de7daad 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -877,6 +877,22 @@ W:	http://www.fluff.org/ben/linux/
 S:	Maintained
 F:	arch/arm/mach-s3c6410/
 
+ARM/S5PC100 ARM ARCHITECTURE
+M:	Kyungmin Park <kyungmin.park@samsung.com>
+M:	Marek Szyprowski <m.szyprowski@samsung.com>
+L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
+L:	linux-samsung-soc at vger.kernel.org (moderated for non-subscribers)
+S:	Supported
+F:	arch/arm/mach-s5pc100/
+
+ARM/S5PC110 ARM ARCHITECTURE
+M:	Kyungmin Park <kyungmin.park@samsung.com>
+M:	Marek Szyprowski <m.szyprowski@samsung.com>
+L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
+L:	linux-samsung-soc at vger.kernel.org (moderated for non-subscribers)
+S:	Supported
+F:	arch/arm/mach-s5pc110/
+
 ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
 M:	Lennert Buytenhek <kernel@wantstofly.org>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
-- 
1.6.4

[PATCH 01/20] ARM: S5PC100: use 0x30008000 as memory base

[jassi brar]

On Fri, Nov 20, 2009 at 10:42 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> From: Kyungmin Park <kyungmin.park@samsung.com>
>
> We decided to use 0x3000'0000 as base memory address on S5PC1XX SoCs
> (s5pc100 and s5pc110).
you might as well want to explain the reason behind it, if any?

> A patch to u-boot that configures SMDKC100 board and sets base memory
> as 0x3000'0000 has been already posted.
>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> ?arch/arm/mach-s5pc100/Makefile.boot ? ? ? ? | ? ?4 ++--
> ?arch/arm/mach-s5pc100/include/mach/map.h ? ?| ? ?2 +-
> ?arch/arm/mach-s5pc100/include/mach/memory.h | ? ?2 +-
> ?3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-s5pc100/Makefile.boot b/arch/arm/mach-s5pc100/Makefile.boot
> index ff90aa1..b0909e3 100644
> --- a/arch/arm/mach-s5pc100/Makefile.boot
> +++ b/arch/arm/mach-s5pc100/Makefile.boot
> @@ -1,2 +1,2 @@
> - ? zreladdr-y ?:= 0x20008000
> -params_phys-y ?:= 0x20000100
> + ? zreladdr-y ?:= 0x30008000
> +params_phys-y ?:= 0x30000100
> diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
> index 4681ebe..f90c033 100644
> --- a/arch/arm/mach-s5pc100/include/mach/map.h
> +++ b/arch/arm/mach-s5pc100/include/mach/map.h
> @@ -113,7 +113,7 @@
> ?#define S5PC100_PA_TSADC ? ? ? (0xF3000000)
>
> ?/* ETC */
> -#define S5PC100_PA_SDRAM ? ? ? (0x20000000)
> +#define S5PC100_PA_SDRAM ? ? ? (0x30000000)
> ?#define S5PC1XX_PA_SDRAM ? ? ? S5PC100_PA_SDRAM
>
> ?/* compatibility defines. */
> diff --git a/arch/arm/mach-s5pc100/include/mach/memory.h b/arch/arm/mach-s5pc100/include/mach/memory.h
> index 4b60d18..21cc182 100644
> --- a/arch/arm/mach-s5pc100/include/mach/memory.h
> +++ b/arch/arm/mach-s5pc100/include/mach/memory.h
> @@ -13,6 +13,6 @@
> ?#ifndef __ASM_ARCH_MEMORY_H
> ?#define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET ? ? ? ? ? ?UL(0x20000000)
> +#define PHYS_OFFSET ? ? ? ? ? ?UL(0x30000000)
>
> ?#endif
> --
> 1.6.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>

[PATCH 09/19] drivers: serial: add support for Samsung S5PC110 SoC uart

[Russell King - ARM Linux]

On Thu, Nov 19, 2009 at 01:09:23PM +0100, Marek Szyprowski wrote:
> What if a device does not operate properly when clocked from one of the
> available clock sources (lets say machine specific problem)? There must
> be a way of setting which clock(s) should not be considered when calculating
> best choice for particular device.

Do you have a real life case where this is true?

[PATCH 01/20] ARM: S5PC100: use 0x30008000 as memory base

[Marek Szyprowski]

Hello,

On Friday, November 20, 2009 3:43 PM jassi brar wrote:

> On Fri, Nov 20, 2009 at 10:42 PM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
> > From: Kyungmin Park <kyungmin.park@samsung.com>
> >
> > We decided to use 0x3000'0000 as base memory address on S5PC1XX SoCs
> > (s5pc100 and s5pc110).
> you might as well want to explain the reason behind it, if any?

We decided to change the base memory address to 0x30000000 to be able to
support systems with 512MB in the second bank (DRAM1) without using HIMEM.
In first bank (DRAM0), which is integrated with SOC (POP) we would always
have no more than 256MB of memory. If we would leave the first bank at
0x2000'0000, we would lose 256MB of kernel virtual address space for
useless memory hole. With this patch (and proper u-boot) we can run kernel
on systems with max 256MB + 512MB of memory in 1GB kernel/3GB userspace
address space configuration.

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center