* [S3C-CLK] ARM: S3C64XX: Fix possible clock look in EPLL and MPLL clock chains
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
@ 2010-01-08 2:30 ` Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: SAMSUNG: Move <plat/clock.h> to plat-samsung Ben Dooks
` (13 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Ben Dooks @ 2010-01-08 2:30 UTC (permalink / raw)
To: linux-arm-kernel
There is a possibility of a loop happening in the PLL output clock
chain on the S3C64XX series. clk_mpll's parent was set to be
clk_mout_mpll, but this is fed from clk_fout_epll (which is also
clk_mpll).
clk_mpll is meant to be the output from the MPLL, and clk_mout_mpll
is a seperate clock derived from the mux of clk_mpll and clk_fin_mpll
and thus should be considered a seperate clock.
Anything using clk_mpll directly really should not be relying on this
being the clock that is eventually routed to a peripheral, so remove the
loop and ensure that the clocks accurately represent the clock chain
in the device.
The clk_mpll is not being used outside of the s3c6400-clock.c code, so
this change should not break anything else.
Do the same for the EPLL.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
arch/arm/plat-s3c64xx/s3c6400-clock.c | 10 +---------
1 files changed, 1 insertions(+), 9 deletions(-)
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 6ffa21e..ffd56de 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -46,6 +46,7 @@ static struct clk clk_ext_xtal_mux = {
#define clk_fin_epll clk_ext_xtal_mux
#define clk_fout_mpll clk_mpll
+#define clk_fout_epll clk_epll
struct clk_sources {
unsigned int nr_sources;
@@ -88,11 +89,6 @@ static struct clksrc_clk clk_mout_apll = {
.sources = &clk_src_apll,
};
-static struct clk clk_fout_epll = {
- .name = "fout_epll",
- .id = -1,
-};
-
static struct clk *clk_src_epll_list[] = {
[0] = &clk_fin_epll,
[1] = &clk_fout_epll,
@@ -715,7 +711,6 @@ static struct clk *clks[] __initdata = {
&clk_iis_cd1,
&clk_pcm_cd,
&clk_mout_epll.clk,
- &clk_fout_epll,
&clk_mout_mpll.clk,
&clk_dout_mpll,
&clk_mmc0.clk,
@@ -760,7 +755,4 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit)
clkp->name, ret);
}
}
-
- clk_mpll.parent = &clk_mout_mpll.clk;
- clk_epll.parent = &clk_mout_epll.clk;
}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [S3C-CLK] ARM: SAMSUNG: Move <plat/clock.h> to plat-samsung
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: S3C64XX: Fix possible clock look in EPLL and MPLL clock chains Ben Dooks
@ 2010-01-08 2:30 ` Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: S3C64XX: Cleanup common init code in s3c6400-clock.c Ben Dooks
` (12 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Ben Dooks @ 2010-01-08 2:30 UTC (permalink / raw)
To: linux-arm-kernel
Move the <plat/clock.h> header to plat-samsung where it can be used by all
the platforms, and readies it for the next round of clock updates where
the clock code will be amalgamated.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
.../include/plat/clock.h | 0
1 files changed, 0 insertions(+), 0 deletions(-)
rename arch/arm/{plat-s3c => plat-samsung}/include/plat/clock.h (100%)
diff --git a/arch/arm/plat-s3c/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
similarity index 100%
rename from arch/arm/plat-s3c/include/plat/clock.h
rename to arch/arm/plat-samsung/include/plat/clock.h
--
1.6.0.4
^ permalink raw reply [flat|nested] 20+ messages in thread* [S3C-CLK] ARM: S3C64XX: Cleanup common init code in s3c6400-clock.c
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: S3C64XX: Fix possible clock look in EPLL and MPLL clock chains Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: SAMSUNG: Move <plat/clock.h> to plat-samsung Ben Dooks
@ 2010-01-08 2:30 ` Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: S3C64XX: Compress s3c6400-clock.c code Ben Dooks
` (11 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Ben Dooks @ 2010-01-08 2:30 UTC (permalink / raw)
To: linux-arm-kernel
Remove the four fields from clksrc_clk.clk which are always the same
and init them when the clock is registered. This helps remove the amount
of repeated code.
This is a re-work of Harald Welte's clock changes for the latest kernel.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
arch/arm/plat-s3c64xx/s3c6400-clock.c | 49 +++-----------------------------
1 files changed, 5 insertions(+), 44 deletions(-)
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index ffd56de..aba08c7 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -360,10 +360,6 @@ static struct clksrc_clk clk_mmc0 = {
.id = 0,
.ctrlbit = S3C_CLKCON_SCLK_MMC0,
.enable = s3c64xx_sclk_ctrl,
- .set_parent = s3c64xx_setparent_clksrc,
- .get_rate = s3c64xx_getrate_clksrc,
- .set_rate = s3c64xx_setrate_clksrc,
- .round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_MMC0_SHIFT,
.mask = S3C6400_CLKSRC_MMC0_MASK,
@@ -378,10 +374,6 @@ static struct clksrc_clk clk_mmc1 = {
.id = 1,
.ctrlbit = S3C_CLKCON_SCLK_MMC1,
.enable = s3c64xx_sclk_ctrl,
- .get_rate = s3c64xx_getrate_clksrc,
- .set_rate = s3c64xx_setrate_clksrc,
- .set_parent = s3c64xx_setparent_clksrc,
- .round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_MMC1_SHIFT,
.mask = S3C6400_CLKSRC_MMC1_MASK,
@@ -396,10 +388,6 @@ static struct clksrc_clk clk_mmc2 = {
.id = 2,
.ctrlbit = S3C_CLKCON_SCLK_MMC2,
.enable = s3c64xx_sclk_ctrl,
- .get_rate = s3c64xx_getrate_clksrc,
- .set_rate = s3c64xx_setrate_clksrc,
- .set_parent = s3c64xx_setparent_clksrc,
- .round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_MMC2_SHIFT,
.mask = S3C6400_CLKSRC_MMC2_MASK,
@@ -414,10 +402,6 @@ static struct clksrc_clk clk_usbhost = {
.id = -1,
.ctrlbit = S3C_CLKCON_SCLK_UHOST,
.enable = s3c64xx_sclk_ctrl,
- .set_parent = s3c64xx_setparent_clksrc,
- .get_rate = s3c64xx_getrate_clksrc,
- .set_rate = s3c64xx_setrate_clksrc,
- .round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_UHOST_SHIFT,
.mask = S3C6400_CLKSRC_UHOST_MASK,
@@ -432,10 +416,6 @@ static struct clksrc_clk clk_uart_uclk1 = {
.id = -1,
.ctrlbit = S3C_CLKCON_SCLK_UART,
.enable = s3c64xx_sclk_ctrl,
- .set_parent = s3c64xx_setparent_clksrc,
- .get_rate = s3c64xx_getrate_clksrc,
- .set_rate = s3c64xx_setrate_clksrc,
- .round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_UART_SHIFT,
.mask = S3C6400_CLKSRC_UART_MASK,
@@ -452,10 +432,6 @@ static struct clksrc_clk clk_spi0 = {
.id = 0,
.ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl,
- .set_parent = s3c64xx_setparent_clksrc,
- .get_rate = s3c64xx_getrate_clksrc,
- .set_rate = s3c64xx_setrate_clksrc,
- .round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_SPI0_SHIFT,
.mask = S3C6400_CLKSRC_SPI0_MASK,
@@ -470,10 +446,6 @@ static struct clksrc_clk clk_spi1 = {
.id = 1,
.ctrlbit = S3C_CLKCON_SCLK_SPI1,
.enable = s3c64xx_sclk_ctrl,
- .set_parent = s3c64xx_setparent_clksrc,
- .get_rate = s3c64xx_getrate_clksrc,
- .set_rate = s3c64xx_setrate_clksrc,
- .round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_SPI1_SHIFT,
.mask = S3C6400_CLKSRC_SPI1_MASK,
@@ -516,10 +488,6 @@ static struct clksrc_clk clk_audio0 = {
.id = 0,
.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
.enable = s3c64xx_sclk_ctrl,
- .set_parent = s3c64xx_setparent_clksrc,
- .get_rate = s3c64xx_getrate_clksrc,
- .set_rate = s3c64xx_setrate_clksrc,
- .round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
.mask = S3C6400_CLKSRC_AUDIO0_MASK,
@@ -547,10 +515,6 @@ static struct clksrc_clk clk_audio1 = {
.id = 1,
.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
.enable = s3c64xx_sclk_ctrl,
- .set_parent = s3c64xx_setparent_clksrc,
- .get_rate = s3c64xx_getrate_clksrc,
- .set_rate = s3c64xx_setrate_clksrc,
- .round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
.mask = S3C6400_CLKSRC_AUDIO1_MASK,
@@ -565,10 +529,6 @@ static struct clksrc_clk clk_irda = {
.id = 0,
.ctrlbit = S3C_CLKCON_SCLK_IRDA,
.enable = s3c64xx_sclk_ctrl,
- .set_parent = s3c64xx_setparent_clksrc,
- .get_rate = s3c64xx_getrate_clksrc,
- .set_rate = s3c64xx_setrate_clksrc,
- .round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_IRDA_SHIFT,
.mask = S3C6400_CLKSRC_IRDA_MASK,
@@ -592,10 +552,6 @@ static struct clksrc_clk clk_camif = {
.id = -1,
.ctrlbit = S3C_CLKCON_SCLK_CAM,
.enable = s3c64xx_sclk_ctrl,
- .set_parent = s3c64xx_setparent_clksrc,
- .get_rate = s3c64xx_getrate_clksrc,
- .set_rate = s3c64xx_setrate_clksrc,
- .round_rate = s3c64xx_roundrate_clksrc,
},
.shift = 0,
.mask = 0,
@@ -637,6 +593,11 @@ static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
return;
}
+ clk->clk.get_rate = s3c64xx_getrate_clksrc;
+ clk->clk.set_rate = s3c64xx_setrate_clksrc;
+ clk->clk.set_parent = s3c64xx_setparent_clksrc;
+ clk->clk.round_rate = s3c64xx_roundrate_clksrc;
+
clk->clk.parent = srcs->sources[clksrc];
printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
--
1.6.0.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [S3C-CLK] ARM: S3C64XX: Compress s3c6400-clock.c code
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
` (2 preceding siblings ...)
2010-01-08 2:30 ` [S3C-CLK] ARM: S3C64XX: Cleanup common init code in s3c6400-clock.c Ben Dooks
@ 2010-01-08 2:30 ` Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: SAMSUNG: Add core clock implementation for clksrc based clocks Ben Dooks
` (10 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Ben Dooks @ 2010-01-08 2:30 UTC (permalink / raw)
To: linux-arm-kernel
The individually named clocks are all static to the code
and thus can be compressed into a single array and then
the array can be referenced. This removes the need for
a seperate array of pointers to clocks.
Fix a minor problem of re-initialising the pointers in
s3c6400_set_clksrc() as this is also called by the cpufreq
code. Move these initialisations to the code that does the
registration.
Based on Harald Welte's original clock changes patch.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
arch/arm/plat-s3c64xx/s3c6400-clock.c | 334 +++++++++++++++------------------
1 files changed, 154 insertions(+), 180 deletions(-)
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index aba08c7..6fde910 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -255,7 +255,6 @@ static struct clk_sources clkset_uhost = {
.nr_sources = ARRAY_SIZE(clkset_uhost_list),
};
-
/* The peripheral clocks are all controlled via clocksource followed
* by an optional divider and gate stage. We currently roll this into
* one clock which hides the intermediate clock from the mux.
@@ -354,105 +353,7 @@ static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
return rate;
}
-static struct clksrc_clk clk_mmc0 = {
- .clk = {
- .name = "mmc_bus",
- .id = 0,
- .ctrlbit = S3C_CLKCON_SCLK_MMC0,
- .enable = s3c64xx_sclk_ctrl,
- },
- .shift = S3C6400_CLKSRC_MMC0_SHIFT,
- .mask = S3C6400_CLKSRC_MMC0_MASK,
- .sources = &clkset_spi_mmc,
- .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT,
- .reg_divider = S3C_CLK_DIV1,
-};
-
-static struct clksrc_clk clk_mmc1 = {
- .clk = {
- .name = "mmc_bus",
- .id = 1,
- .ctrlbit = S3C_CLKCON_SCLK_MMC1,
- .enable = s3c64xx_sclk_ctrl,
- },
- .shift = S3C6400_CLKSRC_MMC1_SHIFT,
- .mask = S3C6400_CLKSRC_MMC1_MASK,
- .sources = &clkset_spi_mmc,
- .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT,
- .reg_divider = S3C_CLK_DIV1,
-};
-
-static struct clksrc_clk clk_mmc2 = {
- .clk = {
- .name = "mmc_bus",
- .id = 2,
- .ctrlbit = S3C_CLKCON_SCLK_MMC2,
- .enable = s3c64xx_sclk_ctrl,
- },
- .shift = S3C6400_CLKSRC_MMC2_SHIFT,
- .mask = S3C6400_CLKSRC_MMC2_MASK,
- .sources = &clkset_spi_mmc,
- .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT,
- .reg_divider = S3C_CLK_DIV1,
-};
-
-static struct clksrc_clk clk_usbhost = {
- .clk = {
- .name = "usb-bus-host",
- .id = -1,
- .ctrlbit = S3C_CLKCON_SCLK_UHOST,
- .enable = s3c64xx_sclk_ctrl,
- },
- .shift = S3C6400_CLKSRC_UHOST_SHIFT,
- .mask = S3C6400_CLKSRC_UHOST_MASK,
- .sources = &clkset_uhost,
- .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT,
- .reg_divider = S3C_CLK_DIV1,
-};
-
-static struct clksrc_clk clk_uart_uclk1 = {
- .clk = {
- .name = "uclk1",
- .id = -1,
- .ctrlbit = S3C_CLKCON_SCLK_UART,
- .enable = s3c64xx_sclk_ctrl,
- },
- .shift = S3C6400_CLKSRC_UART_SHIFT,
- .mask = S3C6400_CLKSRC_UART_MASK,
- .sources = &clkset_uart,
- .divider_shift = S3C6400_CLKDIV2_UART_SHIFT,
- .reg_divider = S3C_CLK_DIV2,
-};
-
-/* Where does UCLK0 come from? */
-
-static struct clksrc_clk clk_spi0 = {
- .clk = {
- .name = "spi-bus",
- .id = 0,
- .ctrlbit = S3C_CLKCON_SCLK_SPI0,
- .enable = s3c64xx_sclk_ctrl,
- },
- .shift = S3C6400_CLKSRC_SPI0_SHIFT,
- .mask = S3C6400_CLKSRC_SPI0_MASK,
- .sources = &clkset_spi_mmc,
- .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT,
- .reg_divider = S3C_CLK_DIV2,
-};
-
-static struct clksrc_clk clk_spi1 = {
- .clk = {
- .name = "spi-bus",
- .id = 1,
- .ctrlbit = S3C_CLKCON_SCLK_SPI1,
- .enable = s3c64xx_sclk_ctrl,
- },
- .shift = S3C6400_CLKSRC_SPI1_SHIFT,
- .mask = S3C6400_CLKSRC_SPI1_MASK,
- .sources = &clkset_spi_mmc,
- .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT,
- .reg_divider = S3C_CLK_DIV2,
-};
+/* clocks that feed other parts of the clock source tree */
static struct clk clk_iis_cd0 = {
.name = "iis_cdclk0",
@@ -482,20 +383,6 @@ static struct clk_sources clkset_audio0 = {
.nr_sources = ARRAY_SIZE(clkset_audio0_list),
};
-static struct clksrc_clk clk_audio0 = {
- .clk = {
- .name = "audio-bus",
- .id = 0,
- .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
- .enable = s3c64xx_sclk_ctrl,
- },
- .shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
- .mask = S3C6400_CLKSRC_AUDIO0_MASK,
- .sources = &clkset_audio0,
- .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT,
- .reg_divider = S3C_CLK_DIV2,
-};
-
static struct clk *clkset_audio1_list[] = {
[0] = &clk_mout_epll.clk,
[1] = &clk_dout_mpll,
@@ -509,34 +396,6 @@ static struct clk_sources clkset_audio1 = {
.nr_sources = ARRAY_SIZE(clkset_audio1_list),
};
-static struct clksrc_clk clk_audio1 = {
- .clk = {
- .name = "audio-bus",
- .id = 1,
- .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
- .enable = s3c64xx_sclk_ctrl,
- },
- .shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
- .mask = S3C6400_CLKSRC_AUDIO1_MASK,
- .sources = &clkset_audio1,
- .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT,
- .reg_divider = S3C_CLK_DIV2,
-};
-
-static struct clksrc_clk clk_irda = {
- .clk = {
- .name = "irda-bus",
- .id = 0,
- .ctrlbit = S3C_CLKCON_SCLK_IRDA,
- .enable = s3c64xx_sclk_ctrl,
- },
- .shift = S3C6400_CLKSRC_IRDA_SHIFT,
- .mask = S3C6400_CLKSRC_IRDA_MASK,
- .sources = &clkset_irda,
- .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT,
- .reg_divider = S3C_CLK_DIV2,
-};
-
static struct clk *clkset_camif_list[] = {
&clk_h2,
};
@@ -546,18 +405,141 @@ static struct clk_sources clkset_camif = {
.nr_sources = ARRAY_SIZE(clkset_camif_list),
};
-static struct clksrc_clk clk_camif = {
- .clk = {
- .name = "camera",
- .id = -1,
- .ctrlbit = S3C_CLKCON_SCLK_CAM,
- .enable = s3c64xx_sclk_ctrl,
+static struct clksrc_clk clksrcs[] = {
+ {
+ .clk = {
+ .name = "mmc_bus",
+ .id = 0,
+ .ctrlbit = S3C_CLKCON_SCLK_MMC0,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .shift = S3C6400_CLKSRC_MMC0_SHIFT,
+ .mask = S3C6400_CLKSRC_MMC0_MASK,
+ .sources = &clkset_spi_mmc,
+ .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT,
+ .reg_divider = S3C_CLK_DIV1,
+ }, {
+ .clk = {
+ .name = "mmc_bus",
+ .id = 1,
+ .ctrlbit = S3C_CLKCON_SCLK_MMC1,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .shift = S3C6400_CLKSRC_MMC1_SHIFT,
+ .mask = S3C6400_CLKSRC_MMC1_MASK,
+ .sources = &clkset_spi_mmc,
+ .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT,
+ .reg_divider = S3C_CLK_DIV1,
+ }, {
+ .clk = {
+ .name = "mmc_bus",
+ .id = 2,
+ .ctrlbit = S3C_CLKCON_SCLK_MMC2,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .shift = S3C6400_CLKSRC_MMC2_SHIFT,
+ .mask = S3C6400_CLKSRC_MMC2_MASK,
+ .sources = &clkset_spi_mmc,
+ .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT,
+ .reg_divider = S3C_CLK_DIV1,
+ }, {
+ .clk = {
+ .name = "usb-bus-host",
+ .id = -1,
+ .ctrlbit = S3C_CLKCON_SCLK_UHOST,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .shift = S3C6400_CLKSRC_UHOST_SHIFT,
+ .mask = S3C6400_CLKSRC_UHOST_MASK,
+ .sources = &clkset_uhost,
+ .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT,
+ .reg_divider = S3C_CLK_DIV1,
+ }, {
+ .clk = {
+ .name = "uclk1",
+ .id = -1,
+ .ctrlbit = S3C_CLKCON_SCLK_UART,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .shift = S3C6400_CLKSRC_UART_SHIFT,
+ .mask = S3C6400_CLKSRC_UART_MASK,
+ .sources = &clkset_uart,
+ .divider_shift = S3C6400_CLKDIV2_UART_SHIFT,
+ .reg_divider = S3C_CLK_DIV2,
+ }, {
+/* Where does UCLK0 come from? */
+ .clk = {
+ .name = "spi-bus",
+ .id = 0,
+ .ctrlbit = S3C_CLKCON_SCLK_SPI0,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .shift = S3C6400_CLKSRC_SPI0_SHIFT,
+ .mask = S3C6400_CLKSRC_SPI0_MASK,
+ .sources = &clkset_spi_mmc,
+ .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT,
+ .reg_divider = S3C_CLK_DIV2,
+ }, {
+ .clk = {
+ .name = "spi-bus",
+ .id = 1,
+ .ctrlbit = S3C_CLKCON_SCLK_SPI1,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .shift = S3C6400_CLKSRC_SPI1_SHIFT,
+ .mask = S3C6400_CLKSRC_SPI1_MASK,
+ .sources = &clkset_spi_mmc,
+ .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT,
+ .reg_divider = S3C_CLK_DIV2,
+ }, {
+ .clk = {
+ .name = "audio-bus",
+ .id = 0,
+ .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
+ .mask = S3C6400_CLKSRC_AUDIO0_MASK,
+ .sources = &clkset_audio0,
+ .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT,
+ .reg_divider = S3C_CLK_DIV2,
+ }, {
+ .clk = {
+ .name = "audio-bus",
+ .id = 1,
+ .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
+ .mask = S3C6400_CLKSRC_AUDIO1_MASK,
+ .sources = &clkset_audio1,
+ .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT,
+ .reg_divider = S3C_CLK_DIV2,
+ }, {
+ .clk = {
+ .name = "irda-bus",
+ .id = 0,
+ .ctrlbit = S3C_CLKCON_SCLK_IRDA,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .shift = S3C6400_CLKSRC_IRDA_SHIFT,
+ .mask = S3C6400_CLKSRC_IRDA_MASK,
+ .sources = &clkset_irda,
+ .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT,
+ .reg_divider = S3C_CLK_DIV2,
+ }, {
+ .clk = {
+ .name = "camera",
+ .id = -1,
+ .ctrlbit = S3C_CLKCON_SCLK_CAM,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .shift = 0,
+ .mask = 0,
+ .sources = &clkset_camif,
+ .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT,
+ .reg_divider = S3C_CLK_DIV0,
},
- .shift = 0,
- .mask = 0,
- .sources = &clkset_camif,
- .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT,
- .reg_divider = S3C_CLK_DIV0,
};
/* Clock initialisation code */
@@ -566,17 +548,6 @@ static struct clksrc_clk *init_parents[] = {
&clk_mout_apll,
&clk_mout_epll,
&clk_mout_mpll,
- &clk_mmc0,
- &clk_mmc1,
- &clk_mmc2,
- &clk_usbhost,
- &clk_uart_uclk1,
- &clk_spi0,
- &clk_spi1,
- &clk_audio0,
- &clk_audio1,
- &clk_irda,
- &clk_camif,
};
static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
@@ -593,11 +564,6 @@ static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
return;
}
- clk->clk.get_rate = s3c64xx_getrate_clksrc;
- clk->clk.set_rate = s3c64xx_setrate_clksrc;
- clk->clk.set_parent = s3c64xx_setparent_clksrc;
- clk->clk.round_rate = s3c64xx_roundrate_clksrc;
-
clk->clk.parent = srcs->sources[clksrc];
printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
@@ -664,6 +630,9 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
s3c6400_set_clksrc(init_parents[ptr]);
+
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+ s3c6400_set_clksrc(&clksrcs[ptr]);
}
static struct clk *clks[] __initdata = {
@@ -674,17 +643,6 @@ static struct clk *clks[] __initdata = {
&clk_mout_epll.clk,
&clk_mout_mpll.clk,
&clk_dout_mpll,
- &clk_mmc0.clk,
- &clk_mmc1.clk,
- &clk_mmc2.clk,
- &clk_usbhost.clk,
- &clk_uart_uclk1.clk,
- &clk_spi0.clk,
- &clk_spi1.clk,
- &clk_audio0.clk,
- &clk_audio1.clk,
- &clk_irda.clk,
- &clk_camif.clk,
&clk_arm,
};
@@ -716,4 +674,20 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit)
clkp->name, ret);
}
}
+
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) {
+ clkp = &clksrcs[ptr].clk;
+
+ /* all clksrc clocks have these */
+ clkp->get_rate = s3c64xx_getrate_clksrc;
+ clkp->set_rate = s3c64xx_setrate_clksrc;
+ clkp->set_parent = s3c64xx_setparent_clksrc;
+ clkp->round_rate = s3c64xx_roundrate_clksrc;
+
+ ret = s3c24xx_register_clock(clkp);
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to register clock %s (%d)\n",
+ clkp->name, ret);
+ }
+ }
}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [S3C-CLK] ARM: SAMSUNG: Add core clock implementation for clksrc based clocks
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
` (3 preceding siblings ...)
2010-01-08 2:30 ` [S3C-CLK] ARM: S3C64XX: Compress s3c6400-clock.c code Ben Dooks
@ 2010-01-08 2:30 ` Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: S3C64XX: Use new clock-clksrc.c code for clocks Ben Dooks
` (9 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Ben Dooks @ 2010-01-08 2:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Harald Welte <laforge@gnumonks.org>
Add a core for the clksrc clock implementation, which is found in many of
the newer Samsung SoCs into plat-samsung.
Signed-off-by: Harald Welte <laforge@gnumonks.org>
[ben-linux at fluff.org: split from original patch to make change smaller]
[ben-linux at fluff.org: split clk and clksrc changes]
[ben-linux at fluff.org: moved to plat-samsung from plat-s3c]
[ben-linux at fluff.org: re-wrote headers after splits]
[ben-linux at fluff.org: added better documentation to headers]
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
arch/arm/plat-samsung/Kconfig | 5 +
arch/arm/plat-samsung/Makefile | 1 +
arch/arm/plat-samsung/clock-clksrc.c | 177 +++++++++++++++++++++
arch/arm/plat-samsung/include/plat/clock-clksrc.h | 75 +++++++++
4 files changed, 258 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/plat-samsung/clock-clksrc.c
create mode 100644 arch/arm/plat-samsung/include/plat/clock-clksrc.h
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 486a0d6..e3ae684 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -13,5 +13,10 @@ config PLAT_SAMSUNG
if PLAT_SAMSUNG
+config SAMSUNG_CLKSRC
+ bool
+ help
+ Select the clock code for the clksrc implementation
+ used by newer systems such as the S3C64XX.
endif
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 4478b9f..ce736ce 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -9,3 +9,4 @@ obj-m :=
obj-n := dummy.o
obj- :=
+obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c
new file mode 100644
index 0000000..5872f0b
--- /dev/null
+++ b/arch/arm/plat-samsung/clock-clksrc.c
@@ -0,0 +1,177 @@
+/* linux/arch/arm/plat-samsung/clock-clksrc.c
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/cpu-freq.h>
+
+static inline struct clksrc_clk *to_clksrc(struct clk *clk)
+{
+ return container_of(clk, struct clksrc_clk, clk);
+}
+
+static inline u32 bit_mask(u32 shift, u32 nr_bits)
+{
+ u32 mask = 0xffffffff >> (32 - nr_bits);
+
+ return mask << shift;
+}
+
+static unsigned long s3c_getrate_clksrc(struct clk *clk)
+{
+ struct clksrc_clk *sclk = to_clksrc(clk);
+ unsigned long rate = clk_get_rate(clk->parent);
+ u32 clkdiv = __raw_readl(sclk->reg_div.reg);
+ u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
+
+ clkdiv &= mask;
+ clkdiv >>= sclk->reg_div.shift;
+ clkdiv++;
+
+ rate /= clkdiv;
+ return rate;
+}
+
+static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate)
+{
+ struct clksrc_clk *sclk = to_clksrc(clk);
+ void __iomem *reg = sclk->reg_div.reg;
+ unsigned int div;
+ u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
+ u32 val;
+
+ rate = clk_round_rate(clk, rate);
+ div = clk_get_rate(clk->parent) / rate;
+ if (div > 16)
+ return -EINVAL;
+
+ val = __raw_readl(reg);
+ val &= ~mask;
+ val |= (div - 1) << sclk->reg_div.shift;
+ __raw_writel(val, reg);
+
+ return 0;
+}
+
+static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent)
+{
+ struct clksrc_clk *sclk = to_clksrc(clk);
+ struct clksrc_sources *srcs = sclk->sources;
+ u32 clksrc = __raw_readl(sclk->reg_src.reg);
+ u32 mask = bit_mask(sclk->reg_src.shift, sclk->reg_src.size);
+ int src_nr = -1;
+ int ptr;
+
+ for (ptr = 0; ptr < srcs->nr_sources; ptr++)
+ if (srcs->sources[ptr] == parent) {
+ src_nr = ptr;
+ break;
+ }
+
+ if (src_nr >= 0 && sclk->reg_src.reg) {
+ clk->parent = parent;
+
+ clksrc &= ~mask;
+ clksrc |= src_nr << sclk->reg_src.shift;
+
+ __raw_writel(clksrc, sclk->reg_src.reg);
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static unsigned long s3c_roundrate_clksrc(struct clk *clk,
+ unsigned long rate)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ int div;
+
+ if (rate >= parent_rate)
+ rate = parent_rate;
+ else {
+ div = parent_rate / rate;
+ if (parent_rate % rate)
+ div++;
+
+ if (div == 0)
+ div = 1;
+ if (div > 16)
+ div = 16;
+
+ rate = parent_rate / div;
+ }
+
+ return rate;
+}
+
+/* Clock initialisation code */
+
+void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk)
+{
+ struct clksrc_sources *srcs = clk->sources;
+ u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size);
+ u32 clksrc = 0;
+
+ if (clk->reg_src.reg)
+ clksrc = __raw_readl(clk->reg_src.reg);
+
+ clksrc &= mask;
+ clksrc >>= clk->reg_src.shift;
+
+ if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
+ printk(KERN_ERR "%s: bad source %d\n",
+ clk->clk.name, clksrc);
+ return;
+ }
+
+ clk->clk.parent = srcs->sources[clksrc];
+
+ printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
+ clk->clk.name, clk->clk.parent->name, clksrc,
+ clk_get_rate(&clk->clk));
+}
+
+void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
+{
+ int ret;
+
+ for (; size > 0; size--, clksrc++) {
+ /* fill in the default functions */
+ if (!clksrc->clk.set_parent)
+ clksrc->clk.set_parent = s3c_setparent_clksrc;
+ if (!clksrc->clk.get_rate)
+ clksrc->clk.get_rate = s3c_getrate_clksrc;
+ if (!clksrc->clk.set_rate)
+ clksrc->clk.set_rate = s3c_setrate_clksrc;
+ if (!clksrc->clk.round_rate)
+ clksrc->clk.round_rate = s3c_roundrate_clksrc;
+
+ s3c_set_clksrc(clksrc);
+
+ ret = s3c24xx_register_clock(&clksrc->clk);
+
+ if (ret < 0) {
+ printk(KERN_ERR "%s: failed to register %s (%d)\n",
+ __func__, clksrc->clk.name, ret);
+ }
+ }
+}
diff --git a/arch/arm/plat-samsung/include/plat/clock-clksrc.h b/arch/arm/plat-samsung/include/plat/clock-clksrc.h
new file mode 100644
index 0000000..283dfa0
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/clock-clksrc.h
@@ -0,0 +1,75 @@
+/* linux/arch/arm/plat-samsung/include/plat/clock-clksrc.h
+ *
+ * Parts taken from arch/arm/plat-s3c64xx/clock.c
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * Copyright 2009 Ben Dooks <ben-linux@fluff.org>
+ * Copyright 2009 Harald Welte
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/**
+ * struct clksrc_sources - list of sources for a given clock
+ * @sources: array of pointers to clocks
+ * @nr_sources: The size of @sources
+ */
+struct clksrc_sources {
+ unsigned int nr_sources;
+ struct clk **sources;
+};
+
+/**
+ * struct clksrc_reg - register definition for clock control bits
+ * @reg: pointer to the register in virtual memory.
+ * @shift: the shift in bits to where the bitfield is.
+ * @size: the size in bits of the bitfield.
+ *
+ * This specifies the size and position of the bits we are interested
+ * in within the register specified by @reg.
+ */
+struct clksrc_reg {
+ void __iomem *reg;
+ unsigned short shift;
+ unsigned short size;
+};
+
+/**
+ * struct clksrc_clk - class of clock for newer style samsung devices.
+ * @clk: the standard clock representation
+ * @sources: the sources for this clock
+ * @reg_src: the register definition for selecting the clock's source
+ * @reg_div: the register definition for the clock's output divisor
+ *
+ * This clock implements the features required by the newer SoCs where
+ * the standard clock block provides an input mux and a post-mux divisor
+ * to provide the periperhal's clock.
+ *
+ * The array of @sources provides the mapping of mux position to the
+ * clock, and @reg_src shows the code where to modify to change the mux
+ * position. The @reg_div defines how to change the divider settings on
+ * the output.
+ */
+struct clksrc_clk {
+ struct clk clk;
+ struct clksrc_sources *sources;
+
+ struct clksrc_reg reg_src;
+ struct clksrc_reg reg_div;
+};
+
+extern void s3c_set_clksrc(struct clksrc_clk *clk);
+
+/**
+ * s3c_register_clksrc() register clocks from an array of clksrc clocks
+ * @srcs: The array of clocks to register
+ * @size: The size of the @srcs array.
+ *
+ * Initialise and register the array of clocks described by @srcs.
+ */
+extern void s3c_register_clksrc(struct clksrc_clk *srcs, int size);
--
1.6.0.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [S3C-CLK] ARM: S3C64XX: Use new clock-clksrc.c code for clocks.
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
` (4 preceding siblings ...)
2010-01-08 2:30 ` [S3C-CLK] ARM: SAMSUNG: Add core clock implementation for clksrc based clocks Ben Dooks
@ 2010-01-08 2:30 ` Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: S3C64XX: Remove unused clock definitions from clock header Ben Dooks
` (8 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Ben Dooks @ 2010-01-08 2:30 UTC (permalink / raw)
To: linux-arm-kernel
Move the s3c6400-clock.c implementation over to use the new common
plat-samsung based clock-clksrc.c.
Note, this does not delete the clocks definitions that are now unused
in the regs-clock.h to reduce the quantity of change in this commit.
Based on original patches by Harald Welte.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
arch/arm/plat-s3c64xx/Kconfig | 1 +
arch/arm/plat-s3c64xx/s3c6400-clock.c | 241 ++++++---------------------------
2 files changed, 40 insertions(+), 202 deletions(-)
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig
index e6da87a..bec1224 100644
--- a/arch/arm/plat-s3c64xx/Kconfig
+++ b/arch/arm/plat-s3c64xx/Kconfig
@@ -13,6 +13,7 @@ config PLAT_S3C64XX
select ARM_VIC
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
+ select SAMSUNG_CLKSRC
select S3C_GPIO_TRACK
select S3C_GPIO_PULL_UPDOWN
select S3C_GPIO_CFG_S3C24XX
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 6fde910..20af0c2 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -29,6 +29,7 @@
#include <plat/regs-clock.h>
#include <plat/clock.h>
+#include <plat/clock-clksrc.h>
#include <plat/cpu.h>
#include <plat/pll.h>
@@ -48,22 +49,6 @@ static struct clk clk_ext_xtal_mux = {
#define clk_fout_mpll clk_mpll
#define clk_fout_epll clk_epll
-struct clk_sources {
- unsigned int nr_sources;
- struct clk **sources;
-};
-
-struct clksrc_clk {
- struct clk clk;
- unsigned int mask;
- unsigned int shift;
-
- struct clk_sources *sources;
-
- unsigned int divider_shift;
- void __iomem *reg_divider;
-};
-
static struct clk clk_fout_apll = {
.name = "fout_apll",
.id = -1,
@@ -74,7 +59,7 @@ static struct clk *clk_src_apll_list[] = {
[1] = &clk_fout_apll,
};
-static struct clk_sources clk_src_apll = {
+static struct clksrc_sources clk_src_apll = {
.sources = clk_src_apll_list,
.nr_sources = ARRAY_SIZE(clk_src_apll_list),
};
@@ -84,8 +69,7 @@ static struct clksrc_clk clk_mout_apll = {
.name = "mout_apll",
.id = -1,
},
- .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT,
- .mask = S3C6400_CLKSRC_APLL_MOUT,
+ .reg_src = { S3C_CLK_SRC, 0, 1 },
.sources = &clk_src_apll,
};
@@ -94,7 +78,7 @@ static struct clk *clk_src_epll_list[] = {
[1] = &clk_fout_epll,
};
-static struct clk_sources clk_src_epll = {
+static struct clksrc_sources clk_src_epll = {
.sources = clk_src_epll_list,
.nr_sources = ARRAY_SIZE(clk_src_epll_list),
};
@@ -104,8 +88,7 @@ static struct clksrc_clk clk_mout_epll = {
.name = "mout_epll",
.id = -1,
},
- .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT,
- .mask = S3C6400_CLKSRC_EPLL_MOUT,
+ .reg_src = { S3C_CLK_SRC, 2, 1 },
.sources = &clk_src_epll,
};
@@ -114,7 +97,7 @@ static struct clk *clk_src_mpll_list[] = {
[1] = &clk_fout_mpll,
};
-static struct clk_sources clk_src_mpll = {
+static struct clksrc_sources clk_src_mpll = {
.sources = clk_src_mpll_list,
.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
};
@@ -124,8 +107,7 @@ static struct clksrc_clk clk_mout_mpll = {
.name = "mout_mpll",
.id = -1,
},
- .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT,
- .mask = S3C6400_CLKSRC_MPLL_MOUT,
+ .reg_src = { S3C_CLK_SRC, 1, 1 },
.sources = &clk_src_mpll,
};
@@ -214,7 +196,7 @@ static struct clk *clkset_spi_mmc_list[] = {
&clk_27m,
};
-static struct clk_sources clkset_spi_mmc = {
+static struct clksrc_sources clkset_spi_mmc = {
.sources = clkset_spi_mmc_list,
.nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
};
@@ -226,7 +208,7 @@ static struct clk *clkset_irda_list[] = {
&clk_27m,
};
-static struct clk_sources clkset_irda = {
+static struct clksrc_sources clkset_irda = {
.sources = clkset_irda_list,
.nr_sources = ARRAY_SIZE(clkset_irda_list),
};
@@ -238,7 +220,7 @@ static struct clk *clkset_uart_list[] = {
NULL
};
-static struct clk_sources clkset_uart = {
+static struct clksrc_sources clkset_uart = {
.sources = clkset_uart_list,
.nr_sources = ARRAY_SIZE(clkset_uart_list),
};
@@ -250,7 +232,7 @@ static struct clk *clkset_uhost_list[] = {
&clk_fin_epll,
};
-static struct clk_sources clkset_uhost = {
+static struct clksrc_sources clkset_uhost = {
.sources = clkset_uhost_list,
.nr_sources = ARRAY_SIZE(clkset_uhost_list),
};
@@ -265,94 +247,6 @@ static struct clk_sources clkset_uhost = {
* have a common parent divisor so are not included here.
*/
-static inline struct clksrc_clk *to_clksrc(struct clk *clk)
-{
- return container_of(clk, struct clksrc_clk, clk);
-}
-
-static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)
-{
- struct clksrc_clk *sclk = to_clksrc(clk);
- unsigned long rate = clk_get_rate(clk->parent);
- u32 clkdiv = __raw_readl(sclk->reg_divider);
-
- clkdiv >>= sclk->divider_shift;
- clkdiv &= 0xf;
- clkdiv++;
-
- rate /= clkdiv;
- return rate;
-}
-
-static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
-{
- struct clksrc_clk *sclk = to_clksrc(clk);
- void __iomem *reg = sclk->reg_divider;
- unsigned int div;
- u32 val;
-
- rate = clk_round_rate(clk, rate);
- div = clk_get_rate(clk->parent) / rate;
- if (div > 16)
- return -EINVAL;
-
- val = __raw_readl(reg);
- val &= ~(0xf << sclk->divider_shift);
- val |= (div - 1) << sclk->divider_shift;
- __raw_writel(val, reg);
-
- return 0;
-}
-
-static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)
-{
- struct clksrc_clk *sclk = to_clksrc(clk);
- struct clk_sources *srcs = sclk->sources;
- u32 clksrc = __raw_readl(S3C_CLK_SRC);
- int src_nr = -1;
- int ptr;
-
- for (ptr = 0; ptr < srcs->nr_sources; ptr++)
- if (srcs->sources[ptr] == parent) {
- src_nr = ptr;
- break;
- }
-
- if (src_nr >= 0) {
- clksrc &= ~sclk->mask;
- clksrc |= src_nr << sclk->shift;
-
- __raw_writel(clksrc, S3C_CLK_SRC);
-
- clk->parent = parent;
- return 0;
- }
-
- return -EINVAL;
-}
-
-static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
- unsigned long rate)
-{
- unsigned long parent_rate = clk_get_rate(clk->parent);
- int div;
-
- if (rate > parent_rate)
- rate = parent_rate;
- else {
- div = parent_rate / rate;
-
- if (div == 0)
- div = 1;
- if (div > 16)
- div = 16;
-
- rate = parent_rate / div;
- }
-
- return rate;
-}
-
/* clocks that feed other parts of the clock source tree */
static struct clk clk_iis_cd0 = {
@@ -378,7 +272,7 @@ static struct clk *clkset_audio0_list[] = {
[4] = &clk_pcm_cd,
};
-static struct clk_sources clkset_audio0 = {
+static struct clksrc_sources clkset_audio0 = {
.sources = clkset_audio0_list,
.nr_sources = ARRAY_SIZE(clkset_audio0_list),
};
@@ -391,7 +285,7 @@ static struct clk *clkset_audio1_list[] = {
[4] = &clk_pcm_cd,
};
-static struct clk_sources clkset_audio1 = {
+static struct clksrc_sources clkset_audio1 = {
.sources = clkset_audio1_list,
.nr_sources = ARRAY_SIZE(clkset_audio1_list),
};
@@ -400,7 +294,7 @@ static struct clk *clkset_camif_list[] = {
&clk_h2,
};
-static struct clk_sources clkset_camif = {
+static struct clksrc_sources clkset_camif = {
.sources = clkset_camif_list,
.nr_sources = ARRAY_SIZE(clkset_camif_list),
};
@@ -413,11 +307,9 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_MMC0,
.enable = s3c64xx_sclk_ctrl,
},
- .shift = S3C6400_CLKSRC_MMC0_SHIFT,
- .mask = S3C6400_CLKSRC_MMC0_MASK,
+ .reg_src = { S3C_CLK_SRC, 18, 2 },
+ .reg_div = { S3C_CLK_DIV1, 0, 4 },
.sources = &clkset_spi_mmc,
- .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT,
- .reg_divider = S3C_CLK_DIV1,
}, {
.clk = {
.name = "mmc_bus",
@@ -425,11 +317,9 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_MMC1,
.enable = s3c64xx_sclk_ctrl,
},
- .shift = S3C6400_CLKSRC_MMC1_SHIFT,
- .mask = S3C6400_CLKSRC_MMC1_MASK,
+ .reg_src = { S3C_CLK_SRC, 20, 2 },
+ .reg_div = { S3C_CLK_DIV1, 4, 4 },
.sources = &clkset_spi_mmc,
- .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT,
- .reg_divider = S3C_CLK_DIV1,
}, {
.clk = {
.name = "mmc_bus",
@@ -437,11 +327,9 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_MMC2,
.enable = s3c64xx_sclk_ctrl,
},
- .shift = S3C6400_CLKSRC_MMC2_SHIFT,
- .mask = S3C6400_CLKSRC_MMC2_MASK,
+ .reg_src = { S3C_CLK_SRC, 22, 2 },
+ .reg_div = { S3C_CLK_DIV1, 8, 4 },
.sources = &clkset_spi_mmc,
- .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT,
- .reg_divider = S3C_CLK_DIV1,
}, {
.clk = {
.name = "usb-bus-host",
@@ -449,11 +337,9 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_UHOST,
.enable = s3c64xx_sclk_ctrl,
},
- .shift = S3C6400_CLKSRC_UHOST_SHIFT,
- .mask = S3C6400_CLKSRC_UHOST_MASK,
+ .reg_src = { S3C_CLK_SRC, 5, 2 },
+ .reg_div = { S3C_CLK_DIV1, 20, 4 },
.sources = &clkset_uhost,
- .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT,
- .reg_divider = S3C_CLK_DIV1,
}, {
.clk = {
.name = "uclk1",
@@ -461,11 +347,9 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_UART,
.enable = s3c64xx_sclk_ctrl,
},
- .shift = S3C6400_CLKSRC_UART_SHIFT,
- .mask = S3C6400_CLKSRC_UART_MASK,
+ .reg_src = { S3C_CLK_SRC, 13, 1 },
+ .reg_div = { S3C_CLK_DIV2, 16, 4 },
.sources = &clkset_uart,
- .divider_shift = S3C6400_CLKDIV2_UART_SHIFT,
- .reg_divider = S3C_CLK_DIV2,
}, {
/* Where does UCLK0 come from? */
.clk = {
@@ -474,11 +358,9 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl,
},
- .shift = S3C6400_CLKSRC_SPI0_SHIFT,
- .mask = S3C6400_CLKSRC_SPI0_MASK,
+ .reg_src = { S3C_CLK_SRC, 14, 2 },
+ .reg_div = { S3C_CLK_DIV2, 0, 4 },
.sources = &clkset_spi_mmc,
- .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT,
- .reg_divider = S3C_CLK_DIV2,
}, {
.clk = {
.name = "spi-bus",
@@ -486,11 +368,9 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_SPI1,
.enable = s3c64xx_sclk_ctrl,
},
- .shift = S3C6400_CLKSRC_SPI1_SHIFT,
- .mask = S3C6400_CLKSRC_SPI1_MASK,
+ .reg_src = { S3C_CLK_SRC, 16, 2 },
+ .reg_div = { S3C_CLK_DIV2, 4, 4 },
.sources = &clkset_spi_mmc,
- .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT,
- .reg_divider = S3C_CLK_DIV2,
}, {
.clk = {
.name = "audio-bus",
@@ -498,11 +378,9 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
.enable = s3c64xx_sclk_ctrl,
},
- .shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
- .mask = S3C6400_CLKSRC_AUDIO0_MASK,
+ .reg_src = { S3C_CLK_SRC, 7, 3 },
+ .reg_div = { S3C_CLK_DIV2, 8, 4 },
.sources = &clkset_audio0,
- .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT,
- .reg_divider = S3C_CLK_DIV2,
}, {
.clk = {
.name = "audio-bus",
@@ -510,11 +388,9 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
.enable = s3c64xx_sclk_ctrl,
},
- .shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
- .mask = S3C6400_CLKSRC_AUDIO1_MASK,
+ .reg_src = { S3C_CLK_SRC, 10, 3 },
+ .reg_div = { S3C_CLK_DIV2, 12, 4 },
.sources = &clkset_audio1,
- .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT,
- .reg_divider = S3C_CLK_DIV2,
}, {
.clk = {
.name = "irda-bus",
@@ -522,11 +398,9 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_IRDA,
.enable = s3c64xx_sclk_ctrl,
},
- .shift = S3C6400_CLKSRC_IRDA_SHIFT,
- .mask = S3C6400_CLKSRC_IRDA_MASK,
+ .reg_src = { S3C_CLK_SRC, 24, 2 },
+ .reg_div = { S3C_CLK_DIV2, 20, 4 },
.sources = &clkset_irda,
- .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT,
- .reg_divider = S3C_CLK_DIV2,
}, {
.clk = {
.name = "camera",
@@ -534,11 +408,9 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_CAM,
.enable = s3c64xx_sclk_ctrl,
},
- .shift = 0,
- .mask = 0,
+ .reg_div = { S3C_CLK_DIV0, 20, 4 },
+ .reg_src = { NULL, 0, 0 },
.sources = &clkset_camif,
- .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT,
- .reg_divider = S3C_CLK_DIV0,
},
};
@@ -550,27 +422,6 @@ static struct clksrc_clk *init_parents[] = {
&clk_mout_mpll,
};
-static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
-{
- struct clk_sources *srcs = clk->sources;
- u32 clksrc = __raw_readl(S3C_CLK_SRC);
-
- clksrc &= clk->mask;
- clksrc >>= clk->shift;
-
- if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
- printk(KERN_ERR "%s: bad source %d\n",
- clk->clk.name, clksrc);
- return;
- }
-
- clk->clk.parent = srcs->sources[clksrc];
-
- printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
- clk->clk.name, clk->clk.parent->name, clksrc,
- clk_get_rate(&clk->clk));
-}
-
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
void __init_or_cpufreq s3c6400_setup_clocks(void)
@@ -629,10 +480,10 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
clk_f.rate = fclk;
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
- s3c6400_set_clksrc(init_parents[ptr]);
+ s3c_set_clksrc(init_parents[ptr]);
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
- s3c6400_set_clksrc(&clksrcs[ptr]);
+ s3c_set_clksrc(&clksrcs[ptr]);
}
static struct clk *clks[] __initdata = {
@@ -675,19 +526,5 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit)
}
}
- for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) {
- clkp = &clksrcs[ptr].clk;
-
- /* all clksrc clocks have these */
- clkp->get_rate = s3c64xx_getrate_clksrc;
- clkp->set_rate = s3c64xx_setrate_clksrc;
- clkp->set_parent = s3c64xx_setparent_clksrc;
- clkp->round_rate = s3c64xx_roundrate_clksrc;
-
- ret = s3c24xx_register_clock(clkp);
- if (ret < 0) {
- printk(KERN_ERR "Failed to register clock %s (%d)\n",
- clkp->name, ret);
- }
- }
+ s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [S3C-CLK] ARM: S3C64XX: Remove unused clock definitions from clock header
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
` (5 preceding siblings ...)
2010-01-08 2:30 ` [S3C-CLK] ARM: S3C64XX: Use new clock-clksrc.c code for clocks Ben Dooks
@ 2010-01-08 2:30 ` Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: SAMSUNG: Reduce size of struct clk Ben Dooks
` (7 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Ben Dooks @ 2010-01-08 2:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Harald Welte <laforge@gnumonks.org>
Clean out the definitions we are no longer using after the new clock
code updates.
Signed-off-by: Harald Welte <laforge@gnumonks.org>
[ben-linux at fluff.org: split from initial patch provided]
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
arch/arm/plat-s3c64xx/include/plat/regs-clock.h | 71 +----------------------
1 files changed, 1 insertions(+), 70 deletions(-)
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
index ff46e7f..3ef6274 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -35,14 +35,6 @@
#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
/* CLKDIV0 */
-#define S3C6400_CLKDIV0_MFC_MASK (0xf << 28)
-#define S3C6400_CLKDIV0_MFC_SHIFT (28)
-#define S3C6400_CLKDIV0_JPEG_MASK (0xf << 24)
-#define S3C6400_CLKDIV0_JPEG_SHIFT (24)
-#define S3C6400_CLKDIV0_CAM_MASK (0xf << 20)
-#define S3C6400_CLKDIV0_CAM_SHIFT (20)
-#define S3C6400_CLKDIV0_SECURITY_MASK (0x3 << 18)
-#define S3C6400_CLKDIV0_SECURITY_SHIFT (18)
#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
#define S3C6400_CLKDIV0_PCLK_SHIFT (12)
#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9)
@@ -51,42 +43,11 @@
#define S3C6400_CLKDIV0_HCLK_SHIFT (8)
#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4)
#define S3C6400_CLKDIV0_MPLL_SHIFT (4)
+
#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0)
#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0)
#define S3C6400_CLKDIV0_ARM_SHIFT (0)
-/* CLKDIV1 */
-#define S3C6410_CLKDIV1_FIMC_MASK (0xf << 24)
-#define S3C6410_CLKDIV1_FIMC_SHIFT (24)
-#define S3C6400_CLKDIV1_UHOST_MASK (0xf << 20)
-#define S3C6400_CLKDIV1_UHOST_SHIFT (20)
-#define S3C6400_CLKDIV1_SCALER_MASK (0xf << 16)
-#define S3C6400_CLKDIV1_SCALER_SHIFT (16)
-#define S3C6400_CLKDIV1_LCD_MASK (0xf << 12)
-#define S3C6400_CLKDIV1_LCD_SHIFT (12)
-#define S3C6400_CLKDIV1_MMC2_MASK (0xf << 8)
-#define S3C6400_CLKDIV1_MMC2_SHIFT (8)
-#define S3C6400_CLKDIV1_MMC1_MASK (0xf << 4)
-#define S3C6400_CLKDIV1_MMC1_SHIFT (4)
-#define S3C6400_CLKDIV1_MMC0_MASK (0xf << 0)
-#define S3C6400_CLKDIV1_MMC0_SHIFT (0)
-
-/* CLKDIV2 */
-#define S3C6410_CLKDIV2_AUDIO2_MASK (0xf << 24)
-#define S3C6410_CLKDIV2_AUDIO2_SHIFT (24)
-#define S3C6400_CLKDIV2_IRDA_MASK (0xf << 20)
-#define S3C6400_CLKDIV2_IRDA_SHIFT (20)
-#define S3C6400_CLKDIV2_UART_MASK (0xf << 16)
-#define S3C6400_CLKDIV2_UART_SHIFT (16)
-#define S3C6400_CLKDIV2_AUDIO1_MASK (0xf << 12)
-#define S3C6400_CLKDIV2_AUDIO1_SHIFT (12)
-#define S3C6400_CLKDIV2_AUDIO0_MASK (0xf << 8)
-#define S3C6400_CLKDIV2_AUDIO0_SHIFT (8)
-#define S3C6400_CLKDIV2_SPI1_MASK (0xf << 4)
-#define S3C6400_CLKDIV2_SPI1_SHIFT (4)
-#define S3C6400_CLKDIV2_SPI0_MASK (0xf << 0)
-#define S3C6400_CLKDIV2_SPI0_SHIFT (0)
-
/* HCLK GATE Registers */
#define S3C_CLKCON_HCLK_3DSE (1<<31)
#define S3C_CLKCON_HCLK_UHOST (1<<29)
@@ -192,34 +153,4 @@
#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2)
#define S3C6400_CLKSRC_MFC (1 << 4)
-#define S3C6410_CLKSRC_TV27_MASK (0x1 << 31)
-#define S3C6410_CLKSRC_TV27_SHIFT (31)
-#define S3C6410_CLKSRC_DAC27_MASK (0x1 << 30)
-#define S3C6410_CLKSRC_DAC27_SHIFT (30)
-#define S3C6400_CLKSRC_SCALER_MASK (0x3 << 28)
-#define S3C6400_CLKSRC_SCALER_SHIFT (28)
-#define S3C6400_CLKSRC_LCD_MASK (0x3 << 26)
-#define S3C6400_CLKSRC_LCD_SHIFT (26)
-#define S3C6400_CLKSRC_IRDA_MASK (0x3 << 24)
-#define S3C6400_CLKSRC_IRDA_SHIFT (24)
-#define S3C6400_CLKSRC_MMC2_MASK (0x3 << 22)
-#define S3C6400_CLKSRC_MMC2_SHIFT (22)
-#define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20)
-#define S3C6400_CLKSRC_MMC1_SHIFT (20)
-#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18)
-#define S3C6400_CLKSRC_MMC0_SHIFT (18)
-#define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16)
-#define S3C6400_CLKSRC_SPI1_SHIFT (16)
-#define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14)
-#define S3C6400_CLKSRC_SPI0_SHIFT (14)
-#define S3C6400_CLKSRC_UART_MASK (0x1 << 13)
-#define S3C6400_CLKSRC_UART_SHIFT (13)
-#define S3C6400_CLKSRC_AUDIO1_MASK (0x7 << 10)
-#define S3C6400_CLKSRC_AUDIO1_SHIFT (10)
-#define S3C6400_CLKSRC_AUDIO0_MASK (0x7 << 7)
-#define S3C6400_CLKSRC_AUDIO0_SHIFT (7)
-#define S3C6400_CLKSRC_UHOST_MASK (0x3 << 5)
-#define S3C6400_CLKSRC_UHOST_SHIFT (5)
-
-
#endif /* _PLAT_REGS_CLOCK_H */
--
1.6.0.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [S3C-CLK] ARM: SAMSUNG: Reduce size of struct clk.
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
` (6 preceding siblings ...)
2010-01-08 2:30 ` [S3C-CLK] ARM: S3C64XX: Remove unused clock definitions from clock header Ben Dooks
@ 2010-01-08 2:30 ` Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: S3C64XX: Fixup .reg_src and .reg_div with named initialisers Ben Dooks
` (6 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Ben Dooks @ 2010-01-08 2:30 UTC (permalink / raw)
To: linux-arm-kernel
Reduce the size of struct clk by 12 bytes and make defining clocks with
common implementation functions easier by moving the set_rate, get_rate,
round_rate and set_parent calls into a new structure called 'struct clk_ops'
and using that instead.
This change does make a few clocks larger as they need their own clk_ops,
but this is outweighed by the number of clocks with either no ops or having
a common set of ops.
Update all the users of this.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
arch/arm/mach-s3c2412/clock.c | 52 +++++++----
arch/arm/mach-s3c2440/clock.c | 6 +-
arch/arm/mach-s3c2442/clock.c | 6 +-
arch/arm/mach-s3c2443/clock.c | 88 +++++++++++++-------
arch/arm/plat-s3c/clock.c | 31 ++++---
arch/arm/plat-s3c/pwm-clock.c | 94 +++++++++++----------
arch/arm/plat-s3c24xx/clock-dclk.c | 22 +++--
arch/arm/plat-s3c24xx/s3c244x-clock.c | 4 +-
arch/arm/plat-s3c64xx/s3c6400-clock.c | 14 ++-
arch/arm/plat-s5pc1xx/clock.c | 8 ++-
arch/arm/plat-s5pc1xx/s5pc100-clock.c | 126 ++++++++++++----------------
arch/arm/plat-samsung/clock-clksrc.c | 17 ++--
arch/arm/plat-samsung/include/plat/clock.h | 29 ++++++-
13 files changed, 286 insertions(+), 211 deletions(-)
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index a037df5..0c0505b 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -124,7 +124,9 @@ static struct clk clk_usysclk = {
.name = "usysclk",
.id = -1,
.parent = &clk_xtal,
- .set_parent = s3c2412_setparent_usysclk,
+ .ops = &(struct clk_ops) {
+ .set_parent = s3c2412_setparent_usysclk,
+ },
};
static struct clk clk_mrefclk = {
@@ -199,10 +201,12 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
static struct clk clk_usbsrc = {
.name = "usbsrc",
.id = -1,
- .get_rate = s3c2412_getrate_usbsrc,
- .set_rate = s3c2412_setrate_usbsrc,
- .round_rate = s3c2412_roundrate_usbsrc,
- .set_parent = s3c2412_setparent_usbsrc,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c2412_getrate_usbsrc,
+ .set_rate = s3c2412_setrate_usbsrc,
+ .round_rate = s3c2412_roundrate_usbsrc,
+ .set_parent = s3c2412_setparent_usbsrc,
+ },
};
static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
@@ -225,7 +229,9 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
static struct clk clk_msysclk = {
.name = "msysclk",
.id = -1,
- .set_parent = s3c2412_setparent_msysclk,
+ .ops = &(struct clk_ops) {
+ .set_parent = s3c2412_setparent_msysclk,
+ },
};
static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
@@ -264,7 +270,9 @@ static struct clk clk_armclk = {
.name = "armclk",
.id = -1,
.parent = &clk_msysclk,
- .set_parent = s3c2412_setparent_armclk,
+ .ops = &(struct clk_ops) {
+ .set_parent = s3c2412_setparent_armclk,
+ },
};
/* these next clocks have an divider immediately after them,
@@ -337,10 +345,12 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
static struct clk clk_uart = {
.name = "uartclk",
.id = -1,
- .get_rate = s3c2412_getrate_uart,
- .set_rate = s3c2412_setrate_uart,
- .set_parent = s3c2412_setparent_uart,
- .round_rate = s3c2412_roundrate_clksrc,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c2412_getrate_uart,
+ .set_rate = s3c2412_setrate_uart,
+ .set_parent = s3c2412_setparent_uart,
+ .round_rate = s3c2412_roundrate_clksrc,
+ },
};
static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
@@ -388,10 +398,12 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
static struct clk clk_i2s = {
.name = "i2sclk",
.id = -1,
- .get_rate = s3c2412_getrate_i2s,
- .set_rate = s3c2412_setrate_i2s,
- .set_parent = s3c2412_setparent_i2s,
- .round_rate = s3c2412_roundrate_clksrc,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c2412_getrate_i2s,
+ .set_rate = s3c2412_setrate_i2s,
+ .set_parent = s3c2412_setparent_i2s,
+ .round_rate = s3c2412_roundrate_clksrc,
+ },
};
static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
@@ -438,10 +450,12 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
static struct clk clk_cam = {
.name = "camif-upll", /* same as 2440 name */
.id = -1,
- .get_rate = s3c2412_getrate_cam,
- .set_rate = s3c2412_setrate_cam,
- .set_parent = s3c2412_setparent_cam,
- .round_rate = s3c2412_roundrate_clksrc,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c2412_getrate_cam,
+ .set_rate = s3c2412_setrate_cam,
+ .set_parent = s3c2412_setparent_cam,
+ .round_rate = s3c2412_roundrate_clksrc,
+ },
};
/* standard clock definitions */
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index d1c29b2..3dc2426 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -98,8 +98,10 @@ static struct clk s3c2440_clk_cam = {
static struct clk s3c2440_clk_cam_upll = {
.name = "camif-upll",
.id = -1,
- .set_rate = s3c2440_camif_upll_setrate,
- .round_rate = s3c2440_camif_upll_round,
+ .ops = &(struct clk_ops) {
+ .set_rate = s3c2440_camif_upll_setrate,
+ .round_rate = s3c2440_camif_upll_round,
+ },
};
static struct clk s3c2440_clk_ac97 = {
diff --git a/arch/arm/mach-s3c2442/clock.c b/arch/arm/mach-s3c2442/clock.c
index ea1aa1f..d9b692a 100644
--- a/arch/arm/mach-s3c2442/clock.c
+++ b/arch/arm/mach-s3c2442/clock.c
@@ -109,8 +109,10 @@ static struct clk s3c2442_clk_cam = {
static struct clk s3c2442_clk_cam_upll = {
.name = "camif-upll",
.id = -1,
- .set_rate = s3c2442_camif_upll_setrate,
- .round_rate = s3c2442_camif_upll_round,
+ .ops = &(struct clk_ops) {
+ .set_rate = s3c2442_camif_upll_setrate,
+ .round_rate = s3c2442_camif_upll_round,
+ },
};
static int s3c2442_clk_add(struct sys_device *sysdev)
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 2785d69..91db4f5 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -187,7 +187,9 @@ static int s3c2443_setparent_epllref(struct clk *clk, struct clk *parent)
static struct clk clk_epllref = {
.name = "epllref",
.id = -1,
- .set_parent = s3c2443_setparent_epllref,
+ .ops = &(struct clk_ops) {
+ .set_parent = s3c2443_setparent_epllref,
+ },
};
static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
@@ -205,7 +207,9 @@ static struct clk clk_mdivclk = {
.name = "mdivclk",
.parent = &clk_mpllref,
.id = -1,
- .get_rate = s3c2443_getrate_mdivclk,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c2443_getrate_mdivclk,
+ },
};
static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent)
@@ -232,7 +236,9 @@ static struct clk clk_msysclk = {
.name = "msysclk",
.parent = &clk_xtal,
.id = -1,
- .set_parent = s3c2443_setparent_msysclk,
+ .ops = &(struct clk_ops) {
+ .set_parent = s3c2443_setparent_msysclk,
+ },
};
/* armdiv
@@ -273,7 +279,9 @@ static int s3c2443_setparent_armclk(struct clk *clk, struct clk *parent)
static struct clk clk_arm = {
.name = "armclk",
.id = -1,
- .set_parent = s3c2443_setparent_armclk,
+ .ops = &(struct clk_ops) {
+ .set_parent = s3c2443_setparent_armclk,
+ },
};
/* esysclk
@@ -302,7 +310,9 @@ static struct clk clk_esysclk = {
.name = "esysclk",
.parent = &clk_epll,
.id = -1,
- .set_parent = s3c2443_setparent_esysclk,
+ .ops = &(struct clk_ops) {
+ .set_parent = s3c2443_setparent_esysclk,
+ },
};
/* uartclk
@@ -341,9 +351,11 @@ static struct clk clk_uart = {
.name = "uartclk",
.id = -1,
.parent = &clk_esysclk,
- .get_rate = s3c2443_getrate_uart,
- .set_rate = s3c2443_setrate_uart,
- .round_rate = s3c2443_roundrate_clksrc16,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c2443_getrate_uart,
+ .set_rate = s3c2443_setrate_uart,
+ .round_rate = s3c2443_roundrate_clksrc16,
+ },
};
/* hsspi
@@ -384,9 +396,11 @@ static struct clk clk_hsspi = {
.parent = &clk_esysclk,
.ctrlbit = S3C2443_SCLKCON_HSSPICLK,
.enable = s3c2443_clkcon_enable_s,
- .get_rate = s3c2443_getrate_hsspi,
- .set_rate = s3c2443_setrate_hsspi,
- .round_rate = s3c2443_roundrate_clksrc4,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c2443_getrate_hsspi,
+ .set_rate = s3c2443_setrate_hsspi,
+ .round_rate = s3c2443_roundrate_clksrc4,
+ },
};
/* usbhost
@@ -426,9 +440,11 @@ static struct clk clk_usb_bus_host = {
.parent = &clk_esysclk,
.ctrlbit = S3C2443_SCLKCON_USBHOST,
.enable = s3c2443_clkcon_enable_s,
- .get_rate = s3c2443_getrate_usbhost,
- .set_rate = s3c2443_setrate_usbhost,
- .round_rate = s3c2443_roundrate_clksrc4,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c2443_getrate_usbhost,
+ .set_rate = s3c2443_setrate_usbhost,
+ .round_rate = s3c2443_roundrate_clksrc4,
+ },
};
/* clk_hsmcc_div
@@ -468,9 +484,11 @@ static struct clk clk_hsmmc_div = {
.name = "hsmmc-div",
.id = -1,
.parent = &clk_esysclk,
- .get_rate = s3c2443_getrate_hsmmc_div,
- .set_rate = s3c2443_setrate_hsmmc_div,
- .round_rate = s3c2443_roundrate_clksrc4,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c2443_getrate_hsmmc_div,
+ .set_rate = s3c2443_setrate_hsmmc_div,
+ .round_rate = s3c2443_roundrate_clksrc4,
+ },
};
static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
@@ -505,7 +523,9 @@ static struct clk clk_hsmmc = {
.id = -1,
.parent = &clk_hsmmc_div,
.enable = s3c2443_enable_hsmmc,
- .set_parent = s3c2443_setparent_hsmmc,
+ .ops = &(struct clk_ops) {
+ .set_parent = s3c2443_setparent_hsmmc,
+ },
};
/* i2s_eplldiv
@@ -543,9 +563,11 @@ static struct clk clk_i2s_eplldiv = {
.name = "i2s-eplldiv",
.id = -1,
.parent = &clk_esysclk,
- .get_rate = s3c2443_getrate_i2s_eplldiv,
- .set_rate = s3c2443_setrate_i2s_eplldiv,
- .round_rate = s3c2443_roundrate_clksrc16,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c2443_getrate_i2s_eplldiv,
+ .set_rate = s3c2443_setrate_i2s_eplldiv,
+ .round_rate = s3c2443_roundrate_clksrc16,
+ },
};
/* i2s-ref
@@ -578,7 +600,9 @@ static struct clk clk_i2s = {
.parent = &clk_i2s_eplldiv,
.ctrlbit = S3C2443_SCLKCON_I2SCLK,
.enable = s3c2443_clkcon_enable_s,
- .set_parent = s3c2443_setparent_i2s,
+ .ops = &(struct clk_ops) {
+ .set_parent = s3c2443_setparent_i2s,
+ },
};
/* cam-if
@@ -618,9 +642,11 @@ static struct clk clk_cam = {
.parent = &clk_esysclk,
.ctrlbit = S3C2443_SCLKCON_CAMCLK,
.enable = s3c2443_clkcon_enable_s,
- .get_rate = s3c2443_getrate_cam,
- .set_rate = s3c2443_setrate_cam,
- .round_rate = s3c2443_roundrate_clksrc16,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c2443_getrate_cam,
+ .set_rate = s3c2443_setrate_cam,
+ .round_rate = s3c2443_roundrate_clksrc16,
+ },
};
/* display-if
@@ -660,9 +686,11 @@ static struct clk clk_display = {
.parent = &clk_esysclk,
.ctrlbit = S3C2443_SCLKCON_DISPCLK,
.enable = s3c2443_clkcon_enable_s,
- .get_rate = s3c2443_getrate_display,
- .set_rate = s3c2443_setrate_display,
- .round_rate = s3c2443_roundrate_clksrc256,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c2443_getrate_display,
+ .set_rate = s3c2443_setrate_display,
+ .round_rate = s3c2443_roundrate_clksrc256,
+ },
};
/* prediv
@@ -685,7 +713,9 @@ static struct clk clk_prediv = {
.name = "prediv",
.id = -1,
.parent = &clk_msysclk,
- .get_rate = s3c2443_prediv_getrate,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c2443_prediv_getrate,
+ },
};
/* standard clock definitions */
diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c
index 619cfa8..fa91125 100644
--- a/arch/arm/plat-s3c/clock.c
+++ b/arch/arm/plat-s3c/clock.c
@@ -150,8 +150,8 @@ unsigned long clk_get_rate(struct clk *clk)
if (clk->rate != 0)
return clk->rate;
- if (clk->get_rate != NULL)
- return (clk->get_rate)(clk);
+ if (clk->ops != NULL && clk->ops->get_rate != NULL)
+ return (clk->ops->get_rate)(clk);
if (clk->parent != NULL)
return clk_get_rate(clk->parent);
@@ -161,8 +161,8 @@ unsigned long clk_get_rate(struct clk *clk)
long clk_round_rate(struct clk *clk, unsigned long rate)
{
- if (!IS_ERR(clk) && clk->round_rate)
- return (clk->round_rate)(clk, rate);
+ if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
+ return (clk->ops->round_rate)(clk, rate);
return rate;
}
@@ -178,13 +178,14 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
* the clock may have been made this way by choice.
*/
- WARN_ON(clk->set_rate == NULL);
+ WARN_ON(clk->ops == NULL);
+ WARN_ON(clk->ops && clk->ops->set_rate == NULL);
- if (clk->set_rate == NULL)
+ if (clk->ops == NULL || clk->ops->set_rate == NULL)
return -EINVAL;
spin_lock(&clocks_lock);
- ret = (clk->set_rate)(clk, rate);
+ ret = (clk->ops->set_rate)(clk, rate);
spin_unlock(&clocks_lock);
return ret;
@@ -204,8 +205,8 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
spin_lock(&clocks_lock);
- if (clk->set_parent)
- ret = (clk->set_parent)(clk, parent);
+ if (clk->ops && clk->ops->set_parent)
+ ret = (clk->ops->set_parent)(clk, parent);
spin_unlock(&clocks_lock);
@@ -230,6 +231,10 @@ static int clk_default_setrate(struct clk *clk, unsigned long rate)
return 0;
}
+static struct clk_ops clk_ops_def_setrate = {
+ .set_rate = clk_default_setrate,
+};
+
struct clk clk_xtal = {
.name = "xtal",
.id = -1,
@@ -251,7 +256,7 @@ struct clk clk_epll = {
struct clk clk_mpll = {
.name = "mpll",
.id = -1,
- .set_rate = clk_default_setrate,
+ .ops = &clk_ops_def_setrate,
};
struct clk clk_upll = {
@@ -267,7 +272,6 @@ struct clk clk_f = {
.rate = 0,
.parent = &clk_mpll,
.ctrlbit = 0,
- .set_rate = clk_default_setrate,
};
struct clk clk_h = {
@@ -276,7 +280,7 @@ struct clk clk_h = {
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
- .set_rate = clk_default_setrate,
+ .ops = &clk_ops_def_setrate,
};
struct clk clk_p = {
@@ -285,7 +289,7 @@ struct clk clk_p = {
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
- .set_rate = clk_default_setrate,
+ .ops = &clk_ops_def_setrate,
};
struct clk clk_usb_bus = {
@@ -296,7 +300,6 @@ struct clk clk_usb_bus = {
};
-
struct clk s3c24xx_uclk = {
.name = "uclk",
.id = -1,
diff --git a/arch/arm/plat-s3c/pwm-clock.c b/arch/arm/plat-s3c/pwm-clock.c
index a318215..1808fa8 100644
--- a/arch/arm/plat-s3c/pwm-clock.c
+++ b/arch/arm/plat-s3c/pwm-clock.c
@@ -130,20 +130,22 @@ static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate)
return 0;
}
+static struct clk_ops clk_pwm_scaler_ops = {
+ .get_rate = clk_pwm_scaler_get_rate,
+ .set_rate = clk_pwm_scaler_set_rate,
+ .round_rate = clk_pwm_scaler_round_rate,
+};
+
static struct clk clk_timer_scaler[] = {
[0] = {
.name = "pwm-scaler0",
.id = -1,
- .get_rate = clk_pwm_scaler_get_rate,
- .set_rate = clk_pwm_scaler_set_rate,
- .round_rate = clk_pwm_scaler_round_rate,
+ .ops = &clk_pwm_scaler_ops,
},
[1] = {
.name = "pwm-scaler1",
.id = -1,
- .get_rate = clk_pwm_scaler_get_rate,
- .set_rate = clk_pwm_scaler_set_rate,
- .round_rate = clk_pwm_scaler_round_rate,
+ .ops = &clk_pwm_scaler_ops,
},
};
@@ -256,50 +258,46 @@ static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
return 0;
}
+static struct clk_ops clk_tdiv_ops = {
+ .get_rate = clk_pwm_tdiv_get_rate,
+ .set_rate = clk_pwm_tdiv_set_rate,
+ .round_rate = clk_pwm_tdiv_round_rate,
+};
+
static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[0] = {
.clk = {
- .name = "pwm-tdiv",
- .parent = &clk_timer_scaler[0],
- .get_rate = clk_pwm_tdiv_get_rate,
- .set_rate = clk_pwm_tdiv_set_rate,
- .round_rate = clk_pwm_tdiv_round_rate,
+ .name = "pwm-tdiv",
+ .ops = &clk_tdiv_ops,
+ .parent = &clk_timer_scaler[0],
},
},
[1] = {
.clk = {
- .name = "pwm-tdiv",
- .parent = &clk_timer_scaler[0],
- .get_rate = clk_pwm_tdiv_get_rate,
- .set_rate = clk_pwm_tdiv_set_rate,
- .round_rate = clk_pwm_tdiv_round_rate,
+ .name = "pwm-tdiv",
+ .ops = &clk_tdiv_ops,
+ .parent = &clk_timer_scaler[0],
}
},
[2] = {
.clk = {
- .name = "pwm-tdiv",
- .parent = &clk_timer_scaler[1],
- .get_rate = clk_pwm_tdiv_get_rate,
- .set_rate = clk_pwm_tdiv_set_rate,
- .round_rate = clk_pwm_tdiv_round_rate,
+ .name = "pwm-tdiv",
+ .ops = &clk_tdiv_ops,
+ .parent = &clk_timer_scaler[1],
},
},
[3] = {
.clk = {
- .name = "pwm-tdiv",
- .parent = &clk_timer_scaler[1],
- .get_rate = clk_pwm_tdiv_get_rate,
- .set_rate = clk_pwm_tdiv_set_rate,
- .round_rate = clk_pwm_tdiv_round_rate,
+ .name = "pwm-tdiv",
+ .ops = &clk_tdiv_ops,
+ .parent = &clk_timer_scaler[1],
},
},
[4] = {
.clk = {
- .name = "pwm-tdiv",
- .parent = &clk_timer_scaler[1],
- .get_rate = clk_pwm_tdiv_get_rate,
- .set_rate = clk_pwm_tdiv_set_rate,
- .round_rate = clk_pwm_tdiv_round_rate,
+ .name = "pwm-tdiv",
+ .ops = &clk_tdiv_ops,
+ .parent = &clk_timer_scaler[1],
},
},
};
@@ -356,31 +354,35 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
return 0;
}
+static struct clk_ops clk_tin_ops = {
+ .set_parent = clk_pwm_tin_set_parent,
+};
+
static struct clk clk_tin[] = {
[0] = {
- .name = "pwm-tin",
- .id = 0,
- .set_parent = clk_pwm_tin_set_parent,
+ .name = "pwm-tin",
+ .id = 0,
+ .ops = &clk_tin_ops,
},
[1] = {
- .name = "pwm-tin",
- .id = 1,
- .set_parent = clk_pwm_tin_set_parent,
+ .name = "pwm-tin",
+ .id = 1,
+ .ops = &clk_tin_ops,
},
[2] = {
- .name = "pwm-tin",
- .id = 2,
- .set_parent = clk_pwm_tin_set_parent,
+ .name = "pwm-tin",
+ .id = 2,
+ .ops = &clk_tin_ops,
},
[3] = {
- .name = "pwm-tin",
- .id = 3,
- .set_parent = clk_pwm_tin_set_parent,
+ .name = "pwm-tin",
+ .id = 3,
+ .ops = &clk_tin_ops,
},
[4] = {
- .name = "pwm-tin",
- .id = 4,
- .set_parent = clk_pwm_tin_set_parent,
+ .name = "pwm-tin",
+ .id = 4,
+ .ops = &clk_tin_ops,
},
};
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index ac061a1..cf97caa 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -161,14 +161,18 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
/* external clock definitions */
+static struct clk_ops dclk_ops = {
+ .set_parent = s3c24xx_dclk_setparent,
+ .set_rate = s3c24xx_set_dclk_rate,
+ .round_rate = s3c24xx_round_dclk_rate,
+};
+
struct clk s3c24xx_dclk0 = {
.name = "dclk0",
.id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK0EN,
.enable = s3c24xx_dclk_enable,
- .set_parent = s3c24xx_dclk_setparent,
- .set_rate = s3c24xx_set_dclk_rate,
- .round_rate = s3c24xx_round_dclk_rate,
+ .ops = &dclk_ops,
};
struct clk s3c24xx_dclk1 = {
@@ -176,19 +180,21 @@ struct clk s3c24xx_dclk1 = {
.id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK1EN,
.enable = s3c24xx_dclk_enable,
- .set_parent = s3c24xx_dclk_setparent,
- .set_rate = s3c24xx_set_dclk_rate,
- .round_rate = s3c24xx_round_dclk_rate,
+ .ops = &dclk_ops,
+};
+
+static struct clk_ops clkout_ops = {
+ .set_parent = s3c24xx_clkout_setparent,
};
struct clk s3c24xx_clkout0 = {
.name = "clkout0",
.id = -1,
- .set_parent = s3c24xx_clkout_setparent,
+ .ops = &clkout_ops,
};
struct clk s3c24xx_clkout1 = {
.name = "clkout1",
.id = -1,
- .set_parent = s3c24xx_clkout_setparent,
+ .ops = &clkout_ops,
};
diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c
index 7937109..f8d9613 100644
--- a/arch/arm/plat-s3c24xx/s3c244x-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c
@@ -68,7 +68,9 @@ static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent)
static struct clk clk_arm = {
.name = "armclk",
.id = -1,
- .set_parent = s3c2440_setparent_armclk,
+ .ops = &(struct clk_ops) {
+ .set_parent = s3c2440_setparent_armclk,
+ },
};
static int s3c244x_clk_add(struct sys_device *sysdev)
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 20af0c2..f85406a 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -165,9 +165,11 @@ static struct clk clk_arm = {
.name = "armclk",
.id = -1,
.parent = &clk_mout_apll.clk,
- .get_rate = s3c64xx_clk_arm_get_rate,
- .set_rate = s3c64xx_clk_arm_set_rate,
- .round_rate = s3c64xx_clk_arm_round_rate,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c64xx_clk_arm_get_rate,
+ .set_rate = s3c64xx_clk_arm_set_rate,
+ .round_rate = s3c64xx_clk_arm_round_rate,
+ },
};
static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
@@ -182,11 +184,15 @@ static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
return rate;
}
+static struct clk_ops clk_dout_ops = {
+ .get_rate = s3c64xx_clk_doutmpll_get_rate,
+};
+
static struct clk clk_dout_mpll = {
.name = "dout_mpll",
.id = -1,
.parent = &clk_mout_mpll.clk,
- .get_rate = s3c64xx_clk_doutmpll_get_rate,
+ .ops = &clk_dout_ops,
};
static struct clk *clkset_spi_mmc_list[] = {
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c
index 26c21d8..2f4d8d4 100644
--- a/arch/arm/plat-s5pc1xx/clock.c
+++ b/arch/arm/plat-s5pc1xx/clock.c
@@ -70,6 +70,10 @@ static int clk_default_setrate(struct clk *clk, unsigned long rate)
return 0;
}
+static struct clk_ops clk_ops_default_setrate = {
+ .set_rate = clk_default_setrate,
+};
+
static int clk_dummy_enable(struct clk *clk, int enable)
{
return 0;
@@ -81,8 +85,8 @@ struct clk clk_hd0 = {
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
- .set_rate = clk_default_setrate,
.enable = clk_dummy_enable,
+ .ops = &clk_ops_default_setrate,
};
struct clk clk_pd0 = {
@@ -91,7 +95,7 @@ struct clk clk_pd0 = {
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
- .set_rate = clk_default_setrate,
+ .ops = &clk_ops_default_setrate,
.enable = clk_dummy_enable,
};
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
index b436d44..16f0b90 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
@@ -111,7 +111,9 @@ static struct clk clk_dout_apll = {
.name = "dout_apll",
.id = -1,
.parent = &clk_mout_apll.clk,
- .get_rate = s5pc100_clk_dout_apll_get_rate,
+ .ops = &(struct clk_ops) {
+ .get_rate = s5pc100_clk_dout_apll_get_rate,
+ },
};
static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk)
@@ -165,9 +167,11 @@ static struct clk clk_arm = {
.name = "armclk",
.id = -1,
.parent = &clk_dout_apll,
- .get_rate = s5pc100_clk_arm_get_rate,
- .set_rate = s5pc100_clk_arm_set_rate,
- .round_rate = s5pc100_clk_arm_round_rate,
+ .ops = &(struct clk_ops) {
+ .get_rate = s5pc100_clk_arm_get_rate,
+ .set_rate = s5pc100_clk_arm_set_rate,
+ .round_rate = s5pc100_clk_arm_round_rate,
+ },
};
static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk)
@@ -185,7 +189,9 @@ static struct clk clk_dout_d0_bus = {
.name = "dout_d0_bus",
.id = -1,
.parent = &clk_arm,
- .get_rate = s5pc100_clk_dout_d0_bus_get_rate,
+ .ops = &(struct clk_ops) {
+ .get_rate = s5pc100_clk_dout_d0_bus_get_rate,
+ },
};
static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk)
@@ -203,7 +209,9 @@ static struct clk clk_dout_pclkd0 = {
.name = "dout_pclkd0",
.id = -1,
.parent = &clk_dout_d0_bus,
- .get_rate = s5pc100_clk_dout_pclkd0_get_rate,
+ .ops = &(struct clk_ops) {
+ .get_rate = s5pc100_clk_dout_pclkd0_get_rate,
+ },
};
static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk)
@@ -221,7 +229,9 @@ static struct clk clk_dout_apll2 = {
.name = "dout_apll2",
.id = -1,
.parent = &clk_mout_apll.clk,
- .get_rate = s5pc100_clk_dout_apll2_get_rate,
+ .ops = &(struct clk_ops) {
+ .get_rate = s5pc100_clk_dout_apll2_get_rate,
+ },
};
/* MPLL */
@@ -284,7 +294,9 @@ static struct clk clk_dout_d1_bus = {
.name = "dout_d1_bus",
.id = -1,
.parent = &clk_mout_am.clk,
- .get_rate = s5pc100_clk_dout_d1_bus_get_rate,
+ .ops = &(struct clk_ops) {
+ .get_rate = s5pc100_clk_dout_d1_bus_get_rate,
+ },
};
static struct clk *clkset_onenand_list[] = {
@@ -325,7 +337,9 @@ static struct clk clk_dout_pclkd1 = {
.name = "dout_pclkd1",
.id = -1,
.parent = &clk_dout_d1_bus,
- .get_rate = s5pc100_clk_dout_pclkd1_get_rate,
+ .ops = &(struct clk_ops) {
+ .get_rate = s5pc100_clk_dout_pclkd1_get_rate,
+ },
};
static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk)
@@ -345,7 +359,9 @@ static struct clk clk_dout_mpll2 = {
.name = "dout_mpll2",
.id = -1,
.parent = &clk_mout_am.clk,
- .get_rate = s5pc100_clk_dout_mpll2_get_rate,
+ .ops = &(struct clk_ops) {
+ .get_rate = s5pc100_clk_dout_mpll2_get_rate,
+ },
};
static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk)
@@ -365,7 +381,9 @@ static struct clk clk_dout_cam = {
.name = "dout_cam",
.id = -1,
.parent = &clk_dout_mpll2,
- .get_rate = s5pc100_clk_dout_cam_get_rate,
+ .ops = &(struct clk_ops) {
+ .get_rate = s5pc100_clk_dout_cam_get_rate,
+ },
};
static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk)
@@ -385,7 +403,9 @@ static struct clk clk_dout_mpll = {
.name = "dout_mpll",
.id = -1,
.parent = &clk_mout_am.clk,
- .get_rate = s5pc100_clk_dout_mpll_get_rate,
+ .ops = &(struct clk_ops) {
+ .get_rate = s5pc100_clk_dout_mpll_get_rate,
+ },
};
/* EPLL */
@@ -540,6 +560,13 @@ static unsigned long s5pc100_roundrate_clksrc(struct clk *clk,
return rate;
}
+static struct clk_ops s5pc100_clksrc_ops = {
+ .set_parent = s5pc100_setparent_clksrc,
+ .get_rate = s5pc100_getrate_clksrc,
+ .set_rate = s5pc100_setrate_clksrc,
+ .round_rate = s5pc100_roundrate_clksrc,
+};
+
static struct clk *clkset_spi_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll2,
@@ -558,10 +585,7 @@ static struct clksrc_clk clk_spi0 = {
.id = 0,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0,
.enable = s5pc100_sclk0_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+
},
.shift = S5PC100_CLKSRC1_SPI0_SHIFT,
.mask = S5PC100_CLKSRC1_SPI0_MASK,
@@ -577,10 +601,7 @@ static struct clksrc_clk clk_spi1 = {
.id = 1,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1,
.enable = s5pc100_sclk0_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+ .ops = &s5pc100_clksrc_ops,
},
.shift = S5PC100_CLKSRC1_SPI1_SHIFT,
.mask = S5PC100_CLKSRC1_SPI1_MASK,
@@ -596,10 +617,7 @@ static struct clksrc_clk clk_spi2 = {
.id = 2,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2,
.enable = s5pc100_sclk0_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+ .ops = &s5pc100_clksrc_ops,
},
.shift = S5PC100_CLKSRC1_SPI2_SHIFT,
.mask = S5PC100_CLKSRC1_SPI2_MASK,
@@ -625,10 +643,7 @@ static struct clksrc_clk clk_uart_uclk1 = {
.id = -1,
.ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
.enable = s5pc100_sclk0_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+ .ops = &s5pc100_clksrc_ops,
},
.shift = S5PC100_CLKSRC1_UART_SHIFT,
.mask = S5PC100_CLKSRC1_UART_MASK,
@@ -683,10 +698,7 @@ static struct clksrc_clk clk_audio0 = {
.id = 0,
.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0,
.enable = s5pc100_sclk1_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+ .ops = &s5pc100_clksrc_ops,
},
.shift = S5PC100_CLKSRC3_AUDIO0_SHIFT,
.mask = S5PC100_CLKSRC3_AUDIO0_MASK,
@@ -716,10 +728,7 @@ static struct clksrc_clk clk_audio1 = {
.id = 1,
.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1,
.enable = s5pc100_sclk1_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+ .ops = &s5pc100_clksrc_ops,
},
.shift = S5PC100_CLKSRC3_AUDIO1_SHIFT,
.mask = S5PC100_CLKSRC3_AUDIO1_MASK,
@@ -748,10 +757,7 @@ static struct clksrc_clk clk_audio2 = {
.id = 2,
.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2,
.enable = s5pc100_sclk1_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+ .ops = &s5pc100_clksrc_ops,
},
.shift = S5PC100_CLKSRC3_AUDIO2_SHIFT,
.mask = S5PC100_CLKSRC3_AUDIO2_MASK,
@@ -801,10 +807,7 @@ static struct clksrc_clk clk_lcd = {
.id = -1,
.ctrlbit = S5PC100_CLKGATE_SCLK1_LCD,
.enable = s5pc100_sclk1_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+ .ops = &s5pc100_clksrc_ops,
},
.shift = S5PC100_CLKSRC2_LCD_SHIFT,
.mask = S5PC100_CLKSRC2_LCD_MASK,
@@ -820,10 +823,7 @@ static struct clksrc_clk clk_fimc0 = {
.id = 0,
.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0,
.enable = s5pc100_sclk1_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+ .ops = &s5pc100_clksrc_ops,
},
.shift = S5PC100_CLKSRC2_FIMC0_SHIFT,
.mask = S5PC100_CLKSRC2_FIMC0_MASK,
@@ -839,10 +839,7 @@ static struct clksrc_clk clk_fimc1 = {
.id = 1,
.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1,
.enable = s5pc100_sclk1_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+ .ops = &s5pc100_clksrc_ops,
},
.shift = S5PC100_CLKSRC2_FIMC1_SHIFT,
.mask = S5PC100_CLKSRC2_FIMC1_MASK,
@@ -858,10 +855,7 @@ static struct clksrc_clk clk_fimc2 = {
.id = 2,
.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
.enable = s5pc100_sclk1_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+ .ops = &s5pc100_clksrc_ops,
},
.shift = S5PC100_CLKSRC2_FIMC2_SHIFT,
.mask = S5PC100_CLKSRC2_FIMC2_MASK,
@@ -889,10 +883,7 @@ static struct clksrc_clk clk_mmc0 = {
.id = 0,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
.enable = s5pc100_sclk0_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+ .ops = &s5pc100_clksrc_ops,
},
.shift = S5PC100_CLKSRC2_MMC0_SHIFT,
.mask = S5PC100_CLKSRC2_MMC0_MASK,
@@ -908,10 +899,7 @@ static struct clksrc_clk clk_mmc1 = {
.id = 1,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
.enable = s5pc100_sclk0_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+ .ops = &s5pc100_clksrc_ops,
},
.shift = S5PC100_CLKSRC2_MMC1_SHIFT,
.mask = S5PC100_CLKSRC2_MMC1_MASK,
@@ -927,10 +915,7 @@ static struct clksrc_clk clk_mmc2 = {
.id = 2,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
.enable = s5pc100_sclk0_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+ .ops = &s5pc100_clksrc_ops,
},
.shift = S5PC100_CLKSRC2_MMC2_SHIFT,
.mask = S5PC100_CLKSRC2_MMC2_MASK,
@@ -959,10 +944,7 @@ static struct clksrc_clk clk_usbhost = {
.id = -1,
.ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
.enable = s5pc100_sclk0_ctrl,
- .set_parent = s5pc100_setparent_clksrc,
- .get_rate = s5pc100_getrate_clksrc,
- .set_rate = s5pc100_setrate_clksrc,
- .round_rate = s5pc100_roundrate_clksrc,
+ .ops = &s5pc100_clksrc_ops,
},
.shift = S5PC100_CLKSRC1_UHOST_SHIFT,
.mask = S5PC100_CLKSRC1_UHOST_MASK,
diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c
index 5872f0b..ad4e872 100644
--- a/arch/arm/plat-samsung/clock-clksrc.c
+++ b/arch/arm/plat-samsung/clock-clksrc.c
@@ -150,20 +150,21 @@ void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk)
clk_get_rate(&clk->clk));
}
+static struct clk_ops clksrc_ops = {
+ .set_parent = s3c_setparent_clksrc,
+ .get_rate = s3c_getrate_clksrc,
+ .set_rate = s3c_setrate_clksrc,
+ .round_rate = s3c_roundrate_clksrc,
+};
+
void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
{
int ret;
for (; size > 0; size--, clksrc++) {
/* fill in the default functions */
- if (!clksrc->clk.set_parent)
- clksrc->clk.set_parent = s3c_setparent_clksrc;
- if (!clksrc->clk.get_rate)
- clksrc->clk.get_rate = s3c_getrate_clksrc;
- if (!clksrc->clk.set_rate)
- clksrc->clk.set_rate = s3c_setrate_clksrc;
- if (!clksrc->clk.round_rate)
- clksrc->clk.round_rate = s3c_roundrate_clksrc;
+ if (!clksrc->clk.ops)
+ clksrc->clk.ops = &clksrc_ops;
s3c_set_clksrc(clksrc);
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index d86af84..43324af 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -11,6 +11,30 @@
#include <linux/spinlock.h>
+struct clk;
+
+/**
+ * struct clk_ops - standard clock operations
+ * @set_rate: set the clock rate, see clk_set_rate().
+ * @get_rate: get the clock rate, see clk_get_rate().
+ * @round_rate: round a given clock rate, see clk_round_rate().
+ * @set_parent: set the clock's parent, see clk_set_parent().
+ *
+ * Group the common clock implementations together so that we
+ * don't have to keep setting the same fiels again. We leave
+ * enable in struct clk.
+ *
+ * Adding an extra layer of indirection into the process should
+ * not be a problem as it is unlikely these operations are going
+ * to need to be called quickly.
+ */
+struct clk_ops {
+ int (*set_rate)(struct clk *c, unsigned long rate);
+ unsigned long (*get_rate)(struct clk *c);
+ unsigned long (*round_rate)(struct clk *c, unsigned long rate);
+ int (*set_parent)(struct clk *c, struct clk *parent);
+};
+
struct clk {
struct list_head list;
struct module *owner;
@@ -21,11 +45,8 @@ struct clk {
unsigned long rate;
unsigned long ctrlbit;
+ struct clk_ops *ops;
int (*enable)(struct clk *, int enable);
- int (*set_rate)(struct clk *c, unsigned long rate);
- unsigned long (*get_rate)(struct clk *c);
- unsigned long (*round_rate)(struct clk *c, unsigned long rate);
- int (*set_parent)(struct clk *c, struct clk *parent);
};
/* other clocks which may be registered by board support */
--
1.6.0.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [S3C-CLK] ARM: S3C64XX: Fixup .reg_src and .reg_div with named initialisers
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
` (7 preceding siblings ...)
2010-01-08 2:30 ` [S3C-CLK] ARM: SAMSUNG: Reduce size of struct clk Ben Dooks
@ 2010-01-08 2:30 ` Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: S3C64XX: Avoid announcing clksrc clocks twice Ben Dooks
` (5 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Ben Dooks @ 2010-01-08 2:30 UTC (permalink / raw)
To: linux-arm-kernel
Change these two fields to have named initialisers as per the
review comments from Kyungmin Park.
sed used:
s@\.reg_src\(.*\)=\(.*\){\(.*\),\(.*\),\(.*\)}@.reg_src\1=\2{ .reg =\3, .shift =\4, .size =\5 }@g
s@\.reg_div\(.*\)=\(.*\){\(.*\),\(.*\),\(.*\)}@.reg_div\1=\2{ .reg =\3, .shift =\4, .size =\5 }@g
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
arch/arm/plat-s3c64xx/s3c6400-clock.c | 50 ++++++++++++++++----------------
1 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index f85406a..555d1aa 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -69,7 +69,7 @@ static struct clksrc_clk clk_mout_apll = {
.name = "mout_apll",
.id = -1,
},
- .reg_src = { S3C_CLK_SRC, 0, 1 },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
.sources = &clk_src_apll,
};
@@ -88,7 +88,7 @@ static struct clksrc_clk clk_mout_epll = {
.name = "mout_epll",
.id = -1,
},
- .reg_src = { S3C_CLK_SRC, 2, 1 },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
.sources = &clk_src_epll,
};
@@ -107,7 +107,7 @@ static struct clksrc_clk clk_mout_mpll = {
.name = "mout_mpll",
.id = -1,
},
- .reg_src = { S3C_CLK_SRC, 1, 1 },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
.sources = &clk_src_mpll,
};
@@ -313,8 +313,8 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_MMC0,
.enable = s3c64xx_sclk_ctrl,
},
- .reg_src = { S3C_CLK_SRC, 18, 2 },
- .reg_div = { S3C_CLK_DIV1, 0, 4 },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
.sources = &clkset_spi_mmc,
}, {
.clk = {
@@ -323,8 +323,8 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_MMC1,
.enable = s3c64xx_sclk_ctrl,
},
- .reg_src = { S3C_CLK_SRC, 20, 2 },
- .reg_div = { S3C_CLK_DIV1, 4, 4 },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
.sources = &clkset_spi_mmc,
}, {
.clk = {
@@ -333,8 +333,8 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_MMC2,
.enable = s3c64xx_sclk_ctrl,
},
- .reg_src = { S3C_CLK_SRC, 22, 2 },
- .reg_div = { S3C_CLK_DIV1, 8, 4 },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
.sources = &clkset_spi_mmc,
}, {
.clk = {
@@ -343,8 +343,8 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_UHOST,
.enable = s3c64xx_sclk_ctrl,
},
- .reg_src = { S3C_CLK_SRC, 5, 2 },
- .reg_div = { S3C_CLK_DIV1, 20, 4 },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
.sources = &clkset_uhost,
}, {
.clk = {
@@ -353,8 +353,8 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_UART,
.enable = s3c64xx_sclk_ctrl,
},
- .reg_src = { S3C_CLK_SRC, 13, 1 },
- .reg_div = { S3C_CLK_DIV2, 16, 4 },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
+ .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
.sources = &clkset_uart,
}, {
/* Where does UCLK0 come from? */
@@ -364,8 +364,8 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl,
},
- .reg_src = { S3C_CLK_SRC, 14, 2 },
- .reg_div = { S3C_CLK_DIV2, 0, 4 },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
.sources = &clkset_spi_mmc,
}, {
.clk = {
@@ -374,8 +374,8 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_SPI1,
.enable = s3c64xx_sclk_ctrl,
},
- .reg_src = { S3C_CLK_SRC, 16, 2 },
- .reg_div = { S3C_CLK_DIV2, 4, 4 },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
.sources = &clkset_spi_mmc,
}, {
.clk = {
@@ -384,8 +384,8 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
.enable = s3c64xx_sclk_ctrl,
},
- .reg_src = { S3C_CLK_SRC, 7, 3 },
- .reg_div = { S3C_CLK_DIV2, 8, 4 },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
+ .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
.sources = &clkset_audio0,
}, {
.clk = {
@@ -394,8 +394,8 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
.enable = s3c64xx_sclk_ctrl,
},
- .reg_src = { S3C_CLK_SRC, 10, 3 },
- .reg_div = { S3C_CLK_DIV2, 12, 4 },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
+ .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
.sources = &clkset_audio1,
}, {
.clk = {
@@ -404,8 +404,8 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_IRDA,
.enable = s3c64xx_sclk_ctrl,
},
- .reg_src = { S3C_CLK_SRC, 24, 2 },
- .reg_div = { S3C_CLK_DIV2, 20, 4 },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 },
.sources = &clkset_irda,
}, {
.clk = {
@@ -414,8 +414,8 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S3C_CLKCON_SCLK_CAM,
.enable = s3c64xx_sclk_ctrl,
},
- .reg_div = { S3C_CLK_DIV0, 20, 4 },
- .reg_src = { NULL, 0, 0 },
+ .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
+ .reg_src = { .reg = NULL, .shift = 0, .size = 0 },
.sources = &clkset_camif,
},
};
--
1.6.0.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [S3C-CLK] ARM: S3C64XX: Avoid announcing clksrc clocks twice
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
` (8 preceding siblings ...)
2010-01-08 2:30 ` [S3C-CLK] ARM: S3C64XX: Fixup .reg_src and .reg_div with named initialisers Ben Dooks
@ 2010-01-08 2:30 ` Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: SAMSUNG: Move clock.c to arch/arm/plat-samsung Ben Dooks
` (4 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Ben Dooks @ 2010-01-08 2:30 UTC (permalink / raw)
To: linux-arm-kernel
The new code calls the clock setup code on registration which
can be before the clock system has been fully initialised. The
following code re-does this setup at the end of the clock
registration and thus we get two printings.
Update the calls to only print on the last pass or when doing
the necessary resume work.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
arch/arm/plat-s3c64xx/s3c6400-clock.c | 4 ++--
arch/arm/plat-samsung/clock-clksrc.c | 16 +++++++++++-----
arch/arm/plat-samsung/include/plat/clock-clksrc.h | 10 +++++++++-
3 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 555d1aa..cb2bf4b 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -486,10 +486,10 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
clk_f.rate = fclk;
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
- s3c_set_clksrc(init_parents[ptr]);
+ s3c_set_clksrc(init_parents[ptr], true);
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
- s3c_set_clksrc(&clksrcs[ptr]);
+ s3c_set_clksrc(&clksrcs[ptr], true);
}
static struct clk *clks[] __initdata = {
diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c
index ad4e872..12129f8 100644
--- a/arch/arm/plat-samsung/clock-clksrc.c
+++ b/arch/arm/plat-samsung/clock-clksrc.c
@@ -125,7 +125,7 @@ static unsigned long s3c_roundrate_clksrc(struct clk *clk,
/* Clock initialisation code */
-void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk)
+void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk, bool announce)
{
struct clksrc_sources *srcs = clk->sources;
u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size);
@@ -145,9 +145,10 @@ void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk)
clk->clk.parent = srcs->sources[clksrc];
- printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
- clk->clk.name, clk->clk.parent->name, clksrc,
- clk_get_rate(&clk->clk));
+ if (announce)
+ printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
+ clk->clk.name, clk->clk.parent->name, clksrc,
+ clk_get_rate(&clk->clk));
}
static struct clk_ops clksrc_ops = {
@@ -166,7 +167,12 @@ void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
if (!clksrc->clk.ops)
clksrc->clk.ops = &clksrc_ops;
- s3c_set_clksrc(clksrc);
+ /* setup the clocksource, but do not announce it
+ * as it may be re-set by the setup routines
+ * called after the rest of the clocks have been
+ * registered
+ */
+ s3c_set_clksrc(clksrc, false);
ret = s3c24xx_register_clock(&clksrc->clk);
diff --git a/arch/arm/plat-samsung/include/plat/clock-clksrc.h b/arch/arm/plat-samsung/include/plat/clock-clksrc.h
index 283dfa0..50a8ca7 100644
--- a/arch/arm/plat-samsung/include/plat/clock-clksrc.h
+++ b/arch/arm/plat-samsung/include/plat/clock-clksrc.h
@@ -63,7 +63,15 @@ struct clksrc_clk {
struct clksrc_reg reg_div;
};
-extern void s3c_set_clksrc(struct clksrc_clk *clk);
+/**
+ * s3c_set_clksrc() - setup the clock from the register settings
+ * @clk: The clock to setup.
+ * @announce: true to announce the setting to printk().
+ *
+ * Setup the clock from the current register settings, for when the
+ * kernel boots or if it is resuming from a possibly unknown state.
+ */
+extern void s3c_set_clksrc(struct clksrc_clk *clk, bool announce);
/**
* s3c_register_clksrc() register clocks from an array of clksrc clocks
--
1.6.0.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [S3C-CLK] ARM: SAMSUNG: Move clock.c to arch/arm/plat-samsung
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
` (9 preceding siblings ...)
2010-01-08 2:30 ` [S3C-CLK] ARM: S3C64XX: Avoid announcing clksrc clocks twice Ben Dooks
@ 2010-01-08 2:30 ` Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: SAMSUNG: Do not allow get/set/round rate calls with no divider Ben Dooks
` (3 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Ben Dooks @ 2010-01-08 2:30 UTC (permalink / raw)
To: linux-arm-kernel
This is the core implementation of the clock code for all Samsung based
SoCs, so move it to arch/arm/plat-samsung (the clock.h file has already
been moved).
Since the file is built for every Samsung SoC, no changes are needed to the
Kconfig system.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
arch/arm/plat-s3c/Makefile | 3 +--
arch/arm/plat-samsung/Makefile | 4 ++++
arch/arm/{plat-s3c => plat-samsung}/clock.c | 0
3 files changed, 5 insertions(+), 2 deletions(-)
rename arch/arm/{plat-s3c => plat-samsung}/clock.c (100%)
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index 50444da..99f91ad 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -11,9 +11,8 @@ obj- :=
# Core support for all Samsung SoCs
-obj-y += init.o
+obj-y += init.o
obj-y += time.o
-obj-y += clock.o
obj-y += pwm-clock.o
obj-y += gpio.o
obj-y += gpio-config.o
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index ce736ce..7612198 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -9,4 +9,8 @@ obj-m :=
obj-n := dummy.o
obj- :=
+# Objects we always build independent of SoC choice
+
+obj-y += clock.o
+
obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-samsung/clock.c
similarity index 100%
rename from arch/arm/plat-s3c/clock.c
rename to arch/arm/plat-samsung/clock.c
--
1.6.0.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [S3C-CLK] ARM: SAMSUNG: Do not allow get/set/round rate calls with no divider
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
` (10 preceding siblings ...)
2010-01-08 2:30 ` [S3C-CLK] ARM: SAMSUNG: Move clock.c to arch/arm/plat-samsung Ben Dooks
@ 2010-01-08 2:30 ` Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: SAMSUNG: Add call to register array of clocks Ben Dooks
` (2 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Ben Dooks @ 2010-01-08 2:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Ben Dooks <ben@ben-laptop.fluff.org>
If the reg_div field is not set, then do not register clk_ops with the
get/set/round rate calls as these will fail to work.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
arch/arm/plat-samsung/clock-clksrc.c | 15 +++++++++++++--
1 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c
index 12129f8..aaf7d5e 100644
--- a/arch/arm/plat-samsung/clock-clksrc.c
+++ b/arch/arm/plat-samsung/clock-clksrc.c
@@ -158,14 +158,25 @@ static struct clk_ops clksrc_ops = {
.round_rate = s3c_roundrate_clksrc,
};
+static struct clk_ops clksrc_ops_nodiv = {
+ .set_parent = s3c_setparent_clksrc,
+};
+
void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
{
int ret;
+ WARN_ON(!clksrc->reg_div.reg && !clksrc->reg_src.reg);
+
for (; size > 0; size--, clksrc++) {
/* fill in the default functions */
- if (!clksrc->clk.ops)
- clksrc->clk.ops = &clksrc_ops;
+
+ if (!clksrc->clk.ops) {
+ if (!clksrc->reg_div.reg)
+ clksrc->clk.ops = &clksrc_ops_nodiv;
+ else
+ clksrc->clk.ops = &clksrc_ops;
+ }
/* setup the clocksource, but do not announce it
* as it may be re-set by the setup routines
--
1.6.0.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [S3C-CLK] ARM: SAMSUNG: Add call to register array of clocks
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
` (11 preceding siblings ...)
2010-01-08 2:30 ` [S3C-CLK] ARM: SAMSUNG: Do not allow get/set/round rate calls with no divider Ben Dooks
@ 2010-01-08 2:30 ` Ben Dooks
2010-01-08 2:30 ` [S3C-CLK] ARM: SAMSUNG: Do not register set_parent call if no source Ben Dooks
2010-01-12 9:16 ` Samsung SoC clock updates Russell King - ARM Linux
14 siblings, 0 replies; 20+ messages in thread
From: Ben Dooks @ 2010-01-08 2:30 UTC (permalink / raw)
To: linux-arm-kernel
Add s3c_register_clocks() to register an array of clocks, printing
an error message if there is a problem. Replace all points in the code
where this could be used.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
arch/arm/mach-s3c2443/clock.c | 9 +--------
arch/arm/plat-s3c/pwm-clock.c | 18 ++++--------------
arch/arm/plat-s3c64xx/clock.c | 10 +---------
arch/arm/plat-s5pc1xx/clock.c | 12 ++----------
arch/arm/plat-samsung/clock.c | 22 ++++++++++++++++++++++
arch/arm/plat-samsung/include/plat/clock.h | 2 ++
6 files changed, 32 insertions(+), 41 deletions(-)
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 91db4f5..3eb8b93 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -1104,14 +1104,7 @@ void __init s3c2443_init_clocks(int xtal)
/* register clocks from clock array */
- clkp = init_clocks;
- for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
- ret = s3c24xx_register_clock(clkp);
- if (ret < 0) {
- printk(KERN_ERR "Failed to register clock %s (%d)\n",
- clkp->name, ret);
- }
- }
+ s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
/* We must be careful disabling the clocks we are not intending to
* be using at boot time, as subsystems such as the LCD which do
diff --git a/arch/arm/plat-s3c/pwm-clock.c b/arch/arm/plat-s3c/pwm-clock.c
index 1808fa8..46c9381 100644
--- a/arch/arm/plat-s3c/pwm-clock.c
+++ b/arch/arm/plat-s3c/pwm-clock.c
@@ -430,25 +430,15 @@ __init void s3c_pwmclk_init(void)
return;
}
- for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) {
+ for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++)
clk_timer_scaler[clk].parent = clk_timers;
- ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
- if (ret < 0) {
- printk(KERN_ERR "error adding pwm scaler%d clock\n", clk);
- return;
- }
- }
- for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) {
- ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
- if (ret < 0) {
- printk(KERN_ERR "error adding pww tclk%d\n", clk);
- return;
- }
- }
+ s3c_register_clocks(clk_timer_scaler, ARRAY_SIZE(clk_timer_scaler));
+ s3c_register_clocks(clk_timer_tclk, ARRAY_SIZE(clk_timer_tclk));
for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
ret = clk_pwm_tdiv_register(clk);
+
if (ret < 0) {
printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
return;
diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c
index 7a36e89..ae5883c 100644
--- a/arch/arm/plat-s3c64xx/clock.c
+++ b/arch/arm/plat-s3c64xx/clock.c
@@ -274,15 +274,7 @@ void __init s3c64xx_register_clocks(void)
int ptr;
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-
- clkp = init_clocks;
- for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
- ret = s3c24xx_register_clock(clkp);
- if (ret < 0) {
- printk(KERN_ERR "Failed to register clock %s (%d)\n",
- clkp->name, ret);
- }
- }
+ s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c
index 2f4d8d4..cc21a8b 100644
--- a/arch/arm/plat-s5pc1xx/clock.c
+++ b/arch/arm/plat-s5pc1xx/clock.c
@@ -704,16 +704,8 @@ void __init s5pc1xx_register_clocks(void)
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
- clkp = s5pc100_init_clocks;
- size = ARRAY_SIZE(s5pc100_init_clocks);
-
- for (ptr = 0; ptr < size; ptr++, clkp++) {
- ret = s3c24xx_register_clock(clkp);
- if (ret < 0) {
- printk(KERN_ERR "Failed to register clock %s (%d)\n",
- clkp->name, ret);
- }
- }
+ s3c_register_clocks(s5pc100_init_clocks,
+ ARRAY_SIZE(s5pc100_init_clocks);
clkp = s5pc100_init_clocks_disable;
size = ARRAY_SIZE(s5pc100_init_clocks_disable);
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index fa91125..9194af9 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -336,6 +336,28 @@ int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
return fails;
}
+/**
+ * s3c_register_clocks() - register an array of clocks
+ * @clkp: Pointer to the first clock in the array.
+ * @nr_clks: Number of clocks to register.
+ *
+ * Call s3c24xx_register_clock() on the @clkp array given, printing an
+ * error if it fails to register the clock (unlikely).
+ */
+void __initdata s3c_register_clocks(struct clk *clkp, int nr_clks)
+{
+ int ret;
+
+ for (; nr_clks > 0; nr_clks--, clkp++) {
+ ret = s3c24xx_register_clock(clkp);
+
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to register clock %s (%d)\n",
+ clkp->name, ret);
+ }
+ }
+}
+
/* initalise all the clocks */
int __init s3c24xx_register_baseclocks(unsigned long xtal)
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 43324af..bd41f82 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -87,6 +87,8 @@ extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
extern int s3c24xx_register_clock(struct clk *clk);
extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
+extern void s3c_register_clocks(struct clk *clk, int nr_clks);
+
extern int s3c24xx_register_baseclocks(unsigned long xtal);
extern void s3c64xx_register_clocks(void);
--
1.6.0.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [S3C-CLK] ARM: SAMSUNG: Do not register set_parent call if no source
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
` (12 preceding siblings ...)
2010-01-08 2:30 ` [S3C-CLK] ARM: SAMSUNG: Add call to register array of clocks Ben Dooks
@ 2010-01-08 2:30 ` Ben Dooks
2010-01-12 9:16 ` Samsung SoC clock updates Russell King - ARM Linux
14 siblings, 0 replies; 20+ messages in thread
From: Ben Dooks @ 2010-01-08 2:30 UTC (permalink / raw)
To: linux-arm-kernel
If there is no source register defined, do not register a clksrc
clock with a valid .set_parent in the ops.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
arch/arm/plat-samsung/clock-clksrc.c | 10 +++++++++-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c
index aaf7d5e..33c633a 100644
--- a/arch/arm/plat-samsung/clock-clksrc.c
+++ b/arch/arm/plat-samsung/clock-clksrc.c
@@ -86,7 +86,7 @@ static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent)
break;
}
- if (src_nr >= 0 && sclk->reg_src.reg) {
+ if (src_nr >= 0) {
clk->parent = parent;
clksrc &= ~mask;
@@ -162,6 +162,12 @@ static struct clk_ops clksrc_ops_nodiv = {
.set_parent = s3c_setparent_clksrc,
};
+static struct clk_ops clksrc_ops_nosrc = {
+ .get_rate = s3c_getrate_clksrc,
+ .set_rate = s3c_setrate_clksrc,
+ .round_rate = s3c_roundrate_clksrc,
+};
+
void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
{
int ret;
@@ -174,6 +180,8 @@ void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
if (!clksrc->clk.ops) {
if (!clksrc->reg_div.reg)
clksrc->clk.ops = &clksrc_ops_nodiv;
+ else if (!clksrc->reg_src.reg)
+ clksrc->clk.ops = &clksrc_ops_nosrc;
else
clksrc->clk.ops = &clksrc_ops;
}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* Samsung SoC clock updates
2010-01-08 2:30 Samsung SoC clock updates Ben Dooks
` (13 preceding siblings ...)
2010-01-08 2:30 ` [S3C-CLK] ARM: SAMSUNG: Do not register set_parent call if no source Ben Dooks
@ 2010-01-12 9:16 ` Russell King - ARM Linux
2010-01-12 22:03 ` Ben Dooks
14 siblings, 1 reply; 20+ messages in thread
From: Russell King - ARM Linux @ 2010-01-12 9:16 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 08, 2010 at 02:30:08AM +0000, Ben Dooks wrote:
> This is a new set of lcokc updates currently in my next-samsung-clock
> branch, this has a few updates from the previous releases, including
> updating of the clock registration code.
When is the Samsung code going to move over to clkdev?
^ permalink raw reply [flat|nested] 20+ messages in thread* Samsung SoC clock updates
2010-01-12 9:16 ` Samsung SoC clock updates Russell King - ARM Linux
@ 2010-01-12 22:03 ` Ben Dooks
2010-01-12 22:48 ` Mark Brown
0 siblings, 1 reply; 20+ messages in thread
From: Ben Dooks @ 2010-01-12 22:03 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 12, 2010 at 09:16:08AM +0000, Russell King - ARM Linux wrote:
> On Fri, Jan 08, 2010 at 02:30:08AM +0000, Ben Dooks wrote:
> > This is a new set of lcokc updates currently in my next-samsung-clock
> > branch, this has a few updates from the previous releases, including
> > updating of the clock registration code.
>
> When is the Samsung code going to move over to clkdev?
I'm not sure that clkdev will do what we need, we have a situatio where
our platform-device names change depending on the system and thus we
would have to either change the clk array at init time or do our own
thing.
My aim is to try and look at this once the move to try and ensure that the
Samsung SoC range is using common code for things like clksrc_clk and
various things like gpiolib and then try and sort out updating the handling
of clocks.
I will certainly eliminate the driver's use of clk_get(dev, "name") to get
their default bus clock.
--
Ben
Q: What's a light-year?
A: One-third less calories than a regular year.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Samsung SoC clock updates
2010-01-12 22:03 ` Ben Dooks
@ 2010-01-12 22:48 ` Mark Brown
2010-01-12 23:50 ` Ben Dooks
0 siblings, 1 reply; 20+ messages in thread
From: Mark Brown @ 2010-01-12 22:48 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 12, 2010 at 10:03:51PM +0000, Ben Dooks wrote:
> I'm not sure that clkdev will do what we need, we have a situatio where
> our platform-device names change depending on the system and thus we
> would have to either change the clk array at init time or do our own
> thing.
Surely this is exactly the sort of use case that clkdev is designed to
handle? Essentially all it does is provide a remapping layer so that
the data associated with the struct clk doesn't have to bear any direct
relationship to the device and name used to look it up. This means that
the SoC specific code can just define its clock tree in some way that
looks good for the hardware and then easily layer a mapping to what the
drivers expect without the two jobs having to interfere with each other.
> I will certainly eliminate the driver's use of clk_get(dev, "name") to get
> their default bus clock.
I don't understand what the problem is with that? That's exactly what
I'd expect to see a driver doing (possibly with NULL instead of a
specific name).
^ permalink raw reply [flat|nested] 20+ messages in thread
* Samsung SoC clock updates
2010-01-12 22:48 ` Mark Brown
@ 2010-01-12 23:50 ` Ben Dooks
2010-01-13 11:57 ` Mark Brown
0 siblings, 1 reply; 20+ messages in thread
From: Ben Dooks @ 2010-01-12 23:50 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 12, 2010 at 10:48:34PM +0000, Mark Brown wrote:
> On Tue, Jan 12, 2010 at 10:03:51PM +0000, Ben Dooks wrote:
>
> > I'm not sure that clkdev will do what we need, we have a situatio where
> > our platform-device names change depending on the system and thus we
> > would have to either change the clk array at init time or do our own
> > thing.
>
> Surely this is exactly the sort of use case that clkdev is designed to
> handle? Essentially all it does is provide a remapping layer so that
> the data associated with the struct clk doesn't have to bear any direct
> relationship to the device and name used to look it up. This means that
> the SoC specific code can just define its clock tree in some way that
> looks good for the hardware and then easily layer a mapping to what the
> drivers expect without the two jobs having to interfere with each other.
For the first thing this ends up allocating more memory at run time when
we've already got a list of our clocks created from the compile time
structures that describe them.
I could certainly see that we could use clkdev to deal with this, but I
would like to schedule looking at this until after the current round of
SoC code cleanups and the addition of the s5p6440 SoC.
> > I will certainly eliminate the driver's use of clk_get(dev, "name") to get
> > their default bus clock.
>
> I don't understand what the problem is with that? That's exactly what
> I'd expect to see a driver doing (possibly with NULL instead of a
> specific name).
^ permalink raw reply [flat|nested] 20+ messages in thread
* Samsung SoC clock updates
2010-01-12 23:50 ` Ben Dooks
@ 2010-01-13 11:57 ` Mark Brown
0 siblings, 0 replies; 20+ messages in thread
From: Mark Brown @ 2010-01-13 11:57 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 12, 2010 at 11:50:19PM +0000, Ben Dooks wrote:
> On Tue, Jan 12, 2010 at 10:48:34PM +0000, Mark Brown wrote:
> > I don't understand what the problem is with that? That's exactly what
> > I'd expect to see a driver doing (possibly with NULL instead of a
> > specific name).
> From what I've looked at, the driver _should_ use clk_get(dev, NULL) for
> the bus clock, and use named clocks only for extra clocks it may need
> such as a codec clock for an audio device. I belive this is what Russell's
> initial complaint about the implementation is.
AFAICT that's a relatively cosmetic issue, but I don't know how Russell
feels about that one. If the block has multiple clocks it can actually
get a bit confusing trying to remember what the default clock should be.
The issues I've noticed have been that at the minute the lookups are
essentially using a global namespace for the clocks (since the only bit
of the struct device that gets looked at when doing lookups is the id
field) and that the muxes for clock sources are handled in individual
drivers (which means the drivers need to know about the clock tree of
the SoC they're running on). Given the way the Samsung SoCs structure
their clock trees the name issue isn't quite so pressing as it might be,
it'd probably only really bite if Samsung decide to change the names of
the clocks.
^ permalink raw reply [flat|nested] 20+ messages in thread