From: paul@pwsan.com (Paul Walmsley)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 12/18] OMAP3 clock: split out DPLL3 M2 divider functions into clkt3xxx_dpll3m2.c
Date: Fri, 15 Jan 2010 02:07:04 -0700 [thread overview]
Message-ID: <20100115090703.30690.171.stgit@localhost.localdomain> (raw)
In-Reply-To: <20100115090613.30690.49355.stgit@localhost.localdomain>
Split the DPLL3 M2 divider clock functions out of clock34xx.c and move them
into clkt3xxx_dpll3m2.c to improve maintainability.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jouni H?gander <jouni.hogander@nokia.com>
---
arch/arm/mach-omap2/Makefile | 3 +
arch/arm/mach-omap2/clkt3xxx_dpll3m2.c | 120 ++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/clock34xx.c | 90 ------------------------
3 files changed, 122 insertions(+), 91 deletions(-)
create mode 100644 arch/arm/mach-omap2/clkt3xxx_dpll3m2.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 7ce5fea..b002c81 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -15,11 +15,12 @@ clock-omap2xxx = clkt2xxx_dpllcore.o \
clkt2xxx_virt_prcm_set.o \
clkt2xxx_apll.o clkt2xxx_osc.o \
clkt2xxx_sys.o
+clock-omap3xxx = clkt3xxx_dpll3m2.o
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
$(clock-omap2xxx)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
- $(omap-3-4-common)
+ $(omap-3-4-common) $(clock-omap3xxx)
obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) $(prcm-common) $(clock-common)
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
diff --git a/arch/arm/mach-omap2/clkt3xxx_dpll3m2.c b/arch/arm/mach-omap2/clkt3xxx_dpll3m2.c
new file mode 100644
index 0000000..14f1a4b
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt3xxx_dpll3m2.c
@@ -0,0 +1,120 @@
+/*
+ * OMAP3 M2 divider clock code
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ * Jouni H?gander
+ *
+ * Parts of this code are based on code written by
+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+#include <plat/sram.h>
+#include <plat/sdrc.h>
+
+#include "clock.h"
+#include "clock34xx.h"
+#include "sdrc.h"
+
+#define CYCLES_PER_MHZ 1000000
+
+/*
+ * CORE DPLL (DPLL3) M2 divider rate programming functions
+ *
+ * These call into SRAM code to do the actual CM writes, since the SDRAM
+ * is clocked from DPLL3.
+ */
+
+/**
+ * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
+ * @clk: struct clk * of DPLL to set
+ * @rate: rounded target rate
+ *
+ * Program the DPLL M2 divider with the rounded target rate. Returns
+ * -EINVAL upon error, or 0 upon success.
+ */
+int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 new_div = 0;
+ u32 unlock_dll = 0;
+ u32 c;
+ unsigned long validrate, sdrcrate, _mpurate;
+ struct omap_sdrc_params *sdrc_cs0;
+ struct omap_sdrc_params *sdrc_cs1;
+ int ret;
+
+ if (!clk || !rate)
+ return -EINVAL;
+
+ validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+ if (validrate != rate)
+ return -EINVAL;
+
+ sdrcrate = sdrc_ick_p->rate;
+ if (rate > clk->rate)
+ sdrcrate <<= ((rate / clk->rate) >> 1);
+ else
+ sdrcrate >>= ((clk->rate / rate) >> 1);
+
+ ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
+ if (ret)
+ return -EINVAL;
+
+ if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
+ pr_debug("clock: will unlock SDRC DLL\n");
+ unlock_dll = 1;
+ }
+
+ /*
+ * XXX This only needs to be done when the CPU frequency changes
+ */
+ _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+ c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
+ c += 1; /* for safety */
+ c *= SDRC_MPURATE_LOOPS;
+ c >>= SDRC_MPURATE_SCALE;
+ if (c == 0)
+ c = 1;
+
+ pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
+ validrate);
+ pr_debug("clock: SDRC CS0 timing params used:"
+ " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+ sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+ sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
+ if (sdrc_cs1)
+ pr_debug("clock: SDRC CS1 timing params used: "
+ " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+ sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+ sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+
+ if (sdrc_cs1)
+ omap3_configure_core_dpll(
+ new_div, unlock_dll, c, rate > clk->rate,
+ sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+ sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+ sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+ sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+ else
+ omap3_configure_core_dpll(
+ new_div, unlock_dll, c, rate > clk->rate,
+ sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+ sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+ 0, 0, 0, 0);
+
+ return 0;
+}
+
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 4c4bb3c..552ad30 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -42,8 +42,6 @@
#include "cm.h"
#include "cm-regbits-34xx.h"
-#define CYCLES_PER_MHZ 1000000
-
/*
* DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
* that are sourced by DPLL5, and both of these require this clock
@@ -162,94 +160,6 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
return omap3_noncore_dpll_set_rate(clk, rate);
}
-
-/*
- * CORE DPLL (DPLL3) rate programming functions
- *
- * These call into SRAM code to do the actual CM writes, since the SDRAM
- * is clocked from DPLL3.
- */
-
-/**
- * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
- * @clk: struct clk * of DPLL to set
- * @rate: rounded target rate
- *
- * Program the DPLL M2 divider with the rounded target rate. Returns
- * -EINVAL upon error, or 0 upon success.
- */
-int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 new_div = 0;
- u32 unlock_dll = 0;
- u32 c;
- unsigned long validrate, sdrcrate, _mpurate;
- struct omap_sdrc_params *sdrc_cs0;
- struct omap_sdrc_params *sdrc_cs1;
- int ret;
-
- if (!clk || !rate)
- return -EINVAL;
-
- validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
- if (validrate != rate)
- return -EINVAL;
-
- sdrcrate = sdrc_ick_p->rate;
- if (rate > clk->rate)
- sdrcrate <<= ((rate / clk->rate) >> 1);
- else
- sdrcrate >>= ((clk->rate / rate) >> 1);
-
- ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
- if (ret)
- return -EINVAL;
-
- if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
- pr_debug("clock: will unlock SDRC DLL\n");
- unlock_dll = 1;
- }
-
- /*
- * XXX This only needs to be done when the CPU frequency changes
- */
- _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
- c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
- c += 1; /* for safety */
- c *= SDRC_MPURATE_LOOPS;
- c >>= SDRC_MPURATE_SCALE;
- if (c == 0)
- c = 1;
-
- pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
- validrate);
- pr_debug("clock: SDRC CS0 timing params used:"
- " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
- sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
- sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
- if (sdrc_cs1)
- pr_debug("clock: SDRC CS1 timing params used: "
- " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
- sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
- sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
-
- if (sdrc_cs1)
- omap3_configure_core_dpll(
- new_div, unlock_dll, c, rate > clk->rate,
- sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
- sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
- sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
- sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
- else
- omap3_configure_core_dpll(
- new_div, unlock_dll, c, rate > clk->rate,
- sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
- sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
- 0, 0, 0, 0);
-
- return 0;
-}
-
/* Common clock code */
/*
next prev parent reply other threads:[~2010-01-15 9:07 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-01-15 9:06 [PATCH 00/18] OMAP2/3/4 clock: split out code for clock types and clean up Paul Walmsley
2010-01-15 9:06 ` [PATCH 01/18] OMAP3 clock: move OMAP3-specific DPLL functions to dpll3xxx.c Paul Walmsley
2010-01-15 9:06 ` [PATCH 02/18] OMAP2/3/4 clock: move DPLL clock functions into clkt_dpll.c Paul Walmsley
2010-01-15 9:06 ` [PATCH 03/18] OMAP2/3/4 clock: move clksel clock functions into clkt_clksel.c Paul Walmsley
2010-01-15 9:06 ` [PATCH 04/18] OMAP2 clock: move all static functions to the top of the file Paul Walmsley
2010-01-15 9:06 ` [PATCH 05/18] OMAP2/3/4 clock: combine all omap2_clk_functions Paul Walmsley
2010-01-15 9:06 ` [PATCH 06/18] OMAP2xxx clock: move the DPLL+CORE composite clock code into clkt2xxx_dpllcore.c Paul Walmsley
2010-01-15 9:06 ` [PATCH 07/18] OMAP2xxx clock: move the DVFS virtual clock code into clkt2xxx_virt_prcm_set.c Paul Walmsley
2010-01-15 9:07 ` [PATCH 08/18] OMAP2xxx clock: move the APLL clock code into clkt2xxx_apll.c Paul Walmsley
2010-01-15 9:07 ` [PATCH 09/18] OMAP2xxx clock: move osc_clk code into clkt2xxx_osc.c Paul Walmsley
2010-01-15 9:07 ` [PATCH 10/18] OMAP2xxx clock: move sys_clk code into clkt2xxx_sys.c Paul Walmsley
2010-01-15 9:07 ` [PATCH 11/18] OMAP2 clock: don't compile OMAP2430-only functions on non-2430 builds Paul Walmsley
2010-01-15 9:07 ` Paul Walmsley [this message]
[not found] ` <20100115125014.GK29059@shisha.kicks-ass.net>
2010-01-19 18:36 ` [PATCH 12/18] OMAP3 clock: split out DPLL3 M2 divider functions into clkt3xxx_dpll3m2.c Paul Walmsley
2010-01-20 13:56 ` Ranjith Lohithakshan
2010-01-15 9:07 ` [PATCH 13/18] OMAP2/3 clock: clean up omap*_clk_arch_init() Paul Walmsley
2010-01-15 9:07 ` [PATCH 14/18] OMAP2/3 clock: remove unnecessary includes and clean up header Paul Walmsley
2010-01-15 9:07 ` [PATCH 15/18] OMAP2/3/4 clock: omap2_clk_prepare_for_reboot() is OMAP2xxx-only Paul Walmsley
2010-01-15 9:07 ` [PATCH 16/18] OMAP3 DPLL: reorganize static functions Paul Walmsley
2010-01-15 9:07 ` [PATCH 17/18] OMAP clock: resolve all remaining sparse warnings Paul Walmsley
2010-01-15 9:07 ` [PATCH 18/18] OMAP2/3/4 clock: rename and clean the omap2_clk_init() functions Paul Walmsley
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