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From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/3] OMAP4: Add L2 Cache support
Date: Fri, 29 Jan 2010 14:30:02 +0000	[thread overview]
Message-ID: <20100129143002.GD16712@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <EAF47CD23C76F840A9E7FCE10091EFAB02C09C688C@dbde02.ent.ti.com>

On Fri, Jan 29, 2010 at 05:56:55PM +0530, Shilimkar, Santosh wrote:
> Thanks for quick comment.
> > -----Original Message-----
> > From: Catalin Marinas [mailto:catalin.marinas at arm.com]
> > Sent: Friday, January 29, 2010 5:46 PM
> > To: Shilimkar, Santosh
> > Cc: tony at atomide.com; linux-arm-kernel at lists.infradead.org; rmk at arm.linux.org.uk; linux-
> > omap at vger.kernel.org
> > Subject: Re: [PATCH 1/3] OMAP4: Add L2 Cache support
> > 
> > On Fri, 2010-01-29 at 11:46 +0000, Santosh Shilimkar wrote:
> > > +#ifdef CONFIG_CACHE_L2X0
> > > +static int __init omap_l2_cache_init(void)
> > > +{
> > > +       void __iomem *l2cache_base;
> > > +
> > > +       /* Static mapping, never released */
> > > +       l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
> > > +       BUG_ON(!l2cache_base);
> > > +
> > > +       /* Enable L2 Cache using secure api
> > > +        * r0 contains the value to be modified and "r12" contains
> > > +        * the monitor API number. This API uses few CPU registers
> > > +        * internally and hence they need be backed up including
> > > +        * link register "lr".
> > > +        */
> > > +       __asm__ __volatile__(
> > > +               "stmfd r13!, {r0-r12, r14}\n"
> > > +               "mov r0, #1\n"
> > > +               "ldr r12, =0x102\n"
> > > +               "dsb\n"
> > > +               "smc\n"
> > > +               "ldmfd r13!, {r0-r12, r14}");
> > 
> > Same comments as on the cache-l2x0.c changes - can you not let the
> > compiler choose what to saved by declaring the clobbered register in the
> > asm directive?
>
> Since this code was used only ones in init, I haven't converted it to
> function. With clobber list as well as you know adding r12 to clobber
> list, compiler don't generate the save code and r11 can't be added to
> clobber list.

Well, we seem to have two places with the same code structure.  Let's
pull them together into a common function, such as:

void omap_smc1(u32 fn, u32 arg)
{
	register u32 r12 asm("r12") = fn;
	register u32 r0 asm("r0") = arg;
	asm volatile(
		"str r11, [sp], #-4\n"
		"dsb\n"
		"smc\n"
		"ldr r11, [sp, #4]!"
		: "+r" (r0), "+r" (r12)
		:
		: "r0-r10", "lr", "cc");
}
EXPORT_SYMBOL(omap_smc1);

The code there probably may not be Thumb-2 compatible.

  reply	other threads:[~2010-01-29 14:30 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-01-29 11:46 [PATCH 1/3] OMAP4: Add L2 Cache support Santosh Shilimkar
2010-01-29 11:46 ` [PATCH 2/3] OMAP4: Clean the secondary_data from L2 Santosh Shilimkar
2010-01-29 11:46   ` [PATCH 3/3] OMAP4: Enable L2 Cache Santosh Shilimkar
2010-01-29 12:16 ` [PATCH 1/3] OMAP4: Add L2 Cache support Catalin Marinas
2010-01-29 12:26   ` Shilimkar, Santosh
2010-01-29 14:30     ` Russell King - ARM Linux [this message]
2010-02-02  6:49       ` Shilimkar, Santosh
2010-01-29 17:52 ` Tony Lindgren

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