[PATCH 1/3] OMAP4: Add L2 Cache support

[PATCH 1/3] OMAP4: Add L2 Cache support

[Santosh Shilimkar]

This patch adds L2 Cache support for OMAP4. External L2 cache
is used in OMPA4

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/board-4430sdp.c        |   33 ++++++++++++++++++++++++++++
 arch/arm/mm/Kconfig                        |    2 +-
 arch/arm/plat-omap/include/plat/omap44xx.h |    1 +
 3 files changed, 35 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 0c6be6b..194d633 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -28,6 +28,7 @@
 #include <plat/control.h>
 #include <plat/timer-gp.h>
 #include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
 
 static struct platform_device sdp4430_lcd_device = {
 	.name		= "sdp4430_lcd",
@@ -49,6 +50,38 @@ static struct omap_lcd_config sdp4430_lcd_config __initdata = {
 static struct omap_board_config_kernel sdp4430_config[] __initdata = {
 	{ OMAP_TAG_LCD,		&sdp4430_lcd_config },
 };
+#ifdef CONFIG_CACHE_L2X0
+static int __init omap_l2_cache_init(void)
+{
+	void __iomem *l2cache_base;
+
+	/* Static mapping, never released */
+	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
+	BUG_ON(!l2cache_base);
+
+	/* Enable L2 Cache using secure api
+	 * r0 contains the value to be modified and "r12" contains
+	 * the monitor API number. This API uses few CPU registers
+	 * internally and hence they need be backed up including
+	 * link register "lr".
+	 */
+	__asm__ __volatile__(
+		"stmfd r13!, {r0-r12, r14}\n"
+		"mov r0, #1\n"
+		"ldr r12, =0x102\n"
+		"dsb\n"
+		"smc\n"
+		"ldmfd r13!, {r0-r12, r14}");
+
+	/* 32KB way size, 16-way associativity,
+	* parity disabled
+	*/
+	l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
+
+	return 0;
+}
+early_initcall(omap_l2_cache_init);
+#endif
 
 static void __init gic_init_irq(void)
 {
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index baf6384..696e83e 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -754,7 +754,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 config CACHE_L2X0
 	bool "Enable the L2x0 outer cache controller"
 	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-		   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK
+		   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
 	default y
 	select OUTER_CACHE
 	help
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index ef870de..c7d628e 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -40,6 +40,7 @@
 #define OMAP44XX_GIC_CPU_BASE		0x48240100
 #define OMAP44XX_SCU_BASE		0x48240000
 #define OMAP44XX_LOCAL_TWD_BASE		0x48240600
+#define OMAP44XX_L2CACHE_BASE		0x48242000
 #define OMAP44XX_WKUPGEN_BASE		0x48281000
 
 #define OMAP44XX_MAILBOX_BASE		(L4_44XX_BASE + 0xF4000)
-- 
1.6.0.4

[PATCH 2/3] OMAP4: Clean the secondary_data from L2

[Santosh Shilimkar]

The boot_secondary() needs to call outer_clean_range() because the
L2 cache is already enabled in the kernel boot with
early_initcall

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/omap-smp.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 38153e5..2d0733a 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -73,6 +73,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 	 * the AuxCoreBoot1 register is updated with cpu state
 	 * A barrier is added to ensure that write buffer is drained
 	 */
+	flush_cache_all();
+	outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
 	omap_modify_auxcoreboot0(0x200, 0x0);
 	flush_cache_all();
 	smp_wmb();
-- 
1.6.0.4

[PATCH 3/3] OMAP4: Enable L2 Cache

[Santosh Shilimkar]

This patch enables L2 cache and associated Errata on the OMAP4430
SDP.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/configs/omap_4430sdp_defconfig |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
index 3de640a..781770f 100644
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -242,6 +242,8 @@ CONFIG_CPU_CP15_MMU=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_HAS_TLS_REG=y
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_L2X0=y
 CONFIG_ARM_L1_CACHE_SHIFT=5
 # CONFIG_ARM_ERRATA_430973 is not set
 # CONFIG_ARM_ERRATA_458693 is not set
-- 
1.6.0.4

[PATCH 1/3] OMAP4: Add L2 Cache support

[Catalin Marinas]

On Fri, 2010-01-29 at 11:46 +0000, Santosh Shilimkar wrote:
> --- a/arch/arm/mach-omap2/board-4430sdp.c
> +++ b/arch/arm/mach-omap2/board-4430sdp.c
> @@ -28,6 +28,7 @@
>  #include <plat/control.h>
>  #include <plat/timer-gp.h>
>  #include <asm/hardware/gic.h>
> +#include <asm/hardware/cache-l2x0.h>
> 
>  static struct platform_device sdp4430_lcd_device = {
>         .name           = "sdp4430_lcd",
> @@ -49,6 +50,38 @@ static struct omap_lcd_config sdp4430_lcd_config __initdata = {
>  static struct omap_board_config_kernel sdp4430_config[] __initdata = {
>         { OMAP_TAG_LCD,         &sdp4430_lcd_config },
>  };
> +#ifdef CONFIG_CACHE_L2X0
> +static int __init omap_l2_cache_init(void)
> +{
> +       void __iomem *l2cache_base;
> +
> +       /* Static mapping, never released */
> +       l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
> +       BUG_ON(!l2cache_base);
> +
> +       /* Enable L2 Cache using secure api
> +        * r0 contains the value to be modified and "r12" contains
> +        * the monitor API number. This API uses few CPU registers
> +        * internally and hence they need be backed up including
> +        * link register "lr".
> +        */
> +       __asm__ __volatile__(
> +               "stmfd r13!, {r0-r12, r14}\n"
> +               "mov r0, #1\n"
> +               "ldr r12, =0x102\n"
> +               "dsb\n"
> +               "smc\n"
> +               "ldmfd r13!, {r0-r12, r14}");

Same comments as on the cache-l2x0.c changes - can you not let the
compiler choose what to saved by declaring the clobbered register in the
asm directive?

-- 
Catalin

[PATCH 1/3] OMAP4: Add L2 Cache support

[Shilimkar, Santosh]

Thanks for quick comment.
> -----Original Message-----
> From: Catalin Marinas [mailto:catalin.marinas at arm.com]
> Sent: Friday, January 29, 2010 5:46 PM
> To: Shilimkar, Santosh
> Cc: tony at atomide.com; linux-arm-kernel at lists.infradead.org; rmk at arm.linux.org.uk; linux-
> omap at vger.kernel.org
> Subject: Re: [PATCH 1/3] OMAP4: Add L2 Cache support
> 
> On Fri, 2010-01-29 at 11:46 +0000, Santosh Shilimkar wrote:
> > --- a/arch/arm/mach-omap2/board-4430sdp.c
> > +++ b/arch/arm/mach-omap2/board-4430sdp.c
> > @@ -28,6 +28,7 @@
> >  #include <plat/control.h>
> >  #include <plat/timer-gp.h>
> >  #include <asm/hardware/gic.h>
> > +#include <asm/hardware/cache-l2x0.h>
> >
> >  static struct platform_device sdp4430_lcd_device = {
> >         .name           = "sdp4430_lcd",
> > @@ -49,6 +50,38 @@ static struct omap_lcd_config sdp4430_lcd_config __initdata = {
> >  static struct omap_board_config_kernel sdp4430_config[] __initdata = {
> >         { OMAP_TAG_LCD,         &sdp4430_lcd_config },
> >  };
> > +#ifdef CONFIG_CACHE_L2X0
> > +static int __init omap_l2_cache_init(void)
> > +{
> > +       void __iomem *l2cache_base;
> > +
> > +       /* Static mapping, never released */
> > +       l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
> > +       BUG_ON(!l2cache_base);
> > +
> > +       /* Enable L2 Cache using secure api
> > +        * r0 contains the value to be modified and "r12" contains
> > +        * the monitor API number. This API uses few CPU registers
> > +        * internally and hence they need be backed up including
> > +        * link register "lr".
> > +        */
> > +       __asm__ __volatile__(
> > +               "stmfd r13!, {r0-r12, r14}\n"
> > +               "mov r0, #1\n"
> > +               "ldr r12, =0x102\n"
> > +               "dsb\n"
> > +               "smc\n"
> > +               "ldmfd r13!, {r0-r12, r14}");
> 
> Same comments as on the cache-l2x0.c changes - can you not let the
> compiler choose what to saved by declaring the clobbered register in the
> asm directive?
Since this code was used only ones in init, I haven't converted it to function. With clobber list
as well as you know adding r12 to clobber list, compiler don't generate the save code
and r11 can't be added to clobber list.

But I can do the same change as I did in the "cache-l2x0.c" Will send updated version.

Regards,
Santosh

[PATCH 1/3] OMAP4: Add L2 Cache support

[Russell King - ARM Linux]

On Fri, Jan 29, 2010 at 05:56:55PM +0530, Shilimkar, Santosh wrote:
> Thanks for quick comment.
> > -----Original Message-----
> > From: Catalin Marinas [mailto:catalin.marinas at arm.com]
> > Sent: Friday, January 29, 2010 5:46 PM
> > To: Shilimkar, Santosh
> > Cc: tony at atomide.com; linux-arm-kernel at lists.infradead.org; rmk at arm.linux.org.uk; linux-
> > omap at vger.kernel.org
> > Subject: Re: [PATCH 1/3] OMAP4: Add L2 Cache support
> > 
> > On Fri, 2010-01-29 at 11:46 +0000, Santosh Shilimkar wrote:
> > > +#ifdef CONFIG_CACHE_L2X0
> > > +static int __init omap_l2_cache_init(void)
> > > +{
> > > +       void __iomem *l2cache_base;
> > > +
> > > +       /* Static mapping, never released */
> > > +       l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
> > > +       BUG_ON(!l2cache_base);
> > > +
> > > +       /* Enable L2 Cache using secure api
> > > +        * r0 contains the value to be modified and "r12" contains
> > > +        * the monitor API number. This API uses few CPU registers
> > > +        * internally and hence they need be backed up including
> > > +        * link register "lr".
> > > +        */
> > > +       __asm__ __volatile__(
> > > +               "stmfd r13!, {r0-r12, r14}\n"
> > > +               "mov r0, #1\n"
> > > +               "ldr r12, =0x102\n"
> > > +               "dsb\n"
> > > +               "smc\n"
> > > +               "ldmfd r13!, {r0-r12, r14}");
> > 
> > Same comments as on the cache-l2x0.c changes - can you not let the
> > compiler choose what to saved by declaring the clobbered register in the
> > asm directive?
>
> Since this code was used only ones in init, I haven't converted it to
> function. With clobber list as well as you know adding r12 to clobber
> list, compiler don't generate the save code and r11 can't be added to
> clobber list.

Well, we seem to have two places with the same code structure.  Let's
pull them together into a common function, such as:

void omap_smc1(u32 fn, u32 arg)
{
	register u32 r12 asm("r12") = fn;
	register u32 r0 asm("r0") = arg;
	asm volatile(
		"str r11, [sp], #-4\n"
		"dsb\n"
		"smc\n"
		"ldr r11, [sp, #4]!"
		: "+r" (r0), "+r" (r12)
		:
		: "r0-r10", "lr", "cc");
}
EXPORT_SYMBOL(omap_smc1);

The code there probably may not be Thumb-2 compatible.

[PATCH 1/3] OMAP4: Add L2 Cache support

[Tony Lindgren]

* Santosh Shilimkar <santosh.shilimkar@ti.com> [100129 03:44]:
> This patch adds L2 Cache support for OMAP4. External L2 cache
> is used in OMPA4
> 
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  arch/arm/mach-omap2/board-4430sdp.c        |   33 ++++++++++++++++++++++++++++
>  arch/arm/mm/Kconfig                        |    2 +-
>  arch/arm/plat-omap/include/plat/omap44xx.h |    1 +
>  3 files changed, 35 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
> index 0c6be6b..194d633 100644
> --- a/arch/arm/mach-omap2/board-4430sdp.c
> +++ b/arch/arm/mach-omap2/board-4430sdp.c
> @@ -28,6 +28,7 @@
>  #include <plat/control.h>
>  #include <plat/timer-gp.h>
>  #include <asm/hardware/gic.h>
> +#include <asm/hardware/cache-l2x0.h>
>  
>  static struct platform_device sdp4430_lcd_device = {
>  	.name		= "sdp4430_lcd",
> @@ -49,6 +50,38 @@ static struct omap_lcd_config sdp4430_lcd_config __initdata = {
>  static struct omap_board_config_kernel sdp4430_config[] __initdata = {
>  	{ OMAP_TAG_LCD,		&sdp4430_lcd_config },
>  };
> +#ifdef CONFIG_CACHE_L2X0
> +static int __init omap_l2_cache_init(void)
> +{
> +	void __iomem *l2cache_base;

Since this is an initcall, you need to return here early to avoid
running on other omaps:

	if (!cpu_is_omap44xx())
		return -ENODEV;

> +
> +	/* Static mapping, never released */
> +	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
> +	BUG_ON(!l2cache_base);
> +
> +	/* Enable L2 Cache using secure api
> +	 * r0 contains the value to be modified and "r12" contains
> +	 * the monitor API number. This API uses few CPU registers
> +	 * internally and hence they need be backed up including
> +	 * link register "lr".
> +	 */
> +	__asm__ __volatile__(
> +		"stmfd r13!, {r0-r12, r14}\n"
> +		"mov r0, #1\n"
> +		"ldr r12, =0x102\n"
> +		"dsb\n"
> +		"smc\n"
> +		"ldmfd r13!, {r0-r12, r14}");
> +
> +	/* 32KB way size, 16-way associativity,
> +	* parity disabled
> +	*/
> +	l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
> +
> +	return 0;
> +}
> +early_initcall(omap_l2_cache_init);
> +#endif

Regards,

Tony

[PATCH 1/3] OMAP4: Add L2 Cache support

[Shilimkar, Santosh]

> > Since this code was used only ones in init, I haven't converted it to
> > function. With clobber list as well as you know adding r12 to clobber
> > list, compiler don't generate the save code and r11 can't be added to
> > clobber list.
> 
> Well, we seem to have two places with the same code structure.  Let's
> pull them together into a common function, such as:
> 
> void omap_smc1(u32 fn, u32 arg)
> {
> 	register u32 r12 asm("r12") = fn;
> 	register u32 r0 asm("r0") = arg;
> 	asm volatile(
> 		"str r11, [sp], #-4\n"
> 		"dsb\n"
> 		"smc\n"
> 		"ldr r11, [sp, #4]!"
> 		: "+r" (r0), "+r" (r12)
> 		:
> 		: "r0-r10", "lr", "cc");
> }
> EXPORT_SYMBOL(omap_smc1);
> 
> The code there probably may not be Thumb-2 compatible.
I will re-arrange the series and sent combined the errata + l2 support
with above change since dependency.

Regards,
Santosh