[PATCH 1/9] omap3/4: uart: fix full-fifo write abort

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* [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
@ 2010-02-18  8:59 Santosh Shilimkar
  2010-02-18  8:59 ` [PATCH 2/9] omap2/3/4: ioremap omap_globals module Santosh Shilimkar
  2010-02-19  5:25 ` [PATCH 1/9] omap3/4: uart: fix full-fifo write abort Shilimkar, Santosh
  0 siblings, 2 replies; 25+ messages in thread
From: Santosh Shilimkar @ 2010-02-18  8:59 UTC (permalink / raw)
  To: linux-arm-kernel

This patch is addition to the already merged commit on non-empty
uart fifo read abort. "ce13d4716a276f4331d78ba28a5093a63822ab95"

OMAP3630 and OMAP4430 UART IP blocks have a restriction on TX FIFO
too. If you try to write to the tx fifo when it is full, the system aborts.

This can be easily reproducible by not suppressing interconnect errors or
long duration testing where continuous prints over console from multiple
threads. This patch is addressing the issue by ensuring that write is
not issued while fifo is full. A timeout is added to avoid any hang
on fifo-full for 10 mS which is unlikely case.

Patch is validated on OMAP3630 and OMAP4 SDP.

V2 version removed the additional 1 uS on every TX as per
Tony's suggestion

Signed-off-by: Woodruff Richard <r-woodruff2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Ghorai Sukumar <s-ghorai@ti.com>
---
 arch/arm/mach-omap2/serial.c |   31 ++++++++++++++++++++++++++++---
 1 files changed, 28 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 5f3035e..b79bc89 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -23,6 +23,7 @@
 #include <linux/serial_reg.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/delay.h>
 
 #include <plat/common.h>
 #include <plat/board.h>
@@ -160,6 +161,13 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
 	return (unsigned int)__raw_readb(up->membase + offset);
 }
 
+static inline void __serial_write_reg(struct uart_port *up, int offset,
+		int value)
+{
+	offset <<= up->regshift;
+	__raw_writeb(value, up->membase + offset);
+}
+
 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
 				    int value)
 {
@@ -620,6 +628,20 @@ static unsigned int serial_in_override(struct uart_port *up, int offset)
 	return __serial_read_reg(up, offset);
 }
 
+static void serial_out_override(struct uart_port *up, int offset, int value)
+{
+	unsigned int status, tmout = 10000;
+
+	status = __serial_read_reg(up, UART_LSR);
+	while (!(status & UART_LSR_THRE)) {
+		/* Wait up to 10ms for the character(s) to be sent. */
+		if (--tmout == 0)
+			break;
+		udelay(1);
+		status = __serial_read_reg(up, UART_LSR);
+	}
+	__serial_write_reg(up, offset, value);
+}
 void __init omap_serial_early_init(void)
 {
 	int i;
@@ -721,11 +743,14 @@ void __init omap_serial_init_port(int port)
 	 * omap3xxx: Never read empty UART fifo on UARTs
 	 * with IP rev >=0x52
 	 */
-	if (cpu_is_omap44xx())
+	if (cpu_is_omap44xx()) {
 		uart->p->serial_in = serial_in_override;
-	else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
-			>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
+		uart->p->serial_out = serial_out_override;
+	} else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
+			>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) {
 		uart->p->serial_in = serial_in_override;
+		uart->p->serial_out = serial_out_override;
+	}
 }
 
 /**
-- 
1.6.0.4

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 2/9] omap2/3/4: ioremap omap_globals module
  2010-02-18  8:59 [PATCH 1/9] omap3/4: uart: fix full-fifo write abort Santosh Shilimkar
@ 2010-02-18  8:59 ` Santosh Shilimkar
  2010-02-18  8:59   ` [PATCH 3/9] omap4: sdma: Enable the idle modes on omap4 Santosh Shilimkar
                     ` (2 more replies)
  2010-02-19  5:25 ` [PATCH 1/9] omap3/4: uart: fix full-fifo write abort Shilimkar, Santosh
  1 sibling, 3 replies; 25+ messages in thread
From: Santosh Shilimkar @ 2010-02-18  8:59 UTC (permalink / raw)
  To: linux-arm-kernel

This is a clean-up patch towards dynamic allocation of IO space
instead of using harcoded macros to calculate virtual addresses.

Also update the sdrc, prcm, tap and control module to
allocate iospace dynamically

As per Tony's suggestion V2 version drops tap changes
becasue ioremap uses cpu_is_omap2420() and cpu_is_omap2430(),
so we can't use that for setting tap_base. Hence ioremap()
won't work for tap until omap2_check_revision() is done

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Kevin Hilman <khilman@deeprootsystems.com>
CC: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap2/control.c            |    6 ++++-
 arch/arm/mach-omap2/prcm.c               |   16 ++++++++++--
 arch/arm/mach-omap2/sdrc.c               |   11 +++++++-
 arch/arm/plat-omap/common.c              |   38 +++++++++++++++---------------
 arch/arm/plat-omap/include/plat/common.h |   17 ++++++++-----
 5 files changed, 56 insertions(+), 32 deletions(-)

diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index cdd1f35..43f8a33 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -140,7 +140,11 @@ static struct omap3_control_regs control_context;
 
 void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
 {
-	omap2_ctrl_base = omap2_globals->ctrl;
+	/* Static mapping, never released */
+	if (omap2_globals->ctrl) {
+		omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
+		WARN_ON(!omap2_ctrl_base);
+	}
 }
 
 void __iomem *omap_ctrl_base_get(void)
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index e8e121a..338d5f6 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -279,9 +279,19 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
 
 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
 {
-	prm_base = omap2_globals->prm;
-	cm_base = omap2_globals->cm;
-	cm2_base = omap2_globals->cm2;
+	/* Static mapping, never released */
+	if (omap2_globals->prm) {
+		prm_base = ioremap(omap2_globals->prm, SZ_8K);
+		WARN_ON(!prm_base);
+	}
+	if (omap2_globals->cm) {
+		cm_base = ioremap(omap2_globals->cm, SZ_8K);
+		WARN_ON(!cm_base);
+	}
+	if (omap2_globals->cm2) {
+		cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
+		WARN_ON(!cm2_base);
+	}
 }
 
 #ifdef CONFIG_ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index cbfbd14..4c65f56 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -119,8 +119,15 @@ int omap2_sdrc_get_params(unsigned long r,
 
 void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
 {
-	omap2_sdrc_base = omap2_globals->sdrc;
-	omap2_sms_base = omap2_globals->sms;
+	/* Static mapping, never released */
+	if (omap2_globals->sdrc) {
+		omap2_sdrc_base = ioremap(omap2_globals->sdrc, SZ_64K);
+		WARN_ON(!omap2_sdrc_base);
+	}
+	if (omap2_globals->sms) {
+		omap2_sms_base = ioremap(omap2_globals->sms, SZ_64K);
+		WARN_ON(!omap2_sms_base);
+	}
 }
 
 /**
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 4f29e8c..088c1a0 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -256,11 +256,11 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
 static struct omap_globals omap242x_globals = {
 	.class	= OMAP242X_CLASS,
 	.tap	= OMAP2_L4_IO_ADDRESS(0x48014000),
-	.sdrc	= OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
-	.sms	= OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE),
-	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP2420_CTRL_BASE),
-	.prm	= OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE),
-	.cm	= OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE),
+	.sdrc	= OMAP2420_SDRC_BASE,
+	.sms	= OMAP2420_SMS_BASE,
+	.ctrl	= OMAP2420_CTRL_BASE,
+	.prm	= OMAP2420_PRM_BASE,
+	.cm	= OMAP2420_CM_BASE,
 	.uart1_phys	= OMAP2_UART1_BASE,
 	.uart2_phys	= OMAP2_UART2_BASE,
 	.uart3_phys	= OMAP2_UART3_BASE,
@@ -277,11 +277,11 @@ void __init omap2_set_globals_242x(void)
 static struct omap_globals omap243x_globals = {
 	.class	= OMAP243X_CLASS,
 	.tap	= OMAP2_L4_IO_ADDRESS(0x4900a000),
-	.sdrc	= OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
-	.sms	= OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE),
-	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
-	.prm	= OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE),
-	.cm	= OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE),
+	.sdrc	= OMAP243X_SDRC_BASE,
+	.sms	= OMAP243X_SMS_BASE,
+	.ctrl	= OMAP243X_CTRL_BASE,
+	.prm	= OMAP2430_PRM_BASE,
+	.cm	= OMAP2430_CM_BASE,
 	.uart1_phys	= OMAP2_UART1_BASE,
 	.uart2_phys	= OMAP2_UART2_BASE,
 	.uart3_phys	= OMAP2_UART3_BASE,
@@ -298,11 +298,11 @@ void __init omap2_set_globals_243x(void)
 static struct omap_globals omap3_globals = {
 	.class	= OMAP343X_CLASS,
 	.tap	= OMAP2_L4_IO_ADDRESS(0x4830A000),
-	.sdrc	= OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
-	.sms	= OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE),
-	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
-	.prm	= OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE),
-	.cm	= OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
+	.sdrc	= OMAP343X_SDRC_BASE,
+	.sms	= OMAP343X_SMS_BASE,
+	.ctrl	= OMAP343X_CTRL_BASE,
+	.prm	= OMAP3430_PRM_BASE,
+	.cm	= OMAP3430_CM_BASE,
 	.uart1_phys	= OMAP3_UART1_BASE,
 	.uart2_phys	= OMAP3_UART2_BASE,
 	.uart3_phys	= OMAP3_UART3_BASE,
@@ -325,10 +325,10 @@ void __init omap2_set_globals_36xx(void)
 static struct omap_globals omap4_globals = {
 	.class	= OMAP443X_CLASS,
 	.tap	= OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
-	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
-	.prm	= OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
-	.cm	= OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
-	.cm2	= OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
+	.ctrl	= OMAP443X_CTRL_BASE,
+	.prm	= OMAP4430_PRM_BASE,
+	.cm	= OMAP4430_CM_BASE,
+	.cm2	= OMAP4430_CM2_BASE,
 	.uart1_phys	= OMAP4_UART1_BASE,
 	.uart2_phys	= OMAP4_UART2_BASE,
 	.uart3_phys	= OMAP4_UART3_BASE,
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index e04a58e..d0faff0 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -37,16 +37,19 @@ extern void __iomem *gic_cpu_base_addr;
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
 
-/* IO bases for various OMAP processors */
+/* IO bases for various OMAP processors
+ * Except the tap base, rest all the io bases
+ * listed are physical addresses.
+ */
 struct omap_globals {
 	u32		class;		/* OMAP class to detect */
 	void __iomem	*tap;		/* Control module ID code */
-	void __iomem	*sdrc;		/* SDRAM Controller */
-	void __iomem	*sms;		/* SDRAM Memory Scheduler */
-	void __iomem	*ctrl;		/* System Control Module */
-	void __iomem	*prm;		/* Power and Reset Management */
-	void __iomem	*cm;		/* Clock Management */
-	void __iomem	*cm2;
+	unsigned long   sdrc;           /* SDRAM Controller */
+	unsigned long   sms;            /* SDRAM Memory Scheduler */
+	unsigned long   ctrl;           /* System Control Module */
+	unsigned long   prm;            /* Power and Reset Management */
+	unsigned long   cm;             /* Clock Management */
+	unsigned long   cm2;
 	unsigned long	uart1_phys;
 	unsigned long	uart2_phys;
 	unsigned long	uart3_phys;
-- 
1.6.0.4

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 3/9] omap4: sdma: Enable the idle modes on omap4
  2010-02-18  8:59 ` [PATCH 2/9] omap2/3/4: ioremap omap_globals module Santosh Shilimkar
@ 2010-02-18  8:59   ` Santosh Shilimkar
  2010-02-18  8:59     ` [PATCH 4/9] omap: sdma: Limit the secure reserve channel fix for omap3 Santosh Shilimkar
  2010-02-18 17:35   ` [PATCH 2/9] omap2/3/4: ioremap omap_globals module Paul Walmsley
  2010-02-18 22:24   ` Kevin Hilman
  2 siblings, 1 reply; 25+ messages in thread
From: Santosh Shilimkar @ 2010-02-18  8:59 UTC (permalink / raw)
  To: linux-arm-kernel

This patch enables smart-idle idlemodes and autoidle for sDMA
on OMAP4

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/plat-omap/dma.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 30ff525..5ec96db 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2138,7 +2138,7 @@ static int __init omap_init_dma(void)
 		setup_irq(irq, &omap24xx_dma_irq);
 	}
 
-	if (cpu_is_omap34xx()) {
+	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 		/* Enable smartidle idlemodes and autoidle */
 		u32 v = dma_read(OCP_SYSCONFIG);
 		v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
-- 
1.6.0.4

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 4/9] omap: sdma: Limit the secure reserve channel fix for omap3
  2010-02-18  8:59   ` [PATCH 3/9] omap4: sdma: Enable the idle modes on omap4 Santosh Shilimkar
@ 2010-02-18  8:59     ` Santosh Shilimkar
  2010-02-18  8:59       ` [PATCH 5/9] omap4: Fix omap_type() for omap4 Santosh Shilimkar
  0 siblings, 1 reply; 25+ messages in thread
From: Santosh Shilimkar @ 2010-02-18  8:59 UTC (permalink / raw)
  To: linux-arm-kernel

The commit 'ba50ea7e' reserves DMA channels 0 and 1 on high
security devices, in order to avoid collision between kernel
dma transfers and ROM code dma transfers.

This fix is applicable only for OMAP3 so add an appropriate
check.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
CC: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/plat-omap/dma.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 5ec96db..049165c 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2149,7 +2149,8 @@ static int __init omap_init_dma(void)
 			DMA_SYSCONFIG_AUTOIDLE);
 		dma_write(v , OCP_SYSCONFIG);
 		/* reserve dma channels 0 and 1 in high security devices */
-		if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
+		if (cpu_is_omap34xx() &&
+			(omap_type() != OMAP2_DEVICE_TYPE_GP)) {
 			printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
 					"HS ROM code\n");
 			dma_chan[0].dev_id = 0;
-- 
1.6.0.4

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 5/9] omap4: Fix omap_type() for omap4
  2010-02-18  8:59     ` [PATCH 4/9] omap: sdma: Limit the secure reserve channel fix for omap3 Santosh Shilimkar
@ 2010-02-18  8:59       ` Santosh Shilimkar
  2010-02-18  8:59         ` [PATCH 6/9] omap3/4: Remove overlapping mapping of L4_WKUP io space Santosh Shilimkar
  0 siblings, 1 reply; 25+ messages in thread
From: Santosh Shilimkar @ 2010-02-18  8:59 UTC (permalink / raw)
  To: linux-arm-kernel

This patch fixes the omap_type function to detect whether the device
is GP or HS

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/id.c                  |    2 ++
 arch/arm/plat-omap/include/plat/control.h |    3 +++
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 9e7c4ae..e73f7e4 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -57,6 +57,8 @@ int omap_type(void)
 		val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
 	} else if (cpu_is_omap34xx()) {
 		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
+	} else if (cpu_is_omap44xx()) {
+		val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS);
 	} else {
 		pr_err("Cannot detect omap type!\n");
 		goto out;
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 2074473..a56deee 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -204,6 +204,9 @@
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
 
+/* 44xx control status register offset */
+#define OMAP44XX_CONTROL_STATUS		0x2c4
+
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
  * that should be added.
-- 
1.6.0.4

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 6/9] omap3/4: Remove overlapping mapping of L4_WKUP io space
  2010-02-18  8:59       ` [PATCH 5/9] omap4: Fix omap_type() for omap4 Santosh Shilimkar
@ 2010-02-18  8:59         ` Santosh Shilimkar
  2010-02-18  8:59           ` [PATCH 7/9] omap4: Add auto-generated irq and dma headers Santosh Shilimkar
  0 siblings, 1 reply; 25+ messages in thread
From: Santosh Shilimkar @ 2010-02-18  8:59 UTC (permalink / raw)
  To: linux-arm-kernel

This patch removes the L4 wakeup io mapping section for omap3
and omap4. L4 wakeup space is part of 4MB L4 space which is
already mapped and hence remove the overlapped mapping.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/io.c             |   12 ------------
 arch/arm/plat-omap/include/plat/io.h |    9 ---------
 arch/arm/plat-omap/io.c              |    4 ----
 3 files changed, 0 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5a3d6f9..0385a28 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -140,12 +140,6 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
 		.type		= MT_DEVICE
 	},
 	{
-		.virtual	= L4_WK_34XX_VIRT,
-		.pfn		= __phys_to_pfn(L4_WK_34XX_PHYS),
-		.length		= L4_WK_34XX_SIZE,
-		.type		= MT_DEVICE
-	},
-	{
 		.virtual	= OMAP34XX_GPMC_VIRT,
 		.pfn		= __phys_to_pfn(OMAP34XX_GPMC_PHYS),
 		.length		= OMAP34XX_GPMC_SIZE,
@@ -192,12 +186,6 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
 		.type		= MT_DEVICE,
 	},
 	{
-		.virtual	= L4_WK_44XX_VIRT,
-		.pfn		= __phys_to_pfn(L4_WK_44XX_PHYS),
-		.length		= L4_WK_44XX_SIZE,
-		.type		= MT_DEVICE,
-	},
-	{
 		.virtual	= OMAP44XX_GPMC_VIRT,
 		.pfn		= __phys_to_pfn(OMAP44XX_GPMC_PHYS),
 		.length		= OMAP44XX_GPMC_SIZE,
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index eef914d..128b549 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -158,10 +158,6 @@
  * VPOM3430 was not working for Int controller
  */
 
-#define L4_WK_34XX_PHYS		L4_WK_34XX_BASE	/* 0x48300000 --> 0xfa300000 */
-#define L4_WK_34XX_VIRT		(L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_WK_34XX_SIZE		SZ_1M
-
 #define L4_PER_34XX_PHYS	L4_PER_34XX_BASE
 						/* 0x49000000 --> 0xfb000000 */
 #define L4_PER_34XX_VIRT	(L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
@@ -204,11 +200,6 @@
 #define L4_44XX_VIRT		(L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_44XX_SIZE		SZ_4M
 
-
-#define L4_WK_44XX_PHYS		L4_WK_44XX_BASE	/* 0x4a300000 --> 0xfc300000 */
-#define L4_WK_44XX_VIRT		(L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_WK_44XX_SIZE		SZ_1M
-
 #define L4_PER_44XX_PHYS	L4_PER_44XX_BASE
 						/* 0x48000000 --> 0xfa000000 */
 #define L4_PER_44XX_VIRT	(L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index 0cfd54f..2c494cf 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -90,8 +90,6 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
 			return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
 		if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
 			return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
-		if (BETWEEN(p, L4_WK_34XX_PHYS, L4_WK_34XX_SIZE))
-			return XLATE(p, L4_WK_34XX_PHYS, L4_WK_34XX_VIRT);
 		if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE))
 			return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT);
 		if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE))
@@ -110,8 +108,6 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
 			return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT);
 		if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE))
 			return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT);
-		if (BETWEEN(p, L4_WK_44XX_PHYS, L4_WK_44XX_SIZE))
-			return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT);
 		if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE))
 			return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT);
 		if (BETWEEN(p, OMAP44XX_EMIF1_PHYS, OMAP44XX_EMIF1_SIZE))
-- 
1.6.0.4

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 7/9] omap4: Add auto-generated irq and dma headers
  2010-02-18  8:59         ` [PATCH 6/9] omap3/4: Remove overlapping mapping of L4_WKUP io space Santosh Shilimkar
@ 2010-02-18  8:59           ` Santosh Shilimkar
  2010-02-18  8:59             ` [PATCH 8/9] omap4: Use dma line defines from dma-44xx.h Santosh Shilimkar
  2010-02-18 17:23             ` [PATCH 7/9] omap4: Add auto-generated irq and dma headers Paul Walmsley
  0 siblings, 2 replies; 25+ messages in thread
From: Santosh Shilimkar @ 2010-02-18  8:59 UTC (permalink / raw)
  To: linux-arm-kernel

These files are generated along with the HWMOD and will eventually be
in the existing header files as soon as all drivers will be migrate to
omap_hwmod / omap_device.

The dma-44xx.h file should be in 'arch/arm/mach-omap2/include/mach/',
but this would need dma.h header also present in the mach directory to
make local include possible, like what is done for irq.h. Then the
script is needed to modify the drivers to include 'mach/dma.h' instead
of 'plat/dma.h'. This would be a bigger change and hence left out for now

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/include/mach/irqs-44xx.h |  144 +++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/dma-44xx.h   |  145 ++++++++++++++++++++++++++
 2 files changed, 289 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-omap2/include/mach/irqs-44xx.h
 create mode 100644 arch/arm/plat-omap/include/plat/dma-44xx.h

diff --git a/arch/arm/mach-omap2/include/mach/irqs-44xx.h b/arch/arm/mach-omap2/include/mach/irqs-44xx.h
new file mode 100644
index 0000000..6dc5887
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/irqs-44xx.h
@@ -0,0 +1,144 @@
+/*
+ * OMAP4 Interrupt lines definitions
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Santosh Shilimkar (santosh.shilimkar at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
+#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
+
+/* OMAP44XX IRQs numbers definitions */
+#define OMAP44XX_IRQ_LOCALTIMER			29
+#define OMAP44XX_IRQ_LOCALWDT			30
+
+#define OMAP44XX_IRQ_GIC_START			32
+
+#define OMAP44XX_IRQ_PL310			(0 + OMAP44XX_IRQ_GIC_START)	/* Level-2 Cache Controller interrupt */
+#define OMAP44XX_IRQ_CTI0			(1 + OMAP44XX_IRQ_GIC_START)	/* TRIGOUT[6] of Cross Trigger Interface 0 (CTI0) */
+#define OMAP44XX_IRQ_CTI1			(2 + OMAP44XX_IRQ_GIC_START)	/* TRIGOUT[6] of Cross Trigger Interface 1 (CTI1) */
+#define OMAP44XX_IRQ_ELM			(4 + OMAP44XX_IRQ_GIC_START)	/* Error location process completion */
+#define OMAP44XX_IRQ_SYS_1N			(7 + OMAP44XX_IRQ_GIC_START)	/* External interrupt (active low) */
+#define OMAP44XX_IRQ_SECURITY_EVENTS		(8 + OMAP44XX_IRQ_GIC_START)	/* Occurs when a firewall (ARTERIS/L4) has generated an out-band error or when power events occurred (including power-on reset, so by default, this interrupt is active after power-up reset). */
+#define OMAP44XX_IRQ_L3_DBG			(9 + OMAP44XX_IRQ_GIC_START)	/* Reports debug errors on L3 */
+#define OMAP44XX_IRQ_L3_APP			(10 + OMAP44XX_IRQ_GIC_START)	/* Reports application or non-attributable errors on L3 */
+#define OMAP44XX_IRQ_PRCM			(11 + OMAP44XX_IRQ_GIC_START)	/* PRCM module */
+#define OMAP44XX_IRQ_SDMA_0			(12 + OMAP44XX_IRQ_GIC_START)	/* System DMA interrupt request 0 */
+#define OMAP44XX_IRQ_SDMA_1			(13 + OMAP44XX_IRQ_GIC_START)	/* System DMA interrupt request 1 */
+#define OMAP44XX_IRQ_SDMA_2			(14 + OMAP44XX_IRQ_GIC_START)	/* System DMA interrupt request 2 */
+#define OMAP44XX_IRQ_SDMA_3			(15 + OMAP44XX_IRQ_GIC_START)	/* System DMA interrupt request 3 */
+#define OMAP44XX_IRQ_MCBSP4			(16 + OMAP44XX_IRQ_GIC_START)	/* McBSP 4 / PORCOMMONIRQ : Common Synchronous Interrupt Request line */
+#define OMAP44XX_IRQ_MCBSP1			(17 + OMAP44XX_IRQ_GIC_START)	/* McBSP 1 / PORCOMMONIRQ : Common Synchronous Interrupt Request line */
+#define OMAP44XX_IRQ_SR_MCU			(18 + OMAP44XX_IRQ_GIC_START)	/* SmartReflex MCU interrupt request */
+#define OMAP44XX_IRQ_SR_CORE			(19 + OMAP44XX_IRQ_GIC_START)	/* SmartReflex Core interrupt request */
+#define OMAP44XX_IRQ_GPMC			(20 + OMAP44XX_IRQ_GIC_START)	/* General purpose memory controller module */
+#define OMAP44XX_IRQ_GFX			(21 + OMAP44XX_IRQ_GIC_START)	/* 2D/3D graphics module */
+#define OMAP44XX_IRQ_MCBSP2			(22 + OMAP44XX_IRQ_GIC_START)	/* McBSP 2 / PORCOMMONIRQ : Common Synchronous Interrupt Request line */
+#define OMAP44XX_IRQ_MCBSP3			(23 + OMAP44XX_IRQ_GIC_START)	/* McBSP 3 / PORCOMMONIRQ : Common Synchronous Interrupt Request line */
+#define OMAP44XX_IRQ_ISS_5			(24 + OMAP44XX_IRQ_GIC_START)	/* Imaging Sub System interrupt request */
+#define OMAP44XX_IRQ_DSS_DISPC			(25 + OMAP44XX_IRQ_GIC_START)	/* Display controller interrupt request */
+#define OMAP44XX_IRQ_MAIL_U0			(26 + OMAP44XX_IRQ_GIC_START)	/* Mailbox user 0 interrupt request */
+#define OMAP44XX_IRQ_C2C_SSCM_0			(27 + OMAP44XX_IRQ_GIC_START)	/* Chip2Chip Status interrupt */
+#define OMAP44XX_IRQ_TESLA_MMU			(28 + OMAP44XX_IRQ_GIC_START)	/* Telsa (Mini64) SS MMU interrupt */
+#define OMAP44XX_IRQ_GPIO1			(29 + OMAP44XX_IRQ_GIC_START)	/* GPIO module 1 interrupt 1 */
+#define OMAP44XX_IRQ_GPIO2			(30 + OMAP44XX_IRQ_GIC_START)	/* GPIO module 2 interrupt 1 */
+#define OMAP44XX_IRQ_GPIO3			(31 + OMAP44XX_IRQ_GIC_START)	/* GPIO module 3 interrupt 1 */
+#define OMAP44XX_IRQ_GPIO4			(32 + OMAP44XX_IRQ_GIC_START)	/* GPIO module 4 interrupt 1 */
+#define OMAP44XX_IRQ_GPIO5			(33 + OMAP44XX_IRQ_GIC_START)	/* GPIO module 5 interrupt 1 */
+#define OMAP44XX_IRQ_GPIO6			(34 + OMAP44XX_IRQ_GIC_START)	/* GPIO module 6 interrupt 1 */
+#define OMAP44XX_IRQ_USIM			(35 + OMAP44XX_IRQ_GIC_START)	/* USIM interrupt */
+#define OMAP44XX_IRQ_WDT3			(36 + OMAP44XX_IRQ_GIC_START)	/* Watchdog timer module 3 overflow (WDT controlled by Mini64) */
+#define OMAP44XX_IRQ_GPT1			(37 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 1 (Timer 1ms / Wakeup domain) */
+#define OMAP44XX_IRQ_GPT2			(38 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 2 (Timer 1ms / Core domain) */
+#define OMAP44XX_IRQ_GPT3			(39 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 3 */
+#define OMAP44XX_IRQ_GPT4			(40 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 4 */
+#define OMAP44XX_IRQ_GPT5			(41 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 5 (Audio BE) */
+#define OMAP44XX_IRQ_GPT6			(42 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 6 (Audio BE) */
+#define OMAP44XX_IRQ_GPT7			(43 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 7 (Audio BE) */
+#define OMAP44XX_IRQ_GPT8			(44 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 8 (Audio BE) */
+#define OMAP44XX_IRQ_GPT9			(45 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 9 */
+#define OMAP44XX_IRQ_GPT10			(46 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 10 (Timer 1ms / Core domain) */
+#define OMAP44XX_IRQ_GPT11			(47 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 11 */
+#define OMAP44XX_IRQ_SPI4			(48 + OMAP44XX_IRQ_GIC_START)	/* McSPI module 4 */
+#define OMAP44XX_IRQ_SHA1_S			(49 + OMAP44XX_IRQ_GIC_START)	/* SHA2/MD5 crypto-accelerator 1 combined secure side */
+#define OMAP44XX_IRQ_FPKA_SINTREQUEST_S		(50 + OMAP44XX_IRQ_GIC_START)	/* PKA crypto-accelerator combined */
+#define OMAP44XX_IRQ_SHA1_P			(51 + OMAP44XX_IRQ_GIC_START)	/* SHA2/MD5 crypto-accelerator 1 combined public side */
+#define OMAP44XX_IRQ_RNG			(52 + OMAP44XX_IRQ_GIC_START)	/* RNG module */
+#define OMAP44XX_IRQ_DSS_DSI1			(53 + OMAP44XX_IRQ_GIC_START)	/* Display DSI1 interrupt request */
+#define OMAP44XX_IRQ_I2C1			(56 + OMAP44XX_IRQ_GIC_START)	/* I2C module 1 */
+#define OMAP44XX_IRQ_I2C2			(57 + OMAP44XX_IRQ_GIC_START)	/* I2C module 2 */
+#define OMAP44XX_IRQ_HDQ			(58 + OMAP44XX_IRQ_GIC_START)	/* HDQ/One wire */
+#define OMAP44XX_IRQ_MMC5			(59 + OMAP44XX_IRQ_GIC_START)	/* MMC5_IRQ */
+#define OMAP44XX_IRQ_I2C3			(61 + OMAP44XX_IRQ_GIC_START)	/* I2C module 3 */
+#define OMAP44XX_IRQ_I2C4			(62 + OMAP44XX_IRQ_GIC_START)	/* I2C module 4 */
+#define OMAP44XX_IRQ_AES2_S			(63 + OMAP44XX_IRQ_GIC_START)	/* AES module 2 Interrupt secure side */
+#define OMAP44XX_IRQ_AES2_P			(64 + OMAP44XX_IRQ_GIC_START)	/* AES module 2 Interrupt public side */
+#define OMAP44XX_IRQ_SPI1			(65 + OMAP44XX_IRQ_GIC_START)	/* McSPI module 1 */
+#define OMAP44XX_IRQ_SPI2			(66 + OMAP44XX_IRQ_GIC_START)	/* McSPI module 2 */
+#define OMAP44XX_IRQ_HSI_P1			(67 + OMAP44XX_IRQ_GIC_START)	/* HSI interrupt request - Port 1 combined interrupt */
+#define OMAP44XX_IRQ_HSI_P2			(68 + OMAP44XX_IRQ_GIC_START)	/* HSI interrupt request - Port 2 combined interrupt */
+#define OMAP44XX_IRQ_FDIF_3			(69 + OMAP44XX_IRQ_GIC_START)	/* Face detect Interrupt */
+#define OMAP44XX_IRQ_UART4			(70 + OMAP44XX_IRQ_GIC_START)	/* UART module 4 */
+#define OMAP44XX_IRQ_HSI_DMA			(71 + OMAP44XX_IRQ_GIC_START)	/* HSI DMA engine */
+#define OMAP44XX_IRQ_UART1			(72 + OMAP44XX_IRQ_GIC_START)	/* UART module 1 */
+#define OMAP44XX_IRQ_UART2			(73 + OMAP44XX_IRQ_GIC_START)	/* UART module 2 */
+#define OMAP44XX_IRQ_UART3			(74 + OMAP44XX_IRQ_GIC_START)	/* UART module 3 (also infrared) */
+#define OMAP44XX_IRQ_PBIAS			(75 + OMAP44XX_IRQ_GIC_START)	/* Merged interrupt for PBIASlite1 and 2 */
+#define OMAP44XX_IRQ_OHCI			(76 + OMAP44XX_IRQ_GIC_START)	/* HSUSB MP Host Interrupt OHCI controller */
+#define OMAP44XX_IRQ_EHCI			(77 + OMAP44XX_IRQ_GIC_START)	/* HSUSB MP Host Interrupt EHCI controller */
+#define OMAP44XX_IRQ_TLL			(78 + OMAP44XX_IRQ_GIC_START)	/* HSUSB MP TLL Interrupt */
+#define OMAP44XX_IRQ_AES1_S			(79 + OMAP44XX_IRQ_GIC_START)	/* AES module 1 interrupt secure side */
+#define OMAP44XX_IRQ_WDT2			(80 + OMAP44XX_IRQ_GIC_START)	/* WDT2 interrupt */
+#define OMAP44XX_IRQ_DES_S			(81 + OMAP44XX_IRQ_GIC_START)	/* DES/3DES module secure side */
+#define OMAP44XX_IRQ_DES_P			(82 + OMAP44XX_IRQ_GIC_START)	/* DES/3DES module Public side */
+#define OMAP44XX_IRQ_MMC1			(83 + OMAP44XX_IRQ_GIC_START)	/* MMC1_IRQ */
+#define OMAP44XX_IRQ_DSS_DSI2			(84 + OMAP44XX_IRQ_GIC_START)	/* Display DSI2 interrupt request */
+#define OMAP44XX_IRQ_AES1_P			(85 + OMAP44XX_IRQ_GIC_START)	/* AES module 1 interrupt public side */
+#define OMAP44XX_IRQ_MMC2			(86 + OMAP44XX_IRQ_GIC_START)	/* MMC/SDIO module 2 */
+#define OMAP44XX_IRQ_MPU_ICR			(87 + OMAP44XX_IRQ_GIC_START)	/* MPU ICR Interrupt from Modem-APE  Inter Processor Communication IP */
+#define OMAP44XX_IRQ_C2C_SSCM_1			(88 + OMAP44XX_IRQ_GIC_START)	/* Chip2Chip GPI interrupt */
+#define OMAP44XX_IRQ_FSUSB			(89 + OMAP44XX_IRQ_GIC_START)	/* FS-USB - Host controller Interrupt */
+#define OMAP44XX_IRQ_FSUSB_SMI			(90 + OMAP44XX_IRQ_GIC_START)	/* FS-USB - Host controller  SMI (system Management) Interrupt */
+#define OMAP44XX_IRQ_SPI3			(91 + OMAP44XX_IRQ_GIC_START)	/* McSPI module 3 */
+#define OMAP44XX_IRQ_HS_USB_MC_N		(92 + OMAP44XX_IRQ_GIC_START)	/* Module HS USB OTG controller */
+#define OMAP44XX_IRQ_HS_USB_DMA_N		(93 + OMAP44XX_IRQ_GIC_START)	/* Module HS USB OTG DMA controller interrupt */
+#define OMAP44XX_IRQ_MMC3			(94 + OMAP44XX_IRQ_GIC_START)	/* MMC/SDIO module 3 */
+#define OMAP44XX_IRQ_GPT12			(95 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 12 (secure timer / Wakeup domain) */
+#define OMAP44XX_IRQ_MMC4			(96 + OMAP44XX_IRQ_GIC_START)	/* MMC/SDIO module 4 */
+#define OMAP44XX_IRQ_SLIMBUS1			(97 + OMAP44XX_IRQ_GIC_START)	/* SLIMBus module 1 */
+#define OMAP44XX_IRQ_SLIMBUS2			(98 + OMAP44XX_IRQ_GIC_START)	/* SLIMBus module 2 */
+#define OMAP44XX_IRQ_ABE			(99 + OMAP44XX_IRQ_GIC_START)	/* Audio Back-End interrupt */
+#define OMAP44XX_IRQ_DUCATI_MMU			(100 + OMAP44XX_IRQ_GIC_START)	/* Ducati MMU interrupt */
+#define OMAP44XX_IRQ_DSS_HDMI			(101 + OMAP44XX_IRQ_GIC_START)	/* Display HDMI interrupt request */
+#define OMAP44XX_IRQ_SR_IVA			(102 + OMAP44XX_IRQ_GIC_START)	/* SmartReflex IVA interrupt request */
+#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1	(103 + OMAP44XX_IRQ_GIC_START)	/* Sync interrupt from ICONT2 (vDMA) */
+#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0	(104 + OMAP44XX_IRQ_GIC_START)	/* Sync interrupt from ICONT1 */
+#define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0	(107 + OMAP44XX_IRQ_GIC_START)	/* IVA-HD Sub System interrupt request (Mailbox interrupt 0) */
+#define OMAP44XX_IRQ_MCASP1_AR			(108 + OMAP44XX_IRQ_GIC_START)	/* McASP Receive interrupt - Module 1 (Audio BE) */
+#define OMAP44XX_IRQ_MCASP1_AX			(109 + OMAP44XX_IRQ_GIC_START)	/* McASP Transmit interrupt - Module 1 (Audio BE) */
+#define OMAP44XX_IRQ_EMIF4_1			(110 + OMAP44XX_IRQ_GIC_START)	/* EMIF4 interrupt - Module 1 */
+#define OMAP44XX_IRQ_EMIF4_2			(111 + OMAP44XX_IRQ_GIC_START)	/* EMIF4 interrupt - Module 2 */
+#define OMAP44XX_IRQ_MCPDM			(112 + OMAP44XX_IRQ_GIC_START)	/* McPDM interrupt (Audio BE) */
+#define OMAP44XX_IRQ_DMM			(113 + OMAP44XX_IRQ_GIC_START)	/* DMM interrupt */
+#define OMAP44XX_IRQ_DMIC			(114 + OMAP44XX_IRQ_GIC_START)	/* DMIC interrupt (Audio BE) */
+#define OMAP44XX_IRQ_CDMA_0			(115 + OMAP44XX_IRQ_GIC_START)	/* Crypto DMA interrupt request 0 */
+#define OMAP44XX_IRQ_CDMA_1			(116 + OMAP44XX_IRQ_GIC_START)	/* Crypto DMA interrupt request 1 */
+#define OMAP44XX_IRQ_CDMA_2			(117 + OMAP44XX_IRQ_GIC_START)	/* Crypto DMA interrupt request 2 */
+#define OMAP44XX_IRQ_CDMA_3			(118 + OMAP44XX_IRQ_GIC_START)	/* Crypto DMA interrupt request 3 */
+#define OMAP44XX_IRQ_SYS_2N			(119 + OMAP44XX_IRQ_GIC_START)	/* External interrupt 2 (active low) */
+#define OMAP44XX_IRQ_KBD_CTL			(120 + OMAP44XX_IRQ_GIC_START)	/* Keyboard controller IRQ */
+#define OMAP44XX_IRQ_UNIPRO1			(124 + OMAP44XX_IRQ_GIC_START)	/* Unipro Module 1 */
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/dma-44xx.h b/arch/arm/plat-omap/include/plat/dma-44xx.h
new file mode 100644
index 0000000..f4f7d15
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/dma-44xx.h
@@ -0,0 +1,145 @@
+/*
+ * OMAP4 SDMA channel definitions
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Santosh Shilimkar (santosh.shilimkar at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
+#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
+
+#define OMAP44XX_DMA_SYS_REQ0			2	/* External DMA request 0 (system expansion) */
+#define OMAP44XX_DMA_SYS_REQ1			3	/* External DMA request 1 (system expansion) */
+#define OMAP44XX_DMA_GPMC			4	/* GPMC request from prefetch engine */
+#define OMAP44XX_DMA_DSS_DISPC_REQ		6	/* The line trigger signal to synchronize a memory to memory logical channel in the DMA4 (system DMA) is generated by the Display Controller IP. */
+#define OMAP44XX_DMA_SYS_REQ2			7	/* External DMA request 2 (system expansion) */
+#define OMAP44XX_DMA_MCASP1_AXEVT		8	/* McASP module 1 (Audio BE) - Data transmit DMA request line */
+#define OMAP44XX_DMA_ISS_REQ1			9	/* ISS DMA request 1 */
+#define OMAP44XX_DMA_ISS_REQ2			10	/* ISS DMA request 2 */
+#define OMAP44XX_DMA_MCASP1_AREVT		11	/* McASP module 1 (Audio BE) - Data receive DMA request line */
+#define OMAP44XX_DMA_ISS_REQ3			12	/* ISS DMA request 3 */
+#define OMAP44XX_DMA_ISS_REQ4			13	/* ISS DMA request 4 */
+#define OMAP44XX_DMA_DSS_RFBI_REQ		14	/* DSS RFBI DMA request */
+#define OMAP44XX_DMA_SPI3_TX0			15	/* McSPI module 3 - transmit request channel 0 */
+#define OMAP44XX_DMA_SPI3_RX0			16	/* McSPI module 3 - receive request channel 0 */
+#define OMAP44XX_DMA_MCBSP2_TX			17	/* MCBSP module 2 - transmit request (audio BE) */
+#define OMAP44XX_DMA_MCBSP2_RX			18	/* MCBSP module 2 - receive request (audio BE) */
+#define OMAP44XX_DMA_MCBSP3_TX			19	/* MCBSP module 3 - transmit request (Audio BE) */
+#define OMAP44XX_DMA_MCBSP3_RX			20	/* MCBSP module 3 - receive request (Audio BE) */
+#define OMAP44XX_DMA_C2C_SSCM_GPO0		21	/* Chip2Chip GPO line 0 (C2C_Sscm_Gpo[0]) */
+#define OMAP44XX_DMA_C2C_SSCM_GPO1		22	/* Chip2Chip GPO line 1 (C2C_Sscm_Gpo[1]) */
+#define OMAP44XX_DMA_SPI3_TX1			23	/* McSPI module 3 - transmit request channel 1 */
+#define OMAP44XX_DMA_SPI3_RX1			24	/* McSPI module 3 - receive request channel 1 */
+#define OMAP44XX_DMA_I2C3_TX			25	/* I2C module 3 - transmit request */
+#define OMAP44XX_DMA_I2C3_RX			26	/* I2C module 3 - receive request */
+#define OMAP44XX_DMA_I2C1_TX			27	/* I2C module 1 - transmit request */
+#define OMAP44XX_DMA_I2C1_RX			28	/* I2C module 1 - receive request */
+#define OMAP44XX_DMA_I2C2_TX			29	/* I2C module 2 - transmit request */
+#define OMAP44XX_DMA_I2C2_RX			30	/* I2C module 2 - receive request */
+#define OMAP44XX_DMA_MCBSP4_TX			31	/* MCBSP module 4 - transmit request */
+#define OMAP44XX_DMA_MCBSP4_RX			32	/* MCBSP module 4 - receive request */
+#define OMAP44XX_DMA_MCBSP1_TX			33	/* MCBSP module 1 - transmit request (Audio BE) */
+#define OMAP44XX_DMA_MCBSP1_RX			34	/* MCBSP module 1 - receive request (Audio BE) */
+#define OMAP44XX_DMA_SPI1_TX0			35	/* McSPI module 1 - transmit request channel 0 */
+#define OMAP44XX_DMA_SPI1_RX0			36	/* McSPI module 1 - receive request channel 0 */
+#define OMAP44XX_DMA_SPI1_TX1			37	/* McSPI module 1 - transmit request channel 1 */
+#define OMAP44XX_DMA_SPI1_RX1			38	/* McSPI module 1 - receive request channel 1 */
+#define OMAP44XX_DMA_SPI1_TX2			39	/* McSPI module 1 - transmit request channel 2 */
+#define OMAP44XX_DMA_SPI1_RX2			40	/* McSPI module 1 - receive request channel 2 */
+#define OMAP44XX_DMA_SPI1_TX3			41	/* McSPI module 1 - transmit request channel 3 */
+#define OMAP44XX_DMA_SPI1_RX3			42	/* McSPI module 1 - receive request channel 3 */
+#define OMAP44XX_DMA_SPI2_TX0			43	/* McSPI module 2 - transmit request channel 0 */
+#define OMAP44XX_DMA_SPI2_RX0			44	/* McSPI module 2 - receive request channel 0 */
+#define OMAP44XX_DMA_SPI2_TX1			45	/* McSPI module 2 - transmit request channel 1 */
+#define OMAP44XX_DMA_SPI2_RX1			46	/* McSPI module 2 - receive request channel 1 */
+#define OMAP44XX_DMA_MMC2_TX			47	/* MMC/SD2 transmit request */
+#define OMAP44XX_DMA_MMC2_RX			48	/* MMC/SD2 receive request */
+#define OMAP44XX_DMA_UART1_TX			49	/* UART module 1 - transmit request */
+#define OMAP44XX_DMA_UART1_RX			50	/* UART module 1 - receive request */
+#define OMAP44XX_DMA_UART2_TX			51	/* UART module 2 - transmit request */
+#define OMAP44XX_DMA_UART2_RX			52	/* UART module 2 - receive request */
+#define OMAP44XX_DMA_UART3_TX			53	/* UART module 3 - transmit request (Also infrared) */
+#define OMAP44XX_DMA_UART3_RX			54	/* UART module 3 - receive request (Also infrared) */
+#define OMAP44XX_DMA_UART4_TX			55	/* UART module 4  transmit request */
+#define OMAP44XX_DMA_UART4_RX			56	/* UART module 4  receive request */
+#define OMAP44XX_DMA_MMC4_TX			57	/* MMC/SD4 transmit request */
+#define OMAP44XX_DMA_MMC4_RX			58	/* MMC/SD4 receive request */
+#define OMAP44XX_DMA_MMC5_TX			59	/* MMC/SD5 transmit request */
+#define OMAP44XX_DMA_MMC5_RX			60	/* MMC/SD5 receive request */
+#define OMAP44XX_DMA_MMC1_TX			61	/* MMC/SD1 transmit request */
+#define OMAP44XX_DMA_MMC1_RX			62	/* MMC/SD1 receive request */
+#define OMAP44XX_DMA_SYS_REQ3			64	/* External DMA request 3 (system expansion) */
+#define OMAP44XX_DMA_MCPDM_UP			65	/* McPDM Uplink DMA request */
+#define OMAP44XX_DMA_MCPDM_DL			66	/* McPDM DownlinkDMA request */
+#define OMAP44XX_DMA_DMIC_REQ			67	/* DMIC DMA request */
+#define OMAP44XX_DMA_C2C_SSCM_GPO2		68	/* Chip2Chip GPO line 2 (C2C_Sscm_Gpo[2]) */
+#define OMAP44XX_DMA_C2C_SSCM_GPO3		69	/* Chip2Chip GPO line 3 (C2C_Sscm_Gpo[3]) */
+#define OMAP44XX_DMA_SPI4_TX0			70	/* McSPI module 4 - transmit request channel 0 */
+#define OMAP44XX_DMA_SPI4_RX0			71	/* McSPI module 4 - receive request channel 0 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ0		72	/* Display subsystem DSI1 DMA request 0 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ1		73	/* Display subsystem DSI1 DMA request 1 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ2		74	/* Display subsystem DSI1 DMA request 2 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ3		75	/* Display subsystem DSI1 DMA request 3 */
+#define OMAP44XX_DMA_DSS_HDMI_REQ		76	/* Display subsystem HDMI Audio DMA request */
+#define OMAP44XX_DMA_MMC3_TX			77	/* MMC/SD3 transmit request */
+#define OMAP44XX_DMA_MMC3_RX			78	/* MMC/SD3 receive request */
+#define OMAP44XX_DMA_USIM_TX			79	/* USIM transmit request */
+#define OMAP44XX_DMA_USIM_RX			80	/* USIM receive request */
+#define OMAP44XX_DMA_DSS_DSI2_REQ0		81	/* Display subsystem DSI2 DMA request 0 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ1		82	/* Display subsystem DSI2 DMA request 1 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ2		83	/* Display subsystem DSI2 DMA request 2 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ3		84	/* Display subsystem DSI2 DMA request 3 */
+#define OMAP44XX_DMA_SLIMBUS1_TX0		85	/* SLIMbus module 1  transmit request channel 0 */
+#define OMAP44XX_DMA_SLIMBUS1_TX1		86	/* SLIMbus module 1  transmit request channel 1 */
+#define OMAP44XX_DMA_SLIMBUS1_TX2		87	/* SLIMbus module 1  transmit request channel 2 */
+#define OMAP44XX_DMA_SLIMBUS1_TX3		88	/* SLIMbus module 1  transmit request channel 3 */
+#define OMAP44XX_DMA_SLIMBUS1_RX0		89	/* SLIMbus module 1  receive request channel 0 */
+#define OMAP44XX_DMA_SLIMBUS1_RX1		90	/* SLIMbus module 1  receive request channel 1 */
+#define OMAP44XX_DMA_SLIMBUS1_RX2		91	/* SLIMbus module 1  receive request channel 2 */
+#define OMAP44XX_DMA_SLIMBUS1_RX3		92	/* SLIMbus module 1  receive request channel 3 */
+#define OMAP44XX_DMA_SLIMBUS2_TX0		93	/* SLIMbus module 2  transmit request channel 0 */
+#define OMAP44XX_DMA_SLIMBUS2_TX1		94	/* SLIMbus module 2  transmit request channel 1 */
+#define OMAP44XX_DMA_SLIMBUS2_TX2		95	/* SLIMbus module 2  transmit request channel 2 */
+#define OMAP44XX_DMA_SLIMBUS2_TX3		96	/* SLIMbus module 2  transmit request channel 3 */
+#define OMAP44XX_DMA_SLIMBUS2_RX0		97	/* SLIMbus module 2  receive request channel 0 */
+#define OMAP44XX_DMA_SLIMBUS2_RX1		98	/* SLIMbus module 2  receive request channel 1 */
+#define OMAP44XX_DMA_SLIMBUS2_RX2		99	/* SLIMbus module 2  receive request channel 2 */
+#define OMAP44XX_DMA_SLIMBUS2_RX3		100	/* SLIMbus module 2  receive request channel 3 */
+#define OMAP44XX_DMA_ABE_REQ_0			101	/* Audio Back-End module  request FIFO 0 */
+#define OMAP44XX_DMA_ABE_REQ_1			102	/* Audio Back-End module  request FIFO 1 */
+#define OMAP44XX_DMA_ABE_REQ_2			103	/* Audio Back-End module  request FIFO 2 */
+#define OMAP44XX_DMA_ABE_REQ_3			104	/* Audio Back-End module  request FIFO 3 */
+#define OMAP44XX_DMA_ABE_REQ_4			105	/* Audio Back-End module  request FIFO 4 */
+#define OMAP44XX_DMA_ABE_REQ_5			106	/* Audio Back-End module  request FIFO 5 */
+#define OMAP44XX_DMA_ABE_REQ_6			107	/* Audio Back-End module  request FIFO 6 */
+#define OMAP44XX_DMA_ABE_REQ_7			108	/* Audio Back-End module  request FIFO 7 */
+#define OMAP44XX_DMA_AES1_P_CTX_IN_REQ		109	/* AES Module 1: Request a new context on the public HIB */
+#define OMAP44XX_DMA_AES1_P_DATA_IN_REQ		110	/* AES Module 1: Request input data on the public HIB */
+#define OMAP44XX_DMA_AES1_P_DATA_OUT_REQ	111	/* AES Module 1: Request output data read on the public HIB */
+#define OMAP44XX_DMA_AES2_P_CTX_IN_REQ		112	/* AES Module 2: Request a new context on the  public HIB */
+#define OMAP44XX_DMA_AES2_P_DATA_IN_REQ		113	/* AES Module 2: Request input data on the public HIB */
+#define OMAP44XX_DMA_AES2_P_DATA_OUT_REQ	114	/* AES Module 2: Request output data read on the public HIB */
+#define OMAP44XX_DMA_DES_P_CTX_IN_REQ		115	/* DES Module: Request a new context on the public HIB */
+#define OMAP44XX_DMA_DES_P_DATA_IN_REQ		116	/* DES Module: Request input data on the public HIB */
+#define OMAP44XX_DMA_DES_P_DATA_OUT_REQ		117	/* DES Module: Request output data read on the public HIB */
+#define OMAP44XX_DMA_SHA2_CTXIN_P		118	/* SHA2MD5 Module 1: Request a context on public HIB */
+#define OMAP44XX_DMA_SHA2_DIN_P			119	/* SHA2MD5 Module 1: Request input data on public HIB */
+#define OMAP44XX_DMA_SHA2_CTXOUT_P		120	/* SHA2MD5 Module 1: Request output data/context on public HIB */
+#define OMAP44XX_DMA_AES1_P_CONTEXT_OUT_REQ	121	/* AES Module 1: Request the authentication result (TAG) or result IV read on public HIB */
+#define OMAP44XX_DMA_AES2_P_CONTEXT_OUT_REQ	122	/* AES Module 2: Request the authentication result (TAG) or result IV read on  public HIB */
+#define OMAP44XX_DMA_I2C4_TX			124	/* I2C module 4 - transmit request */
+#define OMAP44XX_DMA_I2C4_RX			125	/* I2C module 4 - receive request */
+
+#endif
-- 
1.6.0.4

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 8/9] omap4: Use dma line defines from dma-44xx.h
  2010-02-18  8:59           ` [PATCH 7/9] omap4: Add auto-generated irq and dma headers Santosh Shilimkar
@ 2010-02-18  8:59             ` Santosh Shilimkar
  2010-02-18  8:59               ` [PATCH 9/9] omap4: Use irq line defines from irq-44xx.h Santosh Shilimkar
  2010-02-22 22:13               ` [PATCH 8/9] omap4: Use dma line defines from dma-44xx.h Tony Lindgren
  2010-02-18 17:23             ` [PATCH 7/9] omap4: Add auto-generated irq and dma headers Paul Walmsley
  1 sibling, 2 replies; 25+ messages in thread
From: Santosh Shilimkar @ 2010-02-18  8:59 UTC (permalink / raw)
  To: linux-arm-kernel

This patch removes all the omap4 specific dma request
lines defines from plat/dma.h and includes dma-44xx.h

The defines are aligned so no driver should be impacted
because of this change.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/plat-omap/include/plat/dma.h |   86 +-------------------------------
 1 files changed, 3 insertions(+), 83 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 4ede9e1..02232ca 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -21,6 +21,9 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
 
+/* Move omap4 specific defines to dma-44xx.h */
+#include "dma-44xx.h"
+
 /* Hardware registers for omap1 */
 #define OMAP1_DMA_BASE			(0xfffed800)
 
@@ -316,89 +319,6 @@
 #define OMAP34XX_DMA_USIM_TX		79	/* S_DMA_78 */
 #define OMAP34XX_DMA_USIM_RX		80	/* S_DMA_79 */
 
-/* DMA request lines for 44xx */
-#define OMAP44XX_DMA_DSS_DISPC_REQ	6	/* S_DMA_5 */
-#define OMAP44XX_DMA_SYS_REQ2		7	/* S_DMA_6 */
-#define OMAP44XX_DMA_ISS_REQ1		9	/* S_DMA_8 */
-#define OMAP44XX_DMA_ISS_REQ2		10	/* S_DMA_9 */
-#define OMAP44XX_DMA_ISS_REQ3		12	/* S_DMA_11 */
-#define OMAP44XX_DMA_ISS_REQ4		13	/* S_DMA_12 */
-#define OMAP44XX_DMA_DSS_RFBI_REQ	14	/* S_DMA_13 */
-#define OMAP44XX_DMA_SPI3_TX0		15	/* S_DMA_14 */
-#define OMAP44XX_DMA_SPI3_RX0		16	/* S_DMA_15 */
-#define OMAP44XX_DMA_MCBSP2_TX		17	/* S_DMA_16 */
-#define OMAP44XX_DMA_MCBSP2_RX		18	/* S_DMA_17 */
-#define OMAP44XX_DMA_MCBSP3_TX		19	/* S_DMA_18 */
-#define OMAP44XX_DMA_MCBSP3_RX		20	/* S_DMA_19 */
-#define OMAP44XX_DMA_SPI3_TX1		23	/* S_DMA_22 */
-#define OMAP44XX_DMA_SPI3_RX1		24	/* S_DMA_23 */
-#define OMAP44XX_DMA_I2C3_TX		25	/* S_DMA_24 */
-#define OMAP44XX_DMA_I2C3_RX		26	/* S_DMA_25 */
-#define OMAP44XX_DMA_I2C1_TX		27	/* S_DMA_26 */
-#define OMAP44XX_DMA_I2C1_RX		28	/* S_DMA_27 */
-#define OMAP44XX_DMA_I2C2_TX		29	/* S_DMA_28 */
-#define OMAP44XX_DMA_I2C2_RX		30	/* S_DMA_29 */
-#define OMAP44XX_DMA_MCBSP4_TX		31	/* S_DMA_30 */
-#define OMAP44XX_DMA_MCBSP4_RX		32	/* S_DMA_31 */
-#define OMAP44XX_DMA_MCBSP1_TX		33	/* S_DMA_32 */
-#define OMAP44XX_DMA_MCBSP1_RX		34	/* S_DMA_33 */
-#define OMAP44XX_DMA_SPI1_TX0		35	/* S_DMA_34 */
-#define OMAP44XX_DMA_SPI1_RX0		36	/* S_DMA_35 */
-#define OMAP44XX_DMA_SPI1_TX1		37	/* S_DMA_36 */
-#define OMAP44XX_DMA_SPI1_RX1		38	/* S_DMA_37 */
-#define OMAP44XX_DMA_SPI1_TX2		39	/* S_DMA_38 */
-#define OMAP44XX_DMA_SPI1_RX2		40	/* S_DMA_39 */
-#define OMAP44XX_DMA_SPI1_TX3		41	/* S_DMA_40 */
-#define OMAP44XX_DMA_SPI1_RX3		42	/* S_DMA_41 */
-#define OMAP44XX_DMA_SPI2_TX0		43	/* S_DMA_42 */
-#define OMAP44XX_DMA_SPI2_RX0		44	/* S_DMA_43 */
-#define OMAP44XX_DMA_SPI2_TX1		45	/* S_DMA_44 */
-#define OMAP44XX_DMA_SPI2_RX1		46	/* S_DMA_45 */
-#define OMAP44XX_DMA_MMC2_TX		47	/* S_DMA_46 */
-#define OMAP44XX_DMA_MMC2_RX		48	/* S_DMA_47 */
-#define OMAP44XX_DMA_UART1_TX		49	/* S_DMA_48 */
-#define OMAP44XX_DMA_UART1_RX		50	/* S_DMA_49 */
-#define OMAP44XX_DMA_UART2_TX		51	/* S_DMA_50 */
-#define OMAP44XX_DMA_UART2_RX		52	/* S_DMA_51 */
-#define OMAP44XX_DMA_UART3_TX		53	/* S_DMA_52 */
-#define OMAP44XX_DMA_UART3_RX		54	/* S_DMA_53 */
-#define OMAP44XX_DMA_UART4_TX		55	/* S_DMA_54 */
-#define OMAP44XX_DMA_UART4_RX		56	/* S_DMA_55 */
-#define OMAP44XX_DMA_MMC4_TX		57	/* S_DMA_56 */
-#define OMAP44XX_DMA_MMC4_RX		58	/* S_DMA_57 */
-#define OMAP44XX_DMA_MMC5_TX		59	/* S_DMA_58 */
-#define OMAP44XX_DMA_MMC5_RX		60	/* S_DMA_59 */
-#define OMAP44XX_DMA_MMC1_TX		61	/* S_DMA_60 */
-#define OMAP44XX_DMA_MMC1_RX		62	/* S_DMA_61 */
-#define OMAP44XX_DMA_SYS_REQ3		64	/* S_DMA_63 */
-#define OMAP44XX_DMA_MCPDM_UP		65	/* S_DMA_64 */
-#define OMAP44XX_DMA_MCPDM_DL		66	/* S_DMA_65 */
-#define OMAP44XX_DMA_SPI4_TX0		70	/* S_DMA_69 */
-#define OMAP44XX_DMA_SPI4_RX0		71	/* S_DMA_70 */
-#define OMAP44XX_DMA_DSS_DSI1_REQ0	72	/* S_DMA_71 */
-#define OMAP44XX_DMA_DSS_DSI1_REQ1	73	/* S_DMA_72 */
-#define OMAP44XX_DMA_DSS_DSI1_REQ2	74	/* S_DMA_73 */
-#define OMAP44XX_DMA_DSS_DSI1_REQ3	75	/* S_DMA_74 */
-#define OMAP44XX_DMA_DSS_HDMI_REQ	76	/* S_DMA_75 */
-#define OMAP44XX_DMA_MMC3_TX		77	/* S_DMA_76 */
-#define OMAP44XX_DMA_MMC3_RX		78	/* S_DMA_77 */
-#define OMAP44XX_DMA_USIM_TX		79	/* S_DMA_78 */
-#define OMAP44XX_DMA_USIM_RX		80	/* S_DMA_79 */
-#define OMAP44XX_DMA_DSS_DSI2_REQ0	81	/* S_DMA_80 */
-#define OMAP44XX_DMA_DSS_DSI2_REQ1	82	/* S_DMA_81 */
-#define OMAP44XX_DMA_DSS_DSI2_REQ2	83	/* S_DMA_82 */
-#define OMAP44XX_DMA_DSS_DSI2_REQ3	84	/* S_DMA_83 */
-#define OMAP44XX_DMA_ABE_REQ0		101	/* S_DMA_100 */
-#define OMAP44XX_DMA_ABE_REQ1		102	/* S_DMA_101 */
-#define OMAP44XX_DMA_ABE_REQ2		103	/* S_DMA_102 */
-#define OMAP44XX_DMA_ABE_REQ3		104	/* S_DMA_103 */
-#define OMAP44XX_DMA_ABE_REQ4		105	/* S_DMA_104 */
-#define OMAP44XX_DMA_ABE_REQ5		106	/* S_DMA_105 */
-#define OMAP44XX_DMA_ABE_REQ6		107	/* S_DMA_106 */
-#define OMAP44XX_DMA_ABE_REQ7		108	/* S_DMA_107 */
-#define OMAP44XX_DMA_I2C4_TX		124	/* S_DMA_123 */
-#define OMAP44XX_DMA_I2C4_RX		125	/* S_DMA_124 */
-
 /*----------------------------------------------------------------------------*/
 
 #define OMAP1_DMA_TOUT_IRQ		(1 << 0)
-- 
1.6.0.4

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 9/9] omap4: Use irq line defines from irq-44xx.h
  2010-02-18  8:59             ` [PATCH 8/9] omap4: Use dma line defines from dma-44xx.h Santosh Shilimkar
@ 2010-02-18  8:59               ` Santosh Shilimkar
  2010-02-22 22:13               ` [PATCH 8/9] omap4: Use dma line defines from dma-44xx.h Tony Lindgren
  1 sibling, 0 replies; 25+ messages in thread
From: Santosh Shilimkar @ 2010-02-18  8:59 UTC (permalink / raw)
  To: linux-arm-kernel

This patch removes all the omap4 specific irq line
defines from plat/irqs.h and includes auto-generated
irqs-44xx.h
All the legacy naming style defines are replaced with the one
from irqs-44xx.h

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/devices.c           |    8 ++--
 arch/arm/mach-omap2/include/mach/irqs.h |    1 +
 arch/arm/mach-omap2/timer-mpu.c         |    2 +-
 arch/arm/plat-omap/devices.c            |    4 +-
 arch/arm/plat-omap/dma.c                |    2 +-
 arch/arm/plat-omap/dmtimer.c            |   24 ++++----
 arch/arm/plat-omap/gpio.c               |   12 ++--
 arch/arm/plat-omap/include/plat/irqs.h  |   89 -------------------------------
 8 files changed, 27 insertions(+), 115 deletions(-)

diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index c104d5c..23e4d77 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -191,7 +191,7 @@ static struct resource omap4_mbox_resources[] = {
 		.flags          = IORESOURCE_MEM,
 	},
 	{
-		.start          = INT_44XX_MAIL_U0_MPU,
+		.start          = OMAP44XX_IRQ_MAIL_U0,
 		.flags          = IORESOURCE_IRQ,
 	},
 };
@@ -720,13 +720,13 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
 			if (!cpu_is_omap44xx())
 				return;
 			base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
-			irq = INT_44XX_MMC4_IRQ;
+			irq = OMAP44XX_IRQ_MMC4;
 			break;
 		case 4:
 			if (!cpu_is_omap44xx())
 				return;
 			base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
-			irq = INT_44XX_MMC5_IRQ;
+			irq = OMAP44XX_IRQ_MMC4;
 			break;
 		default:
 			continue;
@@ -738,7 +738,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
 		} else if (cpu_is_omap44xx()) {
 			if (i < 3) {
 				base += OMAP4_MMC_REG_OFFSET;
-				irq += IRQ_GIC_START;
+				irq += OMAP44XX_IRQ_GIC_START;
 			}
 			size = OMAP4_HSMMC_SIZE;
 			name = "mmci-omap-hs";
diff --git a/arch/arm/mach-omap2/include/mach/irqs.h b/arch/arm/mach-omap2/include/mach/irqs.h
index 44dab77..573d03e 100644
--- a/arch/arm/mach-omap2/include/mach/irqs.h
+++ b/arch/arm/mach-omap2/include/mach/irqs.h
@@ -3,3 +3,4 @@
  */
 
 #include <plat/irqs.h>
+#include "irqs-44xx.h"
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
index c1a650a..954682e 100644
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -28,7 +28,7 @@
  */
 void __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
-	evt->irq = INT_44XX_LOCALTIMER_IRQ;
+	evt->irq = OMAP44XX_IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
 }
 
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 3a3e357..4a4cd87 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -205,8 +205,8 @@ static struct resource mcpdm_resources[] = {
 	},
 	{
 		.name		= "mcpdm_irq",
-		.start		= INT_44XX_MCPDM_IRQ,
-		.end		= INT_44XX_MCPDM_IRQ,
+		.start		= OMAP44XX_IRQ_MCPDM,
+		.end		= OMAP44XX_IRQ_MCPDM,
 		.flags		= IORESOURCE_IRQ,
 	},
 };
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 049165c..2ab224c 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2132,7 +2132,7 @@ static int __init omap_init_dma(void)
 	if (cpu_class_is_omap2()) {
 		int irq;
 		if (cpu_is_omap44xx())
-			irq = INT_44XX_SDMA_IRQ0;
+			irq = OMAP44XX_IRQ_SDMA_0;
 		else
 			irq = INT_24XX_SDMA_IRQ0;
 		setup_irq(irq, &omap24xx_dma_irq);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 24bf692..4d99dfb 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -250,18 +250,18 @@ static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
 
 #ifdef CONFIG_ARCH_OMAP4
 static struct omap_dm_timer omap4_dm_timers[] = {
-	{ .phys_base = 0x4a318000, .irq = INT_44XX_GPTIMER1 },
-	{ .phys_base = 0x48032000, .irq = INT_44XX_GPTIMER2 },
-	{ .phys_base = 0x48034000, .irq = INT_44XX_GPTIMER3 },
-	{ .phys_base = 0x48036000, .irq = INT_44XX_GPTIMER4 },
-	{ .phys_base = 0x40138000, .irq = INT_44XX_GPTIMER5 },
-	{ .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER6 },
-	{ .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER7 },
-	{ .phys_base = 0x4013e000, .irq = INT_44XX_GPTIMER8 },
-	{ .phys_base = 0x4803e000, .irq = INT_44XX_GPTIMER9 },
-	{ .phys_base = 0x48086000, .irq = INT_44XX_GPTIMER10 },
-	{ .phys_base = 0x48088000, .irq = INT_44XX_GPTIMER11 },
-	{ .phys_base = 0x4a320000, .irq = INT_44XX_GPTIMER12 },
+	{ .phys_base = 0x4a318000, .irq = OMAP44XX_IRQ_GPT1 },
+	{ .phys_base = 0x48032000, .irq = OMAP44XX_IRQ_GPT2 },
+	{ .phys_base = 0x48034000, .irq = OMAP44XX_IRQ_GPT3 },
+	{ .phys_base = 0x48036000, .irq = OMAP44XX_IRQ_GPT4 },
+	{ .phys_base = 0x40138000, .irq = OMAP44XX_IRQ_GPT5 },
+	{ .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT6 },
+	{ .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT7 },
+	{ .phys_base = 0x4013e000, .irq = OMAP44XX_IRQ_GPT8 },
+	{ .phys_base = 0x4803e000, .irq = OMAP44XX_IRQ_GPT9 },
+	{ .phys_base = 0x48086000, .irq = OMAP44XX_IRQ_GPT10 },
+	{ .phys_base = 0x48088000, .irq = OMAP44XX_IRQ_GPT11 },
+	{ .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 },
 };
 static const char *omap4_dm_source_names[] __initdata = {
 	"sys_ck",
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 6055028..337199e 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -312,17 +312,17 @@ static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
 
 #ifdef CONFIG_ARCH_OMAP4
 static struct gpio_bank gpio_bank_44xx[6] = {
-	{ OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,
+	{ OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
 		METHOD_GPIO_44XX },
-	{ OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,
+	{ OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
 		METHOD_GPIO_44XX },
-	{ OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,
+	{ OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
 		METHOD_GPIO_44XX },
-	{ OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,
+	{ OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
 		METHOD_GPIO_44XX },
-	{ OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128,
+	{ OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
 		METHOD_GPIO_44XX },
-	{ OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160,
+	{ OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
 		METHOD_GPIO_44XX },
 };
 
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index e8205c1..be470bd 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -355,95 +355,6 @@
 #define INT_35XX_CCDC_VD1_IRQ		92
 #define INT_35XX_CCDC_VD2_IRQ		93
 
-#define IRQ_GIC_START		32
-#define INT_44XX_LOCALTIMER_IRQ	29
-#define INT_44XX_LOCALWDT_IRQ	30
-
-#define INT_44XX_BENCH_MPU_EMUL	(3 + IRQ_GIC_START)
-#define INT_44XX_SSM_ABORT_IRQ	(6 + IRQ_GIC_START)
-#define INT_44XX_SYS_NIRQ	(7 + IRQ_GIC_START)
-#define INT_44XX_D2D_FW_IRQ	(8 + IRQ_GIC_START)
-#define INT_44XX_PRCM_MPU_IRQ	(11 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ0	(12 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ1	(13 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ2	(14 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ3	(15 + IRQ_GIC_START)
-#define INT_44XX_ISS_IRQ	(24 + IRQ_GIC_START)
-#define INT_44XX_DSS_IRQ	(25 + IRQ_GIC_START)
-#define INT_44XX_MAIL_U0_MPU	(26 + IRQ_GIC_START)
-#define INT_44XX_DSP_MMU	(28 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER1	(37 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER2	(38 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER3	(39 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER4	(40 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER5	(41 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER6	(42 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER7	(43 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER8	(44 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER9	(45 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER10	(46 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER11	(47 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER12	(95 + IRQ_GIC_START)
-#define INT_44XX_SHA1MD5	(51 + IRQ_GIC_START)
-#define INT_44XX_I2C1_IRQ	(56 + IRQ_GIC_START)
-#define INT_44XX_I2C2_IRQ	(57 + IRQ_GIC_START)
-#define INT_44XX_HDQ_IRQ	(58 + IRQ_GIC_START)
-#define INT_44XX_SPI1_IRQ	(65 + IRQ_GIC_START)
-#define INT_44XX_SPI2_IRQ	(66 + IRQ_GIC_START)
-#define INT_44XX_HSI_1_IRQ0	(67 + IRQ_GIC_START)
-#define INT_44XX_HSI_2_IRQ1	(68 + IRQ_GIC_START)
-#define INT_44XX_HSI_1_DMAIRQ	(71 + IRQ_GIC_START)
-#define INT_44XX_UART1_IRQ	(72 + IRQ_GIC_START)
-#define INT_44XX_UART2_IRQ	(73 + IRQ_GIC_START)
-#define INT_44XX_UART3_IRQ	(74 + IRQ_GIC_START)
-#define INT_44XX_UART4_IRQ	(70 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_NISO	(76 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_ISO	(77 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_HGEN	(78 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_HSOF	(79 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_OTG	(80 + IRQ_GIC_START)
-#define INT_44XX_MCBSP4_IRQ_TX	(81 + IRQ_GIC_START)
-#define INT_44XX_MCBSP4_IRQ_RX	(82 + IRQ_GIC_START)
-#define INT_44XX_MMC_IRQ	(83 + IRQ_GIC_START)
-#define INT_44XX_MMC2_IRQ	(86 + IRQ_GIC_START)
-#define INT_44XX_MCBSP2_IRQ_TX	(89 + IRQ_GIC_START)
-#define INT_44XX_MCBSP2_IRQ_RX	(90 + IRQ_GIC_START)
-#define INT_44XX_SPI3_IRQ	(91 + IRQ_GIC_START)
-#define INT_44XX_SPI5_IRQ	(69 + IRQ_GIC_START)
-
-#define INT_44XX_MCBSP5_IRQ	(16 + IRQ_GIC_START)
-#define INT_44xX_MCBSP1_IRQ	(17 + IRQ_GIC_START)
-#define INT_44XX_MCBSP2_IRQ	(22 + IRQ_GIC_START)
-#define INT_44XX_MCBSP3_IRQ	(23 + IRQ_GIC_START)
-#define INT_44XX_MCBSP4_IRQ	(27 + IRQ_GIC_START)
-#define INT_44XX_HS_USB_MC	(92 + IRQ_GIC_START)
-#define INT_44XX_HS_USB_DMA	(93 + IRQ_GIC_START)
-
-#define INT_44XX_GPIO_BANK1	(29 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK2	(30 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK3	(31 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK4	(32 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK5	(33 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK6	(34 + IRQ_GIC_START)
-#define INT_44XX_USIM_IRQ	(35 + IRQ_GIC_START)
-#define INT_44XX_WDT3_IRQ	(36 + IRQ_GIC_START)
-#define INT_44XX_SPI4_IRQ	(48 + IRQ_GIC_START)
-#define INT_44XX_SHA1MD52_IRQ	(49 + IRQ_GIC_START)
-#define INT_44XX_FPKA_READY_IRQ	(50 + IRQ_GIC_START)
-#define INT_44XX_SHA1MD51_IRQ	(51 + IRQ_GIC_START)
-#define INT_44XX_RNG_IRQ	(52 + IRQ_GIC_START)
-#define INT_44XX_MMC5_IRQ	(59 + IRQ_GIC_START)
-#define INT_44XX_I2C3_IRQ	(61 + IRQ_GIC_START)
-#define INT_44XX_FPKA_ERROR_IRQ	(64 + IRQ_GIC_START)
-#define INT_44XX_PBIAS_IRQ	(75 + IRQ_GIC_START)
-#define INT_44XX_OHCI_IRQ	(76 + IRQ_GIC_START)
-#define INT_44XX_EHCI_IRQ	(77 + IRQ_GIC_START)
-#define INT_44XX_TLL_IRQ	(78 + IRQ_GIC_START)
-#define INT_44XX_PARTHASH_IRQ	(79 + IRQ_GIC_START)
-#define INT_44XX_MMC3_IRQ	(94 + IRQ_GIC_START)
-#define INT_44XX_MMC4_IRQ	(96 + IRQ_GIC_START)
-#define INT_44XX_MCPDM_IRQ	(112 + IRQ_GIC_START)
-
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
  * 16 MPUIO lines */
 #define OMAP_MAX_GPIO_LINES	192
-- 
1.6.0.4

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 7/9] omap4: Add auto-generated irq and dma headers
  2010-02-18  8:59           ` [PATCH 7/9] omap4: Add auto-generated irq and dma headers Santosh Shilimkar
  2010-02-18  8:59             ` [PATCH 8/9] omap4: Use dma line defines from dma-44xx.h Santosh Shilimkar
@ 2010-02-18 17:23             ` Paul Walmsley
  2010-02-18 17:33               ` Shilimkar, Santosh
  2010-02-19  5:10               ` Shilimkar, Santosh
  1 sibling, 2 replies; 25+ messages in thread
From: Paul Walmsley @ 2010-02-18 17:23 UTC (permalink / raw)
  To: linux-arm-kernel

Hello Santosh,

thanks for sending these in.  One minor comment:

On Thu, 18 Feb 2010, Santosh Shilimkar wrote:

> These files are generated along with the HWMOD and will eventually be
> in the existing header files as soon as all drivers will be migrate to
> omap_hwmod / omap_device.
> 
> The dma-44xx.h file should be in 'arch/arm/mach-omap2/include/mach/',
> but this would need dma.h header also present in the mach directory to
> make local include possible, like what is done for irq.h. Then the
> script is needed to modify the drivers to include 'mach/dma.h' instead
> of 'plat/dma.h'. This would be a bigger change and hence left out for now

I think I originally wrote the DMA generator script, so please add a Nokia 
copyright and put my name in there also.  After that point, it has my ack.


- Paul

> 
> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  arch/arm/mach-omap2/include/mach/irqs-44xx.h |  144 +++++++++++++++++++++++++
>  arch/arm/plat-omap/include/plat/dma-44xx.h   |  145 ++++++++++++++++++++++++++
>  2 files changed, 289 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-omap2/include/mach/irqs-44xx.h
>  create mode 100644 arch/arm/plat-omap/include/plat/dma-44xx.h
> 
> diff --git a/arch/arm/mach-omap2/include/mach/irqs-44xx.h b/arch/arm/mach-omap2/include/mach/irqs-44xx.h
> new file mode 100644
> index 0000000..6dc5887
> --- /dev/null
> +++ b/arch/arm/mach-omap2/include/mach/irqs-44xx.h
> @@ -0,0 +1,144 @@
> +/*
> + * OMAP4 Interrupt lines definitions
> + *
> + * Copyright (C) 2009-2010 Texas Instruments, Inc.
> + *
> + * Santosh Shilimkar (santosh.shilimkar at ti.com)
> + * Benoit Cousson (b-cousson at ti.com)
> + *
> + * This file is automatically generated from the OMAP hardware databases.
> + * We respectfully ask that any modifications to this file be coordinated
> + * with the public linux-omap at vger.kernel.org mailing list and the
> + * authors above to ensure that the autogeneration scripts are kept
> + * up-to-date with the file contents.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
> +#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
> +
> +/* OMAP44XX IRQs numbers definitions */
> +#define OMAP44XX_IRQ_LOCALTIMER			29
> +#define OMAP44XX_IRQ_LOCALWDT			30
> +
> +#define OMAP44XX_IRQ_GIC_START			32
> +
> +#define OMAP44XX_IRQ_PL310			(0 + OMAP44XX_IRQ_GIC_START)	/* Level-2 Cache Controller interrupt */
> +#define OMAP44XX_IRQ_CTI0			(1 + OMAP44XX_IRQ_GIC_START)	/* TRIGOUT[6] of Cross Trigger Interface 0 (CTI0) */
> +#define OMAP44XX_IRQ_CTI1			(2 + OMAP44XX_IRQ_GIC_START)	/* TRIGOUT[6] of Cross Trigger Interface 1 (CTI1) */
> +#define OMAP44XX_IRQ_ELM			(4 + OMAP44XX_IRQ_GIC_START)	/* Error location process completion */
> +#define OMAP44XX_IRQ_SYS_1N			(7 + OMAP44XX_IRQ_GIC_START)	/* External interrupt (active low) */
> +#define OMAP44XX_IRQ_SECURITY_EVENTS		(8 + OMAP44XX_IRQ_GIC_START)	/* Occurs when a firewall (ARTERIS/L4) has generated an out-band error or when power events occurred (including power-on reset, so by default, this interrupt is active after power-up reset). */
> +#define OMAP44XX_IRQ_L3_DBG			(9 + OMAP44XX_IRQ_GIC_START)	/* Reports debug errors on L3 */
> +#define OMAP44XX_IRQ_L3_APP			(10 + OMAP44XX_IRQ_GIC_START)	/* Reports application or non-attributable errors on L3 */
> +#define OMAP44XX_IRQ_PRCM			(11 + OMAP44XX_IRQ_GIC_START)	/* PRCM module */
> +#define OMAP44XX_IRQ_SDMA_0			(12 + OMAP44XX_IRQ_GIC_START)	/* System DMA interrupt request 0 */
> +#define OMAP44XX_IRQ_SDMA_1			(13 + OMAP44XX_IRQ_GIC_START)	/* System DMA interrupt request 1 */
> +#define OMAP44XX_IRQ_SDMA_2			(14 + OMAP44XX_IRQ_GIC_START)	/* System DMA interrupt request 2 */
> +#define OMAP44XX_IRQ_SDMA_3			(15 + OMAP44XX_IRQ_GIC_START)	/* System DMA interrupt request 3 */
> +#define OMAP44XX_IRQ_MCBSP4			(16 + OMAP44XX_IRQ_GIC_START)	/* McBSP 4 / PORCOMMONIRQ : Common Synchronous Interrupt Request line */
> +#define OMAP44XX_IRQ_MCBSP1			(17 + OMAP44XX_IRQ_GIC_START)	/* McBSP 1 / PORCOMMONIRQ : Common Synchronous Interrupt Request line */
> +#define OMAP44XX_IRQ_SR_MCU			(18 + OMAP44XX_IRQ_GIC_START)	/* SmartReflex MCU interrupt request */
> +#define OMAP44XX_IRQ_SR_CORE			(19 + OMAP44XX_IRQ_GIC_START)	/* SmartReflex Core interrupt request */
> +#define OMAP44XX_IRQ_GPMC			(20 + OMAP44XX_IRQ_GIC_START)	/* General purpose memory controller module */
> +#define OMAP44XX_IRQ_GFX			(21 + OMAP44XX_IRQ_GIC_START)	/* 2D/3D graphics module */
> +#define OMAP44XX_IRQ_MCBSP2			(22 + OMAP44XX_IRQ_GIC_START)	/* McBSP 2 / PORCOMMONIRQ : Common Synchronous Interrupt Request line */
> +#define OMAP44XX_IRQ_MCBSP3			(23 + OMAP44XX_IRQ_GIC_START)	/* McBSP 3 / PORCOMMONIRQ : Common Synchronous Interrupt Request line */
> +#define OMAP44XX_IRQ_ISS_5			(24 + OMAP44XX_IRQ_GIC_START)	/* Imaging Sub System interrupt request */
> +#define OMAP44XX_IRQ_DSS_DISPC			(25 + OMAP44XX_IRQ_GIC_START)	/* Display controller interrupt request */
> +#define OMAP44XX_IRQ_MAIL_U0			(26 + OMAP44XX_IRQ_GIC_START)	/* Mailbox user 0 interrupt request */
> +#define OMAP44XX_IRQ_C2C_SSCM_0			(27 + OMAP44XX_IRQ_GIC_START)	/* Chip2Chip Status interrupt */
> +#define OMAP44XX_IRQ_TESLA_MMU			(28 + OMAP44XX_IRQ_GIC_START)	/* Telsa (Mini64) SS MMU interrupt */
> +#define OMAP44XX_IRQ_GPIO1			(29 + OMAP44XX_IRQ_GIC_START)	/* GPIO module 1 interrupt 1 */
> +#define OMAP44XX_IRQ_GPIO2			(30 + OMAP44XX_IRQ_GIC_START)	/* GPIO module 2 interrupt 1 */
> +#define OMAP44XX_IRQ_GPIO3			(31 + OMAP44XX_IRQ_GIC_START)	/* GPIO module 3 interrupt 1 */
> +#define OMAP44XX_IRQ_GPIO4			(32 + OMAP44XX_IRQ_GIC_START)	/* GPIO module 4 interrupt 1 */
> +#define OMAP44XX_IRQ_GPIO5			(33 + OMAP44XX_IRQ_GIC_START)	/* GPIO module 5 interrupt 1 */
> +#define OMAP44XX_IRQ_GPIO6			(34 + OMAP44XX_IRQ_GIC_START)	/* GPIO module 6 interrupt 1 */
> +#define OMAP44XX_IRQ_USIM			(35 + OMAP44XX_IRQ_GIC_START)	/* USIM interrupt */
> +#define OMAP44XX_IRQ_WDT3			(36 + OMAP44XX_IRQ_GIC_START)	/* Watchdog timer module 3 overflow (WDT controlled by Mini64) */
> +#define OMAP44XX_IRQ_GPT1			(37 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 1 (Timer 1ms / Wakeup domain) */
> +#define OMAP44XX_IRQ_GPT2			(38 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 2 (Timer 1ms / Core domain) */
> +#define OMAP44XX_IRQ_GPT3			(39 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 3 */
> +#define OMAP44XX_IRQ_GPT4			(40 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 4 */
> +#define OMAP44XX_IRQ_GPT5			(41 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 5 (Audio BE) */
> +#define OMAP44XX_IRQ_GPT6			(42 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 6 (Audio BE) */
> +#define OMAP44XX_IRQ_GPT7			(43 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 7 (Audio BE) */
> +#define OMAP44XX_IRQ_GPT8			(44 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 8 (Audio BE) */
> +#define OMAP44XX_IRQ_GPT9			(45 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 9 */
> +#define OMAP44XX_IRQ_GPT10			(46 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 10 (Timer 1ms / Core domain) */
> +#define OMAP44XX_IRQ_GPT11			(47 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 11 */
> +#define OMAP44XX_IRQ_SPI4			(48 + OMAP44XX_IRQ_GIC_START)	/* McSPI module 4 */
> +#define OMAP44XX_IRQ_SHA1_S			(49 + OMAP44XX_IRQ_GIC_START)	/* SHA2/MD5 crypto-accelerator 1 combined secure side */
> +#define OMAP44XX_IRQ_FPKA_SINTREQUEST_S		(50 + OMAP44XX_IRQ_GIC_START)	/* PKA crypto-accelerator combined */
> +#define OMAP44XX_IRQ_SHA1_P			(51 + OMAP44XX_IRQ_GIC_START)	/* SHA2/MD5 crypto-accelerator 1 combined public side */
> +#define OMAP44XX_IRQ_RNG			(52 + OMAP44XX_IRQ_GIC_START)	/* RNG module */
> +#define OMAP44XX_IRQ_DSS_DSI1			(53 + OMAP44XX_IRQ_GIC_START)	/* Display DSI1 interrupt request */
> +#define OMAP44XX_IRQ_I2C1			(56 + OMAP44XX_IRQ_GIC_START)	/* I2C module 1 */
> +#define OMAP44XX_IRQ_I2C2			(57 + OMAP44XX_IRQ_GIC_START)	/* I2C module 2 */
> +#define OMAP44XX_IRQ_HDQ			(58 + OMAP44XX_IRQ_GIC_START)	/* HDQ/One wire */
> +#define OMAP44XX_IRQ_MMC5			(59 + OMAP44XX_IRQ_GIC_START)	/* MMC5_IRQ */
> +#define OMAP44XX_IRQ_I2C3			(61 + OMAP44XX_IRQ_GIC_START)	/* I2C module 3 */
> +#define OMAP44XX_IRQ_I2C4			(62 + OMAP44XX_IRQ_GIC_START)	/* I2C module 4 */
> +#define OMAP44XX_IRQ_AES2_S			(63 + OMAP44XX_IRQ_GIC_START)	/* AES module 2 Interrupt secure side */
> +#define OMAP44XX_IRQ_AES2_P			(64 + OMAP44XX_IRQ_GIC_START)	/* AES module 2 Interrupt public side */
> +#define OMAP44XX_IRQ_SPI1			(65 + OMAP44XX_IRQ_GIC_START)	/* McSPI module 1 */
> +#define OMAP44XX_IRQ_SPI2			(66 + OMAP44XX_IRQ_GIC_START)	/* McSPI module 2 */
> +#define OMAP44XX_IRQ_HSI_P1			(67 + OMAP44XX_IRQ_GIC_START)	/* HSI interrupt request - Port 1 combined interrupt */
> +#define OMAP44XX_IRQ_HSI_P2			(68 + OMAP44XX_IRQ_GIC_START)	/* HSI interrupt request - Port 2 combined interrupt */
> +#define OMAP44XX_IRQ_FDIF_3			(69 + OMAP44XX_IRQ_GIC_START)	/* Face detect Interrupt */
> +#define OMAP44XX_IRQ_UART4			(70 + OMAP44XX_IRQ_GIC_START)	/* UART module 4 */
> +#define OMAP44XX_IRQ_HSI_DMA			(71 + OMAP44XX_IRQ_GIC_START)	/* HSI DMA engine */
> +#define OMAP44XX_IRQ_UART1			(72 + OMAP44XX_IRQ_GIC_START)	/* UART module 1 */
> +#define OMAP44XX_IRQ_UART2			(73 + OMAP44XX_IRQ_GIC_START)	/* UART module 2 */
> +#define OMAP44XX_IRQ_UART3			(74 + OMAP44XX_IRQ_GIC_START)	/* UART module 3 (also infrared) */
> +#define OMAP44XX_IRQ_PBIAS			(75 + OMAP44XX_IRQ_GIC_START)	/* Merged interrupt for PBIASlite1 and 2 */
> +#define OMAP44XX_IRQ_OHCI			(76 + OMAP44XX_IRQ_GIC_START)	/* HSUSB MP Host Interrupt OHCI controller */
> +#define OMAP44XX_IRQ_EHCI			(77 + OMAP44XX_IRQ_GIC_START)	/* HSUSB MP Host Interrupt EHCI controller */
> +#define OMAP44XX_IRQ_TLL			(78 + OMAP44XX_IRQ_GIC_START)	/* HSUSB MP TLL Interrupt */
> +#define OMAP44XX_IRQ_AES1_S			(79 + OMAP44XX_IRQ_GIC_START)	/* AES module 1 interrupt secure side */
> +#define OMAP44XX_IRQ_WDT2			(80 + OMAP44XX_IRQ_GIC_START)	/* WDT2 interrupt */
> +#define OMAP44XX_IRQ_DES_S			(81 + OMAP44XX_IRQ_GIC_START)	/* DES/3DES module secure side */
> +#define OMAP44XX_IRQ_DES_P			(82 + OMAP44XX_IRQ_GIC_START)	/* DES/3DES module Public side */
> +#define OMAP44XX_IRQ_MMC1			(83 + OMAP44XX_IRQ_GIC_START)	/* MMC1_IRQ */
> +#define OMAP44XX_IRQ_DSS_DSI2			(84 + OMAP44XX_IRQ_GIC_START)	/* Display DSI2 interrupt request */
> +#define OMAP44XX_IRQ_AES1_P			(85 + OMAP44XX_IRQ_GIC_START)	/* AES module 1 interrupt public side */
> +#define OMAP44XX_IRQ_MMC2			(86 + OMAP44XX_IRQ_GIC_START)	/* MMC/SDIO module 2 */
> +#define OMAP44XX_IRQ_MPU_ICR			(87 + OMAP44XX_IRQ_GIC_START)	/* MPU ICR Interrupt from Modem-APE  Inter Processor Communication IP */
> +#define OMAP44XX_IRQ_C2C_SSCM_1			(88 + OMAP44XX_IRQ_GIC_START)	/* Chip2Chip GPI interrupt */
> +#define OMAP44XX_IRQ_FSUSB			(89 + OMAP44XX_IRQ_GIC_START)	/* FS-USB - Host controller Interrupt */
> +#define OMAP44XX_IRQ_FSUSB_SMI			(90 + OMAP44XX_IRQ_GIC_START)	/* FS-USB - Host controller  SMI (system Management) Interrupt */
> +#define OMAP44XX_IRQ_SPI3			(91 + OMAP44XX_IRQ_GIC_START)	/* McSPI module 3 */
> +#define OMAP44XX_IRQ_HS_USB_MC_N		(92 + OMAP44XX_IRQ_GIC_START)	/* Module HS USB OTG controller */
> +#define OMAP44XX_IRQ_HS_USB_DMA_N		(93 + OMAP44XX_IRQ_GIC_START)	/* Module HS USB OTG DMA controller interrupt */
> +#define OMAP44XX_IRQ_MMC3			(94 + OMAP44XX_IRQ_GIC_START)	/* MMC/SDIO module 3 */
> +#define OMAP44XX_IRQ_GPT12			(95 + OMAP44XX_IRQ_GIC_START)	/* General purpose timer module 12 (secure timer / Wakeup domain) */
> +#define OMAP44XX_IRQ_MMC4			(96 + OMAP44XX_IRQ_GIC_START)	/* MMC/SDIO module 4 */
> +#define OMAP44XX_IRQ_SLIMBUS1			(97 + OMAP44XX_IRQ_GIC_START)	/* SLIMBus module 1 */
> +#define OMAP44XX_IRQ_SLIMBUS2			(98 + OMAP44XX_IRQ_GIC_START)	/* SLIMBus module 2 */
> +#define OMAP44XX_IRQ_ABE			(99 + OMAP44XX_IRQ_GIC_START)	/* Audio Back-End interrupt */
> +#define OMAP44XX_IRQ_DUCATI_MMU			(100 + OMAP44XX_IRQ_GIC_START)	/* Ducati MMU interrupt */
> +#define OMAP44XX_IRQ_DSS_HDMI			(101 + OMAP44XX_IRQ_GIC_START)	/* Display HDMI interrupt request */
> +#define OMAP44XX_IRQ_SR_IVA			(102 + OMAP44XX_IRQ_GIC_START)	/* SmartReflex IVA interrupt request */
> +#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1	(103 + OMAP44XX_IRQ_GIC_START)	/* Sync interrupt from ICONT2 (vDMA) */
> +#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0	(104 + OMAP44XX_IRQ_GIC_START)	/* Sync interrupt from ICONT1 */
> +#define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0	(107 + OMAP44XX_IRQ_GIC_START)	/* IVA-HD Sub System interrupt request (Mailbox interrupt 0) */
> +#define OMAP44XX_IRQ_MCASP1_AR			(108 + OMAP44XX_IRQ_GIC_START)	/* McASP Receive interrupt - Module 1 (Audio BE) */
> +#define OMAP44XX_IRQ_MCASP1_AX			(109 + OMAP44XX_IRQ_GIC_START)	/* McASP Transmit interrupt - Module 1 (Audio BE) */
> +#define OMAP44XX_IRQ_EMIF4_1			(110 + OMAP44XX_IRQ_GIC_START)	/* EMIF4 interrupt - Module 1 */
> +#define OMAP44XX_IRQ_EMIF4_2			(111 + OMAP44XX_IRQ_GIC_START)	/* EMIF4 interrupt - Module 2 */
> +#define OMAP44XX_IRQ_MCPDM			(112 + OMAP44XX_IRQ_GIC_START)	/* McPDM interrupt (Audio BE) */
> +#define OMAP44XX_IRQ_DMM			(113 + OMAP44XX_IRQ_GIC_START)	/* DMM interrupt */
> +#define OMAP44XX_IRQ_DMIC			(114 + OMAP44XX_IRQ_GIC_START)	/* DMIC interrupt (Audio BE) */
> +#define OMAP44XX_IRQ_CDMA_0			(115 + OMAP44XX_IRQ_GIC_START)	/* Crypto DMA interrupt request 0 */
> +#define OMAP44XX_IRQ_CDMA_1			(116 + OMAP44XX_IRQ_GIC_START)	/* Crypto DMA interrupt request 1 */
> +#define OMAP44XX_IRQ_CDMA_2			(117 + OMAP44XX_IRQ_GIC_START)	/* Crypto DMA interrupt request 2 */
> +#define OMAP44XX_IRQ_CDMA_3			(118 + OMAP44XX_IRQ_GIC_START)	/* Crypto DMA interrupt request 3 */
> +#define OMAP44XX_IRQ_SYS_2N			(119 + OMAP44XX_IRQ_GIC_START)	/* External interrupt 2 (active low) */
> +#define OMAP44XX_IRQ_KBD_CTL			(120 + OMAP44XX_IRQ_GIC_START)	/* Keyboard controller IRQ */
> +#define OMAP44XX_IRQ_UNIPRO1			(124 + OMAP44XX_IRQ_GIC_START)	/* Unipro Module 1 */
> +
> +#endif
> diff --git a/arch/arm/plat-omap/include/plat/dma-44xx.h b/arch/arm/plat-omap/include/plat/dma-44xx.h
> new file mode 100644
> index 0000000..f4f7d15
> --- /dev/null
> +++ b/arch/arm/plat-omap/include/plat/dma-44xx.h
> @@ -0,0 +1,145 @@
> +/*
> + * OMAP4 SDMA channel definitions
> + *
> + * Copyright (C) 2009-2010 Texas Instruments, Inc.
> + *
> + * Santosh Shilimkar (santosh.shilimkar at ti.com)
> + * Benoit Cousson (b-cousson at ti.com)
> + *
> + * This file is automatically generated from the OMAP hardware databases.
> + * We respectfully ask that any modifications to this file be coordinated
> + * with the public linux-omap at vger.kernel.org mailing list and the
> + * authors above to ensure that the autogeneration scripts are kept
> + * up-to-date with the file contents.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
> +#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
> +
> +#define OMAP44XX_DMA_SYS_REQ0			2	/* External DMA request 0 (system expansion) */
> +#define OMAP44XX_DMA_SYS_REQ1			3	/* External DMA request 1 (system expansion) */
> +#define OMAP44XX_DMA_GPMC			4	/* GPMC request from prefetch engine */
> +#define OMAP44XX_DMA_DSS_DISPC_REQ		6	/* The line trigger signal to synchronize a memory to memory logical channel in the DMA4 (system DMA) is generated by the Display Controller IP. */
> +#define OMAP44XX_DMA_SYS_REQ2			7	/* External DMA request 2 (system expansion) */
> +#define OMAP44XX_DMA_MCASP1_AXEVT		8	/* McASP module 1 (Audio BE) - Data transmit DMA request line */
> +#define OMAP44XX_DMA_ISS_REQ1			9	/* ISS DMA request 1 */
> +#define OMAP44XX_DMA_ISS_REQ2			10	/* ISS DMA request 2 */
> +#define OMAP44XX_DMA_MCASP1_AREVT		11	/* McASP module 1 (Audio BE) - Data receive DMA request line */
> +#define OMAP44XX_DMA_ISS_REQ3			12	/* ISS DMA request 3 */
> +#define OMAP44XX_DMA_ISS_REQ4			13	/* ISS DMA request 4 */
> +#define OMAP44XX_DMA_DSS_RFBI_REQ		14	/* DSS RFBI DMA request */
> +#define OMAP44XX_DMA_SPI3_TX0			15	/* McSPI module 3 - transmit request channel 0 */
> +#define OMAP44XX_DMA_SPI3_RX0			16	/* McSPI module 3 - receive request channel 0 */
> +#define OMAP44XX_DMA_MCBSP2_TX			17	/* MCBSP module 2 - transmit request (audio BE) */
> +#define OMAP44XX_DMA_MCBSP2_RX			18	/* MCBSP module 2 - receive request (audio BE) */
> +#define OMAP44XX_DMA_MCBSP3_TX			19	/* MCBSP module 3 - transmit request (Audio BE) */
> +#define OMAP44XX_DMA_MCBSP3_RX			20	/* MCBSP module 3 - receive request (Audio BE) */
> +#define OMAP44XX_DMA_C2C_SSCM_GPO0		21	/* Chip2Chip GPO line 0 (C2C_Sscm_Gpo[0]) */
> +#define OMAP44XX_DMA_C2C_SSCM_GPO1		22	/* Chip2Chip GPO line 1 (C2C_Sscm_Gpo[1]) */
> +#define OMAP44XX_DMA_SPI3_TX1			23	/* McSPI module 3 - transmit request channel 1 */
> +#define OMAP44XX_DMA_SPI3_RX1			24	/* McSPI module 3 - receive request channel 1 */
> +#define OMAP44XX_DMA_I2C3_TX			25	/* I2C module 3 - transmit request */
> +#define OMAP44XX_DMA_I2C3_RX			26	/* I2C module 3 - receive request */
> +#define OMAP44XX_DMA_I2C1_TX			27	/* I2C module 1 - transmit request */
> +#define OMAP44XX_DMA_I2C1_RX			28	/* I2C module 1 - receive request */
> +#define OMAP44XX_DMA_I2C2_TX			29	/* I2C module 2 - transmit request */
> +#define OMAP44XX_DMA_I2C2_RX			30	/* I2C module 2 - receive request */
> +#define OMAP44XX_DMA_MCBSP4_TX			31	/* MCBSP module 4 - transmit request */
> +#define OMAP44XX_DMA_MCBSP4_RX			32	/* MCBSP module 4 - receive request */
> +#define OMAP44XX_DMA_MCBSP1_TX			33	/* MCBSP module 1 - transmit request (Audio BE) */
> +#define OMAP44XX_DMA_MCBSP1_RX			34	/* MCBSP module 1 - receive request (Audio BE) */
> +#define OMAP44XX_DMA_SPI1_TX0			35	/* McSPI module 1 - transmit request channel 0 */
> +#define OMAP44XX_DMA_SPI1_RX0			36	/* McSPI module 1 - receive request channel 0 */
> +#define OMAP44XX_DMA_SPI1_TX1			37	/* McSPI module 1 - transmit request channel 1 */
> +#define OMAP44XX_DMA_SPI1_RX1			38	/* McSPI module 1 - receive request channel 1 */
> +#define OMAP44XX_DMA_SPI1_TX2			39	/* McSPI module 1 - transmit request channel 2 */
> +#define OMAP44XX_DMA_SPI1_RX2			40	/* McSPI module 1 - receive request channel 2 */
> +#define OMAP44XX_DMA_SPI1_TX3			41	/* McSPI module 1 - transmit request channel 3 */
> +#define OMAP44XX_DMA_SPI1_RX3			42	/* McSPI module 1 - receive request channel 3 */
> +#define OMAP44XX_DMA_SPI2_TX0			43	/* McSPI module 2 - transmit request channel 0 */
> +#define OMAP44XX_DMA_SPI2_RX0			44	/* McSPI module 2 - receive request channel 0 */
> +#define OMAP44XX_DMA_SPI2_TX1			45	/* McSPI module 2 - transmit request channel 1 */
> +#define OMAP44XX_DMA_SPI2_RX1			46	/* McSPI module 2 - receive request channel 1 */
> +#define OMAP44XX_DMA_MMC2_TX			47	/* MMC/SD2 transmit request */
> +#define OMAP44XX_DMA_MMC2_RX			48	/* MMC/SD2 receive request */
> +#define OMAP44XX_DMA_UART1_TX			49	/* UART module 1 - transmit request */
> +#define OMAP44XX_DMA_UART1_RX			50	/* UART module 1 - receive request */
> +#define OMAP44XX_DMA_UART2_TX			51	/* UART module 2 - transmit request */
> +#define OMAP44XX_DMA_UART2_RX			52	/* UART module 2 - receive request */
> +#define OMAP44XX_DMA_UART3_TX			53	/* UART module 3 - transmit request (Also infrared) */
> +#define OMAP44XX_DMA_UART3_RX			54	/* UART module 3 - receive request (Also infrared) */
> +#define OMAP44XX_DMA_UART4_TX			55	/* UART module 4  transmit request */
> +#define OMAP44XX_DMA_UART4_RX			56	/* UART module 4  receive request */
> +#define OMAP44XX_DMA_MMC4_TX			57	/* MMC/SD4 transmit request */
> +#define OMAP44XX_DMA_MMC4_RX			58	/* MMC/SD4 receive request */
> +#define OMAP44XX_DMA_MMC5_TX			59	/* MMC/SD5 transmit request */
> +#define OMAP44XX_DMA_MMC5_RX			60	/* MMC/SD5 receive request */
> +#define OMAP44XX_DMA_MMC1_TX			61	/* MMC/SD1 transmit request */
> +#define OMAP44XX_DMA_MMC1_RX			62	/* MMC/SD1 receive request */
> +#define OMAP44XX_DMA_SYS_REQ3			64	/* External DMA request 3 (system expansion) */
> +#define OMAP44XX_DMA_MCPDM_UP			65	/* McPDM Uplink DMA request */
> +#define OMAP44XX_DMA_MCPDM_DL			66	/* McPDM DownlinkDMA request */
> +#define OMAP44XX_DMA_DMIC_REQ			67	/* DMIC DMA request */
> +#define OMAP44XX_DMA_C2C_SSCM_GPO2		68	/* Chip2Chip GPO line 2 (C2C_Sscm_Gpo[2]) */
> +#define OMAP44XX_DMA_C2C_SSCM_GPO3		69	/* Chip2Chip GPO line 3 (C2C_Sscm_Gpo[3]) */
> +#define OMAP44XX_DMA_SPI4_TX0			70	/* McSPI module 4 - transmit request channel 0 */
> +#define OMAP44XX_DMA_SPI4_RX0			71	/* McSPI module 4 - receive request channel 0 */
> +#define OMAP44XX_DMA_DSS_DSI1_REQ0		72	/* Display subsystem DSI1 DMA request 0 */
> +#define OMAP44XX_DMA_DSS_DSI1_REQ1		73	/* Display subsystem DSI1 DMA request 1 */
> +#define OMAP44XX_DMA_DSS_DSI1_REQ2		74	/* Display subsystem DSI1 DMA request 2 */
> +#define OMAP44XX_DMA_DSS_DSI1_REQ3		75	/* Display subsystem DSI1 DMA request 3 */
> +#define OMAP44XX_DMA_DSS_HDMI_REQ		76	/* Display subsystem HDMI Audio DMA request */
> +#define OMAP44XX_DMA_MMC3_TX			77	/* MMC/SD3 transmit request */
> +#define OMAP44XX_DMA_MMC3_RX			78	/* MMC/SD3 receive request */
> +#define OMAP44XX_DMA_USIM_TX			79	/* USIM transmit request */
> +#define OMAP44XX_DMA_USIM_RX			80	/* USIM receive request */
> +#define OMAP44XX_DMA_DSS_DSI2_REQ0		81	/* Display subsystem DSI2 DMA request 0 */
> +#define OMAP44XX_DMA_DSS_DSI2_REQ1		82	/* Display subsystem DSI2 DMA request 1 */
> +#define OMAP44XX_DMA_DSS_DSI2_REQ2		83	/* Display subsystem DSI2 DMA request 2 */
> +#define OMAP44XX_DMA_DSS_DSI2_REQ3		84	/* Display subsystem DSI2 DMA request 3 */
> +#define OMAP44XX_DMA_SLIMBUS1_TX0		85	/* SLIMbus module 1  transmit request channel 0 */
> +#define OMAP44XX_DMA_SLIMBUS1_TX1		86	/* SLIMbus module 1  transmit request channel 1 */
> +#define OMAP44XX_DMA_SLIMBUS1_TX2		87	/* SLIMbus module 1  transmit request channel 2 */
> +#define OMAP44XX_DMA_SLIMBUS1_TX3		88	/* SLIMbus module 1  transmit request channel 3 */
> +#define OMAP44XX_DMA_SLIMBUS1_RX0		89	/* SLIMbus module 1  receive request channel 0 */
> +#define OMAP44XX_DMA_SLIMBUS1_RX1		90	/* SLIMbus module 1  receive request channel 1 */
> +#define OMAP44XX_DMA_SLIMBUS1_RX2		91	/* SLIMbus module 1  receive request channel 2 */
> +#define OMAP44XX_DMA_SLIMBUS1_RX3		92	/* SLIMbus module 1  receive request channel 3 */
> +#define OMAP44XX_DMA_SLIMBUS2_TX0		93	/* SLIMbus module 2  transmit request channel 0 */
> +#define OMAP44XX_DMA_SLIMBUS2_TX1		94	/* SLIMbus module 2  transmit request channel 1 */
> +#define OMAP44XX_DMA_SLIMBUS2_TX2		95	/* SLIMbus module 2  transmit request channel 2 */
> +#define OMAP44XX_DMA_SLIMBUS2_TX3		96	/* SLIMbus module 2  transmit request channel 3 */
> +#define OMAP44XX_DMA_SLIMBUS2_RX0		97	/* SLIMbus module 2  receive request channel 0 */
> +#define OMAP44XX_DMA_SLIMBUS2_RX1		98	/* SLIMbus module 2  receive request channel 1 */
> +#define OMAP44XX_DMA_SLIMBUS2_RX2		99	/* SLIMbus module 2  receive request channel 2 */
> +#define OMAP44XX_DMA_SLIMBUS2_RX3		100	/* SLIMbus module 2  receive request channel 3 */
> +#define OMAP44XX_DMA_ABE_REQ_0			101	/* Audio Back-End module  request FIFO 0 */
> +#define OMAP44XX_DMA_ABE_REQ_1			102	/* Audio Back-End module  request FIFO 1 */
> +#define OMAP44XX_DMA_ABE_REQ_2			103	/* Audio Back-End module  request FIFO 2 */
> +#define OMAP44XX_DMA_ABE_REQ_3			104	/* Audio Back-End module  request FIFO 3 */
> +#define OMAP44XX_DMA_ABE_REQ_4			105	/* Audio Back-End module  request FIFO 4 */
> +#define OMAP44XX_DMA_ABE_REQ_5			106	/* Audio Back-End module  request FIFO 5 */
> +#define OMAP44XX_DMA_ABE_REQ_6			107	/* Audio Back-End module  request FIFO 6 */
> +#define OMAP44XX_DMA_ABE_REQ_7			108	/* Audio Back-End module  request FIFO 7 */
> +#define OMAP44XX_DMA_AES1_P_CTX_IN_REQ		109	/* AES Module 1: Request a new context on the public HIB */
> +#define OMAP44XX_DMA_AES1_P_DATA_IN_REQ		110	/* AES Module 1: Request input data on the public HIB */
> +#define OMAP44XX_DMA_AES1_P_DATA_OUT_REQ	111	/* AES Module 1: Request output data read on the public HIB */
> +#define OMAP44XX_DMA_AES2_P_CTX_IN_REQ		112	/* AES Module 2: Request a new context on the  public HIB */
> +#define OMAP44XX_DMA_AES2_P_DATA_IN_REQ		113	/* AES Module 2: Request input data on the public HIB */
> +#define OMAP44XX_DMA_AES2_P_DATA_OUT_REQ	114	/* AES Module 2: Request output data read on the public HIB */
> +#define OMAP44XX_DMA_DES_P_CTX_IN_REQ		115	/* DES Module: Request a new context on the public HIB */
> +#define OMAP44XX_DMA_DES_P_DATA_IN_REQ		116	/* DES Module: Request input data on the public HIB */
> +#define OMAP44XX_DMA_DES_P_DATA_OUT_REQ		117	/* DES Module: Request output data read on the public HIB */
> +#define OMAP44XX_DMA_SHA2_CTXIN_P		118	/* SHA2MD5 Module 1: Request a context on public HIB */
> +#define OMAP44XX_DMA_SHA2_DIN_P			119	/* SHA2MD5 Module 1: Request input data on public HIB */
> +#define OMAP44XX_DMA_SHA2_CTXOUT_P		120	/* SHA2MD5 Module 1: Request output data/context on public HIB */
> +#define OMAP44XX_DMA_AES1_P_CONTEXT_OUT_REQ	121	/* AES Module 1: Request the authentication result (TAG) or result IV read on public HIB */
> +#define OMAP44XX_DMA_AES2_P_CONTEXT_OUT_REQ	122	/* AES Module 2: Request the authentication result (TAG) or result IV read on  public HIB */
> +#define OMAP44XX_DMA_I2C4_TX			124	/* I2C module 4 - transmit request */
> +#define OMAP44XX_DMA_I2C4_RX			125	/* I2C module 4 - receive request */
> +
> +#endif
> -- 
> 1.6.0.4
> 
> --
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> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 7/9] omap4: Add auto-generated irq and dma headers
  2010-02-18 17:23             ` [PATCH 7/9] omap4: Add auto-generated irq and dma headers Paul Walmsley
@ 2010-02-18 17:33               ` Shilimkar, Santosh
  2010-02-19  5:10               ` Shilimkar, Santosh
  1 sibling, 0 replies; 25+ messages in thread
From: Shilimkar, Santosh @ 2010-02-18 17:33 UTC (permalink / raw)
  To: linux-arm-kernel

> -----Original Message-----
> From: Paul Walmsley [mailto:paul at pwsan.com]
> Sent: Thursday, February 18, 2010 10:53 PM
> To: Shilimkar, Santosh
> Cc: tony at atomide.com; linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Cousson,
> Benoit
> Subject: Re: [PATCH 7/9] omap4: Add auto-generated irq and dma headers
> 
> Hello Santosh,
> 
> thanks for sending these in.  One minor comment:
> 
> On Thu, 18 Feb 2010, Santosh Shilimkar wrote:
> 
> > These files are generated along with the HWMOD and will eventually be
> > in the existing header files as soon as all drivers will be migrate to
> > omap_hwmod / omap_device.
> >
> > The dma-44xx.h file should be in 'arch/arm/mach-omap2/include/mach/',
> > but this would need dma.h header also present in the mach directory to
> > make local include possible, like what is done for irq.h. Then the
> > script is needed to modify the drivers to include 'mach/dma.h' instead
> > of 'plat/dma.h'. This would be a bigger change and hence left out for now
> 
> I think I originally wrote the DMA generator script, so please add a Nokia
> copyright and put my name in there also.  After that point, it has my ack.
Sure Paul. Will add that information and send updated patch.

Benoit,
We need to update the scripts and regenerate this. I will do that.

Regards,
Santosh 

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 2/9] omap2/3/4: ioremap omap_globals module
  2010-02-18  8:59 ` [PATCH 2/9] omap2/3/4: ioremap omap_globals module Santosh Shilimkar
  2010-02-18  8:59   ` [PATCH 3/9] omap4: sdma: Enable the idle modes on omap4 Santosh Shilimkar
@ 2010-02-18 17:35   ` Paul Walmsley
  2010-02-18 22:24   ` Kevin Hilman
  2 siblings, 0 replies; 25+ messages in thread
From: Paul Walmsley @ 2010-02-18 17:35 UTC (permalink / raw)
  To: linux-arm-kernel

One nitpicky comment on this one also:

On Thu, 18 Feb 2010, Santosh Shilimkar wrote:

> This is a clean-up patch towards dynamic allocation of IO space
> instead of using harcoded macros to calculate virtual addresses.
> 
> Also update the sdrc, prcm, tap and control module to
> allocate iospace dynamically
> 
> As per Tony's suggestion V2 version drops tap changes
> becasue ioremap uses cpu_is_omap2420() and cpu_is_omap2430(),
> so we can't use that for setting tap_base. Hence ioremap()
> won't work for tap until omap2_check_revision() is done
> 
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> CC: Kevin Hilman <khilman@deeprootsystems.com>
> CC: Tony Lindgren <tony@atomide.com>
> ---
>  arch/arm/mach-omap2/control.c            |    6 ++++-
>  arch/arm/mach-omap2/prcm.c               |   16 ++++++++++--
>  arch/arm/mach-omap2/sdrc.c               |   11 +++++++-
>  arch/arm/plat-omap/common.c              |   38 +++++++++++++++---------------
>  arch/arm/plat-omap/include/plat/common.h |   17 ++++++++-----
>  5 files changed, 56 insertions(+), 32 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> index cdd1f35..43f8a33 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -140,7 +140,11 @@ static struct omap3_control_regs control_context;
>  
>  void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
>  {
> -	omap2_ctrl_base = omap2_globals->ctrl;
> +	/* Static mapping, never released */
> +	if (omap2_globals->ctrl) {
> +		omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
> +		WARN_ON(!omap2_ctrl_base);
> +	}
>  }
>  
>  void __iomem *omap_ctrl_base_get(void)
> diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
> index e8e121a..338d5f6 100644
> --- a/arch/arm/mach-omap2/prcm.c
> +++ b/arch/arm/mach-omap2/prcm.c
> @@ -279,9 +279,19 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
>  
>  void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
>  {
> -	prm_base = omap2_globals->prm;
> -	cm_base = omap2_globals->cm;
> -	cm2_base = omap2_globals->cm2;
> +	/* Static mapping, never released */
> +	if (omap2_globals->prm) {
> +		prm_base = ioremap(omap2_globals->prm, SZ_8K);
> +		WARN_ON(!prm_base);
> +	}
> +	if (omap2_globals->cm) {
> +		cm_base = ioremap(omap2_globals->cm, SZ_8K);
> +		WARN_ON(!cm_base);
> +	}
> +	if (omap2_globals->cm2) {
> +		cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
> +		WARN_ON(!cm2_base);
> +	}
>  }
>  
>  #ifdef CONFIG_ARCH_OMAP3
> diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
> index cbfbd14..4c65f56 100644
> --- a/arch/arm/mach-omap2/sdrc.c
> +++ b/arch/arm/mach-omap2/sdrc.c
> @@ -119,8 +119,15 @@ int omap2_sdrc_get_params(unsigned long r,
>  
>  void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
>  {
> -	omap2_sdrc_base = omap2_globals->sdrc;
> -	omap2_sms_base = omap2_globals->sms;
> +	/* Static mapping, never released */
> +	if (omap2_globals->sdrc) {
> +		omap2_sdrc_base = ioremap(omap2_globals->sdrc, SZ_64K);
> +		WARN_ON(!omap2_sdrc_base);
> +	}
> +	if (omap2_globals->sms) {
> +		omap2_sms_base = ioremap(omap2_globals->sms, SZ_64K);
> +		WARN_ON(!omap2_sms_base);
> +	}
>  }
>  
>  /**
> diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
> index 4f29e8c..088c1a0 100644
> --- a/arch/arm/plat-omap/common.c
> +++ b/arch/arm/plat-omap/common.c
> @@ -256,11 +256,11 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
>  static struct omap_globals omap242x_globals = {
>  	.class	= OMAP242X_CLASS,
>  	.tap	= OMAP2_L4_IO_ADDRESS(0x48014000),
> -	.sdrc	= OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
> -	.sms	= OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE),
> -	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP2420_CTRL_BASE),
> -	.prm	= OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE),
> -	.cm	= OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE),
> +	.sdrc	= OMAP2420_SDRC_BASE,
> +	.sms	= OMAP2420_SMS_BASE,
> +	.ctrl	= OMAP2420_CTRL_BASE,
> +	.prm	= OMAP2420_PRM_BASE,
> +	.cm	= OMAP2420_CM_BASE,
>  	.uart1_phys	= OMAP2_UART1_BASE,
>  	.uart2_phys	= OMAP2_UART2_BASE,
>  	.uart3_phys	= OMAP2_UART3_BASE,
> @@ -277,11 +277,11 @@ void __init omap2_set_globals_242x(void)
>  static struct omap_globals omap243x_globals = {
>  	.class	= OMAP243X_CLASS,
>  	.tap	= OMAP2_L4_IO_ADDRESS(0x4900a000),
> -	.sdrc	= OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
> -	.sms	= OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE),
> -	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
> -	.prm	= OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE),
> -	.cm	= OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE),
> +	.sdrc	= OMAP243X_SDRC_BASE,
> +	.sms	= OMAP243X_SMS_BASE,
> +	.ctrl	= OMAP243X_CTRL_BASE,
> +	.prm	= OMAP2430_PRM_BASE,
> +	.cm	= OMAP2430_CM_BASE,
>  	.uart1_phys	= OMAP2_UART1_BASE,
>  	.uart2_phys	= OMAP2_UART2_BASE,
>  	.uart3_phys	= OMAP2_UART3_BASE,
> @@ -298,11 +298,11 @@ void __init omap2_set_globals_243x(void)
>  static struct omap_globals omap3_globals = {
>  	.class	= OMAP343X_CLASS,
>  	.tap	= OMAP2_L4_IO_ADDRESS(0x4830A000),
> -	.sdrc	= OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
> -	.sms	= OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE),
> -	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
> -	.prm	= OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE),
> -	.cm	= OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
> +	.sdrc	= OMAP343X_SDRC_BASE,
> +	.sms	= OMAP343X_SMS_BASE,
> +	.ctrl	= OMAP343X_CTRL_BASE,
> +	.prm	= OMAP3430_PRM_BASE,
> +	.cm	= OMAP3430_CM_BASE,
>  	.uart1_phys	= OMAP3_UART1_BASE,
>  	.uart2_phys	= OMAP3_UART2_BASE,
>  	.uart3_phys	= OMAP3_UART3_BASE,
> @@ -325,10 +325,10 @@ void __init omap2_set_globals_36xx(void)
>  static struct omap_globals omap4_globals = {
>  	.class	= OMAP443X_CLASS,
>  	.tap	= OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
> -	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
> -	.prm	= OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
> -	.cm	= OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
> -	.cm2	= OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
> +	.ctrl	= OMAP443X_CTRL_BASE,
> +	.prm	= OMAP4430_PRM_BASE,
> +	.cm	= OMAP4430_CM_BASE,
> +	.cm2	= OMAP4430_CM2_BASE,
>  	.uart1_phys	= OMAP4_UART1_BASE,
>  	.uart2_phys	= OMAP4_UART2_BASE,
>  	.uart3_phys	= OMAP4_UART3_BASE,
> diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
> index e04a58e..d0faff0 100644
> --- a/arch/arm/plat-omap/include/plat/common.h
> +++ b/arch/arm/plat-omap/include/plat/common.h
> @@ -37,16 +37,19 @@ extern void __iomem *gic_cpu_base_addr;
>  extern void omap_map_common_io(void);
>  extern struct sys_timer omap_timer;
>  
> -/* IO bases for various OMAP processors */
> +/* IO bases for various OMAP processors
> + * Except the tap base, rest all the io bases
> + * listed are physical addresses.
> + */

Please be careful with CodingStyle, this should follow the rules for 
multiline comments.

>  struct omap_globals {
>  	u32		class;		/* OMAP class to detect */
>  	void __iomem	*tap;		/* Control module ID code */
> -	void __iomem	*sdrc;		/* SDRAM Controller */
> -	void __iomem	*sms;		/* SDRAM Memory Scheduler */
> -	void __iomem	*ctrl;		/* System Control Module */
> -	void __iomem	*prm;		/* Power and Reset Management */
> -	void __iomem	*cm;		/* Clock Management */
> -	void __iomem	*cm2;
> +	unsigned long   sdrc;           /* SDRAM Controller */
> +	unsigned long   sms;            /* SDRAM Memory Scheduler */
> +	unsigned long   ctrl;           /* System Control Module */
> +	unsigned long   prm;            /* Power and Reset Management */
> +	unsigned long   cm;             /* Clock Management */
> +	unsigned long   cm2;
>  	unsigned long	uart1_phys;
>  	unsigned long	uart2_phys;
>  	unsigned long	uart3_phys;
> -- 
> 1.6.0.4
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


- Paul

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 2/9] omap2/3/4: ioremap omap_globals module
  2010-02-18  8:59 ` [PATCH 2/9] omap2/3/4: ioremap omap_globals module Santosh Shilimkar
  2010-02-18  8:59   ` [PATCH 3/9] omap4: sdma: Enable the idle modes on omap4 Santosh Shilimkar
  2010-02-18 17:35   ` [PATCH 2/9] omap2/3/4: ioremap omap_globals module Paul Walmsley
@ 2010-02-18 22:24   ` Kevin Hilman
  2010-02-19  5:13     ` Shilimkar, Santosh
  2 siblings, 1 reply; 25+ messages in thread
From: Kevin Hilman @ 2010-02-18 22:24 UTC (permalink / raw)
  To: linux-arm-kernel

Santosh Shilimkar <santosh.shilimkar@ti.com> writes:

> This is a clean-up patch towards dynamic allocation of IO space
> instead of using harcoded macros to calculate virtual addresses.
>
> Also update the sdrc, prcm, tap and control module to
> allocate iospace dynamically

You should drop the referenece to the TAP here since it's dropped.

> As per Tony's suggestion V2 version drops tap changes
> becasue ioremap uses cpu_is_omap2420() and cpu_is_omap2430(),
> so we can't use that for setting tap_base. Hence ioremap()
> won't work for tap until omap2_check_revision() is done

And this type of comment should come after the '---' since 
it's relevant to the reviewers, but not to the final git history.


> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> CC: Kevin Hilman <khilman@deeprootsystems.com>
> CC: Tony Lindgren <tony@atomide.com>

After that, you can change the CC for me to a Reviewed-by.

Kevin

> ---
>  arch/arm/mach-omap2/control.c            |    6 ++++-
>  arch/arm/mach-omap2/prcm.c               |   16 ++++++++++--
>  arch/arm/mach-omap2/sdrc.c               |   11 +++++++-
>  arch/arm/plat-omap/common.c              |   38 +++++++++++++++---------------
>  arch/arm/plat-omap/include/plat/common.h |   17 ++++++++-----
>  5 files changed, 56 insertions(+), 32 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> index cdd1f35..43f8a33 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -140,7 +140,11 @@ static struct omap3_control_regs control_context;
>  
>  void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
>  {
> -	omap2_ctrl_base = omap2_globals->ctrl;
> +	/* Static mapping, never released */
> +	if (omap2_globals->ctrl) {
> +		omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
> +		WARN_ON(!omap2_ctrl_base);
> +	}
>  }
>  
>  void __iomem *omap_ctrl_base_get(void)
> diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
> index e8e121a..338d5f6 100644
> --- a/arch/arm/mach-omap2/prcm.c
> +++ b/arch/arm/mach-omap2/prcm.c
> @@ -279,9 +279,19 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
>  
>  void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
>  {
> -	prm_base = omap2_globals->prm;
> -	cm_base = omap2_globals->cm;
> -	cm2_base = omap2_globals->cm2;
> +	/* Static mapping, never released */
> +	if (omap2_globals->prm) {
> +		prm_base = ioremap(omap2_globals->prm, SZ_8K);
> +		WARN_ON(!prm_base);
> +	}
> +	if (omap2_globals->cm) {
> +		cm_base = ioremap(omap2_globals->cm, SZ_8K);
> +		WARN_ON(!cm_base);
> +	}
> +	if (omap2_globals->cm2) {
> +		cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
> +		WARN_ON(!cm2_base);
> +	}
>  }
>  
>  #ifdef CONFIG_ARCH_OMAP3
> diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
> index cbfbd14..4c65f56 100644
> --- a/arch/arm/mach-omap2/sdrc.c
> +++ b/arch/arm/mach-omap2/sdrc.c
> @@ -119,8 +119,15 @@ int omap2_sdrc_get_params(unsigned long r,
>  
>  void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
>  {
> -	omap2_sdrc_base = omap2_globals->sdrc;
> -	omap2_sms_base = omap2_globals->sms;
> +	/* Static mapping, never released */
> +	if (omap2_globals->sdrc) {
> +		omap2_sdrc_base = ioremap(omap2_globals->sdrc, SZ_64K);
> +		WARN_ON(!omap2_sdrc_base);
> +	}
> +	if (omap2_globals->sms) {
> +		omap2_sms_base = ioremap(omap2_globals->sms, SZ_64K);
> +		WARN_ON(!omap2_sms_base);
> +	}
>  }
>  
>  /**
> diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
> index 4f29e8c..088c1a0 100644
> --- a/arch/arm/plat-omap/common.c
> +++ b/arch/arm/plat-omap/common.c
> @@ -256,11 +256,11 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
>  static struct omap_globals omap242x_globals = {
>  	.class	= OMAP242X_CLASS,
>  	.tap	= OMAP2_L4_IO_ADDRESS(0x48014000),
> -	.sdrc	= OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
> -	.sms	= OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE),
> -	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP2420_CTRL_BASE),
> -	.prm	= OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE),
> -	.cm	= OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE),
> +	.sdrc	= OMAP2420_SDRC_BASE,
> +	.sms	= OMAP2420_SMS_BASE,
> +	.ctrl	= OMAP2420_CTRL_BASE,
> +	.prm	= OMAP2420_PRM_BASE,
> +	.cm	= OMAP2420_CM_BASE,
>  	.uart1_phys	= OMAP2_UART1_BASE,
>  	.uart2_phys	= OMAP2_UART2_BASE,
>  	.uart3_phys	= OMAP2_UART3_BASE,
> @@ -277,11 +277,11 @@ void __init omap2_set_globals_242x(void)
>  static struct omap_globals omap243x_globals = {
>  	.class	= OMAP243X_CLASS,
>  	.tap	= OMAP2_L4_IO_ADDRESS(0x4900a000),
> -	.sdrc	= OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
> -	.sms	= OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE),
> -	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
> -	.prm	= OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE),
> -	.cm	= OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE),
> +	.sdrc	= OMAP243X_SDRC_BASE,
> +	.sms	= OMAP243X_SMS_BASE,
> +	.ctrl	= OMAP243X_CTRL_BASE,
> +	.prm	= OMAP2430_PRM_BASE,
> +	.cm	= OMAP2430_CM_BASE,
>  	.uart1_phys	= OMAP2_UART1_BASE,
>  	.uart2_phys	= OMAP2_UART2_BASE,
>  	.uart3_phys	= OMAP2_UART3_BASE,
> @@ -298,11 +298,11 @@ void __init omap2_set_globals_243x(void)
>  static struct omap_globals omap3_globals = {
>  	.class	= OMAP343X_CLASS,
>  	.tap	= OMAP2_L4_IO_ADDRESS(0x4830A000),
> -	.sdrc	= OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
> -	.sms	= OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE),
> -	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
> -	.prm	= OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE),
> -	.cm	= OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
> +	.sdrc	= OMAP343X_SDRC_BASE,
> +	.sms	= OMAP343X_SMS_BASE,
> +	.ctrl	= OMAP343X_CTRL_BASE,
> +	.prm	= OMAP3430_PRM_BASE,
> +	.cm	= OMAP3430_CM_BASE,
>  	.uart1_phys	= OMAP3_UART1_BASE,
>  	.uart2_phys	= OMAP3_UART2_BASE,
>  	.uart3_phys	= OMAP3_UART3_BASE,
> @@ -325,10 +325,10 @@ void __init omap2_set_globals_36xx(void)
>  static struct omap_globals omap4_globals = {
>  	.class	= OMAP443X_CLASS,
>  	.tap	= OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
> -	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
> -	.prm	= OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
> -	.cm	= OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
> -	.cm2	= OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
> +	.ctrl	= OMAP443X_CTRL_BASE,
> +	.prm	= OMAP4430_PRM_BASE,
> +	.cm	= OMAP4430_CM_BASE,
> +	.cm2	= OMAP4430_CM2_BASE,
>  	.uart1_phys	= OMAP4_UART1_BASE,
>  	.uart2_phys	= OMAP4_UART2_BASE,
>  	.uart3_phys	= OMAP4_UART3_BASE,
> diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
> index e04a58e..d0faff0 100644
> --- a/arch/arm/plat-omap/include/plat/common.h
> +++ b/arch/arm/plat-omap/include/plat/common.h
> @@ -37,16 +37,19 @@ extern void __iomem *gic_cpu_base_addr;
>  extern void omap_map_common_io(void);
>  extern struct sys_timer omap_timer;
>  
> -/* IO bases for various OMAP processors */
> +/* IO bases for various OMAP processors
> + * Except the tap base, rest all the io bases
> + * listed are physical addresses.
> + */
>  struct omap_globals {
>  	u32		class;		/* OMAP class to detect */
>  	void __iomem	*tap;		/* Control module ID code */
> -	void __iomem	*sdrc;		/* SDRAM Controller */
> -	void __iomem	*sms;		/* SDRAM Memory Scheduler */
> -	void __iomem	*ctrl;		/* System Control Module */
> -	void __iomem	*prm;		/* Power and Reset Management */
> -	void __iomem	*cm;		/* Clock Management */
> -	void __iomem	*cm2;
> +	unsigned long   sdrc;           /* SDRAM Controller */
> +	unsigned long   sms;            /* SDRAM Memory Scheduler */
> +	unsigned long   ctrl;           /* System Control Module */
> +	unsigned long   prm;            /* Power and Reset Management */
> +	unsigned long   cm;             /* Clock Management */
> +	unsigned long   cm2;
>  	unsigned long	uart1_phys;
>  	unsigned long	uart2_phys;
>  	unsigned long	uart3_phys;
> -- 
> 1.6.0.4

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 7/9] omap4: Add auto-generated irq and dma headers
  2010-02-18 17:23             ` [PATCH 7/9] omap4: Add auto-generated irq and dma headers Paul Walmsley
  2010-02-18 17:33               ` Shilimkar, Santosh
@ 2010-02-19  5:10               ` Shilimkar, Santosh
  1 sibling, 0 replies; 25+ messages in thread
From: Shilimkar, Santosh @ 2010-02-19  5:10 UTC (permalink / raw)
  To: linux-arm-kernel

> -----Original Message-----
> From: Paul Walmsley [mailto:paul at pwsan.com]
> Sent: Thursday, February 18, 2010 10:53 PM
> To: Shilimkar, Santosh
> Cc: tony at atomide.com; linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Cousson,
> Benoit
> Subject: Re: [PATCH 7/9] omap4: Add auto-generated irq and dma headers
> 
> Hello Santosh,
> 
> thanks for sending these in.  One minor comment:
> 
> On Thu, 18 Feb 2010, Santosh Shilimkar wrote:
> 
> > These files are generated along with the HWMOD and will eventually be
> > in the existing header files as soon as all drivers will be migrate to
> > omap_hwmod / omap_device.
> >
> > The dma-44xx.h file should be in 'arch/arm/mach-omap2/include/mach/',
> > but this would need dma.h header also present in the mach directory to
> > make local include possible, like what is done for irq.h. Then the
> > script is needed to modify the drivers to include 'mach/dma.h' instead
> > of 'plat/dma.h'. This would be a bigger change and hence left out for now
> 
> I think I originally wrote the DMA generator script, so please add a Nokia
> copyright and put my name in there also.  After that point, it has my ack.
>
Updated patch attached with Paul's contributions added to the dma-44xx.h file.

Regards,
Santosh

 
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* [PATCH 2/9] omap2/3/4: ioremap omap_globals module
  2010-02-18 22:24   ` Kevin Hilman
@ 2010-02-19  5:13     ` Shilimkar, Santosh
  0 siblings, 0 replies; 25+ messages in thread
From: Shilimkar, Santosh @ 2010-02-19  5:13 UTC (permalink / raw)
  To: linux-arm-kernel

> -----Original Message-----
> From: Kevin Hilman [mailto:khilman at deeprootsystems.com]
> Sent: Friday, February 19, 2010 3:55 AM
> To: Shilimkar, Santosh
> Cc: tony at atomide.com; linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 2/9] omap2/3/4: ioremap omap_globals module
> 
> Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> 
> > This is a clean-up patch towards dynamic allocation of IO space
> > instead of using harcoded macros to calculate virtual addresses.
> >
> > Also update the sdrc, prcm, tap and control module to
> > allocate iospace dynamically
> 
> You should drop the referenece to the TAP here since it's dropped.
> 
> > As per Tony's suggestion V2 version drops tap changes
> > becasue ioremap uses cpu_is_omap2420() and cpu_is_omap2430(),
> > so we can't use that for setting tap_base. Hence ioremap()
> > won't work for tap until omap2_check_revision() is done
> 
> And this type of comment should come after the '---' since
> it's relevant to the reviewers, but not to the final git history.
> 
> 
> > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > CC: Kevin Hilman <khilman@deeprootsystems.com>
> > CC: Tony Lindgren <tony@atomide.com>
> 
> After that, you can change the CC for me to a Reviewed-by.

Refreshed version attached with style fix and adding the Paul, Kevin's
Reviewed-by.

Regards,
Santosh
 
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^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
  2010-02-18  8:59 [PATCH 1/9] omap3/4: uart: fix full-fifo write abort Santosh Shilimkar
  2010-02-18  8:59 ` [PATCH 2/9] omap2/3/4: ioremap omap_globals module Santosh Shilimkar
@ 2010-02-19  5:25 ` Shilimkar, Santosh
  2010-02-22 21:39   ` Tony Lindgren
  1 sibling, 1 reply; 25+ messages in thread
From: Shilimkar, Santosh @ 2010-02-19  5:25 UTC (permalink / raw)
  To: linux-arm-kernel

Bye the way just to add bit more clarity, this patch addresses TX
hardware restriction in the new UART IP used on omap3630 and omap4430.
First part of the fix for RX is already in mainline,
Commit: "ce13d4716a276f4331d78ba28a5093a63822ab95"

More details on this thread are here.
http://www.mail-archive.com/linux-omap at vger.kernel.org/msg19447.html

> -----Original Message-----
> From: Shilimkar, Santosh
> Sent: Thursday, February 18, 2010 2:29 PM
> To: tony at atomide.com
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Shilimkar, Santosh; Woodruff,
> Richard; Ghorai, Sukumar
> Subject: [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
> 
> This patch is addition to the already merged commit on non-empty
> uart fifo read abort. "ce13d4716a276f4331d78ba28a5093a63822ab95"
> 
> OMAP3630 and OMAP4430 UART IP blocks have a restriction on TX FIFO
> too. If you try to write to the tx fifo when it is full, the system aborts.
> 
> This can be easily reproducible by not suppressing interconnect errors or
> long duration testing where continuous prints over console from multiple
> threads. This patch is addressing the issue by ensuring that write is
> not issued while fifo is full. A timeout is added to avoid any hang
> on fifo-full for 10 mS which is unlikely case.
> 
> Patch is validated on OMAP3630 and OMAP4 SDP.
> 
> V2 version removed the additional 1 uS on every TX as per
> Tony's suggestion
> 
> Signed-off-by: Woodruff Richard <r-woodruff2@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> CC: Ghorai Sukumar <s-ghorai@ti.com>
> ---
>  arch/arm/mach-omap2/serial.c |   31 ++++++++++++++++++++++++++++---
>  1 files changed, 28 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
> index 5f3035e..b79bc89 100644
> --- a/arch/arm/mach-omap2/serial.c
> +++ b/arch/arm/mach-omap2/serial.c
> @@ -23,6 +23,7 @@
>  #include <linux/serial_reg.h>
>  #include <linux/clk.h>
>  #include <linux/io.h>
> +#include <linux/delay.h>
> 
>  #include <plat/common.h>
>  #include <plat/board.h>
> @@ -160,6 +161,13 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
>  	return (unsigned int)__raw_readb(up->membase + offset);
>  }
> 
> +static inline void __serial_write_reg(struct uart_port *up, int offset,
> +		int value)
> +{
> +	offset <<= up->regshift;
> +	__raw_writeb(value, up->membase + offset);
> +}
> +
>  static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
>  				    int value)
>  {
> @@ -620,6 +628,20 @@ static unsigned int serial_in_override(struct uart_port *up, int offset)
>  	return __serial_read_reg(up, offset);
>  }
> 
> +static void serial_out_override(struct uart_port *up, int offset, int value)
> +{
> +	unsigned int status, tmout = 10000;
> +
> +	status = __serial_read_reg(up, UART_LSR);
> +	while (!(status & UART_LSR_THRE)) {
> +		/* Wait up to 10ms for the character(s) to be sent. */
> +		if (--tmout == 0)
> +			break;
> +		udelay(1);
> +		status = __serial_read_reg(up, UART_LSR);
> +	}
> +	__serial_write_reg(up, offset, value);
> +}
>  void __init omap_serial_early_init(void)
>  {
>  	int i;
> @@ -721,11 +743,14 @@ void __init omap_serial_init_port(int port)
>  	 * omap3xxx: Never read empty UART fifo on UARTs
>  	 * with IP rev >=0x52
>  	 */
> -	if (cpu_is_omap44xx())
> +	if (cpu_is_omap44xx()) {
>  		uart->p->serial_in = serial_in_override;
> -	else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
> -			>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
> +		uart->p->serial_out = serial_out_override;
> +	} else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
> +			>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) {
>  		uart->p->serial_in = serial_in_override;
> +		uart->p->serial_out = serial_out_override;
> +	}
>  }
> 
>  /**
> --
> 1.6.0.4

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
  2010-02-19  5:25 ` [PATCH 1/9] omap3/4: uart: fix full-fifo write abort Shilimkar, Santosh
@ 2010-02-22 21:39   ` Tony Lindgren
  2010-02-22 23:07     ` Tony Lindgren
  2010-02-23 16:17     ` Shilimkar, Santosh
  0 siblings, 2 replies; 25+ messages in thread
From: Tony Lindgren @ 2010-02-22 21:39 UTC (permalink / raw)
  To: linux-arm-kernel

* Shilimkar, Santosh <santosh.shilimkar@ti.com> [100218 21:22]:
> Bye the way just to add bit more clarity, this patch addresses TX
> hardware restriction in the new UART IP used on omap3630 and omap4430.
> First part of the fix for RX is already in mainline,
> Commit: "ce13d4716a276f4331d78ba28a5093a63822ab95"
> 
> More details on this thread are here.
> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg19447.html

Thanks, I've updated the comments for this patch with the link above
and added the whole series into omap for-next.

Regards,

Tony
 
> > -----Original Message-----
> > From: Shilimkar, Santosh
> > Sent: Thursday, February 18, 2010 2:29 PM
> > To: tony at atomide.com
> > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Shilimkar, Santosh; Woodruff,
> > Richard; Ghorai, Sukumar
> > Subject: [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
> > 
> > This patch is addition to the already merged commit on non-empty
> > uart fifo read abort. "ce13d4716a276f4331d78ba28a5093a63822ab95"
> > 
> > OMAP3630 and OMAP4430 UART IP blocks have a restriction on TX FIFO
> > too. If you try to write to the tx fifo when it is full, the system aborts.
> > 
> > This can be easily reproducible by not suppressing interconnect errors or
> > long duration testing where continuous prints over console from multiple
> > threads. This patch is addressing the issue by ensuring that write is
> > not issued while fifo is full. A timeout is added to avoid any hang
> > on fifo-full for 10 mS which is unlikely case.
> > 
> > Patch is validated on OMAP3630 and OMAP4 SDP.
> > 
> > V2 version removed the additional 1 uS on every TX as per
> > Tony's suggestion
> > 
> > Signed-off-by: Woodruff Richard <r-woodruff2@ti.com>
> > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > CC: Ghorai Sukumar <s-ghorai@ti.com>
> > ---
> >  arch/arm/mach-omap2/serial.c |   31 ++++++++++++++++++++++++++++---
> >  1 files changed, 28 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
> > index 5f3035e..b79bc89 100644
> > --- a/arch/arm/mach-omap2/serial.c
> > +++ b/arch/arm/mach-omap2/serial.c
> > @@ -23,6 +23,7 @@
> >  #include <linux/serial_reg.h>
> >  #include <linux/clk.h>
> >  #include <linux/io.h>
> > +#include <linux/delay.h>
> > 
> >  #include <plat/common.h>
> >  #include <plat/board.h>
> > @@ -160,6 +161,13 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
> >  	return (unsigned int)__raw_readb(up->membase + offset);
> >  }
> > 
> > +static inline void __serial_write_reg(struct uart_port *up, int offset,
> > +		int value)
> > +{
> > +	offset <<= up->regshift;
> > +	__raw_writeb(value, up->membase + offset);
> > +}
> > +
> >  static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
> >  				    int value)
> >  {
> > @@ -620,6 +628,20 @@ static unsigned int serial_in_override(struct uart_port *up, int offset)
> >  	return __serial_read_reg(up, offset);
> >  }
> > 
> > +static void serial_out_override(struct uart_port *up, int offset, int value)
> > +{
> > +	unsigned int status, tmout = 10000;
> > +
> > +	status = __serial_read_reg(up, UART_LSR);
> > +	while (!(status & UART_LSR_THRE)) {
> > +		/* Wait up to 10ms for the character(s) to be sent. */
> > +		if (--tmout == 0)
> > +			break;
> > +		udelay(1);
> > +		status = __serial_read_reg(up, UART_LSR);
> > +	}
> > +	__serial_write_reg(up, offset, value);
> > +}
> >  void __init omap_serial_early_init(void)
> >  {
> >  	int i;
> > @@ -721,11 +743,14 @@ void __init omap_serial_init_port(int port)
> >  	 * omap3xxx: Never read empty UART fifo on UARTs
> >  	 * with IP rev >=0x52
> >  	 */
> > -	if (cpu_is_omap44xx())
> > +	if (cpu_is_omap44xx()) {
> >  		uart->p->serial_in = serial_in_override;
> > -	else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
> > -			>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
> > +		uart->p->serial_out = serial_out_override;
> > +	} else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
> > +			>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) {
> >  		uart->p->serial_in = serial_in_override;
> > +		uart->p->serial_out = serial_out_override;
> > +	}
> >  }
> > 
> >  /**
> > --
> > 1.6.0.4
> 

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 8/9] omap4: Use dma line defines from dma-44xx.h
  2010-02-18  8:59             ` [PATCH 8/9] omap4: Use dma line defines from dma-44xx.h Santosh Shilimkar
  2010-02-18  8:59               ` [PATCH 9/9] omap4: Use irq line defines from irq-44xx.h Santosh Shilimkar
@ 2010-02-22 22:13               ` Tony Lindgren
  1 sibling, 0 replies; 25+ messages in thread
From: Tony Lindgren @ 2010-02-22 22:13 UTC (permalink / raw)
  To: linux-arm-kernel

* Santosh Shilimkar <santosh.shilimkar@ti.com> [100218 00:56]:
> This patch removes all the omap4 specific dma request
> lines defines from plat/dma.h and includes dma-44xx.h
> 
> The defines are aligned so no driver should be impacted
> because of this change.

Dropped this and the next patch as they break compile for _all_
omap1 machines:

arch/arm/plat-omap/dma.c: In function 'omap_init_dma':
arch/arm/plat-omap/dma.c:2135: error: 'OMAP44XX_IRQ_SDMA_0' undeclared (first use in this function)
arch/arm/plat-omap/dma.c:2135: error: (Each undeclared identifier is reported only once
arch/arm/plat-omap/dma.c:2135: error: for each function it appears in.)

Suspect the next patch will too, not even going to try to
build test that.

Regards,

Tony

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
  2010-02-22 21:39   ` Tony Lindgren
@ 2010-02-22 23:07     ` Tony Lindgren
  2010-02-23  5:42       ` Shilimkar, Santosh
  2010-02-23  7:19       ` Shilimkar, Santosh
  2010-02-23 16:17     ` Shilimkar, Santosh
  1 sibling, 2 replies; 25+ messages in thread
From: Tony Lindgren @ 2010-02-22 23:07 UTC (permalink / raw)
  To: linux-arm-kernel

* Tony Lindgren <tony@atomide.com> [100222 13:35]:
> * Shilimkar, Santosh <santosh.shilimkar@ti.com> [100218 21:22]:
> > Bye the way just to add bit more clarity, this patch addresses TX
> > hardware restriction in the new UART IP used on omap3630 and omap4430.
> > First part of the fix for RX is already in mainline,
> > Commit: "ce13d4716a276f4331d78ba28a5093a63822ab95"
> > 
> > More details on this thread are here.
> > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg19447.html
> 
> Thanks, I've updated the comments for this patch with the link above
> and added the whole series into omap for-next.

Except patches 8 and 9 as they break compile for mach-omap1
and need to be updated.

Regards,

Tony

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
  2010-02-22 23:07     ` Tony Lindgren
@ 2010-02-23  5:42       ` Shilimkar, Santosh
  2010-02-23  7:19       ` Shilimkar, Santosh
  1 sibling, 0 replies; 25+ messages in thread
From: Shilimkar, Santosh @ 2010-02-23  5:42 UTC (permalink / raw)
  To: linux-arm-kernel

Thanks Tony
> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, February 23, 2010 4:37 AM
> To: Shilimkar, Santosh
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Woodruff, Richard; Ghorai,
> Sukumar
> Subject: Re: [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
> 
> * Tony Lindgren <tony@atomide.com> [100222 13:35]:
> > * Shilimkar, Santosh <santosh.shilimkar@ti.com> [100218 21:22]:
> > > Bye the way just to add bit more clarity, this patch addresses TX
> > > hardware restriction in the new UART IP used on omap3630 and omap4430.
> > > First part of the fix for RX is already in mainline,
> > > Commit: "ce13d4716a276f4331d78ba28a5093a63822ab95"
> > >
> > > More details on this thread are here.
> > > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg19447.html
> >
> > Thanks, I've updated the comments for this patch with the link above
> > and added the whole series into omap for-next.
> 
> Except patches 8 and 9 as they break compile for mach-omap1
> and need to be updated.

I will check these two patches tony and also boot test the OMAP1.

Regards,
Santosh

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
  2010-02-22 23:07     ` Tony Lindgren
  2010-02-23  5:42       ` Shilimkar, Santosh
@ 2010-02-23  7:19       ` Shilimkar, Santosh
  2010-02-23 23:12         ` Tony Lindgren
  1 sibling, 1 reply; 25+ messages in thread
From: Shilimkar, Santosh @ 2010-02-23  7:19 UTC (permalink / raw)
  To: linux-arm-kernel

Tony,
> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, February 23, 2010 4:37 AM
> To: Shilimkar, Santosh
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Woodruff, Richard; Ghorai,
> Sukumar
> Subject: Re: [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
> 
> * Tony Lindgren <tony@atomide.com> [100222 13:35]:
> > * Shilimkar, Santosh <santosh.shilimkar@ti.com> [100218 21:22]:
> > > Bye the way just to add bit more clarity, this patch addresses TX
> > > hardware restriction in the new UART IP used on omap3630 and omap4430.
> > > First part of the fix for RX is already in mainline,
> > > Commit: "ce13d4716a276f4331d78ba28a5093a63822ab95"
> > >
> > > More details on this thread are here.
> > > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg19447.html
> >
> > Thanks, I've updated the comments for this patch with the link above
> > and added the whole series into omap for-next.
> 
> Except patches 8 and 9 as they break compile for mach-omap1
> and need to be updated.
>
Patch 8 is alright and doesn't break omap1. Patch 7 and patch 9 needs update to fix
the mach-omap1 build issue by moving irqs-44xx.h header file to plat-omap directory.
Attached are updated 7 and 9.
Build tested for omap1 (omap_generic_1710_defconfig and omap_h2_1610_defconfig) and boot
tested with omap3_defconfig on omap4430sdp board.

Thanks!!

Regards,
Santosh


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^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
  2010-02-22 21:39   ` Tony Lindgren
  2010-02-22 23:07     ` Tony Lindgren
@ 2010-02-23 16:17     ` Shilimkar, Santosh
  2010-02-23 18:54       ` Tony Lindgren
  1 sibling, 1 reply; 25+ messages in thread
From: Shilimkar, Santosh @ 2010-02-23 16:17 UTC (permalink / raw)
  To: linux-arm-kernel

Tony,
> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, February 23, 2010 3:10 AM
> To: Shilimkar, Santosh
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Woodruff, Richard; Ghorai,
> Sukumar
> Subject: Re: [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
> 
> * Shilimkar, Santosh <santosh.shilimkar@ti.com> [100218 21:22]:
> > Bye the way just to add bit more clarity, this patch addresses TX
> > hardware restriction in the new UART IP used on omap3630 and omap4430.
> > First part of the fix for RX is already in mainline,
> > Commit: "ce13d4716a276f4331d78ba28a5093a63822ab95"
> >
> > More details on this thread are here.
> > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg19447.html
> 
> Thanks, I've updated the comments for this patch with the link above
> and added the whole series into omap for-next.
> 
Please drop this patch since it has introduces regression on interrupt latency
while traces are enabled. Since 8250 driver calls serial_out() function is with
interrupt disabled ( spin_lock_irqsave), the interrupt latency at times is 
as high as in few milliseconds because of error case.

I shall work towards this issue but for now we should drop this since the side effect
of this change is known

> 
> > > -----Original Message-----
> > > From: Shilimkar, Santosh
> > > Sent: Thursday, February 18, 2010 2:29 PM
> > > To: tony at atomide.com
> > > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Shilimkar, Santosh;
> Woodruff,
> > > Richard; Ghorai, Sukumar
> > > Subject: [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
> > >
> > > This patch is addition to the already merged commit on non-empty
> > > uart fifo read abort. "ce13d4716a276f4331d78ba28a5093a63822ab95"
> > >
> > > OMAP3630 and OMAP4430 UART IP blocks have a restriction on TX FIFO
> > > too. If you try to write to the tx fifo when it is full, the system aborts.
> > >
> > > This can be easily reproducible by not suppressing interconnect errors or
> > > long duration testing where continuous prints over console from multiple
> > > threads. This patch is addressing the issue by ensuring that write is
> > > not issued while fifo is full. A timeout is added to avoid any hang
> > > on fifo-full for 10 mS which is unlikely case.
> > >
> > > Patch is validated on OMAP3630 and OMAP4 SDP.
> > >
> > > V2 version removed the additional 1 uS on every TX as per
> > > Tony's suggestion
> > >
> > > Signed-off-by: Woodruff Richard <r-woodruff2@ti.com>
> > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > > CC: Ghorai Sukumar <s-ghorai@ti.com>
> > > ---
> > >  arch/arm/mach-omap2/serial.c |   31 ++++++++++++++++++++++++++++---
> > >  1 files changed, 28 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
> > > index 5f3035e..b79bc89 100644
> > > --- a/arch/arm/mach-omap2/serial.c
> > > +++ b/arch/arm/mach-omap2/serial.c
> > > @@ -23,6 +23,7 @@
> > >  #include <linux/serial_reg.h>
> > >  #include <linux/clk.h>
> > >  #include <linux/io.h>
> > > +#include <linux/delay.h>
> > >
> > >  #include <plat/common.h>
> > >  #include <plat/board.h>
> > > @@ -160,6 +161,13 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
> > >  	return (unsigned int)__raw_readb(up->membase + offset);
> > >  }
> > >
> > > +static inline void __serial_write_reg(struct uart_port *up, int offset,
> > > +		int value)
> > > +{
> > > +	offset <<= up->regshift;
> > > +	__raw_writeb(value, up->membase + offset);
> > > +}
> > > +
> > >  static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
> > >  				    int value)
> > >  {
> > > @@ -620,6 +628,20 @@ static unsigned int serial_in_override(struct uart_port *up, int offset)
> > >  	return __serial_read_reg(up, offset);
> > >  }
> > >
> > > +static void serial_out_override(struct uart_port *up, int offset, int value)
> > > +{
> > > +	unsigned int status, tmout = 10000;
> > > +
> > > +	status = __serial_read_reg(up, UART_LSR);
> > > +	while (!(status & UART_LSR_THRE)) {
> > > +		/* Wait up to 10ms for the character(s) to be sent. */
> > > +		if (--tmout == 0)
> > > +			break;
> > > +		udelay(1);
> > > +		status = __serial_read_reg(up, UART_LSR);
> > > +	}
> > > +	__serial_write_reg(up, offset, value);
> > > +}
> > >  void __init omap_serial_early_init(void)
> > >  {
> > >  	int i;
> > > @@ -721,11 +743,14 @@ void __init omap_serial_init_port(int port)
> > >  	 * omap3xxx: Never read empty UART fifo on UARTs
> > >  	 * with IP rev >=0x52
> > >  	 */
> > > -	if (cpu_is_omap44xx())
> > > +	if (cpu_is_omap44xx()) {
> > >  		uart->p->serial_in = serial_in_override;
> > > -	else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
> > > -			>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
> > > +		uart->p->serial_out = serial_out_override;
> > > +	} else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
> > > +			>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) {
> > >  		uart->p->serial_in = serial_in_override;
> > > +		uart->p->serial_out = serial_out_override;
> > > +	}
> > >  }
> > >
> > >  /**
> > > --
> > > 1.6.0.4
> >

Regards,
Santosh

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
  2010-02-23 16:17     ` Shilimkar, Santosh
@ 2010-02-23 18:54       ` Tony Lindgren
  0 siblings, 0 replies; 25+ messages in thread
From: Tony Lindgren @ 2010-02-23 18:54 UTC (permalink / raw)
  To: linux-arm-kernel

* Shilimkar, Santosh <santosh.shilimkar@ti.com> [100223 08:14]:
> Tony,
> > -----Original Message-----
> > From: Tony Lindgren [mailto:tony at atomide.com]
> > Sent: Tuesday, February 23, 2010 3:10 AM
> > To: Shilimkar, Santosh
> > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Woodruff, Richard; Ghorai,
> > Sukumar
> > Subject: Re: [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
> > 
> > * Shilimkar, Santosh <santosh.shilimkar@ti.com> [100218 21:22]:
> > > Bye the way just to add bit more clarity, this patch addresses TX
> > > hardware restriction in the new UART IP used on omap3630 and omap4430.
> > > First part of the fix for RX is already in mainline,
> > > Commit: "ce13d4716a276f4331d78ba28a5093a63822ab95"
> > >
> > > More details on this thread are here.
> > > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg19447.html
> > 
> > Thanks, I've updated the comments for this patch with the link above
> > and added the whole series into omap for-next.
> > 
> Please drop this patch since it has introduces regression on interrupt latency
> while traces are enabled. Since 8250 driver calls serial_out() function is with
> interrupt disabled ( spin_lock_irqsave), the interrupt latency at times is 
> as high as in few milliseconds because of error case.
> 
> I shall work towards this issue but for now we should drop this since the side effect
> of this change is known

OK, dropping it. We can merge something better as a fix during the -rc cycle
once you have it working.

Regards,

Tony

 
> > 
> > > > -----Original Message-----
> > > > From: Shilimkar, Santosh
> > > > Sent: Thursday, February 18, 2010 2:29 PM
> > > > To: tony at atomide.com
> > > > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Shilimkar, Santosh;
> > Woodruff,
> > > > Richard; Ghorai, Sukumar
> > > > Subject: [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
> > > >
> > > > This patch is addition to the already merged commit on non-empty
> > > > uart fifo read abort. "ce13d4716a276f4331d78ba28a5093a63822ab95"
> > > >
> > > > OMAP3630 and OMAP4430 UART IP blocks have a restriction on TX FIFO
> > > > too. If you try to write to the tx fifo when it is full, the system aborts.
> > > >
> > > > This can be easily reproducible by not suppressing interconnect errors or
> > > > long duration testing where continuous prints over console from multiple
> > > > threads. This patch is addressing the issue by ensuring that write is
> > > > not issued while fifo is full. A timeout is added to avoid any hang
> > > > on fifo-full for 10 mS which is unlikely case.
> > > >
> > > > Patch is validated on OMAP3630 and OMAP4 SDP.
> > > >
> > > > V2 version removed the additional 1 uS on every TX as per
> > > > Tony's suggestion
> > > >
> > > > Signed-off-by: Woodruff Richard <r-woodruff2@ti.com>
> > > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > > > CC: Ghorai Sukumar <s-ghorai@ti.com>
> > > > ---
> > > >  arch/arm/mach-omap2/serial.c |   31 ++++++++++++++++++++++++++++---
> > > >  1 files changed, 28 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
> > > > index 5f3035e..b79bc89 100644
> > > > --- a/arch/arm/mach-omap2/serial.c
> > > > +++ b/arch/arm/mach-omap2/serial.c
> > > > @@ -23,6 +23,7 @@
> > > >  #include <linux/serial_reg.h>
> > > >  #include <linux/clk.h>
> > > >  #include <linux/io.h>
> > > > +#include <linux/delay.h>
> > > >
> > > >  #include <plat/common.h>
> > > >  #include <plat/board.h>
> > > > @@ -160,6 +161,13 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
> > > >  	return (unsigned int)__raw_readb(up->membase + offset);
> > > >  }
> > > >
> > > > +static inline void __serial_write_reg(struct uart_port *up, int offset,
> > > > +		int value)
> > > > +{
> > > > +	offset <<= up->regshift;
> > > > +	__raw_writeb(value, up->membase + offset);
> > > > +}
> > > > +
> > > >  static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
> > > >  				    int value)
> > > >  {
> > > > @@ -620,6 +628,20 @@ static unsigned int serial_in_override(struct uart_port *up, int offset)
> > > >  	return __serial_read_reg(up, offset);
> > > >  }
> > > >
> > > > +static void serial_out_override(struct uart_port *up, int offset, int value)
> > > > +{
> > > > +	unsigned int status, tmout = 10000;
> > > > +
> > > > +	status = __serial_read_reg(up, UART_LSR);
> > > > +	while (!(status & UART_LSR_THRE)) {
> > > > +		/* Wait up to 10ms for the character(s) to be sent. */
> > > > +		if (--tmout == 0)
> > > > +			break;
> > > > +		udelay(1);
> > > > +		status = __serial_read_reg(up, UART_LSR);
> > > > +	}
> > > > +	__serial_write_reg(up, offset, value);
> > > > +}
> > > >  void __init omap_serial_early_init(void)
> > > >  {
> > > >  	int i;
> > > > @@ -721,11 +743,14 @@ void __init omap_serial_init_port(int port)
> > > >  	 * omap3xxx: Never read empty UART fifo on UARTs
> > > >  	 * with IP rev >=0x52
> > > >  	 */
> > > > -	if (cpu_is_omap44xx())
> > > > +	if (cpu_is_omap44xx()) {
> > > >  		uart->p->serial_in = serial_in_override;
> > > > -	else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
> > > > -			>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
> > > > +		uart->p->serial_out = serial_out_override;
> > > > +	} else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
> > > > +			>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) {
> > > >  		uart->p->serial_in = serial_in_override;
> > > > +		uart->p->serial_out = serial_out_override;
> > > > +	}
> > > >  }
> > > >
> > > >  /**
> > > > --
> > > > 1.6.0.4
> > >
> 
> Regards,
> Santosh

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
  2010-02-23  7:19       ` Shilimkar, Santosh
@ 2010-02-23 23:12         ` Tony Lindgren
  2010-02-24  4:09           ` Shilimkar, Santosh
  0 siblings, 1 reply; 25+ messages in thread
From: Tony Lindgren @ 2010-02-23 23:12 UTC (permalink / raw)
  To: linux-arm-kernel

* Shilimkar, Santosh <santosh.shilimkar@ti.com> [100222 23:16]:
> Tony,
> > -----Original Message-----
> > From: Tony Lindgren [mailto:tony at atomide.com]
> > Sent: Tuesday, February 23, 2010 4:37 AM
> > To: Shilimkar, Santosh
> > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Woodruff, Richard; Ghorai,
> > Sukumar
> > Subject: Re: [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
> > 
> > * Tony Lindgren <tony@atomide.com> [100222 13:35]:
> > > * Shilimkar, Santosh <santosh.shilimkar@ti.com> [100218 21:22]:
> > > > Bye the way just to add bit more clarity, this patch addresses TX
> > > > hardware restriction in the new UART IP used on omap3630 and omap4430.
> > > > First part of the fix for RX is already in mainline,
> > > > Commit: "ce13d4716a276f4331d78ba28a5093a63822ab95"
> > > >
> > > > More details on this thread are here.
> > > > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg19447.html
> > >
> > > Thanks, I've updated the comments for this patch with the link above
> > > and added the whole series into omap for-next.
> > 
> > Except patches 8 and 9 as they break compile for mach-omap1
> > and need to be updated.
> >
> Patch 8 is alright and doesn't break omap1. Patch 7 and patch 9 needs update to fix
> the mach-omap1 build issue by moving irqs-44xx.h header file to plat-omap directory.
> Attached are updated 7 and 9.
> Build tested for omap1 (omap_generic_1710_defconfig and omap_h2_1610_defconfig) and boot
> tested with omap3_defconfig on omap4430sdp board.

Next time, one patch per email please. And updates as replies
to the original patches, or else the whole series. And patches
as inline attachments.

Otherwise it's hard to keep track of the patches and comment
them.

I've updated your patch 9/9 with the following as in omap for-next
I was getting:

arch/arm/mach-omap2/usb-musb.c:97: Building for omap_3430sdp_defconfigred (first use in this function)                                                              Building for omap_3630sdp_defconfigch-omap2/usb-musb.c:97: error: (Each undeclared identifier is reported only once
arch/arm/mach-omap2/usb-musb.c:97: error: for each function it appears in.)
arch/arm/mach-omap2/usb-musb.c:98: error: 'INT_44XX_HS_USB_DMA' undeclared (first use in this function)

Regards,

Tony

--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -94,8 +94,8 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
 		musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;
 	} else if (cpu_is_omap44xx()) {
 		musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE;
-		musb_resources[1].start = INT_44XX_HS_USB_MC;
-		musb_resources[2].start = INT_44XX_HS_USB_DMA;
+		musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N;
+		musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N;
 	}
 	musb_resources[0].end = musb_resources[0].start + SZ_4K - 1;
 

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
  2010-02-23 23:12         ` Tony Lindgren
@ 2010-02-24  4:09           ` Shilimkar, Santosh
  0 siblings, 0 replies; 25+ messages in thread
From: Shilimkar, Santosh @ 2010-02-24  4:09 UTC (permalink / raw)
  To: linux-arm-kernel

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Wednesday, February 24, 2010 4:42 AM
> To: Shilimkar, Santosh
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Woodruff, Richard; Ghorai,
> Sukumar
> Subject: Re: [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
> 
> * Shilimkar, Santosh <santosh.shilimkar@ti.com> [100222 23:16]:
> > Tony,
> > > -----Original Message-----
> > > From: Tony Lindgren [mailto:tony at atomide.com]
> > > Sent: Tuesday, February 23, 2010 4:37 AM
> > > To: Shilimkar, Santosh
> > > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Woodruff, Richard; Ghorai,
> > > Sukumar
> > > Subject: Re: [PATCH 1/9] omap3/4: uart: fix full-fifo write abort
> > >
> > > * Tony Lindgren <tony@atomide.com> [100222 13:35]:
> > > > * Shilimkar, Santosh <santosh.shilimkar@ti.com> [100218 21:22]:
> > > > > Bye the way just to add bit more clarity, this patch addresses TX
> > > > > hardware restriction in the new UART IP used on omap3630 and omap4430.
> > > > > First part of the fix for RX is already in mainline,
> > > > > Commit: "ce13d4716a276f4331d78ba28a5093a63822ab95"
> > > > >
> > > > > More details on this thread are here.
> > > > > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg19447.html
> > > >
> > > > Thanks, I've updated the comments for this patch with the link above
> > > > and added the whole series into omap for-next.
> > >
> > > Except patches 8 and 9 as they break compile for mach-omap1
> > > and need to be updated.
> > >
> > Patch 8 is alright and doesn't break omap1. Patch 7 and patch 9 needs update to fix
> > the mach-omap1 build issue by moving irqs-44xx.h header file to plat-omap directory.
> > Attached are updated 7 and 9.
> > Build tested for omap1 (omap_generic_1710_defconfig and omap_h2_1610_defconfig) and boot
> > tested with omap3_defconfig on omap4430sdp board.
> 
> Next time, one patch per email please. And updates as replies
> to the original patches, or else the whole series. And patches
> as inline attachments.
> 
> Otherwise it's hard to keep track of the patches and comment
> them.
> 
Ok. Will take care next time.
> I've updated your patch 9/9 with the following as in omap for-next
> I was getting:
> 
> arch/arm/mach-omap2/usb-musb.c:97: Building for omap_3430sdp_defconfigred (first use in this
> function)                                                              Building for
> omap_3630sdp_defconfigch-omap2/usb-musb.c:97: error: (Each undeclared identifier is reported only
> once
> arch/arm/mach-omap2/usb-musb.c:97: error: for each function it appears in.)
> arch/arm/mach-omap2/usb-musb.c:98: error: 'INT_44XX_HS_USB_DMA' undeclared (first use in this
> function)
> 
Looks like musb is also merged now. My yesterday's pull of omap-for-linus didn't have musb.

> Regards,
> 
> Tony
> 
> --- a/arch/arm/mach-omap2/usb-musb.c
> +++ b/arch/arm/mach-omap2/usb-musb.c
> @@ -94,8 +94,8 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
>  		musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;
>  	} else if (cpu_is_omap44xx()) {
>  		musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE;
> -		musb_resources[1].start = INT_44XX_HS_USB_MC;
> -		musb_resources[2].start = INT_44XX_HS_USB_DMA;
> +		musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N;
> +		musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N;
>  	}
>  	musb_resources[0].end = musb_resources[0].start + SZ_4K - 1;
> 
Thanks for fixing this.

Regards,
Santosh

^ permalink raw reply	[flat|nested] 25+ messages in thread

end of thread, other threads:[~2010-02-24  4:09 UTC | newest]

Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2010-02-18  8:59 [PATCH 1/9] omap3/4: uart: fix full-fifo write abort Santosh Shilimkar
2010-02-18  8:59 ` [PATCH 2/9] omap2/3/4: ioremap omap_globals module Santosh Shilimkar
2010-02-18  8:59   ` [PATCH 3/9] omap4: sdma: Enable the idle modes on omap4 Santosh Shilimkar
2010-02-18  8:59     ` [PATCH 4/9] omap: sdma: Limit the secure reserve channel fix for omap3 Santosh Shilimkar
2010-02-18  8:59       ` [PATCH 5/9] omap4: Fix omap_type() for omap4 Santosh Shilimkar
2010-02-18  8:59         ` [PATCH 6/9] omap3/4: Remove overlapping mapping of L4_WKUP io space Santosh Shilimkar
2010-02-18  8:59           ` [PATCH 7/9] omap4: Add auto-generated irq and dma headers Santosh Shilimkar
2010-02-18  8:59             ` [PATCH 8/9] omap4: Use dma line defines from dma-44xx.h Santosh Shilimkar
2010-02-18  8:59               ` [PATCH 9/9] omap4: Use irq line defines from irq-44xx.h Santosh Shilimkar
2010-02-22 22:13               ` [PATCH 8/9] omap4: Use dma line defines from dma-44xx.h Tony Lindgren
2010-02-18 17:23             ` [PATCH 7/9] omap4: Add auto-generated irq and dma headers Paul Walmsley
2010-02-18 17:33               ` Shilimkar, Santosh
2010-02-19  5:10               ` Shilimkar, Santosh
2010-02-18 17:35   ` [PATCH 2/9] omap2/3/4: ioremap omap_globals module Paul Walmsley
2010-02-18 22:24   ` Kevin Hilman
2010-02-19  5:13     ` Shilimkar, Santosh
2010-02-19  5:25 ` [PATCH 1/9] omap3/4: uart: fix full-fifo write abort Shilimkar, Santosh
2010-02-22 21:39   ` Tony Lindgren
2010-02-22 23:07     ` Tony Lindgren
2010-02-23  5:42       ` Shilimkar, Santosh
2010-02-23  7:19       ` Shilimkar, Santosh
2010-02-23 23:12         ` Tony Lindgren
2010-02-24  4:09           ` Shilimkar, Santosh
2010-02-23 16:17     ` Shilimkar, Santosh
2010-02-23 18:54       ` Tony Lindgren

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