From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: Add support for the 16-way L310 L2 cache controller
Date: Thu, 29 Apr 2010 19:28:40 +0100 [thread overview]
Message-ID: <20100429182840.GI4877@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <000701cae7b7$e61d45f0$b257d1d0$@deacon@arm.com>
On Thu, Apr 29, 2010 at 05:20:35PM +0100, Will Deacon wrote:
> Hi Jason,
>
> The patch entitled `Add support for the 16-way L310 L2 cache controller'
> which you submitted to RMK's patch system appears to perform a 16-way
> invalidation even when the ways might not be present. This results in
> writes to the reserved bits [15:8] of the invalidate-by-way ctrl register.
>
> You can check the associativity by reading bit 16 of the auxiliary ctrl
> register.
I'll discard it then; seems it needs review on the mailing list.
next prev parent reply other threads:[~2010-04-29 18:28 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-04-29 16:20 Add support for the 16-way L310 L2 cache controller Will Deacon
2010-04-29 18:28 ` Russell King - ARM Linux [this message]
[not found] <3756028016583358140@unknownmsgid>
2010-04-30 17:17 ` Jason McMullan
[not found] <-5319252541413655868@unknownmsgid>
2010-05-03 16:48 ` Jason McMullan
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