* [PATCH 01/34] davinci: misc cleanups from sparse
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
@ 2010-05-06 23:23 ` Kevin Hilman
2010-05-06 23:23 ` [PATCH 02/34] davinci: sparse: gpio: void casting Kevin Hilman
` (32 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:23 UTC (permalink / raw)
To: linux-arm-kernel
- Convert data/functions to static
- include headers for missing declarations
- pointer cleanups: struct foo *__iomem f --> struct foo __iomem *f;
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/board-dm644x-evm.c | 2 +-
arch/arm/mach-davinci/board-neuros-osd2.c | 2 +-
arch/arm/mach-davinci/board-sffsdr.c | 2 +-
arch/arm/mach-davinci/cdce949.c | 1 +
arch/arm/mach-davinci/clock.c | 1 +
arch/arm/mach-davinci/devices.c | 2 ++
arch/arm/mach-davinci/dm355.c | 2 +-
arch/arm/mach-davinci/dm365.c | 2 +-
arch/arm/mach-davinci/dm644x.c | 4 ++--
arch/arm/mach-davinci/dm646x.c | 6 +++---
arch/arm/mach-davinci/gpio.c | 24 ++++++++++++------------
arch/arm/mach-davinci/include/mach/gpio.h | 8 ++++----
arch/arm/mach-davinci/mux.c | 1 +
13 files changed, 31 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 976e11b..95cef1f 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -111,7 +111,7 @@ static struct platform_device davinci_evm_norflash_device = {
* It may used instead of the (default) NOR chip to boot, using TI's
* tools to install the secondary boot loader (UBL) and U-Boot.
*/
-struct mtd_partition davinci_evm_nandflash_partition[] = {
+static struct mtd_partition davinci_evm_nandflash_partition[] = {
/* Bootloader layout depends on whose u-boot is installed, but we
* can hide all the details.
* - block 0 for u-boot environment ... in mainline u-boot
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index bd9ca07..1fadc68 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -60,7 +60,7 @@
#define NAND_BLOCK_SIZE SZ_128K
-struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
+static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
{
/* UBL (a few copies) plus U-Boot */
.name = "bootloader",
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 08d373b..a7cf810 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -48,7 +48,7 @@
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
+static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
/* U-Boot Environment: Block 0
* UBL: Block 1
* U-Boot: Blocks 6-7 (256 kb)
diff --git a/arch/arm/mach-davinci/cdce949.c b/arch/arm/mach-davinci/cdce949.c
index aec3756..ba8b12b 100644
--- a/arch/arm/mach-davinci/cdce949.c
+++ b/arch/arm/mach-davinci/cdce949.c
@@ -19,6 +19,7 @@
#include <linux/i2c.h>
#include <mach/clock.h>
+#include <mach/cdce949.h>
#include "clock.h"
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index bf6218e..058c77f 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -22,6 +22,7 @@
#include <mach/hardware.h>
+#include <mach/clock.h>
#include <mach/psc.h>
#include <mach/cputype.h>
#include "clock.h"
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 1479496..ef28080 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -23,6 +23,8 @@
#include <mach/mmc.h>
#include <mach/time.h>
+#include "clock.h"
+
#define DAVINCI_I2C_BASE 0x01C21000
#define DAVINCI_MMCSD0_BASE 0x01E10000
#define DM355_MMCSD0_BASE 0x01E11000
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 3dc0a88..5efce70 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -798,7 +798,7 @@ static void __iomem *dm355_psc_bases[] = {
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
*/
-struct davinci_timer_info dm355_timer_info = {
+static struct davinci_timer_info dm355_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0d6ee58..871be5a 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1010,7 +1010,7 @@ static void __iomem *dm365_psc_bases[] = {
IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};
-struct davinci_timer_info dm365_timer_info = {
+static struct davinci_timer_info dm365_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 2f2ae8b..23cbe9d 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -277,7 +277,7 @@ static struct clk timer2_clk = {
.usecount = 1, /* REVISIT: why cant' this be disabled? */
};
-struct clk_lookup dm644x_clks[] = {
+static struct clk_lookup dm644x_clks[] = {
CLK(NULL, "ref", &ref_clk),
CLK(NULL, "pll1", &pll1_clk),
CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
@@ -687,7 +687,7 @@ static void __iomem *dm644x_psc_bases[] = {
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
*/
-struct davinci_timer_info dm644x_timer_info = {
+static struct davinci_timer_info dm644x_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 893baf4..b67b997 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -311,7 +311,7 @@ static struct clk vpif1_clk = {
.flags = ALWAYS_ENABLED,
};
-struct clk_lookup dm646x_clks[] = {
+static struct clk_lookup dm646x_clks[] = {
CLK(NULL, "ref", &ref_clk),
CLK(NULL, "aux", &aux_clkin),
CLK(NULL, "pll1", &pll1_clk),
@@ -797,7 +797,7 @@ static void __iomem *dm646x_psc_bases[] = {
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
*/
-struct davinci_timer_info dm646x_timer_info = {
+static struct davinci_timer_info dm646x_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
@@ -867,7 +867,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
.sram_len = SZ_32K,
};
-void __init dm646x_init_ide()
+void __init dm646x_init_ide(void)
{
davinci_cfg_reg(DM646X_ATAEN);
platform_device_register(&ide_dev);
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 744755b..3f77062 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -24,14 +24,14 @@ static DEFINE_SPINLOCK(gpio_lock);
struct davinci_gpio {
struct gpio_chip chip;
- struct gpio_controller *__iomem regs;
+ struct gpio_controller __iomem *regs;
int irq_base;
};
static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
/* create a non-inlined version */
-static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
+static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
{
return __gpio_to_controller(gpio);
}
@@ -48,7 +48,7 @@ static int __init davinci_gpio_irq_setup(void);
static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
- struct gpio_controller *__iomem g = d->regs;
+ struct gpio_controller __iomem *g = d->regs;
u32 temp;
spin_lock(&gpio_lock);
@@ -70,7 +70,7 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
- struct gpio_controller *__iomem g = d->regs;
+ struct gpio_controller __iomem *g = d->regs;
return (1 << offset) & __raw_readl(&g->in_data);
}
@@ -79,7 +79,7 @@ static int
davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
- struct gpio_controller *__iomem g = d->regs;
+ struct gpio_controller __iomem *g = d->regs;
u32 temp;
u32 mask = 1 << offset;
@@ -99,7 +99,7 @@ static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
- struct gpio_controller *__iomem g = d->regs;
+ struct gpio_controller __iomem *g = d->regs;
__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
}
@@ -161,7 +161,7 @@ pure_initcall(davinci_gpio_setup);
static void gpio_irq_disable(unsigned irq)
{
- struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+ struct gpio_controller __iomem *g = get_irq_chip_data(irq);
u32 mask = (u32) get_irq_data(irq);
__raw_writel(mask, &g->clr_falling);
@@ -170,7 +170,7 @@ static void gpio_irq_disable(unsigned irq)
static void gpio_irq_enable(unsigned irq)
{
- struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+ struct gpio_controller __iomem *g = get_irq_chip_data(irq);
u32 mask = (u32) get_irq_data(irq);
unsigned status = irq_desc[irq].status;
@@ -186,7 +186,7 @@ static void gpio_irq_enable(unsigned irq)
static int gpio_irq_type(unsigned irq, unsigned trigger)
{
- struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+ struct gpio_controller __iomem *g = get_irq_chip_data(irq);
u32 mask = (u32) get_irq_data(irq);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -215,7 +215,7 @@ static struct irq_chip gpio_irqchip = {
static void
gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
- struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+ struct gpio_controller __iomem *g = get_irq_chip_data(irq);
u32 mask = 0xffff;
/* we only care about one bank */
@@ -276,7 +276,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
{
- struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+ struct gpio_controller __iomem *g = get_irq_chip_data(irq);
u32 mask = (u32) get_irq_data(irq);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -305,7 +305,7 @@ static int __init davinci_gpio_irq_setup(void)
u32 binten = 0;
unsigned ngpio, bank_irq;
struct davinci_soc_info *soc_info = &davinci_soc_info;
- struct gpio_controller *__iomem g;
+ struct gpio_controller __iomem *g;
ngpio = soc_info->gpio_num;
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index f3b8ef8..0099e6e 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -67,10 +67,10 @@ struct gpio_controller {
*
* These are NOT part of the cross-platform GPIO interface
*/
-static inline struct gpio_controller *__iomem
+static inline struct gpio_controller __iomem *
__gpio_to_controller(unsigned gpio)
{
- void *__iomem ptr;
+ void __iomem *ptr;
void __iomem *base = davinci_soc_info.gpio_base;
if (gpio < 32 * 1)
@@ -102,7 +102,7 @@ static inline u32 __gpio_mask(unsigned gpio)
static inline void gpio_set_value(unsigned gpio, int value)
{
if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
- struct gpio_controller *__iomem g;
+ struct gpio_controller __iomem *g;
u32 mask;
g = __gpio_to_controller(gpio);
@@ -128,7 +128,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
*/
static inline int gpio_get_value(unsigned gpio)
{
- struct gpio_controller *__iomem g;
+ struct gpio_controller __iomem *g;
if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
return __gpio_get_value(gpio);
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index f757e83..c942c89 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -21,6 +21,7 @@
#include <mach/mux.h>
#include <mach/common.h>
+#include <mach/da8xx.h>
/*
* Sets the DAVINCI MUX register based on the table
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 02/34] davinci: sparse: gpio: void casting
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
2010-05-06 23:23 ` [PATCH 01/34] davinci: misc cleanups from sparse Kevin Hilman
@ 2010-05-06 23:23 ` Kevin Hilman
2010-05-06 23:23 ` [PATCH 03/34] davinci: da830/omap-l137 evm: add support for GPIO based MMC/SD card detection Kevin Hilman
` (31 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:23 UTC (permalink / raw)
To: linux-arm-kernel
Cleanup usage of void pointers when using genirq. genirq API
takes and returns void *, where this GPIO API is using those
as __iomem pointers.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/gpio.c | 27 ++++++++++++++++++---------
1 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 3f77062..5476ad1 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -36,6 +36,15 @@ static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
return __gpio_to_controller(gpio);
}
+static inline struct gpio_controller __iomem *irq2controller(int irq)
+{
+ struct gpio_controller __iomem *g;
+
+ g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq);
+
+ return g;
+}
+
static int __init davinci_gpio_irq_setup(void);
/*--------------------------------------------------------------------------*/
@@ -161,7 +170,7 @@ pure_initcall(davinci_gpio_setup);
static void gpio_irq_disable(unsigned irq)
{
- struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+ struct gpio_controller __iomem *g = irq2controller(irq);
u32 mask = (u32) get_irq_data(irq);
__raw_writel(mask, &g->clr_falling);
@@ -170,7 +179,7 @@ static void gpio_irq_disable(unsigned irq)
static void gpio_irq_enable(unsigned irq)
{
- struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+ struct gpio_controller __iomem *g = irq2controller(irq);
u32 mask = (u32) get_irq_data(irq);
unsigned status = irq_desc[irq].status;
@@ -186,7 +195,7 @@ static void gpio_irq_enable(unsigned irq)
static int gpio_irq_type(unsigned irq, unsigned trigger)
{
- struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+ struct gpio_controller __iomem *g = irq2controller(irq);
u32 mask = (u32) get_irq_data(irq);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -215,7 +224,7 @@ static struct irq_chip gpio_irqchip = {
static void
gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
- struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+ struct gpio_controller __iomem *g = irq2controller(irq);
u32 mask = 0xffff;
/* we only care about one bank */
@@ -276,7 +285,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
{
- struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+ struct gpio_controller __iomem *g = irq2controller(irq);
u32 mask = (u32) get_irq_data(irq);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -362,7 +371,7 @@ static int __init davinci_gpio_irq_setup(void)
for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
set_irq_chip(irq, &gpio_irqchip_unbanked);
set_irq_data(irq, (void *) __gpio_mask(gpio));
- set_irq_chip_data(irq, g);
+ set_irq_chip_data(irq, (__force void *) g);
irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
}
@@ -385,12 +394,12 @@ static int __init davinci_gpio_irq_setup(void)
/* set up all irqs in this bank */
set_irq_chained_handler(bank_irq, gpio_irq_handler);
- set_irq_chip_data(bank_irq, g);
- set_irq_data(bank_irq, (void *)irq);
+ set_irq_chip_data(bank_irq, (__force void *) g);
+ set_irq_data(bank_irq, (void *) irq);
for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
set_irq_chip(irq, &gpio_irqchip);
- set_irq_chip_data(irq, g);
+ set_irq_chip_data(irq, (__force void *) g);
set_irq_data(irq, (void *) __gpio_mask(gpio));
set_irq_handler(irq, handle_simple_irq);
set_irq_flags(irq, IRQF_VALID);
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 03/34] davinci: da830/omap-l137 evm: add support for GPIO based MMC/SD card detection
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
2010-05-06 23:23 ` [PATCH 01/34] davinci: misc cleanups from sparse Kevin Hilman
2010-05-06 23:23 ` [PATCH 02/34] davinci: sparse: gpio: void casting Kevin Hilman
@ 2010-05-06 23:23 ` Kevin Hilman
2010-05-06 23:23 ` [PATCH 04/34] davinci: da830/omap-l137 evm: use 8-wire MMC/SD card support Kevin Hilman
` (30 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:23 UTC (permalink / raw)
To: linux-arm-kernel
From: Vipin Bhandari <vipin.bhandari@ti.com>
The DA830/OMAP-L137 EVM has GPIO based card detection logic, but the current
code does not use it.
Add support for GPIO based card detection to avoid reading the card to see
if a card is present or not.
Signed-off-by: Vipin Bhandari <vipin.bhandari@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/board-da830-evm.c | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index dc19870..8e67037 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -229,14 +229,21 @@ static const short da830_evm_mmc_sd_pins[] = {
};
#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1)
+#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2)
static int da830_evm_mmc_get_ro(int index)
{
return gpio_get_value(DA830_MMCSD_WP_PIN);
}
+static int da830_evm_mmc_get_cd(int index)
+{
+ return !gpio_get_value(DA830_MMCSD_CD_PIN);
+}
+
static struct davinci_mmc_config da830_evm_mmc_config = {
.get_ro = da830_evm_mmc_get_ro,
+ .get_cd = da830_evm_mmc_get_cd,
.wires = 4,
.max_freq = 50000000,
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
@@ -262,6 +269,14 @@ static inline void da830_evm_init_mmc(void)
}
gpio_direction_input(DA830_MMCSD_WP_PIN);
+ ret = gpio_request(DA830_MMCSD_CD_PIN, "MMC CD\n");
+ if (ret) {
+ pr_warning("da830_evm_init: can not open GPIO %d\n",
+ DA830_MMCSD_CD_PIN);
+ return;
+ }
+ gpio_direction_input(DA830_MMCSD_CD_PIN);
+
ret = da8xx_register_mmcsd0(&da830_evm_mmc_config);
if (ret) {
pr_warning("da830_evm_init: mmc/sd registration failed: %d\n",
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 04/34] davinci: da830/omap-l137 evm: use 8-wire MMC/SD card support
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (2 preceding siblings ...)
2010-05-06 23:23 ` [PATCH 03/34] davinci: da830/omap-l137 evm: add support for GPIO based MMC/SD card detection Kevin Hilman
@ 2010-05-06 23:23 ` Kevin Hilman
2010-05-06 23:23 ` [PATCH 05/34] davinci: edma: clear interrupt status for interrupt enabled channels only Kevin Hilman
` (29 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:23 UTC (permalink / raw)
To: linux-arm-kernel
From: Vipin Bhandari <vipin.bhandari@ti.com>
The merge for 2.6.34 brings in 8-bit support to the DaVinci MMC/SD driver.
This patch updates the platform data for DA830/OMAP-L137 EVM to use 8-wire
support available in the driver.
Signed-off-by: Vipin Bhandari <vipin.bhandari@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/board-da830-evm.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 8e67037..ea293b8 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -244,7 +244,7 @@ static int da830_evm_mmc_get_cd(int index)
static struct davinci_mmc_config da830_evm_mmc_config = {
.get_ro = da830_evm_mmc_get_ro,
.get_cd = da830_evm_mmc_get_cd,
- .wires = 4,
+ .wires = 8,
.max_freq = 50000000,
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
.version = MMC_CTLR_VERSION_2,
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 05/34] davinci: edma: clear interrupt status for interrupt enabled channels only
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (3 preceding siblings ...)
2010-05-06 23:23 ` [PATCH 04/34] davinci: da830/omap-l137 evm: use 8-wire MMC/SD card support Kevin Hilman
@ 2010-05-06 23:23 ` Kevin Hilman
2010-05-06 23:23 ` [PATCH 06/34] RTC: DaVinci RTC driver Kevin Hilman
` (28 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:23 UTC (permalink / raw)
To: linux-arm-kernel
From: Anuj Aggarwal <anuj.aggarwal@ti.com>
Currently, the ISR in the EDMA driver clears the pending interrupt for all
channels without regard to whether that channel has a registered callback
or not.
This causes problems for devices like DM355/DM365 where the multimedia
accelerator uses EDMA by polling on the interrupt pending bits of some of the
EDMA channels. Since these channels are actually allocated through the Linux
EDMA driver (by an out-of-kernel module), the same shadow region is used by
Linux and accelerator. There a race between the Linux ISR and the polling code
running on the accelerator on the IPR (interrupt pending register).
This patch fixes the issue by making the ISR clear the interrupts only for
those channels which have interrupt enabled. The channels which are allocated
for the purpose of being polled on by the accelerator will not have a callback
function provided and so will not have IER (interrupt enable register) bits set.
Tested on DM365 and OMAP-L137/L138 with audio and MMC/SD (as EDMA users).
Signed-off-by: Anuj Aggarwal <anuj.aggarwal@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
CC: Archith John Bency <archith@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/dma.c | 11 +++++++----
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 5313738..0bf290b 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -359,9 +359,11 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
while (1) {
int j;
- if (edma_shadow0_read_array(ctlr, SH_IPR, 0))
+ if (edma_shadow0_read_array(ctlr, SH_IPR, 0) &
+ edma_shadow0_read_array(ctlr, SH_IER, 0))
j = 0;
- else if (edma_shadow0_read_array(ctlr, SH_IPR, 1))
+ else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) &
+ edma_shadow0_read_array(ctlr, SH_IER, 1))
j = 1;
else
break;
@@ -369,8 +371,9 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
edma_shadow0_read_array(ctlr, SH_IPR, j));
for (i = 0; i < 32; i++) {
int k = (j << 5) + i;
- if (edma_shadow0_read_array(ctlr, SH_IPR, j) &
- (1 << i)) {
+ if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i))
+ && (edma_shadow0_read_array(ctlr,
+ SH_IER, j) & BIT(i))) {
/* Clear the corresponding IPR bits */
edma_shadow0_write_array(ctlr, SH_ICR, j,
(1 << i));
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 06/34] RTC: DaVinci RTC driver
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (4 preceding siblings ...)
2010-05-06 23:23 ` [PATCH 05/34] davinci: edma: clear interrupt status for interrupt enabled channels only Kevin Hilman
@ 2010-05-06 23:23 ` Kevin Hilman
2010-05-13 9:15 ` Russell King - ARM Linux
2010-05-06 23:23 ` [PATCH 07/34] rtc: omap: let device wakeup capability be configured from chip init logic Kevin Hilman
` (27 subsequent siblings)
33 siblings, 1 reply; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:23 UTC (permalink / raw)
To: linux-arm-kernel
From: Miguel Aguilar <miguel.aguilar@ridgerun.com>
This driver features:
* Alarm support.
* Periodic interrupt by using a timer include into the RTC module.
* The update interrupt is not supported by this RTC module.
This driver was tested on a DM365 EVM by using the rtc-test application
from the Documentation/rtc.txt.
Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Acked-by: Alessandro Zummo <a.zummo@towertech.it>
---
drivers/rtc/Kconfig | 10 +
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-davinci.c | 673 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 684 insertions(+), 0 deletions(-)
create mode 100644 drivers/rtc/rtc-davinci.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 6a13037..50ac047 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -620,6 +620,16 @@ config RTC_DRV_NUC900
comment "on-CPU RTC drivers"
+config RTC_DRV_DAVINCI
+ tristate "TI DaVinci RTC"
+ depends on ARCH_DAVINCI_DM365
+ help
+ If you say yes here you get support for the RTC on the
+ DaVinci platforms (DM365).
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-davinci.
+
config RTC_DRV_OMAP
tristate "TI OMAP1"
depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 44ef194..245311a 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_RTC_DRV_BQ32K) += rtc-bq32k.o
obj-$(CONFIG_RTC_DRV_BQ4802) += rtc-bq4802.o
obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o
obj-$(CONFIG_RTC_DRV_COH901331) += rtc-coh901331.o
+obj-$(CONFIG_RTC_DRV_DAVINCI) += rtc-davinci.o
obj-$(CONFIG_RTC_DRV_DM355EVM) += rtc-dm355evm.o
obj-$(CONFIG_RTC_DRV_DS1216) += rtc-ds1216.o
obj-$(CONFIG_RTC_DRV_DS1286) += rtc-ds1286.o
diff --git a/drivers/rtc/rtc-davinci.c b/drivers/rtc/rtc-davinci.c
new file mode 100644
index 0000000..92a8f6c
--- /dev/null
+++ b/drivers/rtc/rtc-davinci.c
@@ -0,0 +1,673 @@
+/*
+ * DaVinci Power Management and Real Time Clock Driver for TI platforms
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc
+ *
+ * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/rtc.h>
+#include <linux/bcd.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+/*
+ * The DaVinci RTC is a simple RTC with the following
+ * Sec: 0 - 59 : BCD count
+ * Min: 0 - 59 : BCD count
+ * Hour: 0 - 23 : BCD count
+ * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
+ */
+
+/* PRTC interface registers */
+#define DAVINCI_PRTCIF_PID 0x00
+#define PRTCIF_CTLR 0x04
+#define PRTCIF_LDATA 0x08
+#define PRTCIF_UDATA 0x0C
+#define PRTCIF_INTEN 0x10
+#define PRTCIF_INTFLG 0x14
+
+/* PRTCIF_CTLR bit fields */
+#define PRTCIF_CTLR_BUSY BIT(31)
+#define PRTCIF_CTLR_SIZE BIT(25)
+#define PRTCIF_CTLR_DIR BIT(24)
+#define PRTCIF_CTLR_BENU_MSB BIT(23)
+#define PRTCIF_CTLR_BENU_3RD_BYTE BIT(22)
+#define PRTCIF_CTLR_BENU_2ND_BYTE BIT(21)
+#define PRTCIF_CTLR_BENU_LSB BIT(20)
+#define PRTCIF_CTLR_BENU_MASK (0x00F00000)
+#define PRTCIF_CTLR_BENL_MSB BIT(19)
+#define PRTCIF_CTLR_BENL_3RD_BYTE BIT(18)
+#define PRTCIF_CTLR_BENL_2ND_BYTE BIT(17)
+#define PRTCIF_CTLR_BENL_LSB BIT(16)
+#define PRTCIF_CTLR_BENL_MASK (0x000F0000)
+
+/* PRTCIF_INTEN bit fields */
+#define PRTCIF_INTEN_RTCSS BIT(1)
+#define PRTCIF_INTEN_RTCIF BIT(0)
+#define PRTCIF_INTEN_MASK (PRTCIF_INTEN_RTCSS \
+ | PRTCIF_INTEN_RTCIF)
+
+/* PRTCIF_INTFLG bit fields */
+#define PRTCIF_INTFLG_RTCSS BIT(1)
+#define PRTCIF_INTFLG_RTCIF BIT(0)
+#define PRTCIF_INTFLG_MASK (PRTCIF_INTFLG_RTCSS \
+ | PRTCIF_INTFLG_RTCIF)
+
+/* PRTC subsystem registers */
+#define PRTCSS_RTC_INTC_EXTENA1 (0x0C)
+#define PRTCSS_RTC_CTRL (0x10)
+#define PRTCSS_RTC_WDT (0x11)
+#define PRTCSS_RTC_TMR0 (0x12)
+#define PRTCSS_RTC_TMR1 (0x13)
+#define PRTCSS_RTC_CCTRL (0x14)
+#define PRTCSS_RTC_SEC (0x15)
+#define PRTCSS_RTC_MIN (0x16)
+#define PRTCSS_RTC_HOUR (0x17)
+#define PRTCSS_RTC_DAY0 (0x18)
+#define PRTCSS_RTC_DAY1 (0x19)
+#define PRTCSS_RTC_AMIN (0x1A)
+#define PRTCSS_RTC_AHOUR (0x1B)
+#define PRTCSS_RTC_ADAY0 (0x1C)
+#define PRTCSS_RTC_ADAY1 (0x1D)
+#define PRTCSS_RTC_CLKC_CNT (0x20)
+
+/* PRTCSS_RTC_INTC_EXTENA1 */
+#define PRTCSS_RTC_INTC_EXTENA1_MASK (0x07)
+
+/* PRTCSS_RTC_CTRL bit fields */
+#define PRTCSS_RTC_CTRL_WDTBUS BIT(7)
+#define PRTCSS_RTC_CTRL_WEN BIT(6)
+#define PRTCSS_RTC_CTRL_WDRT BIT(5)
+#define PRTCSS_RTC_CTRL_WDTFLG BIT(4)
+#define PRTCSS_RTC_CTRL_TE BIT(3)
+#define PRTCSS_RTC_CTRL_TIEN BIT(2)
+#define PRTCSS_RTC_CTRL_TMRFLG BIT(1)
+#define PRTCSS_RTC_CTRL_TMMD BIT(0)
+
+/* PRTCSS_RTC_CCTRL bit fields */
+#define PRTCSS_RTC_CCTRL_CALBUSY BIT(7)
+#define PRTCSS_RTC_CCTRL_DAEN BIT(5)
+#define PRTCSS_RTC_CCTRL_HAEN BIT(4)
+#define PRTCSS_RTC_CCTRL_MAEN BIT(3)
+#define PRTCSS_RTC_CCTRL_ALMFLG BIT(2)
+#define PRTCSS_RTC_CCTRL_AIEN BIT(1)
+#define PRTCSS_RTC_CCTRL_CAEN BIT(0)
+
+static DEFINE_SPINLOCK(davinci_rtc_lock);
+
+struct davinci_rtc {
+ struct rtc_device *rtc;
+ void __iomem *base;
+ resource_size_t pbase;
+ size_t base_size;
+ int irq;
+};
+
+static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
+ u32 val, u32 addr)
+{
+ writel(val, davinci_rtc->base + addr);
+}
+
+static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
+{
+ return readl(davinci_rtc->base + addr);
+}
+
+static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
+{
+ while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
+ cpu_relax();
+}
+
+static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
+ unsigned long val, u8 addr)
+{
+ rtcif_wait(davinci_rtc);
+
+ rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
+ rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
+
+ rtcif_wait(davinci_rtc);
+}
+
+static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
+{
+ rtcif_wait(davinci_rtc);
+
+ rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
+ PRTCIF_CTLR);
+
+ rtcif_wait(davinci_rtc);
+
+ return rtcif_read(davinci_rtc, PRTCIF_LDATA);
+}
+
+static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
+{
+ while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
+ PRTCSS_RTC_CCTRL_CALBUSY)
+ cpu_relax();
+}
+
+static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
+{
+ struct davinci_rtc *davinci_rtc = class_dev;
+ unsigned long events = 0;
+ u32 irq_flg;
+ u8 alm_irq, tmr_irq;
+ u8 rtc_ctrl, rtc_cctrl;
+ int ret = IRQ_NONE;
+
+ irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
+ PRTCIF_INTFLG_RTCSS;
+
+ alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
+ PRTCSS_RTC_CCTRL_ALMFLG;
+
+ tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
+ PRTCSS_RTC_CTRL_TMRFLG;
+
+ if (irq_flg) {
+ if (alm_irq) {
+ events |= RTC_IRQF | RTC_AF;
+ rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
+ rtc_cctrl |= PRTCSS_RTC_CCTRL_ALMFLG;
+ rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
+ } else if (tmr_irq) {
+ events |= RTC_IRQF | RTC_PF;
+ rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
+ rtc_ctrl |= PRTCSS_RTC_CTRL_TMRFLG;
+ rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
+ }
+
+ rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
+ PRTCIF_INTFLG);
+ rtc_update_irq(davinci_rtc->rtc, 1, events);
+
+ ret = IRQ_HANDLED;
+ }
+
+ return ret;
+}
+
+static int
+davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
+{
+ struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+ u8 rtc_ctrl;
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+ rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
+
+ switch (cmd) {
+ case RTC_WIE_ON:
+ rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
+ break;
+ case RTC_WIE_OFF:
+ rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
+ break;
+ case RTC_UIE_OFF:
+ case RTC_UIE_ON:
+ ret = -ENOTTY;
+ break;
+ default:
+ ret = -ENOIOCTLCMD;
+ }
+
+ rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
+
+ spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+ return ret;
+}
+
+static int convertfromdays(u16 days, struct rtc_time *tm)
+{
+ int tmp_days, year, mon;
+
+ for (year = 2000;; year++) {
+ tmp_days = rtc_year_days(1, 12, year);
+ if (days >= tmp_days)
+ days -= tmp_days;
+ else {
+ for (mon = 0;; mon++) {
+ tmp_days = rtc_month_days(mon, year);
+ if (days >= tmp_days) {
+ days -= tmp_days;
+ } else {
+ tm->tm_year = year - 1900;
+ tm->tm_mon = mon;
+ tm->tm_mday = days + 1;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ return 0;
+}
+
+static int convert2days(u16 *days, struct rtc_time *tm)
+{
+ int i;
+ *days = 0;
+
+ /* epoch == 1900 */
+ if (tm->tm_year < 100 || tm->tm_year > 199)
+ return -EINVAL;
+
+ for (i = 2000; i < 1900 + tm->tm_year; i++)
+ *days += rtc_year_days(1, 12, i);
+
+ *days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
+
+ return 0;
+}
+
+static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+ u16 days = 0;
+ u8 day0, day1;
+ unsigned long flags;
+
+ spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
+
+ spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+ days |= day1;
+ days <<= 8;
+ days |= day0;
+
+ if (convertfromdays(days, tm) < 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+ struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+ u16 days;
+ u8 rtc_cctrl;
+ unsigned long flags;
+
+ if (convert2days(&days, tm) < 0)
+ return -EINVAL;
+
+ spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
+
+ rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
+ rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
+ rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
+
+ spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+ return 0;
+}
+
+static int davinci_rtc_alarm_irq_enable(struct device *dev,
+ unsigned int enabled)
+{
+ struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+ unsigned long flags;
+ u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
+
+ spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+ if (enabled)
+ rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
+ PRTCSS_RTC_CCTRL_HAEN |
+ PRTCSS_RTC_CCTRL_MAEN |
+ PRTCSS_RTC_CCTRL_ALMFLG |
+ PRTCSS_RTC_CCTRL_AIEN;
+ else
+ rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
+
+ spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+ return 0;
+}
+
+static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
+{
+ struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+ u16 days = 0;
+ u8 day0, day1;
+ unsigned long flags;
+
+ spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
+
+ spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+ days |= day1;
+ days <<= 8;
+ days |= day0;
+
+ if (convertfromdays(days, &alm->time) < 0)
+ return -EINVAL;
+
+ alm->pending = !!(rtcss_read(davinci_rtc,
+ PRTCSS_RTC_CCTRL) &
+ PRTCSS_RTC_CCTRL_AIEN);
+ alm->enabled = alm->pending && device_may_wakeup(dev);
+
+ return 0;
+}
+
+static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
+{
+ struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+ unsigned long flags;
+ u16 days;
+
+ if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0
+ && alm->time.tm_year < 0) {
+ struct rtc_time tm;
+ unsigned long now, then;
+
+ davinci_rtc_read_time(dev, &tm);
+ rtc_tm_to_time(&tm, &now);
+
+ alm->time.tm_mday = tm.tm_mday;
+ alm->time.tm_mon = tm.tm_mon;
+ alm->time.tm_year = tm.tm_year;
+ rtc_tm_to_time(&alm->time, &then);
+
+ if (then < now) {
+ rtc_time_to_tm(now + 24 * 60 * 60, &tm);
+ alm->time.tm_mday = tm.tm_mday;
+ alm->time.tm_mon = tm.tm_mon;
+ alm->time.tm_year = tm.tm_year;
+ }
+ }
+
+ if (convert2days(&days, &alm->time) < 0)
+ return -EINVAL;
+
+ spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
+
+ davinci_rtcss_calendar_wait(davinci_rtc);
+ rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
+
+ spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+ return 0;
+}
+
+static int davinci_rtc_irq_set_state(struct device *dev, int enabled)
+{
+ struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+ unsigned long flags;
+ u8 rtc_ctrl;
+
+ spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+ rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
+
+ if (enabled) {
+ while (rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL)
+ & PRTCSS_RTC_CTRL_WDTBUS)
+ cpu_relax();
+
+ rtc_ctrl |= PRTCSS_RTC_CTRL_TE;
+ rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
+
+ rtcss_write(davinci_rtc, 0x0, PRTCSS_RTC_CLKC_CNT);
+
+ rtc_ctrl |= PRTCSS_RTC_CTRL_TIEN |
+ PRTCSS_RTC_CTRL_TMMD |
+ PRTCSS_RTC_CTRL_TMRFLG;
+ } else
+ rtc_ctrl &= ~PRTCSS_RTC_CTRL_TIEN;
+
+ rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
+
+ spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+ return 0;
+}
+
+static int davinci_rtc_irq_set_freq(struct device *dev, int freq)
+{
+ struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+ unsigned long flags;
+ u16 tmr_counter = (0x8000 >> (ffs(freq) - 1));
+
+ spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+ rtcss_write(davinci_rtc, tmr_counter & 0xFF, PRTCSS_RTC_TMR0);
+ rtcss_write(davinci_rtc, (tmr_counter & 0xFF00) >> 8, PRTCSS_RTC_TMR1);
+
+ spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+ return 0;
+}
+
+static struct rtc_class_ops davinci_rtc_ops = {
+ .ioctl = davinci_rtc_ioctl,
+ .read_time = davinci_rtc_read_time,
+ .set_time = davinci_rtc_set_time,
+ .alarm_irq_enable = davinci_rtc_alarm_irq_enable,
+ .read_alarm = davinci_rtc_read_alarm,
+ .set_alarm = davinci_rtc_set_alarm,
+ .irq_set_state = davinci_rtc_irq_set_state,
+ .irq_set_freq = davinci_rtc_irq_set_freq,
+};
+
+static int __init davinci_rtc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct davinci_rtc *davinci_rtc;
+ struct resource *res, *mem;
+ int ret = 0;
+
+ davinci_rtc = kzalloc(sizeof(struct davinci_rtc), GFP_KERNEL);
+ if (!davinci_rtc) {
+ dev_dbg(dev, "could not allocate memory for private data\n");
+ return -ENOMEM;
+ }
+
+ davinci_rtc->irq = platform_get_irq(pdev, 0);
+ if (davinci_rtc->irq < 0) {
+ dev_err(dev, "no RTC irq\n");
+ ret = davinci_rtc->irq;
+ goto fail1;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "no mem resource\n");
+ ret = -EINVAL;
+ goto fail1;
+ }
+
+ davinci_rtc->pbase = res->start;
+ davinci_rtc->base_size = resource_size(res);
+
+ mem = request_mem_region(davinci_rtc->pbase, davinci_rtc->base_size,
+ pdev->name);
+ if (!mem) {
+ dev_err(dev, "RTC registers at %08x are not free\n",
+ davinci_rtc->pbase);
+ ret = -EBUSY;
+ goto fail1;
+ }
+
+ davinci_rtc->base = ioremap(davinci_rtc->pbase, davinci_rtc->base_size);
+ if (!davinci_rtc->base) {
+ dev_err(dev, "unable to ioremap MEM resource\n");
+ ret = -ENOMEM;
+ goto fail2;
+ }
+
+ davinci_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
+ &davinci_rtc_ops, THIS_MODULE);
+ if (IS_ERR(davinci_rtc->rtc)) {
+ dev_err(dev, "unable to register RTC device, err %ld\n",
+ PTR_ERR(davinci_rtc->rtc));
+ goto fail3;
+ }
+
+ rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
+ rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
+ rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
+
+ rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
+ rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
+
+ ret = request_irq(davinci_rtc->irq, davinci_rtc_interrupt,
+ IRQF_DISABLED, "davinci_rtc", davinci_rtc);
+ if (ret < 0) {
+ dev_err(dev, "unable to register davinci RTC interrupt\n");
+ goto fail4;
+ }
+
+ /* Enable interrupts */
+ rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
+ rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
+ PRTCSS_RTC_INTC_EXTENA1);
+
+ rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
+
+ platform_set_drvdata(pdev, davinci_rtc);
+
+ device_init_wakeup(&pdev->dev, 0);
+
+ return 0;
+
+fail4:
+ rtc_device_unregister(davinci_rtc->rtc);
+fail3:
+ iounmap(davinci_rtc->base);
+fail2:
+ release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
+fail1:
+ kfree(davinci_rtc);
+
+ return ret;
+}
+
+static int __devexit davinci_rtc_remove(struct platform_device *pdev)
+{
+ struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
+
+ device_init_wakeup(&pdev->dev, 0);
+
+ rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
+
+ free_irq(davinci_rtc->irq, davinci_rtc);
+
+ rtc_device_unregister(davinci_rtc->rtc);
+
+ iounmap(davinci_rtc->base);
+ release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
+
+ platform_set_drvdata(pdev, NULL);
+
+ kfree(davinci_rtc);
+
+ return 0;
+}
+
+static struct platform_driver davinci_rtc_driver = {
+ .probe = davinci_rtc_probe,
+ .remove = __devexit_p(davinci_rtc_remove),
+ .driver = {
+ .name = "rtc_davinci",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init rtc_init(void)
+{
+ return platform_driver_probe(&davinci_rtc_driver, davinci_rtc_probe);
+}
+module_init(rtc_init);
+
+static void __exit rtc_exit(void)
+{
+ platform_driver_unregister(&davinci_rtc_driver);
+}
+module_exit(rtc_exit);
+
+MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar@ridgerun.com>");
+MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
+MODULE_LICENSE("GPL");
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 06/34] RTC: DaVinci RTC driver
2010-05-06 23:23 ` [PATCH 06/34] RTC: DaVinci RTC driver Kevin Hilman
@ 2010-05-13 9:15 ` Russell King - ARM Linux
2010-05-13 13:44 ` Kevin Hilman
0 siblings, 1 reply; 38+ messages in thread
From: Russell King - ARM Linux @ 2010-05-13 9:15 UTC (permalink / raw)
To: linux-arm-kernel
This should also go to the RTC people.
On Thu, May 06, 2010 at 04:23:57PM -0700, Kevin Hilman wrote:
> From: Miguel Aguilar <miguel.aguilar@ridgerun.com>
>
> This driver features:
>
> * Alarm support.
> * Periodic interrupt by using a timer include into the RTC module.
> * The update interrupt is not supported by this RTC module.
>
> This driver was tested on a DM365 EVM by using the rtc-test application
> from the Documentation/rtc.txt.
>
> Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com>
> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
> Acked-by: Alessandro Zummo <a.zummo@towertech.it>
> ---
> drivers/rtc/Kconfig | 10 +
> drivers/rtc/Makefile | 1 +
> drivers/rtc/rtc-davinci.c | 673 +++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 684 insertions(+), 0 deletions(-)
> create mode 100644 drivers/rtc/rtc-davinci.c
>
> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
> index 6a13037..50ac047 100644
> --- a/drivers/rtc/Kconfig
> +++ b/drivers/rtc/Kconfig
> @@ -620,6 +620,16 @@ config RTC_DRV_NUC900
>
> comment "on-CPU RTC drivers"
>
> +config RTC_DRV_DAVINCI
> + tristate "TI DaVinci RTC"
> + depends on ARCH_DAVINCI_DM365
> + help
> + If you say yes here you get support for the RTC on the
> + DaVinci platforms (DM365).
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-davinci.
> +
> config RTC_DRV_OMAP
> tristate "TI OMAP1"
> depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX
> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
> index 44ef194..245311a 100644
> --- a/drivers/rtc/Makefile
> +++ b/drivers/rtc/Makefile
> @@ -27,6 +27,7 @@ obj-$(CONFIG_RTC_DRV_BQ32K) += rtc-bq32k.o
> obj-$(CONFIG_RTC_DRV_BQ4802) += rtc-bq4802.o
> obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o
> obj-$(CONFIG_RTC_DRV_COH901331) += rtc-coh901331.o
> +obj-$(CONFIG_RTC_DRV_DAVINCI) += rtc-davinci.o
> obj-$(CONFIG_RTC_DRV_DM355EVM) += rtc-dm355evm.o
> obj-$(CONFIG_RTC_DRV_DS1216) += rtc-ds1216.o
> obj-$(CONFIG_RTC_DRV_DS1286) += rtc-ds1286.o
> diff --git a/drivers/rtc/rtc-davinci.c b/drivers/rtc/rtc-davinci.c
> new file mode 100644
> index 0000000..92a8f6c
> --- /dev/null
> +++ b/drivers/rtc/rtc-davinci.c
> @@ -0,0 +1,673 @@
> +/*
> + * DaVinci Power Management and Real Time Clock Driver for TI platforms
> + *
> + * Copyright (C) 2009 Texas Instruments, Inc
> + *
> + * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + */
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/ioport.h>
> +#include <linux/delay.h>
> +#include <linux/spinlock.h>
> +#include <linux/rtc.h>
> +#include <linux/bcd.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +/*
> + * The DaVinci RTC is a simple RTC with the following
> + * Sec: 0 - 59 : BCD count
> + * Min: 0 - 59 : BCD count
> + * Hour: 0 - 23 : BCD count
> + * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
> + */
> +
> +/* PRTC interface registers */
> +#define DAVINCI_PRTCIF_PID 0x00
> +#define PRTCIF_CTLR 0x04
> +#define PRTCIF_LDATA 0x08
> +#define PRTCIF_UDATA 0x0C
> +#define PRTCIF_INTEN 0x10
> +#define PRTCIF_INTFLG 0x14
> +
> +/* PRTCIF_CTLR bit fields */
> +#define PRTCIF_CTLR_BUSY BIT(31)
> +#define PRTCIF_CTLR_SIZE BIT(25)
> +#define PRTCIF_CTLR_DIR BIT(24)
> +#define PRTCIF_CTLR_BENU_MSB BIT(23)
> +#define PRTCIF_CTLR_BENU_3RD_BYTE BIT(22)
> +#define PRTCIF_CTLR_BENU_2ND_BYTE BIT(21)
> +#define PRTCIF_CTLR_BENU_LSB BIT(20)
> +#define PRTCIF_CTLR_BENU_MASK (0x00F00000)
> +#define PRTCIF_CTLR_BENL_MSB BIT(19)
> +#define PRTCIF_CTLR_BENL_3RD_BYTE BIT(18)
> +#define PRTCIF_CTLR_BENL_2ND_BYTE BIT(17)
> +#define PRTCIF_CTLR_BENL_LSB BIT(16)
> +#define PRTCIF_CTLR_BENL_MASK (0x000F0000)
> +
> +/* PRTCIF_INTEN bit fields */
> +#define PRTCIF_INTEN_RTCSS BIT(1)
> +#define PRTCIF_INTEN_RTCIF BIT(0)
> +#define PRTCIF_INTEN_MASK (PRTCIF_INTEN_RTCSS \
> + | PRTCIF_INTEN_RTCIF)
> +
> +/* PRTCIF_INTFLG bit fields */
> +#define PRTCIF_INTFLG_RTCSS BIT(1)
> +#define PRTCIF_INTFLG_RTCIF BIT(0)
> +#define PRTCIF_INTFLG_MASK (PRTCIF_INTFLG_RTCSS \
> + | PRTCIF_INTFLG_RTCIF)
> +
> +/* PRTC subsystem registers */
> +#define PRTCSS_RTC_INTC_EXTENA1 (0x0C)
> +#define PRTCSS_RTC_CTRL (0x10)
> +#define PRTCSS_RTC_WDT (0x11)
> +#define PRTCSS_RTC_TMR0 (0x12)
> +#define PRTCSS_RTC_TMR1 (0x13)
> +#define PRTCSS_RTC_CCTRL (0x14)
> +#define PRTCSS_RTC_SEC (0x15)
> +#define PRTCSS_RTC_MIN (0x16)
> +#define PRTCSS_RTC_HOUR (0x17)
> +#define PRTCSS_RTC_DAY0 (0x18)
> +#define PRTCSS_RTC_DAY1 (0x19)
> +#define PRTCSS_RTC_AMIN (0x1A)
> +#define PRTCSS_RTC_AHOUR (0x1B)
> +#define PRTCSS_RTC_ADAY0 (0x1C)
> +#define PRTCSS_RTC_ADAY1 (0x1D)
> +#define PRTCSS_RTC_CLKC_CNT (0x20)
> +
> +/* PRTCSS_RTC_INTC_EXTENA1 */
> +#define PRTCSS_RTC_INTC_EXTENA1_MASK (0x07)
> +
> +/* PRTCSS_RTC_CTRL bit fields */
> +#define PRTCSS_RTC_CTRL_WDTBUS BIT(7)
> +#define PRTCSS_RTC_CTRL_WEN BIT(6)
> +#define PRTCSS_RTC_CTRL_WDRT BIT(5)
> +#define PRTCSS_RTC_CTRL_WDTFLG BIT(4)
> +#define PRTCSS_RTC_CTRL_TE BIT(3)
> +#define PRTCSS_RTC_CTRL_TIEN BIT(2)
> +#define PRTCSS_RTC_CTRL_TMRFLG BIT(1)
> +#define PRTCSS_RTC_CTRL_TMMD BIT(0)
> +
> +/* PRTCSS_RTC_CCTRL bit fields */
> +#define PRTCSS_RTC_CCTRL_CALBUSY BIT(7)
> +#define PRTCSS_RTC_CCTRL_DAEN BIT(5)
> +#define PRTCSS_RTC_CCTRL_HAEN BIT(4)
> +#define PRTCSS_RTC_CCTRL_MAEN BIT(3)
> +#define PRTCSS_RTC_CCTRL_ALMFLG BIT(2)
> +#define PRTCSS_RTC_CCTRL_AIEN BIT(1)
> +#define PRTCSS_RTC_CCTRL_CAEN BIT(0)
> +
> +static DEFINE_SPINLOCK(davinci_rtc_lock);
> +
> +struct davinci_rtc {
> + struct rtc_device *rtc;
> + void __iomem *base;
> + resource_size_t pbase;
> + size_t base_size;
> + int irq;
> +};
> +
> +static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
> + u32 val, u32 addr)
> +{
> + writel(val, davinci_rtc->base + addr);
> +}
> +
> +static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
> +{
> + return readl(davinci_rtc->base + addr);
> +}
> +
> +static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
> +{
> + while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
> + cpu_relax();
> +}
> +
> +static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
> + unsigned long val, u8 addr)
> +{
> + rtcif_wait(davinci_rtc);
> +
> + rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
> + rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
> +
> + rtcif_wait(davinci_rtc);
> +}
> +
> +static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
> +{
> + rtcif_wait(davinci_rtc);
> +
> + rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
> + PRTCIF_CTLR);
> +
> + rtcif_wait(davinci_rtc);
> +
> + return rtcif_read(davinci_rtc, PRTCIF_LDATA);
> +}
> +
> +static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
> +{
> + while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
> + PRTCSS_RTC_CCTRL_CALBUSY)
> + cpu_relax();
> +}
> +
> +static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
> +{
> + struct davinci_rtc *davinci_rtc = class_dev;
> + unsigned long events = 0;
> + u32 irq_flg;
> + u8 alm_irq, tmr_irq;
> + u8 rtc_ctrl, rtc_cctrl;
> + int ret = IRQ_NONE;
> +
> + irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
> + PRTCIF_INTFLG_RTCSS;
> +
> + alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
> + PRTCSS_RTC_CCTRL_ALMFLG;
> +
> + tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
> + PRTCSS_RTC_CTRL_TMRFLG;
> +
> + if (irq_flg) {
> + if (alm_irq) {
> + events |= RTC_IRQF | RTC_AF;
> + rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
> + rtc_cctrl |= PRTCSS_RTC_CCTRL_ALMFLG;
> + rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
> + } else if (tmr_irq) {
> + events |= RTC_IRQF | RTC_PF;
> + rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
> + rtc_ctrl |= PRTCSS_RTC_CTRL_TMRFLG;
> + rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
> + }
> +
> + rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
> + PRTCIF_INTFLG);
> + rtc_update_irq(davinci_rtc->rtc, 1, events);
> +
> + ret = IRQ_HANDLED;
> + }
> +
> + return ret;
> +}
> +
> +static int
> +davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
> +{
> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> + u8 rtc_ctrl;
> + unsigned long flags;
> + int ret = 0;
> +
> + spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> + rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
> +
> + switch (cmd) {
> + case RTC_WIE_ON:
> + rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
> + break;
> + case RTC_WIE_OFF:
> + rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
> + break;
> + case RTC_UIE_OFF:
> + case RTC_UIE_ON:
> + ret = -ENOTTY;
> + break;
> + default:
> + ret = -ENOIOCTLCMD;
> + }
> +
> + rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
> +
> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +
> + return ret;
> +}
> +
> +static int convertfromdays(u16 days, struct rtc_time *tm)
> +{
> + int tmp_days, year, mon;
> +
> + for (year = 2000;; year++) {
> + tmp_days = rtc_year_days(1, 12, year);
> + if (days >= tmp_days)
> + days -= tmp_days;
> + else {
> + for (mon = 0;; mon++) {
> + tmp_days = rtc_month_days(mon, year);
> + if (days >= tmp_days) {
> + days -= tmp_days;
> + } else {
> + tm->tm_year = year - 1900;
> + tm->tm_mon = mon;
> + tm->tm_mday = days + 1;
> + break;
> + }
> + }
> + break;
> + }
> + }
> + return 0;
> +}
> +
> +static int convert2days(u16 *days, struct rtc_time *tm)
> +{
> + int i;
> + *days = 0;
> +
> + /* epoch == 1900 */
> + if (tm->tm_year < 100 || tm->tm_year > 199)
> + return -EINVAL;
> +
> + for (i = 2000; i < 1900 + tm->tm_year; i++)
> + *days += rtc_year_days(1, 12, i);
> +
> + *days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
> +
> + return 0;
> +}
> +
> +static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
> +{
> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> + u16 days = 0;
> + u8 day0, day1;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
> +
> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +
> + days |= day1;
> + days <<= 8;
> + days |= day0;
> +
> + if (convertfromdays(days, tm) < 0)
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
> +{
> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> + u16 days;
> + u8 rtc_cctrl;
> + unsigned long flags;
> +
> + if (convert2days(&days, tm) < 0)
> + return -EINVAL;
> +
> + spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
> +
> + rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
> + rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
> + rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
> +
> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +
> + return 0;
> +}
> +
> +static int davinci_rtc_alarm_irq_enable(struct device *dev,
> + unsigned int enabled)
> +{
> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> + unsigned long flags;
> + u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
> +
> + spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> + if (enabled)
> + rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
> + PRTCSS_RTC_CCTRL_HAEN |
> + PRTCSS_RTC_CCTRL_MAEN |
> + PRTCSS_RTC_CCTRL_ALMFLG |
> + PRTCSS_RTC_CCTRL_AIEN;
> + else
> + rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
> +
> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +
> + return 0;
> +}
> +
> +static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
> +{
> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> + u16 days = 0;
> + u8 day0, day1;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
> +
> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> + days |= day1;
> + days <<= 8;
> + days |= day0;
> +
> + if (convertfromdays(days, &alm->time) < 0)
> + return -EINVAL;
> +
> + alm->pending = !!(rtcss_read(davinci_rtc,
> + PRTCSS_RTC_CCTRL) &
> + PRTCSS_RTC_CCTRL_AIEN);
> + alm->enabled = alm->pending && device_may_wakeup(dev);
> +
> + return 0;
> +}
> +
> +static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
> +{
> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> + unsigned long flags;
> + u16 days;
> +
> + if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0
> + && alm->time.tm_year < 0) {
> + struct rtc_time tm;
> + unsigned long now, then;
> +
> + davinci_rtc_read_time(dev, &tm);
> + rtc_tm_to_time(&tm, &now);
> +
> + alm->time.tm_mday = tm.tm_mday;
> + alm->time.tm_mon = tm.tm_mon;
> + alm->time.tm_year = tm.tm_year;
> + rtc_tm_to_time(&alm->time, &then);
> +
> + if (then < now) {
> + rtc_time_to_tm(now + 24 * 60 * 60, &tm);
> + alm->time.tm_mday = tm.tm_mday;
> + alm->time.tm_mon = tm.tm_mon;
> + alm->time.tm_year = tm.tm_year;
> + }
> + }
> +
> + if (convert2days(&days, &alm->time) < 0)
> + return -EINVAL;
> +
> + spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
> +
> + davinci_rtcss_calendar_wait(davinci_rtc);
> + rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
> +
> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +
> + return 0;
> +}
> +
> +static int davinci_rtc_irq_set_state(struct device *dev, int enabled)
> +{
> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> + unsigned long flags;
> + u8 rtc_ctrl;
> +
> + spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> + rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
> +
> + if (enabled) {
> + while (rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL)
> + & PRTCSS_RTC_CTRL_WDTBUS)
> + cpu_relax();
> +
> + rtc_ctrl |= PRTCSS_RTC_CTRL_TE;
> + rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
> +
> + rtcss_write(davinci_rtc, 0x0, PRTCSS_RTC_CLKC_CNT);
> +
> + rtc_ctrl |= PRTCSS_RTC_CTRL_TIEN |
> + PRTCSS_RTC_CTRL_TMMD |
> + PRTCSS_RTC_CTRL_TMRFLG;
> + } else
> + rtc_ctrl &= ~PRTCSS_RTC_CTRL_TIEN;
> +
> + rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
> +
> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +
> + return 0;
> +}
> +
> +static int davinci_rtc_irq_set_freq(struct device *dev, int freq)
> +{
> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> + unsigned long flags;
> + u16 tmr_counter = (0x8000 >> (ffs(freq) - 1));
> +
> + spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> + rtcss_write(davinci_rtc, tmr_counter & 0xFF, PRTCSS_RTC_TMR0);
> + rtcss_write(davinci_rtc, (tmr_counter & 0xFF00) >> 8, PRTCSS_RTC_TMR1);
> +
> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +
> + return 0;
> +}
> +
> +static struct rtc_class_ops davinci_rtc_ops = {
> + .ioctl = davinci_rtc_ioctl,
> + .read_time = davinci_rtc_read_time,
> + .set_time = davinci_rtc_set_time,
> + .alarm_irq_enable = davinci_rtc_alarm_irq_enable,
> + .read_alarm = davinci_rtc_read_alarm,
> + .set_alarm = davinci_rtc_set_alarm,
> + .irq_set_state = davinci_rtc_irq_set_state,
> + .irq_set_freq = davinci_rtc_irq_set_freq,
> +};
> +
> +static int __init davinci_rtc_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct davinci_rtc *davinci_rtc;
> + struct resource *res, *mem;
> + int ret = 0;
> +
> + davinci_rtc = kzalloc(sizeof(struct davinci_rtc), GFP_KERNEL);
> + if (!davinci_rtc) {
> + dev_dbg(dev, "could not allocate memory for private data\n");
> + return -ENOMEM;
> + }
> +
> + davinci_rtc->irq = platform_get_irq(pdev, 0);
> + if (davinci_rtc->irq < 0) {
> + dev_err(dev, "no RTC irq\n");
> + ret = davinci_rtc->irq;
> + goto fail1;
> + }
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "no mem resource\n");
> + ret = -EINVAL;
> + goto fail1;
> + }
> +
> + davinci_rtc->pbase = res->start;
> + davinci_rtc->base_size = resource_size(res);
> +
> + mem = request_mem_region(davinci_rtc->pbase, davinci_rtc->base_size,
> + pdev->name);
> + if (!mem) {
> + dev_err(dev, "RTC registers at %08x are not free\n",
> + davinci_rtc->pbase);
> + ret = -EBUSY;
> + goto fail1;
> + }
> +
> + davinci_rtc->base = ioremap(davinci_rtc->pbase, davinci_rtc->base_size);
> + if (!davinci_rtc->base) {
> + dev_err(dev, "unable to ioremap MEM resource\n");
> + ret = -ENOMEM;
> + goto fail2;
> + }
> +
> + davinci_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
> + &davinci_rtc_ops, THIS_MODULE);
> + if (IS_ERR(davinci_rtc->rtc)) {
> + dev_err(dev, "unable to register RTC device, err %ld\n",
> + PTR_ERR(davinci_rtc->rtc));
> + goto fail3;
> + }
> +
> + rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
> + rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
> + rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
> +
> + rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
> + rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
> +
> + ret = request_irq(davinci_rtc->irq, davinci_rtc_interrupt,
> + IRQF_DISABLED, "davinci_rtc", davinci_rtc);
> + if (ret < 0) {
> + dev_err(dev, "unable to register davinci RTC interrupt\n");
> + goto fail4;
> + }
> +
> + /* Enable interrupts */
> + rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
> + rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
> + PRTCSS_RTC_INTC_EXTENA1);
> +
> + rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
> +
> + platform_set_drvdata(pdev, davinci_rtc);
> +
> + device_init_wakeup(&pdev->dev, 0);
> +
> + return 0;
> +
> +fail4:
> + rtc_device_unregister(davinci_rtc->rtc);
> +fail3:
> + iounmap(davinci_rtc->base);
> +fail2:
> + release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
> +fail1:
> + kfree(davinci_rtc);
> +
> + return ret;
> +}
> +
> +static int __devexit davinci_rtc_remove(struct platform_device *pdev)
> +{
> + struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
> +
> + device_init_wakeup(&pdev->dev, 0);
> +
> + rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
> +
> + free_irq(davinci_rtc->irq, davinci_rtc);
> +
> + rtc_device_unregister(davinci_rtc->rtc);
> +
> + iounmap(davinci_rtc->base);
> + release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
> +
> + platform_set_drvdata(pdev, NULL);
> +
> + kfree(davinci_rtc);
> +
> + return 0;
> +}
> +
> +static struct platform_driver davinci_rtc_driver = {
> + .probe = davinci_rtc_probe,
> + .remove = __devexit_p(davinci_rtc_remove),
> + .driver = {
> + .name = "rtc_davinci",
> + .owner = THIS_MODULE,
> + },
> +};
> +
> +static int __init rtc_init(void)
> +{
> + return platform_driver_probe(&davinci_rtc_driver, davinci_rtc_probe);
> +}
> +module_init(rtc_init);
> +
> +static void __exit rtc_exit(void)
> +{
> + platform_driver_unregister(&davinci_rtc_driver);
> +}
> +module_exit(rtc_exit);
> +
> +MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar@ridgerun.com>");
> +MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
> +MODULE_LICENSE("GPL");
> --
> 1.7.0.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 06/34] RTC: DaVinci RTC driver
2010-05-13 9:15 ` Russell King - ARM Linux
@ 2010-05-13 13:44 ` Kevin Hilman
0 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-13 13:44 UTC (permalink / raw)
To: linux-arm-kernel
Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
> This should also go to the RTC people.
Forgot the Cc here, but this has already been discussed ack'd by RTC folks
and agreed that it should merge via my tree.
Kevin
> On Thu, May 06, 2010 at 04:23:57PM -0700, Kevin Hilman wrote:
>> From: Miguel Aguilar <miguel.aguilar@ridgerun.com>
>>
>> This driver features:
>>
>> * Alarm support.
>> * Periodic interrupt by using a timer include into the RTC module.
>> * The update interrupt is not supported by this RTC module.
>>
>> This driver was tested on a DM365 EVM by using the rtc-test application
>> from the Documentation/rtc.txt.
>>
>> Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com>
>> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
>> Acked-by: Alessandro Zummo <a.zummo@towertech.it>
>> ---
>> drivers/rtc/Kconfig | 10 +
>> drivers/rtc/Makefile | 1 +
>> drivers/rtc/rtc-davinci.c | 673 +++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 684 insertions(+), 0 deletions(-)
>> create mode 100644 drivers/rtc/rtc-davinci.c
>>
>> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
>> index 6a13037..50ac047 100644
>> --- a/drivers/rtc/Kconfig
>> +++ b/drivers/rtc/Kconfig
>> @@ -620,6 +620,16 @@ config RTC_DRV_NUC900
>>
>> comment "on-CPU RTC drivers"
>>
>> +config RTC_DRV_DAVINCI
>> + tristate "TI DaVinci RTC"
>> + depends on ARCH_DAVINCI_DM365
>> + help
>> + If you say yes here you get support for the RTC on the
>> + DaVinci platforms (DM365).
>> +
>> + This driver can also be built as a module. If so, the module
>> + will be called rtc-davinci.
>> +
>> config RTC_DRV_OMAP
>> tristate "TI OMAP1"
>> depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX
>> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
>> index 44ef194..245311a 100644
>> --- a/drivers/rtc/Makefile
>> +++ b/drivers/rtc/Makefile
>> @@ -27,6 +27,7 @@ obj-$(CONFIG_RTC_DRV_BQ32K) += rtc-bq32k.o
>> obj-$(CONFIG_RTC_DRV_BQ4802) += rtc-bq4802.o
>> obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o
>> obj-$(CONFIG_RTC_DRV_COH901331) += rtc-coh901331.o
>> +obj-$(CONFIG_RTC_DRV_DAVINCI) += rtc-davinci.o
>> obj-$(CONFIG_RTC_DRV_DM355EVM) += rtc-dm355evm.o
>> obj-$(CONFIG_RTC_DRV_DS1216) += rtc-ds1216.o
>> obj-$(CONFIG_RTC_DRV_DS1286) += rtc-ds1286.o
>> diff --git a/drivers/rtc/rtc-davinci.c b/drivers/rtc/rtc-davinci.c
>> new file mode 100644
>> index 0000000..92a8f6c
>> --- /dev/null
>> +++ b/drivers/rtc/rtc-davinci.c
>> @@ -0,0 +1,673 @@
>> +/*
>> + * DaVinci Power Management and Real Time Clock Driver for TI platforms
>> + *
>> + * Copyright (C) 2009 Texas Instruments, Inc
>> + *
>> + * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
>> + */
>> +#include <linux/kernel.h>
>> +#include <linux/init.h>
>> +#include <linux/module.h>
>> +#include <linux/ioport.h>
>> +#include <linux/delay.h>
>> +#include <linux/spinlock.h>
>> +#include <linux/rtc.h>
>> +#include <linux/bcd.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/io.h>
>> +
>> +/*
>> + * The DaVinci RTC is a simple RTC with the following
>> + * Sec: 0 - 59 : BCD count
>> + * Min: 0 - 59 : BCD count
>> + * Hour: 0 - 23 : BCD count
>> + * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
>> + */
>> +
>> +/* PRTC interface registers */
>> +#define DAVINCI_PRTCIF_PID 0x00
>> +#define PRTCIF_CTLR 0x04
>> +#define PRTCIF_LDATA 0x08
>> +#define PRTCIF_UDATA 0x0C
>> +#define PRTCIF_INTEN 0x10
>> +#define PRTCIF_INTFLG 0x14
>> +
>> +/* PRTCIF_CTLR bit fields */
>> +#define PRTCIF_CTLR_BUSY BIT(31)
>> +#define PRTCIF_CTLR_SIZE BIT(25)
>> +#define PRTCIF_CTLR_DIR BIT(24)
>> +#define PRTCIF_CTLR_BENU_MSB BIT(23)
>> +#define PRTCIF_CTLR_BENU_3RD_BYTE BIT(22)
>> +#define PRTCIF_CTLR_BENU_2ND_BYTE BIT(21)
>> +#define PRTCIF_CTLR_BENU_LSB BIT(20)
>> +#define PRTCIF_CTLR_BENU_MASK (0x00F00000)
>> +#define PRTCIF_CTLR_BENL_MSB BIT(19)
>> +#define PRTCIF_CTLR_BENL_3RD_BYTE BIT(18)
>> +#define PRTCIF_CTLR_BENL_2ND_BYTE BIT(17)
>> +#define PRTCIF_CTLR_BENL_LSB BIT(16)
>> +#define PRTCIF_CTLR_BENL_MASK (0x000F0000)
>> +
>> +/* PRTCIF_INTEN bit fields */
>> +#define PRTCIF_INTEN_RTCSS BIT(1)
>> +#define PRTCIF_INTEN_RTCIF BIT(0)
>> +#define PRTCIF_INTEN_MASK (PRTCIF_INTEN_RTCSS \
>> + | PRTCIF_INTEN_RTCIF)
>> +
>> +/* PRTCIF_INTFLG bit fields */
>> +#define PRTCIF_INTFLG_RTCSS BIT(1)
>> +#define PRTCIF_INTFLG_RTCIF BIT(0)
>> +#define PRTCIF_INTFLG_MASK (PRTCIF_INTFLG_RTCSS \
>> + | PRTCIF_INTFLG_RTCIF)
>> +
>> +/* PRTC subsystem registers */
>> +#define PRTCSS_RTC_INTC_EXTENA1 (0x0C)
>> +#define PRTCSS_RTC_CTRL (0x10)
>> +#define PRTCSS_RTC_WDT (0x11)
>> +#define PRTCSS_RTC_TMR0 (0x12)
>> +#define PRTCSS_RTC_TMR1 (0x13)
>> +#define PRTCSS_RTC_CCTRL (0x14)
>> +#define PRTCSS_RTC_SEC (0x15)
>> +#define PRTCSS_RTC_MIN (0x16)
>> +#define PRTCSS_RTC_HOUR (0x17)
>> +#define PRTCSS_RTC_DAY0 (0x18)
>> +#define PRTCSS_RTC_DAY1 (0x19)
>> +#define PRTCSS_RTC_AMIN (0x1A)
>> +#define PRTCSS_RTC_AHOUR (0x1B)
>> +#define PRTCSS_RTC_ADAY0 (0x1C)
>> +#define PRTCSS_RTC_ADAY1 (0x1D)
>> +#define PRTCSS_RTC_CLKC_CNT (0x20)
>> +
>> +/* PRTCSS_RTC_INTC_EXTENA1 */
>> +#define PRTCSS_RTC_INTC_EXTENA1_MASK (0x07)
>> +
>> +/* PRTCSS_RTC_CTRL bit fields */
>> +#define PRTCSS_RTC_CTRL_WDTBUS BIT(7)
>> +#define PRTCSS_RTC_CTRL_WEN BIT(6)
>> +#define PRTCSS_RTC_CTRL_WDRT BIT(5)
>> +#define PRTCSS_RTC_CTRL_WDTFLG BIT(4)
>> +#define PRTCSS_RTC_CTRL_TE BIT(3)
>> +#define PRTCSS_RTC_CTRL_TIEN BIT(2)
>> +#define PRTCSS_RTC_CTRL_TMRFLG BIT(1)
>> +#define PRTCSS_RTC_CTRL_TMMD BIT(0)
>> +
>> +/* PRTCSS_RTC_CCTRL bit fields */
>> +#define PRTCSS_RTC_CCTRL_CALBUSY BIT(7)
>> +#define PRTCSS_RTC_CCTRL_DAEN BIT(5)
>> +#define PRTCSS_RTC_CCTRL_HAEN BIT(4)
>> +#define PRTCSS_RTC_CCTRL_MAEN BIT(3)
>> +#define PRTCSS_RTC_CCTRL_ALMFLG BIT(2)
>> +#define PRTCSS_RTC_CCTRL_AIEN BIT(1)
>> +#define PRTCSS_RTC_CCTRL_CAEN BIT(0)
>> +
>> +static DEFINE_SPINLOCK(davinci_rtc_lock);
>> +
>> +struct davinci_rtc {
>> + struct rtc_device *rtc;
>> + void __iomem *base;
>> + resource_size_t pbase;
>> + size_t base_size;
>> + int irq;
>> +};
>> +
>> +static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
>> + u32 val, u32 addr)
>> +{
>> + writel(val, davinci_rtc->base + addr);
>> +}
>> +
>> +static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
>> +{
>> + return readl(davinci_rtc->base + addr);
>> +}
>> +
>> +static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
>> +{
>> + while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
>> + cpu_relax();
>> +}
>> +
>> +static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
>> + unsigned long val, u8 addr)
>> +{
>> + rtcif_wait(davinci_rtc);
>> +
>> + rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
>> + rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
>> +
>> + rtcif_wait(davinci_rtc);
>> +}
>> +
>> +static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
>> +{
>> + rtcif_wait(davinci_rtc);
>> +
>> + rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
>> + PRTCIF_CTLR);
>> +
>> + rtcif_wait(davinci_rtc);
>> +
>> + return rtcif_read(davinci_rtc, PRTCIF_LDATA);
>> +}
>> +
>> +static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
>> +{
>> + while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
>> + PRTCSS_RTC_CCTRL_CALBUSY)
>> + cpu_relax();
>> +}
>> +
>> +static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
>> +{
>> + struct davinci_rtc *davinci_rtc = class_dev;
>> + unsigned long events = 0;
>> + u32 irq_flg;
>> + u8 alm_irq, tmr_irq;
>> + u8 rtc_ctrl, rtc_cctrl;
>> + int ret = IRQ_NONE;
>> +
>> + irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
>> + PRTCIF_INTFLG_RTCSS;
>> +
>> + alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
>> + PRTCSS_RTC_CCTRL_ALMFLG;
>> +
>> + tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
>> + PRTCSS_RTC_CTRL_TMRFLG;
>> +
>> + if (irq_flg) {
>> + if (alm_irq) {
>> + events |= RTC_IRQF | RTC_AF;
>> + rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
>> + rtc_cctrl |= PRTCSS_RTC_CCTRL_ALMFLG;
>> + rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
>> + } else if (tmr_irq) {
>> + events |= RTC_IRQF | RTC_PF;
>> + rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
>> + rtc_ctrl |= PRTCSS_RTC_CTRL_TMRFLG;
>> + rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
>> + }
>> +
>> + rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
>> + PRTCIF_INTFLG);
>> + rtc_update_irq(davinci_rtc->rtc, 1, events);
>> +
>> + ret = IRQ_HANDLED;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static int
>> +davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
>> +{
>> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> + u8 rtc_ctrl;
>> + unsigned long flags;
>> + int ret = 0;
>> +
>> + spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> + rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
>> +
>> + switch (cmd) {
>> + case RTC_WIE_ON:
>> + rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
>> + break;
>> + case RTC_WIE_OFF:
>> + rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
>> + break;
>> + case RTC_UIE_OFF:
>> + case RTC_UIE_ON:
>> + ret = -ENOTTY;
>> + break;
>> + default:
>> + ret = -ENOIOCTLCMD;
>> + }
>> +
>> + rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
>> +
>> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +
>> + return ret;
>> +}
>> +
>> +static int convertfromdays(u16 days, struct rtc_time *tm)
>> +{
>> + int tmp_days, year, mon;
>> +
>> + for (year = 2000;; year++) {
>> + tmp_days = rtc_year_days(1, 12, year);
>> + if (days >= tmp_days)
>> + days -= tmp_days;
>> + else {
>> + for (mon = 0;; mon++) {
>> + tmp_days = rtc_month_days(mon, year);
>> + if (days >= tmp_days) {
>> + days -= tmp_days;
>> + } else {
>> + tm->tm_year = year - 1900;
>> + tm->tm_mon = mon;
>> + tm->tm_mday = days + 1;
>> + break;
>> + }
>> + }
>> + break;
>> + }
>> + }
>> + return 0;
>> +}
>> +
>> +static int convert2days(u16 *days, struct rtc_time *tm)
>> +{
>> + int i;
>> + *days = 0;
>> +
>> + /* epoch == 1900 */
>> + if (tm->tm_year < 100 || tm->tm_year > 199)
>> + return -EINVAL;
>> +
>> + for (i = 2000; i < 1900 + tm->tm_year; i++)
>> + *days += rtc_year_days(1, 12, i);
>> +
>> + *days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
>> +
>> + return 0;
>> +}
>> +
>> +static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
>> +{
>> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> + u16 days = 0;
>> + u8 day0, day1;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
>> +
>> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +
>> + days |= day1;
>> + days <<= 8;
>> + days |= day0;
>> +
>> + if (convertfromdays(days, tm) < 0)
>> + return -EINVAL;
>> +
>> + return 0;
>> +}
>> +
>> +static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
>> +{
>> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> + u16 days;
>> + u8 rtc_cctrl;
>> + unsigned long flags;
>> +
>> + if (convert2days(&days, tm) < 0)
>> + return -EINVAL;
>> +
>> + spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
>> +
>> + rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
>> + rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
>> + rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
>> +
>> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static int davinci_rtc_alarm_irq_enable(struct device *dev,
>> + unsigned int enabled)
>> +{
>> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> + unsigned long flags;
>> + u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
>> +
>> + spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> + if (enabled)
>> + rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
>> + PRTCSS_RTC_CCTRL_HAEN |
>> + PRTCSS_RTC_CCTRL_MAEN |
>> + PRTCSS_RTC_CCTRL_ALMFLG |
>> + PRTCSS_RTC_CCTRL_AIEN;
>> + else
>> + rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
>> +
>> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
>> +{
>> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> + u16 days = 0;
>> + u8 day0, day1;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
>> +
>> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> + days |= day1;
>> + days <<= 8;
>> + days |= day0;
>> +
>> + if (convertfromdays(days, &alm->time) < 0)
>> + return -EINVAL;
>> +
>> + alm->pending = !!(rtcss_read(davinci_rtc,
>> + PRTCSS_RTC_CCTRL) &
>> + PRTCSS_RTC_CCTRL_AIEN);
>> + alm->enabled = alm->pending && device_may_wakeup(dev);
>> +
>> + return 0;
>> +}
>> +
>> +static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
>> +{
>> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> + unsigned long flags;
>> + u16 days;
>> +
>> + if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0
>> + && alm->time.tm_year < 0) {
>> + struct rtc_time tm;
>> + unsigned long now, then;
>> +
>> + davinci_rtc_read_time(dev, &tm);
>> + rtc_tm_to_time(&tm, &now);
>> +
>> + alm->time.tm_mday = tm.tm_mday;
>> + alm->time.tm_mon = tm.tm_mon;
>> + alm->time.tm_year = tm.tm_year;
>> + rtc_tm_to_time(&alm->time, &then);
>> +
>> + if (then < now) {
>> + rtc_time_to_tm(now + 24 * 60 * 60, &tm);
>> + alm->time.tm_mday = tm.tm_mday;
>> + alm->time.tm_mon = tm.tm_mon;
>> + alm->time.tm_year = tm.tm_year;
>> + }
>> + }
>> +
>> + if (convert2days(&days, &alm->time) < 0)
>> + return -EINVAL;
>> +
>> + spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
>> +
>> + davinci_rtcss_calendar_wait(davinci_rtc);
>> + rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
>> +
>> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static int davinci_rtc_irq_set_state(struct device *dev, int enabled)
>> +{
>> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> + unsigned long flags;
>> + u8 rtc_ctrl;
>> +
>> + spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> + rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
>> +
>> + if (enabled) {
>> + while (rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL)
>> + & PRTCSS_RTC_CTRL_WDTBUS)
>> + cpu_relax();
>> +
>> + rtc_ctrl |= PRTCSS_RTC_CTRL_TE;
>> + rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
>> +
>> + rtcss_write(davinci_rtc, 0x0, PRTCSS_RTC_CLKC_CNT);
>> +
>> + rtc_ctrl |= PRTCSS_RTC_CTRL_TIEN |
>> + PRTCSS_RTC_CTRL_TMMD |
>> + PRTCSS_RTC_CTRL_TMRFLG;
>> + } else
>> + rtc_ctrl &= ~PRTCSS_RTC_CTRL_TIEN;
>> +
>> + rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
>> +
>> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static int davinci_rtc_irq_set_freq(struct device *dev, int freq)
>> +{
>> + struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> + unsigned long flags;
>> + u16 tmr_counter = (0x8000 >> (ffs(freq) - 1));
>> +
>> + spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> + rtcss_write(davinci_rtc, tmr_counter & 0xFF, PRTCSS_RTC_TMR0);
>> + rtcss_write(davinci_rtc, (tmr_counter & 0xFF00) >> 8, PRTCSS_RTC_TMR1);
>> +
>> + spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static struct rtc_class_ops davinci_rtc_ops = {
>> + .ioctl = davinci_rtc_ioctl,
>> + .read_time = davinci_rtc_read_time,
>> + .set_time = davinci_rtc_set_time,
>> + .alarm_irq_enable = davinci_rtc_alarm_irq_enable,
>> + .read_alarm = davinci_rtc_read_alarm,
>> + .set_alarm = davinci_rtc_set_alarm,
>> + .irq_set_state = davinci_rtc_irq_set_state,
>> + .irq_set_freq = davinci_rtc_irq_set_freq,
>> +};
>> +
>> +static int __init davinci_rtc_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct davinci_rtc *davinci_rtc;
>> + struct resource *res, *mem;
>> + int ret = 0;
>> +
>> + davinci_rtc = kzalloc(sizeof(struct davinci_rtc), GFP_KERNEL);
>> + if (!davinci_rtc) {
>> + dev_dbg(dev, "could not allocate memory for private data\n");
>> + return -ENOMEM;
>> + }
>> +
>> + davinci_rtc->irq = platform_get_irq(pdev, 0);
>> + if (davinci_rtc->irq < 0) {
>> + dev_err(dev, "no RTC irq\n");
>> + ret = davinci_rtc->irq;
>> + goto fail1;
>> + }
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + if (!res) {
>> + dev_err(dev, "no mem resource\n");
>> + ret = -EINVAL;
>> + goto fail1;
>> + }
>> +
>> + davinci_rtc->pbase = res->start;
>> + davinci_rtc->base_size = resource_size(res);
>> +
>> + mem = request_mem_region(davinci_rtc->pbase, davinci_rtc->base_size,
>> + pdev->name);
>> + if (!mem) {
>> + dev_err(dev, "RTC registers at %08x are not free\n",
>> + davinci_rtc->pbase);
>> + ret = -EBUSY;
>> + goto fail1;
>> + }
>> +
>> + davinci_rtc->base = ioremap(davinci_rtc->pbase, davinci_rtc->base_size);
>> + if (!davinci_rtc->base) {
>> + dev_err(dev, "unable to ioremap MEM resource\n");
>> + ret = -ENOMEM;
>> + goto fail2;
>> + }
>> +
>> + davinci_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
>> + &davinci_rtc_ops, THIS_MODULE);
>> + if (IS_ERR(davinci_rtc->rtc)) {
>> + dev_err(dev, "unable to register RTC device, err %ld\n",
>> + PTR_ERR(davinci_rtc->rtc));
>> + goto fail3;
>> + }
>> +
>> + rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
>> + rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
>> + rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
>> +
>> + rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
>> + rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
>> +
>> + ret = request_irq(davinci_rtc->irq, davinci_rtc_interrupt,
>> + IRQF_DISABLED, "davinci_rtc", davinci_rtc);
>> + if (ret < 0) {
>> + dev_err(dev, "unable to register davinci RTC interrupt\n");
>> + goto fail4;
>> + }
>> +
>> + /* Enable interrupts */
>> + rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
>> + rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
>> + PRTCSS_RTC_INTC_EXTENA1);
>> +
>> + rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
>> +
>> + platform_set_drvdata(pdev, davinci_rtc);
>> +
>> + device_init_wakeup(&pdev->dev, 0);
>> +
>> + return 0;
>> +
>> +fail4:
>> + rtc_device_unregister(davinci_rtc->rtc);
>> +fail3:
>> + iounmap(davinci_rtc->base);
>> +fail2:
>> + release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
>> +fail1:
>> + kfree(davinci_rtc);
>> +
>> + return ret;
>> +}
>> +
>> +static int __devexit davinci_rtc_remove(struct platform_device *pdev)
>> +{
>> + struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
>> +
>> + device_init_wakeup(&pdev->dev, 0);
>> +
>> + rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
>> +
>> + free_irq(davinci_rtc->irq, davinci_rtc);
>> +
>> + rtc_device_unregister(davinci_rtc->rtc);
>> +
>> + iounmap(davinci_rtc->base);
>> + release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
>> +
>> + platform_set_drvdata(pdev, NULL);
>> +
>> + kfree(davinci_rtc);
>> +
>> + return 0;
>> +}
>> +
>> +static struct platform_driver davinci_rtc_driver = {
>> + .probe = davinci_rtc_probe,
>> + .remove = __devexit_p(davinci_rtc_remove),
>> + .driver = {
>> + .name = "rtc_davinci",
>> + .owner = THIS_MODULE,
>> + },
>> +};
>> +
>> +static int __init rtc_init(void)
>> +{
>> + return platform_driver_probe(&davinci_rtc_driver, davinci_rtc_probe);
>> +}
>> +module_init(rtc_init);
>> +
>> +static void __exit rtc_exit(void)
>> +{
>> + platform_driver_unregister(&davinci_rtc_driver);
>> +}
>> +module_exit(rtc_exit);
>> +
>> +MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar@ridgerun.com>");
>> +MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
>> +MODULE_LICENSE("GPL");
>> --
>> 1.7.0.2
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 07/34] rtc: omap: let device wakeup capability be configured from chip init logic
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (5 preceding siblings ...)
2010-05-06 23:23 ` [PATCH 06/34] RTC: DaVinci RTC driver Kevin Hilman
@ 2010-05-06 23:23 ` Kevin Hilman
2010-05-13 9:15 ` Russell King - ARM Linux
2010-05-06 23:23 ` [PATCH 08/34] Davinci: allow SOCs based on other ARM CPUs Kevin Hilman
` (26 subsequent siblings)
33 siblings, 1 reply; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:23 UTC (permalink / raw)
To: linux-arm-kernel
From: Sekhar Nori <nsekhar@ti.com>
The rtc-omap driver currently hardcodes the RTC wakeup capability
to be "not capable". While this seems to be true for existing OMAP1
boards which are not wired for this, the DA850/OMAP-L138 SoC, the
RTC can always be wake up source from its "deep sleep" mode.
This patch lets the wakeup capability to be set from platform data and
does not override the setting from the driver. For DA850/OMAP-L138, this
is done from arch/arm/mach-davinci/devices-da8xx.c:da8xx_register_rtc()
Note that this patch does not change the behavior on any existing OMAP1
board since the platform device registration sets the wakeup capability
to 0 by default.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
drivers/rtc/rtc-omap.c | 12 +++++++-----
1 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
index 64d9727..73377b0 100644
--- a/drivers/rtc/rtc-omap.c
+++ b/drivers/rtc/rtc-omap.c
@@ -34,7 +34,8 @@
* Board-specific wiring options include using split power mode with
* RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
* and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
- * low power modes). See the BOARD-SPECIFIC CUSTOMIZATION comment.
+ * low power modes) for OMAP1 boards (OMAP-L138 has this built into
+ * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
*/
#define OMAP_RTC_BASE 0xfffb4800
@@ -401,16 +402,17 @@ static int __init omap_rtc_probe(struct platform_device *pdev)
/* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
*
- * - Boards wired so that RTC_WAKE_INT does something, and muxed
- * right (W13_1610_RTC_WAKE_INT is the default after chip reset),
- * should initialize the device wakeup flag appropriately.
+ * - Device wake-up capability setting should come through chip
+ * init logic. OMAP1 boards should initialize the "wakeup capable"
+ * flag in the platform device if the board is wired right for
+ * being woken up by RTC alarm. For OMAP-L138, this capability
+ * is built into the SoC by the "Deep Sleep" capability.
*
* - Boards wired so RTC_ON_nOFF is used as the reset signal,
* rather than nPWRON_RESET, should forcibly enable split
* power mode. (Some chip errata report that RTC_CTRL_SPLIT
* is write-only, and always reads as zero...)
*/
- device_init_wakeup(&pdev->dev, 0);
if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT)
pr_info("%s: split power mode\n", pdev->name);
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 07/34] rtc: omap: let device wakeup capability be configured from chip init logic
2010-05-06 23:23 ` [PATCH 07/34] rtc: omap: let device wakeup capability be configured from chip init logic Kevin Hilman
@ 2010-05-13 9:15 ` Russell King - ARM Linux
0 siblings, 0 replies; 38+ messages in thread
From: Russell King - ARM Linux @ 2010-05-13 9:15 UTC (permalink / raw)
To: linux-arm-kernel
-> rtc people
On Thu, May 06, 2010 at 04:23:58PM -0700, Kevin Hilman wrote:
> From: Sekhar Nori <nsekhar@ti.com>
>
> The rtc-omap driver currently hardcodes the RTC wakeup capability
> to be "not capable". While this seems to be true for existing OMAP1
> boards which are not wired for this, the DA850/OMAP-L138 SoC, the
> RTC can always be wake up source from its "deep sleep" mode.
>
> This patch lets the wakeup capability to be set from platform data and
> does not override the setting from the driver. For DA850/OMAP-L138, this
> is done from arch/arm/mach-davinci/devices-da8xx.c:da8xx_register_rtc()
>
> Note that this patch does not change the behavior on any existing OMAP1
> board since the platform device registration sets the wakeup capability
> to 0 by default.
>
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
> ---
> drivers/rtc/rtc-omap.c | 12 +++++++-----
> 1 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
> index 64d9727..73377b0 100644
> --- a/drivers/rtc/rtc-omap.c
> +++ b/drivers/rtc/rtc-omap.c
> @@ -34,7 +34,8 @@
> * Board-specific wiring options include using split power mode with
> * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
> * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
> - * low power modes). See the BOARD-SPECIFIC CUSTOMIZATION comment.
> + * low power modes) for OMAP1 boards (OMAP-L138 has this built into
> + * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
> */
>
> #define OMAP_RTC_BASE 0xfffb4800
> @@ -401,16 +402,17 @@ static int __init omap_rtc_probe(struct platform_device *pdev)
>
> /* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
> *
> - * - Boards wired so that RTC_WAKE_INT does something, and muxed
> - * right (W13_1610_RTC_WAKE_INT is the default after chip reset),
> - * should initialize the device wakeup flag appropriately.
> + * - Device wake-up capability setting should come through chip
> + * init logic. OMAP1 boards should initialize the "wakeup capable"
> + * flag in the platform device if the board is wired right for
> + * being woken up by RTC alarm. For OMAP-L138, this capability
> + * is built into the SoC by the "Deep Sleep" capability.
> *
> * - Boards wired so RTC_ON_nOFF is used as the reset signal,
> * rather than nPWRON_RESET, should forcibly enable split
> * power mode. (Some chip errata report that RTC_CTRL_SPLIT
> * is write-only, and always reads as zero...)
> */
> - device_init_wakeup(&pdev->dev, 0);
>
> if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT)
> pr_info("%s: split power mode\n", pdev->name);
> --
> 1.7.0.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 08/34] Davinci: allow SOCs based on other ARM CPUs
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (6 preceding siblings ...)
2010-05-06 23:23 ` [PATCH 07/34] rtc: omap: let device wakeup capability be configured from chip init logic Kevin Hilman
@ 2010-05-06 23:23 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 09/34] Davinci: enable timer clock before use Kevin Hilman
` (25 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:23 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
Preliminary modification prior to adding support for TNETV107X based on
ARM1176. This change allows for CPUs other than ARM926T to be used for Davinci
derivative SoCs. Existing devices (DA8x and DMx) operate unchanged.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/Kconfig | 1 -
arch/arm/mach-davinci/Kconfig | 2 ++
2 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 92622eb..1151d1a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -776,7 +776,6 @@ config ARCH_NOMADIK
config ARCH_DAVINCI
bool "TI DaVinci"
- select CPU_ARM926T
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select GENERIC_GPIO
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 0ebe185..0316e20 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -7,6 +7,7 @@ config CP_INTC
bool
config ARCH_DAVINCI_DMx
+ select CPU_ARM926T
bool
menu "TI DaVinci Implementations"
@@ -41,6 +42,7 @@ config ARCH_DAVINCI_DA850
select ARCH_HAS_CPUFREQ
config ARCH_DAVINCI_DA8XX
+ select CPU_ARM926T
bool
config ARCH_DAVINCI_DM365
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 09/34] Davinci: enable timer clock before use
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (7 preceding siblings ...)
2010-05-06 23:23 ` [PATCH 08/34] Davinci: allow SOCs based on other ARM CPUs Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 10/34] Davinci: cpintc host map configuration Kevin Hilman
` (24 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
timer_init() programs timer64 hardware. The module should ideally be brought
out of reset before this happens.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/time.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 9e0b106..b21f763 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -361,13 +361,13 @@ static void __init davinci_timer_init(void)
}
}
- /* init timer hw */
- timer_init();
-
timer_clk = clk_get(NULL, "timer0");
BUG_ON(IS_ERR(timer_clk));
clk_enable(timer_clk);
+ /* init timer hw */
+ timer_init();
+
davinci_clock_tick_rate = clk_get_rate(timer_clk);
/* setup clocksource */
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 10/34] Davinci: cpintc host map configuration
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (8 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 09/34] Davinci: enable timer clock before use Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 11/34] Davinci: support LPSC SwRstDisable state Kevin Hilman
` (23 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
Host map configuration instructs the interrupt controller to route interrupt
channels to FIQ or IRQ lines. Currently, DA8xx family of devices leave these
registers at their reset-default values.
TNETV107X however does not have sane reset defaults, and therefore this
architecture needs to reconfigure the host-map such that channels 0 and 1
go to FIQ, and the remaining channels raise IRQs.
This patch adds an optional host map argument to cp_intc_init() for this.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/board-da830-evm.c | 2 +-
arch/arm/mach-davinci/board-da850-evm.c | 2 +-
arch/arm/mach-davinci/cp_intc.c | 6 +++++-
arch/arm/mach-davinci/include/mach/cp_intc.h | 2 +-
4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index ea293b8..db5ac0f 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -569,7 +569,7 @@ static __init void da830_evm_irq_init(void)
struct davinci_soc_info *soc_info = &davinci_soc_info;
cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ,
- soc_info->intc_irq_prios);
+ soc_info->intc_irq_prios, NULL);
}
static void __init da830_evm_map_io(void)
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 411284d..ef691ae 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -741,7 +741,7 @@ static __init void da850_evm_irq_init(void)
struct davinci_soc_info *soc_info = &davinci_soc_info;
cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA850_N_CP_INTC_IRQ,
- soc_info->intc_irq_prios);
+ soc_info->intc_irq_prios, NULL);
}
static void __init da850_evm_map_io(void)
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 37311d1..2a8d26e 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -101,7 +101,7 @@ static struct irq_chip cp_intc_irq_chip = {
};
void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
- u8 *irq_prio)
+ u8 *irq_prio, u32 *host_map)
{
unsigned num_reg = BITS_TO_LONGS(num_irq);
int i;
@@ -157,6 +157,10 @@ void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
}
+ if (host_map)
+ for (i = 0; host_map[i] != -1; i++)
+ cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
+
/* Set up genirq dispatching for cp_intc */
for (i = 0; i < num_irq; i++) {
set_irq_chip(i, &cp_intc_irq_chip);
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
index c4d27ee..121b114 100644
--- a/arch/arm/mach-davinci/include/mach/cp_intc.h
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -52,6 +52,6 @@
#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2))
void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
- u8 *irq_prio);
+ u8 *irq_prio, u32 *host_map);
#endif /* __ASM_HARDWARE_CP_INTC_H */
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 11/34] Davinci: support LPSC SwRstDisable state
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (9 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 10/34] Davinci: cpintc host map configuration Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 12/34] Davinci: promote da8xx_pinmux_setup() Kevin Hilman
` (22 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
The current clock control code always gates the clock (PSC state Disable = 2)
on clk_disable(). Some on-chip peripherals (e.g. LCD controller on TNETV107X)
need to be put into SwRstDisable = 0 on clock disable, to maintain
hardware sanity.
This patch extends the davinci_psc_config() arguments to pass in the desired
module state instead of a boolean enable/disable. Further, clk_disable() now
checks for the PSC_SWRSTDISABLE clk flag before selecting the target state.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/clock.c | 12 +++++++++---
arch/arm/mach-davinci/clock.h | 7 ++++---
arch/arm/mach-davinci/include/mach/psc.h | 8 +++++++-
arch/arm/mach-davinci/psc.c | 3 +--
4 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 058c77f..5de60ae 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -43,7 +43,8 @@ static void __clk_enable(struct clk *clk)
if (clk->parent)
__clk_enable(clk->parent);
if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
- davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 1);
+ davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
+ PSC_STATE_ENABLE);
}
static void __clk_disable(struct clk *clk)
@@ -52,7 +53,9 @@ static void __clk_disable(struct clk *clk)
return;
if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
(clk->flags & CLK_PSC))
- davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0);
+ davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
+ (clk->flags & PSC_SWRSTDISABLE) ?
+ PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
if (clk->parent)
__clk_disable(clk->parent);
}
@@ -234,7 +237,10 @@ static int __init clk_disable_unused(void)
continue;
pr_info("Clocks: disable unused %s\n", ck->name);
- davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, 0);
+
+ davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
+ (ck->flags & PSC_SWRSTDISABLE) ?
+ PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
}
spin_unlock_irq(&clockfw_lock);
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index aa0a611..53a0f7b 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -101,10 +101,11 @@ struct clk {
/* Clock flags: SoC-specific flags start at BIT(16) */
#define ALWAYS_ENABLED BIT(1)
-#define CLK_PSC BIT(2)
-#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
+#define CLK_PSC BIT(2)
+#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
#define CLK_PLL BIT(4) /* PLL-derived clock */
-#define PRE_PLL BIT(5) /* source is before PLL mult/div */
+#define PRE_PLL BIT(5) /* source is before PLL mult/div */
+#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */
#define CLK(dev, con, ck) \
{ \
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 651f6d8..7dd2962 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -189,13 +189,19 @@
#define MDSTAT 0x800
#define MDCTL 0xA00
+/* PSC module states */
+#define PSC_STATE_SWRSTDISABLE 0
+#define PSC_STATE_SYNCRST 1
+#define PSC_STATE_DISABLE 2
+#define PSC_STATE_ENABLE 3
+
#define MDSTAT_STATE_MASK 0x1f
#ifndef __ASSEMBLER__
extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
- unsigned int id, char enable);
+ unsigned int id, u32 next_state);
#endif
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index adf6b5c..d7cb438 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -47,12 +47,11 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
/* Enable or disable a PSC domain */
void davinci_psc_config(unsigned int domain, unsigned int ctlr,
- unsigned int id, char enable)
+ unsigned int id, u32 next_state)
{
u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
void __iomem *psc_base;
struct davinci_soc_info *soc_info = &davinci_soc_info;
- u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 12/34] Davinci: promote da8xx_pinmux_setup()
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (10 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 11/34] Davinci: support LPSC SwRstDisable state Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 13/34] Davinci: tnetv107x pin list Kevin Hilman
` (21 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
Rename da8xx_pinmux_setup() to davinci_cfg_reg_list() and promote it for use in
other SOCs that may need the ability to configure multiple pins in one shot.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/board-da830-evm.c | 14 +++++++-------
arch/arm/mach-davinci/board-da850-evm.c | 18 +++++++++---------
arch/arm/mach-davinci/include/mach/da8xx.h | 6 ------
arch/arm/mach-davinci/include/mach/mux.h | 5 +++++
arch/arm/mach-davinci/mux.c | 3 +--
5 files changed, 22 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index db5ac0f..9257056 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -157,7 +157,7 @@ static __init void da830_evm_usb_init(void)
__func__, ret);
}
- ret = da8xx_pinmux_setup(da830_evm_usb11_pins);
+ ret = davinci_cfg_reg_list(da830_evm_usb11_pins);
if (ret) {
pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
__func__, ret);
@@ -254,7 +254,7 @@ static inline void da830_evm_init_mmc(void)
{
int ret;
- ret = da8xx_pinmux_setup(da830_evm_mmc_sd_pins);
+ ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins);
if (ret) {
pr_warning("da830_evm_init: mmc/sd mux setup failed: %d\n",
ret);
@@ -407,7 +407,7 @@ static inline void da830_evm_init_nand(int mux_mode)
return;
}
- ret = da8xx_pinmux_setup(da830_evm_emif25_pins);
+ ret = davinci_cfg_reg_list(da830_evm_emif25_pins);
if (ret)
pr_warning("da830_evm_init: emif25 mux setup failed: %d\n",
ret);
@@ -427,7 +427,7 @@ static inline void da830_evm_init_lcdc(int mux_mode)
{
int ret;
- ret = da8xx_pinmux_setup(da830_lcdcntl_pins);
+ ret = davinci_cfg_reg_list(da830_lcdcntl_pins);
if (ret)
pr_warning("da830_evm_init: lcdcntl mux setup failed: %d\n",
ret);
@@ -507,7 +507,7 @@ static __init void da830_evm_init(void)
pr_warning("da830_evm_init: edma registration failed: %d\n",
ret);
- ret = da8xx_pinmux_setup(da830_i2c0_pins);
+ ret = davinci_cfg_reg_list(da830_i2c0_pins);
if (ret)
pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n",
ret);
@@ -523,7 +523,7 @@ static __init void da830_evm_init(void)
soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY;
soc_info->emac_pdata->rmii_en = 1;
- ret = da8xx_pinmux_setup(da830_cpgmac_pins);
+ ret = davinci_cfg_reg_list(da830_cpgmac_pins);
if (ret)
pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n",
ret);
@@ -542,7 +542,7 @@ static __init void da830_evm_init(void)
i2c_register_board_info(1, da830_evm_i2c_devices,
ARRAY_SIZE(da830_evm_i2c_devices));
- ret = da8xx_pinmux_setup(da830_evm_mcasp1_pins);
+ ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins);
if (ret)
pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n",
ret);
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index ef691ae..6c137e0 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -206,12 +206,12 @@ static __init void da850_evm_setup_nor_nand(void)
int ret = 0;
if (ui_card_detected & !HAS_MMC) {
- ret = da8xx_pinmux_setup(da850_nand_pins);
+ ret = davinci_cfg_reg_list(da850_nand_pins);
if (ret)
pr_warning("da850_evm_init: nand mux setup failed: "
"%d\n", ret);
- ret = da8xx_pinmux_setup(da850_nor_pins);
+ ret = davinci_cfg_reg_list(da850_nor_pins);
if (ret)
pr_warning("da850_evm_init: nor mux setup failed: %d\n",
ret);
@@ -568,12 +568,12 @@ static int __init da850_evm_config_emac(void)
if (rmii_en) {
val |= BIT(8);
- ret = da8xx_pinmux_setup(da850_rmii_pins);
+ ret = davinci_cfg_reg_list(da850_rmii_pins);
pr_info("EMAC: RMII PHY configured, MII PHY will not be"
" functional\n");
} else {
val &= ~BIT(8);
- ret = da8xx_pinmux_setup(da850_cpgmac_pins);
+ ret = davinci_cfg_reg_list(da850_cpgmac_pins);
pr_info("EMAC: MII PHY configured, RMII PHY will not be"
" functional\n");
}
@@ -626,7 +626,7 @@ static __init void da850_evm_init(void)
pr_warning("da850_evm_init: edma registration failed: %d\n",
ret);
- ret = da8xx_pinmux_setup(da850_i2c0_pins);
+ ret = davinci_cfg_reg_list(da850_i2c0_pins);
if (ret)
pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n",
ret);
@@ -643,7 +643,7 @@ static __init void da850_evm_init(void)
ret);
if (HAS_MMC) {
- ret = da8xx_pinmux_setup(da850_mmcsd0_pins);
+ ret = davinci_cfg_reg_list(da850_mmcsd0_pins);
if (ret)
pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
" %d\n", ret);
@@ -679,20 +679,20 @@ static __init void da850_evm_init(void)
__raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
__raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
- ret = da8xx_pinmux_setup(da850_mcasp_pins);
+ ret = davinci_cfg_reg_list(da850_mcasp_pins);
if (ret)
pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
ret);
da8xx_register_mcasp(0, &da850_evm_snd_data);
- ret = da8xx_pinmux_setup(da850_lcdcntl_pins);
+ ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
if (ret)
pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
ret);
/* Handle board specific muxing for LCD here */
- ret = da8xx_pinmux_setup(da850_evm_lcdc_pins);
+ ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
if (ret)
pr_warning("da850_evm_init: evm specific lcd mux setup "
"failed: %d\n", ret);
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 03acfd3..33471c9 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -146,10 +146,4 @@ extern const short da850_mmcsd0_pins[];
extern const short da850_nand_pins[];
extern const short da850_nor_pins[];
-#ifdef CONFIG_DAVINCI_MUX
-int da8xx_pinmux_setup(const short pins[]);
-#else
-static inline int da8xx_pinmux_setup(const short pins[]) { return 0; }
-#endif
-
#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 2a68c1d..48888db 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -907,9 +907,14 @@ enum davinci_da850_index {
#ifdef CONFIG_DAVINCI_MUX
/* setup pin muxing */
extern int davinci_cfg_reg(unsigned long reg_cfg);
+extern int davinci_cfg_reg_list(const short pins[]);
#else
/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
+static inline int davinci_cfg_reg_list(const short pins[])
+{
+ return 0;
+}
#endif
#endif /* __INC_MACH_MUX_H */
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index c942c89..e9d530a 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -21,7 +21,6 @@
#include <mach/mux.h>
#include <mach/common.h>
-#include <mach/da8xx.h>
/*
* Sets the DAVINCI MUX register based on the table
@@ -92,7 +91,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
}
EXPORT_SYMBOL(davinci_cfg_reg);
-int da8xx_pinmux_setup(const short pins[])
+int __init_or_module davinci_cfg_reg_list(const short pins[])
{
int i, error = -EINVAL;
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 13/34] Davinci: tnetv107x pin list
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (11 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 12/34] Davinci: promote da8xx_pinmux_setup() Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 14/34] Davinci: tnetv107x LPSC modules Kevin Hilman
` (20 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
Added list of muxed pins on the tnetv107x SOC.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/include/mach/mux.h | 269 ++++++++++++++++++++++++++++++
1 files changed, 269 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 48888db..8638903 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -904,6 +904,275 @@ enum davinci_da850_index {
DA850_RTC_ALARM,
};
+enum davinci_tnetv107x_index {
+ TNETV107X_ASR_A00,
+ TNETV107X_GPIO32,
+ TNETV107X_ASR_A01,
+ TNETV107X_GPIO33,
+ TNETV107X_ASR_A02,
+ TNETV107X_GPIO34,
+ TNETV107X_ASR_A03,
+ TNETV107X_GPIO35,
+ TNETV107X_ASR_A04,
+ TNETV107X_GPIO36,
+ TNETV107X_ASR_A05,
+ TNETV107X_GPIO37,
+ TNETV107X_ASR_A06,
+ TNETV107X_GPIO38,
+ TNETV107X_ASR_A07,
+ TNETV107X_GPIO39,
+ TNETV107X_ASR_A08,
+ TNETV107X_GPIO40,
+ TNETV107X_ASR_A09,
+ TNETV107X_GPIO41,
+ TNETV107X_ASR_A10,
+ TNETV107X_GPIO42,
+ TNETV107X_ASR_A11,
+ TNETV107X_BOOT_STRP_0,
+ TNETV107X_ASR_A12,
+ TNETV107X_BOOT_STRP_1,
+ TNETV107X_ASR_A13,
+ TNETV107X_GPIO43,
+ TNETV107X_ASR_A14,
+ TNETV107X_GPIO44,
+ TNETV107X_ASR_A15,
+ TNETV107X_GPIO45,
+ TNETV107X_ASR_A16,
+ TNETV107X_GPIO46,
+ TNETV107X_ASR_A17,
+ TNETV107X_GPIO47,
+ TNETV107X_ASR_A18,
+ TNETV107X_GPIO48,
+ TNETV107X_SDIO1_DATA3_0,
+ TNETV107X_ASR_A19,
+ TNETV107X_GPIO49,
+ TNETV107X_SDIO1_DATA2_0,
+ TNETV107X_ASR_A20,
+ TNETV107X_GPIO50,
+ TNETV107X_SDIO1_DATA1_0,
+ TNETV107X_ASR_A21,
+ TNETV107X_GPIO51,
+ TNETV107X_SDIO1_DATA0_0,
+ TNETV107X_ASR_A22,
+ TNETV107X_GPIO52,
+ TNETV107X_SDIO1_CMD_0,
+ TNETV107X_ASR_A23,
+ TNETV107X_GPIO53,
+ TNETV107X_SDIO1_CLK_0,
+ TNETV107X_ASR_BA_1,
+ TNETV107X_GPIO54,
+ TNETV107X_SYS_PLL_CLK,
+ TNETV107X_ASR_CS0,
+ TNETV107X_ASR_CS1,
+ TNETV107X_ASR_CS2,
+ TNETV107X_TDM_PLL_CLK,
+ TNETV107X_ASR_CS3,
+ TNETV107X_ETH_PHY_CLK,
+ TNETV107X_ASR_D00,
+ TNETV107X_GPIO55,
+ TNETV107X_ASR_D01,
+ TNETV107X_GPIO56,
+ TNETV107X_ASR_D02,
+ TNETV107X_GPIO57,
+ TNETV107X_ASR_D03,
+ TNETV107X_GPIO58,
+ TNETV107X_ASR_D04,
+ TNETV107X_GPIO59_0,
+ TNETV107X_ASR_D05,
+ TNETV107X_GPIO60_0,
+ TNETV107X_ASR_D06,
+ TNETV107X_GPIO61_0,
+ TNETV107X_ASR_D07,
+ TNETV107X_GPIO62_0,
+ TNETV107X_ASR_D08,
+ TNETV107X_GPIO63_0,
+ TNETV107X_ASR_D09,
+ TNETV107X_GPIO64_0,
+ TNETV107X_ASR_D10,
+ TNETV107X_SDIO1_DATA3_1,
+ TNETV107X_ASR_D11,
+ TNETV107X_SDIO1_DATA2_1,
+ TNETV107X_ASR_D12,
+ TNETV107X_SDIO1_DATA1_1,
+ TNETV107X_ASR_D13,
+ TNETV107X_SDIO1_DATA0_1,
+ TNETV107X_ASR_D14,
+ TNETV107X_SDIO1_CMD_1,
+ TNETV107X_ASR_D15,
+ TNETV107X_SDIO1_CLK_1,
+ TNETV107X_ASR_OE,
+ TNETV107X_BOOT_STRP_2,
+ TNETV107X_ASR_RNW,
+ TNETV107X_GPIO29_0,
+ TNETV107X_ASR_WAIT,
+ TNETV107X_GPIO30_0,
+ TNETV107X_ASR_WE,
+ TNETV107X_BOOT_STRP_3,
+ TNETV107X_ASR_WE_DQM0,
+ TNETV107X_GPIO31,
+ TNETV107X_LCD_PD17_0,
+ TNETV107X_ASR_WE_DQM1,
+ TNETV107X_ASR_BA0_0,
+ TNETV107X_VLYNQ_CLK,
+ TNETV107X_GPIO14,
+ TNETV107X_LCD_PD19_0,
+ TNETV107X_VLYNQ_RXD0,
+ TNETV107X_GPIO15,
+ TNETV107X_LCD_PD20_0,
+ TNETV107X_VLYNQ_RXD1,
+ TNETV107X_GPIO16,
+ TNETV107X_LCD_PD21_0,
+ TNETV107X_VLYNQ_TXD0,
+ TNETV107X_GPIO17,
+ TNETV107X_LCD_PD22_0,
+ TNETV107X_VLYNQ_TXD1,
+ TNETV107X_GPIO18,
+ TNETV107X_LCD_PD23_0,
+ TNETV107X_SDIO0_CLK,
+ TNETV107X_GPIO19,
+ TNETV107X_SDIO0_CMD,
+ TNETV107X_GPIO20,
+ TNETV107X_SDIO0_DATA0,
+ TNETV107X_GPIO21,
+ TNETV107X_SDIO0_DATA1,
+ TNETV107X_GPIO22,
+ TNETV107X_SDIO0_DATA2,
+ TNETV107X_GPIO23,
+ TNETV107X_SDIO0_DATA3,
+ TNETV107X_GPIO24,
+ TNETV107X_EMU0,
+ TNETV107X_EMU1,
+ TNETV107X_RTCK,
+ TNETV107X_TRST_N,
+ TNETV107X_TCK,
+ TNETV107X_TDI,
+ TNETV107X_TDO,
+ TNETV107X_TMS,
+ TNETV107X_TDM1_CLK,
+ TNETV107X_TDM1_RX,
+ TNETV107X_TDM1_TX,
+ TNETV107X_TDM1_FS,
+ TNETV107X_KEYPAD_R0,
+ TNETV107X_KEYPAD_R1,
+ TNETV107X_KEYPAD_R2,
+ TNETV107X_KEYPAD_R3,
+ TNETV107X_KEYPAD_R4,
+ TNETV107X_KEYPAD_R5,
+ TNETV107X_KEYPAD_R6,
+ TNETV107X_GPIO12,
+ TNETV107X_KEYPAD_R7,
+ TNETV107X_GPIO10,
+ TNETV107X_KEYPAD_C0,
+ TNETV107X_KEYPAD_C1,
+ TNETV107X_KEYPAD_C2,
+ TNETV107X_KEYPAD_C3,
+ TNETV107X_KEYPAD_C4,
+ TNETV107X_KEYPAD_C5,
+ TNETV107X_KEYPAD_C6,
+ TNETV107X_GPIO13,
+ TNETV107X_TEST_CLK_IN,
+ TNETV107X_KEYPAD_C7,
+ TNETV107X_GPIO11,
+ TNETV107X_SSP0_0,
+ TNETV107X_SCC_DCLK,
+ TNETV107X_LCD_PD20_1,
+ TNETV107X_SSP0_1,
+ TNETV107X_SCC_CS_N,
+ TNETV107X_LCD_PD21_1,
+ TNETV107X_SSP0_2,
+ TNETV107X_SCC_D,
+ TNETV107X_LCD_PD22_1,
+ TNETV107X_SSP0_3,
+ TNETV107X_SCC_RESETN,
+ TNETV107X_LCD_PD23_1,
+ TNETV107X_SSP1_0,
+ TNETV107X_GPIO25,
+ TNETV107X_UART2_CTS,
+ TNETV107X_SSP1_1,
+ TNETV107X_GPIO26,
+ TNETV107X_UART2_RD,
+ TNETV107X_SSP1_2,
+ TNETV107X_GPIO27,
+ TNETV107X_UART2_RTS,
+ TNETV107X_SSP1_3,
+ TNETV107X_GPIO28,
+ TNETV107X_UART2_TD,
+ TNETV107X_UART0_CTS,
+ TNETV107X_UART0_RD,
+ TNETV107X_UART0_RTS,
+ TNETV107X_UART0_TD,
+ TNETV107X_UART1_RD,
+ TNETV107X_UART1_TD,
+ TNETV107X_LCD_AC_NCS,
+ TNETV107X_LCD_HSYNC_RNW,
+ TNETV107X_LCD_VSYNC_A0,
+ TNETV107X_LCD_MCLK,
+ TNETV107X_LCD_PD16_0,
+ TNETV107X_LCD_PCLK_E,
+ TNETV107X_LCD_PD00,
+ TNETV107X_LCD_PD01,
+ TNETV107X_LCD_PD02,
+ TNETV107X_LCD_PD03,
+ TNETV107X_LCD_PD04,
+ TNETV107X_LCD_PD05,
+ TNETV107X_LCD_PD06,
+ TNETV107X_LCD_PD07,
+ TNETV107X_LCD_PD08,
+ TNETV107X_GPIO59_1,
+ TNETV107X_LCD_PD09,
+ TNETV107X_GPIO60_1,
+ TNETV107X_LCD_PD10,
+ TNETV107X_ASR_BA0_1,
+ TNETV107X_GPIO61_1,
+ TNETV107X_LCD_PD11,
+ TNETV107X_GPIO62_1,
+ TNETV107X_LCD_PD12,
+ TNETV107X_GPIO63_1,
+ TNETV107X_LCD_PD13,
+ TNETV107X_GPIO64_1,
+ TNETV107X_LCD_PD14,
+ TNETV107X_GPIO29_1,
+ TNETV107X_LCD_PD15,
+ TNETV107X_GPIO30_1,
+ TNETV107X_EINT0,
+ TNETV107X_GPIO08,
+ TNETV107X_EINT1,
+ TNETV107X_GPIO09,
+ TNETV107X_GPIO00,
+ TNETV107X_LCD_PD20_2,
+ TNETV107X_TDM_CLK_IN_2,
+ TNETV107X_GPIO01,
+ TNETV107X_LCD_PD21_2,
+ TNETV107X_24M_CLK_OUT_1,
+ TNETV107X_GPIO02,
+ TNETV107X_LCD_PD22_2,
+ TNETV107X_GPIO03,
+ TNETV107X_LCD_PD23_2,
+ TNETV107X_GPIO04,
+ TNETV107X_LCD_PD16_1,
+ TNETV107X_USB0_RXERR,
+ TNETV107X_GPIO05,
+ TNETV107X_LCD_PD17_1,
+ TNETV107X_TDM_CLK_IN_1,
+ TNETV107X_GPIO06,
+ TNETV107X_LCD_PD18,
+ TNETV107X_24M_CLK_OUT_2,
+ TNETV107X_GPIO07,
+ TNETV107X_LCD_PD19_1,
+ TNETV107X_USB1_RXERR,
+ TNETV107X_ETH_PLL_CLK,
+ TNETV107X_MDIO,
+ TNETV107X_MDC,
+ TNETV107X_AIC_MUTE_STAT_N,
+ TNETV107X_TDM0_CLK,
+ TNETV107X_AIC_HNS_EN_N,
+ TNETV107X_TDM0_FS,
+ TNETV107X_AIC_HDS_EN_STAT_N,
+ TNETV107X_TDM0_TX,
+ TNETV107X_AIC_HNF_EN_STAT_N,
+ TNETV107X_TDM0_RX,
+};
+
#ifdef CONFIG_DAVINCI_MUX
/* setup pin muxing */
extern int davinci_cfg_reg(unsigned long reg_cfg);
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 14/34] Davinci: tnetv107x LPSC modules
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (12 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 13/34] Davinci: tnetv107x pin list Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 15/34] Davinci: tnetv107x IRQ definitions Kevin Hilman
` (19 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
Added definitions for LPSC modules in the tnetv107x SOC
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/include/mach/psc.h | 47 ++++++++++++++++++++++++++++++
1 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 7dd2962..983da6e 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -180,6 +180,53 @@
#define DA8XX_LPSC1_CR_P3_SS 26
#define DA8XX_LPSC1_L3_CBA_RAM 31
+/* TNETV107X LPSC Assignments */
+#define TNETV107X_LPSC_ARM 0
+#define TNETV107X_LPSC_GEM 1
+#define TNETV107X_LPSC_DDR2_PHY 2
+#define TNETV107X_LPSC_TPCC 3
+#define TNETV107X_LPSC_TPTC0 4
+#define TNETV107X_LPSC_TPTC1 5
+#define TNETV107X_LPSC_RAM 6
+#define TNETV107X_LPSC_MBX_LITE 7
+#define TNETV107X_LPSC_LCD 8
+#define TNETV107X_LPSC_ETHSS 9
+#define TNETV107X_LPSC_AEMIF 10
+#define TNETV107X_LPSC_CHIP_CFG 11
+#define TNETV107X_LPSC_TSC 12
+#define TNETV107X_LPSC_ROM 13
+#define TNETV107X_LPSC_UART2 14
+#define TNETV107X_LPSC_PKTSEC 15
+#define TNETV107X_LPSC_SECCTL 16
+#define TNETV107X_LPSC_KEYMGR 17
+#define TNETV107X_LPSC_KEYPAD 18
+#define TNETV107X_LPSC_GPIO 19
+#define TNETV107X_LPSC_MDIO 20
+#define TNETV107X_LPSC_SDIO0 21
+#define TNETV107X_LPSC_UART0 22
+#define TNETV107X_LPSC_UART1 23
+#define TNETV107X_LPSC_TIMER0 24
+#define TNETV107X_LPSC_TIMER1 25
+#define TNETV107X_LPSC_WDT_ARM 26
+#define TNETV107X_LPSC_WDT_DSP 27
+#define TNETV107X_LPSC_SSP 28
+#define TNETV107X_LPSC_TDM0 29
+#define TNETV107X_LPSC_VLYNQ 30
+#define TNETV107X_LPSC_MCDMA 31
+#define TNETV107X_LPSC_USB0 32
+#define TNETV107X_LPSC_TDM1 33
+#define TNETV107X_LPSC_DEBUGSS 34
+#define TNETV107X_LPSC_ETHSS_RGMII 35
+#define TNETV107X_LPSC_SYSTEM 36
+#define TNETV107X_LPSC_IMCOP 37
+#define TNETV107X_LPSC_SPARE 38
+#define TNETV107X_LPSC_SDIO1 39
+#define TNETV107X_LPSC_USB1 40
+#define TNETV107X_LPSC_USBSS 41
+#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
+#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
+#define TNETV107X_LPSC_MAX 44
+
/* PSC register offsets */
#define EPCPR 0x070
#define PTCMD 0x120
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 15/34] Davinci: tnetv107x IRQ definitions
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (13 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 14/34] Davinci: tnetv107x LPSC modules Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 16/34] Davinci: tnetv107x cpu types Kevin Hilman
` (18 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
IRQ numbers as defined for tnetv107x cp_intc.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/include/mach/irqs.h | 97 +++++++++++++++++++++++++++++
1 files changed, 97 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 354af71..ec76c77 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -401,6 +401,103 @@
#define DA850_N_CP_INTC_IRQ 101
+
+/* TNETV107X specific interrupts */
+#define IRQ_TNETV107X_TDM1_TXDMA 0
+#define IRQ_TNETV107X_EXT_INT_0 1
+#define IRQ_TNETV107X_EXT_INT_1 2
+#define IRQ_TNETV107X_GPIO_INT12 3
+#define IRQ_TNETV107X_GPIO_INT13 4
+#define IRQ_TNETV107X_TIMER_0_TINT12 5
+#define IRQ_TNETV107X_TIMER_1_TINT12 6
+#define IRQ_TNETV107X_UART0 7
+#define IRQ_TNETV107X_TDM1_RXDMA 8
+#define IRQ_TNETV107X_MCDMA_INT0 9
+#define IRQ_TNETV107X_MCDMA_INT1 10
+#define IRQ_TNETV107X_TPCC 11
+#define IRQ_TNETV107X_TPCC_INT0 12
+#define IRQ_TNETV107X_TPCC_INT1 13
+#define IRQ_TNETV107X_TPCC_INT2 14
+#define IRQ_TNETV107X_TPCC_INT3 15
+#define IRQ_TNETV107X_TPTC0 16
+#define IRQ_TNETV107X_TPTC1 17
+#define IRQ_TNETV107X_TIMER_0_TINT34 18
+#define IRQ_TNETV107X_ETHSS 19
+#define IRQ_TNETV107X_TIMER_1_TINT34 20
+#define IRQ_TNETV107X_DSP2ARM_INT0 21
+#define IRQ_TNETV107X_DSP2ARM_INT1 22
+#define IRQ_TNETV107X_ARM_NPMUIRQ 23
+#define IRQ_TNETV107X_USB1 24
+#define IRQ_TNETV107X_VLYNQ 25
+#define IRQ_TNETV107X_UART0_DMATX 26
+#define IRQ_TNETV107X_UART0_DMARX 27
+#define IRQ_TNETV107X_TDM1_TXMCSP 28
+#define IRQ_TNETV107X_SSP 29
+#define IRQ_TNETV107X_MCDMA_INT2 30
+#define IRQ_TNETV107X_MCDMA_INT3 31
+#define IRQ_TNETV107X_TDM_CODECIF_EOT 32
+#define IRQ_TNETV107X_IMCOP_SQR_ARM 33
+#define IRQ_TNETV107X_USB0 34
+#define IRQ_TNETV107X_USB_CDMA 35
+#define IRQ_TNETV107X_LCD 36
+#define IRQ_TNETV107X_KEYPAD 37
+#define IRQ_TNETV107X_KEYPAD_FREE 38
+#define IRQ_TNETV107X_RNG 39
+#define IRQ_TNETV107X_PKA 40
+#define IRQ_TNETV107X_TDM0_TXDMA 41
+#define IRQ_TNETV107X_TDM0_RXDMA 42
+#define IRQ_TNETV107X_TDM0_TXMCSP 43
+#define IRQ_TNETV107X_TDM0_RXMCSP 44
+#define IRQ_TNETV107X_TDM1_RXMCSP 45
+#define IRQ_TNETV107X_SDIO1 46
+#define IRQ_TNETV107X_SDIO0 47
+#define IRQ_TNETV107X_TSC 48
+#define IRQ_TNETV107X_TS 49
+#define IRQ_TNETV107X_UART1 50
+#define IRQ_TNETV107X_MBX_LITE 51
+#define IRQ_TNETV107X_GPIO_INT00 52
+#define IRQ_TNETV107X_GPIO_INT01 53
+#define IRQ_TNETV107X_GPIO_INT02 54
+#define IRQ_TNETV107X_GPIO_INT03 55
+#define IRQ_TNETV107X_UART2 56
+#define IRQ_TNETV107X_UART2_DMATX 57
+#define IRQ_TNETV107X_UART2_DMARX 58
+#define IRQ_TNETV107X_IMCOP_IMX 59
+#define IRQ_TNETV107X_IMCOP_VLCD 60
+#define IRQ_TNETV107X_AES 61
+#define IRQ_TNETV107X_DES 62
+#define IRQ_TNETV107X_SHAMD5 63
+#define IRQ_TNETV107X_TPCC_ERR 68
+#define IRQ_TNETV107X_TPCC_PROT 69
+#define IRQ_TNETV107X_TPTC0_ERR 70
+#define IRQ_TNETV107X_TPTC1_ERR 71
+#define IRQ_TNETV107X_UART0_ERR 72
+#define IRQ_TNETV107X_UART1_ERR 73
+#define IRQ_TNETV107X_AEMIF_ERR 74
+#define IRQ_TNETV107X_DDR_ERR 75
+#define IRQ_TNETV107X_WDTARM_INT0 76
+#define IRQ_TNETV107X_MCDMA_ERR 77
+#define IRQ_TNETV107X_GPIO_ERR 78
+#define IRQ_TNETV107X_MPU_ADDR 79
+#define IRQ_TNETV107X_MPU_PROT 80
+#define IRQ_TNETV107X_IOPU_ADDR 81
+#define IRQ_TNETV107X_IOPU_PROT 82
+#define IRQ_TNETV107X_KEYPAD_ADDR_ERR 83
+#define IRQ_TNETV107X_WDT0_ADDR_ERR 84
+#define IRQ_TNETV107X_WDT1_ADDR_ERR 85
+#define IRQ_TNETV107X_CLKCTL_ADDR_ERR 86
+#define IRQ_TNETV107X_PLL_UNLOCK 87
+#define IRQ_TNETV107X_WDTDSP_INT0 88
+#define IRQ_TNETV107X_SEC_CTRL_VIOLATION 89
+#define IRQ_TNETV107X_KEY_MNG_VIOLATION 90
+#define IRQ_TNETV107X_PBIST_CPU 91
+#define IRQ_TNETV107X_WDTARM 92
+#define IRQ_TNETV107X_PSC 93
+#define IRQ_TNETV107X_MMC0 94
+#define IRQ_TNETV107X_MMC1 95
+
+#define TNETV107X_N_CP_INTC_IRQ 96
+
/* da850 currently has the most gpio pins (144) */
#define DAVINCI_N_GPIO 144
/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 16/34] Davinci: tnetv107x cpu types
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (14 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 15/34] Davinci: tnetv107x IRQ definitions Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 17/34] DaVinci: move AEMIF #define's to the proper headers Kevin Hilman
` (17 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
Added tnetv107x cpu type definitions and cpu identification macros.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/include/mach/cputype.h | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index 189b1ff..cea6b89 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -33,6 +33,7 @@ struct davinci_id {
#define DAVINCI_CPU_ID_DM365 0x03650000
#define DAVINCI_CPU_ID_DA830 0x08300000
#define DAVINCI_CPU_ID_DA850 0x08500000
+#define DAVINCI_CPU_ID_TNETV107X 0x0b8a0000
#define IS_DAVINCI_CPU(type, id) \
static inline int is_davinci_ ##type(void) \
@@ -46,6 +47,7 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
+IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
#ifdef CONFIG_ARCH_DAVINCI_DM644x
#define cpu_is_davinci_dm644x() is_davinci_dm644x()
@@ -83,4 +85,10 @@ IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
#define cpu_is_davinci_da850() 0
#endif
+#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
+#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
+#else
+#define cpu_is_davinci_tnetv107x() 0
+#endif
+
#endif
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 17/34] DaVinci: move AEMIF #define's to the proper headers
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (15 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 16/34] Davinci: tnetv107x cpu types Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 18/34] DA830 EVM: use DA8XX_AEMIF_*_BASE #define's Kevin Hilman
` (16 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Currently each DaVinci board file #define's its own version of the EMIFA base
addresses (all named DAVINCI_ASYNC_EMIF_*_BASE), which leads to duplication.
Move these #define's to the SoC specific headers, changing their prefixes from
'DAVINCI' to the 'DM355', 'DM644X', and 'DM646X' since all these base addresses
are SoC specific...
And while at it, rename DM646X_ASYNC_EMIF_DATA_CE0_BASE to
DM646X_ASYNC_EMIF_CS2_SPACE_BASE in order to match the DM646x datasheet.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/board-dm355-evm.c | 11 ++++-------
arch/arm/mach-davinci/board-dm355-leopard.c | 11 ++++-------
arch/arm/mach-davinci/board-dm365-evm.c | 5 -----
arch/arm/mach-davinci/board-dm644x-evm.c | 18 ++++++------------
arch/arm/mach-davinci/board-dm646x-evm.c | 11 ++++-------
arch/arm/mach-davinci/board-neuros-osd2.c | 11 ++++-------
arch/arm/mach-davinci/board-sffsdr.c | 11 ++++-------
arch/arm/mach-davinci/include/mach/dm355.h | 3 +++
arch/arm/mach-davinci/include/mach/dm365.h | 4 ++++
arch/arm/mach-davinci/include/mach/dm644x.h | 6 ++++++
arch/arm/mach-davinci/include/mach/dm646x.h | 3 +++
11 files changed, 42 insertions(+), 52 deletions(-)
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index aa48e3f..a0ad7d9 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -33,9 +33,6 @@
#include <mach/mmc.h>
#include <mach/usb.h>
-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-
/* NOTE: this is geared for the standard config, with a socketed
* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
* swap chips, maybe with a different block size, partitioning may
@@ -86,12 +83,12 @@ static struct davinci_nand_pdata davinci_nand_data = {
static struct resource davinci_nand_resources[] = {
{
- .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
+ .start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
+ .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
- .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+ .start = DM355_ASYNC_EMIF_CONTROL_BASE,
+ .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 21f32eb..c3d5a70 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -30,9 +30,6 @@
#include <mach/mmc.h>
#include <mach/usb.h>
-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-
/* NOTE: this is geared for the standard config, with a socketed
* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
* swap chips, maybe with a different block size, partitioning may
@@ -82,12 +79,12 @@ static struct davinci_nand_pdata davinci_nand_data = {
static struct resource davinci_nand_resources[] = {
{
- .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
+ .start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
+ .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
- .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+ .start = DM355_ASYNC_EMIF_CONTROL_BASE,
+ .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index df4ab21..b98b35c 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -54,11 +54,6 @@ static inline int have_tvp7002(void)
return 0;
}
-
-#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
-#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
-
#define DM365_EVM_PHY_MASK (0x2)
#define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 95cef1f..d028bab 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -43,12 +43,6 @@
#define DAVINCI_CFC_ATA_BASE 0x01C66000
-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
-
#define LXT971_PHY_ID (0x001378e2)
#define LXT971_PHY_MASK (0xfffffff0)
@@ -92,8 +86,8 @@ static struct physmap_flash_data davinci_evm_norflash_data = {
/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
* limits addresses to 16M, so using addresses past 16M will wrap */
static struct resource davinci_evm_norflash_resource = {
- .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
+ .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
+ .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
};
@@ -154,12 +148,12 @@ static struct davinci_nand_pdata davinci_evm_nandflash_data = {
static struct resource davinci_evm_nandflash_resource[] = {
{
- .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
+ .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
+ .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
- .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+ .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
+ .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 5ba3cb2..b22e22c 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -80,17 +80,14 @@ static struct davinci_nand_pdata davinci_nand_data = {
.options = 0,
};
-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
-
static struct resource davinci_nand_resources[] = {
{
- .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
+ .start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
+ .end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
- .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+ .start = DM646X_ASYNC_EMIF_CONTROL_BASE,
+ .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 1fadc68..5afe37e 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -43,9 +43,6 @@
#define DAVINCI_CFC_ATA_BASE 0x01C66000
-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-
#define LXT971_PHY_ID 0x001378e2
#define LXT971_PHY_MASK 0xfffffff0
@@ -98,12 +95,12 @@ static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
static struct resource davinci_ntosd2_nandflash_resource[] = {
{
- .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
+ .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
+ .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
- .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+ .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
+ .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index a7cf810..1ed0662 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -45,9 +45,6 @@
#define SFFSDR_PHY_MASK (0x2)
#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-
static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
/* U-Boot Environment: Block 0
* UBL: Block 1
@@ -76,12 +73,12 @@ static struct flash_platform_data davinci_sffsdr_nandflash_data = {
static struct resource davinci_sffsdr_nandflash_resource[] = {
{
- .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
+ .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
+ .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
- .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+ .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
+ .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h
index 85536d8..36dff4a 100644
--- a/arch/arm/mach-davinci/include/mach/dm355.h
+++ b/arch/arm/mach-davinci/include/mach/dm355.h
@@ -15,6 +15,9 @@
#include <mach/asp.h>
#include <media/davinci/vpfe_capture.h>
+#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01E10000
+#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
+
#define ASP1_TX_EVT_EN 1
#define ASP1_RX_EVT_EN 2
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index 3a37b5a..ea5df3b 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -36,6 +36,10 @@
#define DAVINCI_DMA_VC_TX 2
#define DAVINCI_DMA_VC_RX 3
+#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01D10000
+#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
+#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
+
void __init dm365_init(void);
void __init dm365_init_asp(struct snd_platform_data *pdata);
void __init dm365_init_vc(struct snd_platform_data *pdata);
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 1a8b09c..6fca568 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -34,6 +34,12 @@
#define DM644X_EMAC_MDIO_OFFSET (0x4000)
#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000)
+#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01E00000
+#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
+#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
+#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
+#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
+
void __init dm644x_init(void);
void __init dm644x_init_asp(struct snd_platform_data *pdata);
void dm644x_set_vpfe_config(struct vpfe_config *cfg);
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 846da98..4d62db7 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -27,6 +27,9 @@
#define DM646X_ATA_REG_BASE (0x01C66000)
+#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
+#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
+
void __init dm646x_init(void);
void __init dm646x_init_ide(void);
void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 18/34] DA830 EVM: use DA8XX_AEMIF_*_BASE #define's
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (16 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 17/34] DaVinci: move AEMIF #define's to the proper headers Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 19/34] davinci: DM365: Allow use of GPIO64_57 Kevin Hilman
` (15 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Sergei Shtylyov <sshtylyov@ru.mvista.com>
The board file #define's its own version of EMIFA base addresses, while there
are DA8XX_AEMIF_*_BASE macros #define'd in <mach/da8xx.h>. Start using them
instead.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/board-da830-evm.c | 11 ++++-------
1 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 9257056..8f079d2 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -33,9 +33,6 @@
#define DA830_EVM_PHY_MASK 0x0
#define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
-#define DA830_EMIF25_ASYNC_DATA_CE3_BASE 0x62000000
-#define DA830_EMIF25_CONTROL_BASE 0x68000000
-
/*
* USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
*/
@@ -375,13 +372,13 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = {
static struct resource da830_evm_nand_resources[] = {
[0] = { /* First memory resource is NAND I/O window */
- .start = DA830_EMIF25_ASYNC_DATA_CE3_BASE,
- .end = DA830_EMIF25_ASYNC_DATA_CE3_BASE + PAGE_SIZE - 1,
+ .start = DA8XX_AEMIF_CS3_BASE,
+ .end = DA8XX_AEMIF_CS3_BASE + PAGE_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = { /* Second memory resource is AEMIF control registers */
- .start = DA830_EMIF25_CONTROL_BASE,
- .end = DA830_EMIF25_CONTROL_BASE + SZ_32K - 1,
+ .start = DA8XX_AEMIF_CTL_BASE,
+ .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
.flags = IORESOURCE_MEM,
},
};
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 19/34] davinci: DM365: Allow use of GPIO64_57
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (17 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 18/34] DA830 EVM: use DA8XX_AEMIF_*_BASE #define's Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 20/34] Davinci: configurable pll divider mask Kevin Hilman
` (14 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Thomas Koeller <thomas.koeller@baslerweb.com>
Extended the MUX configuration to allow use of GPIO
terminals 64..57.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/dm365.c | 1 +
arch/arm/mach-davinci/include/mach/mux.h | 1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 871be5a..1ee3fc8 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -576,6 +576,7 @@ MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
+MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 8638903..923debe 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -291,6 +291,7 @@ enum davinci_dm365_index {
DM365_GPIO20,
DM365_GPIO33,
DM365_GPIO40,
+ DM365_GPIO64_57,
/* Video */
DM365_VOUT_FIELD,
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 20/34] Davinci: configurable pll divider mask
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (18 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 19/34] davinci: DM365: Allow use of GPIO64_57 Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 21/34] davinci: mach/common.h: add missing includes Kevin Hilman
` (13 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
This patch allows socs to override the divider ratio mask by setting an
optional field (div_ratio_mask) in the pll_data structure.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/clock.c | 9 ++++++---
arch/arm/mach-davinci/clock.h | 1 +
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 5de60ae..868cb76 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -279,7 +279,7 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
v = __raw_readl(pll->base + clk->div_reg);
if (v & PLLDIV_EN) {
- plldiv = (v & PLLDIV_RATIO_MASK) + 1;
+ plldiv = (v & pll->div_ratio_mask) + 1;
if (plldiv)
rate /= plldiv;
}
@@ -319,7 +319,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
if (pll->flags & PLL_HAS_PREDIV) {
prediv = __raw_readl(pll->base + PREDIV);
if (prediv & PLLDIV_EN)
- prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
+ prediv = (prediv & pll->div_ratio_mask) + 1;
else
prediv = 1;
}
@@ -331,7 +331,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
if (pll->flags & PLL_HAS_POSTDIV) {
postdiv = __raw_readl(pll->base + POSTDIV);
if (postdiv & PLLDIV_EN)
- postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
+ postdiv = (postdiv & pll->div_ratio_mask) + 1;
else
postdiv = 1;
}
@@ -458,6 +458,9 @@ int __init davinci_clk_init(struct clk_lookup *clocks)
clk->recalc = clk_leafclk_recalc;
}
+ if (clk->pll_data && !clk->pll_data->div_ratio_mask)
+ clk->pll_data->div_ratio_mask = PLLDIV_RATIO_MASK;
+
if (clk->recalc)
clk->rate = clk->recalc(clk);
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 53a0f7b..ce26015 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -76,6 +76,7 @@ struct pll_data {
u32 num;
u32 flags;
u32 input_rate;
+ u32 div_ratio_mask;
};
#define PLL_HAS_PREDIV 0x01
#define PLL_HAS_POSTDIV 0x02
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 21/34] davinci: mach/common.h: add missing includes
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (19 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 20/34] Davinci: configurable pll divider mask Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 22/34] DaVinci: move IDE platform device to its proper place Kevin Hilman
` (12 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Thomas Koeller <thomas.koeller@baslerweb.com>
linux/compiler.h is required for __iomem
linux/types.h is required u32
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/include/mach/common.h | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 50a955f..d88104e 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -12,6 +12,9 @@
#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
#define __ARCH_ARM_MACH_DAVINCI_COMMON_H
+#include <linux/compiler.h>
+#include <linux/types.h>
+
struct sys_timer;
extern struct sys_timer davinci_timer;
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 22/34] DaVinci: move IDE platform device to its proper place
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (20 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 21/34] davinci: mach/common.h: add missing includes Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 23/34] Davinci: gpio - minor cleanup Kevin Hilman
` (11 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Sergei Shtylyov <sshtylyov@ru.mvista.com>
The IDE platform device is registered in three different places (2 board files
for DM644x and in dm646x.c for DM646x) while both the IDE base address and the
IDE IRQ are the same for both SoCs -- therefore, the proper place for the IDE
platform seems to be in devices.c. Merge the IDE platform data and registration
code and create davinci_init_ide() in place of dm646x_init_ide()...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/board-dm644x-evm.c | 33 +-------------------
arch/arm/mach-davinci/board-dm646x-evm.c | 2 +-
arch/arm/mach-davinci/board-neuros-osd2.c | 34 +-------------------
arch/arm/mach-davinci/devices.c | 44 +++++++++++++++++++++++++++
arch/arm/mach-davinci/dm646x.c | 32 -------------------
arch/arm/mach-davinci/include/mach/common.h | 1 +
arch/arm/mach-davinci/include/mach/dm646x.h | 3 --
7 files changed, 49 insertions(+), 100 deletions(-)
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index d028bab..73c0b04 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -41,8 +41,6 @@
#define DM644X_EVM_PHY_MASK (0x2)
#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
-#define DAVINCI_CFC_ATA_BASE 0x01C66000
-
#define LXT971_PHY_ID (0x001378e2)
#define LXT971_PHY_MASK (0xfffffff0)
@@ -252,32 +250,6 @@ static struct platform_device rtc_dev = {
.id = -1,
};
-static struct resource ide_resources[] = {
- {
- .start = DAVINCI_CFC_ATA_BASE,
- .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_IDE,
- .end = IRQ_IDE,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 ide_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device ide_dev = {
- .name = "palm_bk3710",
- .id = -1,
- .resource = ide_resources,
- .num_resources = ARRAY_SIZE(ide_resources),
- .dev = {
- .dma_mask = &ide_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
static struct snd_platform_data dm644x_evm_snd_data;
/*----------------------------------------------------------------------*/
@@ -698,10 +670,7 @@ static __init void davinci_evm_init(void)
pr_warning("WARNING: both IDE and Flash are "
"enabled, but they share AEMIF pins.\n"
"\tDisable IDE for NAND/NOR support.\n");
- davinci_cfg_reg(DM644X_HPIEN_DISABLE);
- davinci_cfg_reg(DM644X_ATAEN);
- davinci_cfg_reg(DM644X_HDIREN);
- platform_device_register(&ide_dev);
+ davinci_init_ide();
} else if (HAS_NAND || HAS_NOR) {
davinci_cfg_reg(DM644X_HPIEN_DISABLE);
davinci_cfg_reg(DM644X_ATAEN_DISABLE);
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index b22e22c..e2ac06f 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -733,7 +733,7 @@ static __init void evm_init(void)
platform_device_register(&davinci_nand_device);
if (HAS_ATA)
- dm646x_init_ide();
+ davinci_init_ide();
soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 5afe37e..875770c 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -31,6 +31,7 @@
#include <asm/mach/arch.h>
#include <mach/dm644x.h>
+#include <mach/common.h>
#include <mach/i2c.h>
#include <mach/serial.h>
#include <mach/mux.h>
@@ -41,8 +42,6 @@
#define NEUROS_OSD2_PHY_MASK 0x2
#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
-#define DAVINCI_CFC_ATA_BASE 0x01C66000
-
#define LXT971_PHY_ID 0x001378e2
#define LXT971_PHY_MASK 0xfffffff0
@@ -127,32 +126,6 @@ static struct platform_device davinci_fb_device = {
.num_resources = 0,
};
-static struct resource ide_resources[] = {
- {
- .start = DAVINCI_CFC_ATA_BASE,
- .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_IDE,
- .end = IRQ_IDE,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 ide_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device ide_dev = {
- .name = "palm_bk3710",
- .id = -1,
- .resource = ide_resources,
- .num_resources = ARRAY_SIZE(ide_resources),
- .dev = {
- .dma_mask = &ide_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
static struct snd_platform_data dm644x_ntosd2_snd_data;
static struct gpio_led ntosd2_leds[] = {
@@ -256,10 +229,7 @@ static __init void davinci_ntosd2_init(void)
pr_warning("WARNING: both IDE and Flash are "
"enabled, but they share AEMIF pins.\n"
"\tDisable IDE for NAND/NOR support.\n");
- davinci_cfg_reg(DM644X_HPIEN_DISABLE);
- davinci_cfg_reg(DM644X_ATAEN);
- davinci_cfg_reg(DM644X_HDIREN);
- platform_device_register(&ide_dev);
+ davinci_init_ide();
} else if (HAS_NAND) {
davinci_cfg_reg(DM644X_HPIEN_DISABLE);
davinci_cfg_reg(DM644X_ATAEN_DISABLE);
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index ef28080..d9c82ee 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -26,6 +26,7 @@
#include "clock.h"
#define DAVINCI_I2C_BASE 0x01C21000
+#define DAVINCI_ATA_BASE 0x01C66000
#define DAVINCI_MMCSD0_BASE 0x01E10000
#define DM355_MMCSD0_BASE 0x01E11000
#define DM355_MMCSD1_BASE 0x01E00000
@@ -60,6 +61,49 @@ void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
(void) platform_device_register(&davinci_i2c_device);
}
+static struct resource ide_resources[] = {
+ {
+ .start = DAVINCI_ATA_BASE,
+ .end = DAVINCI_ATA_BASE + 0x7ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_IDE,
+ .end = IRQ_IDE,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 ide_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device ide_device = {
+ .name = "palm_bk3710",
+ .id = -1,
+ .resource = ide_resources,
+ .num_resources = ARRAY_SIZE(ide_resources),
+ .dev = {
+ .dma_mask = &ide_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+void __init davinci_init_ide(void)
+{
+ if (cpu_is_davinci_dm644x()) {
+ davinci_cfg_reg(DM644X_HPIEN_DISABLE);
+ davinci_cfg_reg(DM644X_ATAEN);
+ davinci_cfg_reg(DM644X_HDIREN);
+ } else if (cpu_is_davinci_dm646x()) {
+ /* IRQ_DM646X_IDE is the same as IRQ_IDE */
+ davinci_cfg_reg(DM646X_ATAEN);
+ } else {
+ WARN_ON(1);
+ return;
+ }
+
+ platform_device_register(&ide_device);
+}
+
#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index b67b997..a0b3739 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -596,32 +596,6 @@ static struct platform_device dm646x_edma_device = {
.resource = edma_resources,
};
-static struct resource ide_resources[] = {
- {
- .start = DM646X_ATA_REG_BASE,
- .end = DM646X_ATA_REG_BASE + 0x7ff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_DM646X_IDE,
- .end = IRQ_DM646X_IDE,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 ide_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device ide_dev = {
- .name = "palm_bk3710",
- .id = -1,
- .resource = ide_resources,
- .num_resources = ARRAY_SIZE(ide_resources),
- .dev = {
- .dma_mask = &ide_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
static struct resource dm646x_mcasp0_resources[] = {
{
.name = "mcasp0",
@@ -867,12 +841,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
.sram_len = SZ_32K,
};
-void __init dm646x_init_ide(void)
-{
- davinci_cfg_reg(DM646X_ATAEN);
- platform_device_register(&ide_dev);
-}
-
void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
{
dm646x_mcasp0_device.dev.platform_data = pdata;
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index d88104e..884dc72 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -70,6 +70,7 @@ struct davinci_soc_info {
extern struct davinci_soc_info davinci_soc_info;
extern void davinci_common_init(struct davinci_soc_info *soc_info);
+extern void davinci_init_ide(void);
/* standard place to map on-chip SRAMs; they *may* support DMA */
#define SRAM_VIRT 0xfffe0000
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 4d62db7..add6f79 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -25,13 +25,10 @@
#define DM646X_EMAC_MDIO_OFFSET (0x4000)
#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000)
-#define DM646X_ATA_REG_BASE (0x01C66000)
-
#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
void __init dm646x_init(void);
-void __init dm646x_init_ide(void);
void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
void __init dm646x_board_setup_refclk(struct clk *clk);
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 23/34] Davinci: gpio - minor cleanup
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (21 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 22/34] DaVinci: move IDE platform device to its proper place Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 24/34] Davinci: gpio - structs and functions renamed Kevin Hilman
` (10 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
macroized repeated container_of()s to improve readability.
unified direction in/out functions.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/gpio.c | 50 ++++++++++++++++++++++-------------------
1 files changed, 27 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 5476ad1..93f7c68 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -28,6 +28,9 @@ struct davinci_gpio {
int irq_base;
};
+#define chip2controller(chip) \
+ container_of(chip, struct davinci_gpio, chip)
+
static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
/* create a non-inlined version */
@@ -54,21 +57,39 @@ static int __init davinci_gpio_irq_setup(void);
* needed, and enable the GPIO clock.
*/
-static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
+static inline int __davinci_direction(struct gpio_chip *chip,
+ unsigned offset, bool out, int value)
{
- struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+ struct davinci_gpio *d = chip2controller(chip);
struct gpio_controller __iomem *g = d->regs;
u32 temp;
+ u32 mask = 1 << offset;
spin_lock(&gpio_lock);
temp = __raw_readl(&g->dir);
- temp |= (1 << offset);
+ if (out) {
+ temp &= ~mask;
+ __raw_writel(mask, value ? &g->set_data : &g->clr_data);
+ } else {
+ temp |= mask;
+ }
__raw_writel(temp, &g->dir);
spin_unlock(&gpio_lock);
return 0;
}
+static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
+{
+ return __davinci_direction(chip, offset, false, 0);
+}
+
+static int
+davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
+{
+ return __davinci_direction(chip, offset, true, value);
+}
+
/*
* Read the pin's value (works even if it's set up as output);
* returns zero/nonzero.
@@ -78,36 +99,19 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
*/
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
- struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+ struct davinci_gpio *d = chip2controller(chip);
struct gpio_controller __iomem *g = d->regs;
return (1 << offset) & __raw_readl(&g->in_data);
}
-static int
-davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
-{
- struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
- struct gpio_controller __iomem *g = d->regs;
- u32 temp;
- u32 mask = 1 << offset;
-
- spin_lock(&gpio_lock);
- temp = __raw_readl(&g->dir);
- temp &= ~mask;
- __raw_writel(mask, value ? &g->set_data : &g->clr_data);
- __raw_writel(temp, &g->dir);
- spin_unlock(&gpio_lock);
- return 0;
-}
-
/*
* Assuming the pin is muxed as a gpio output, set its output value.
*/
static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
- struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+ struct davinci_gpio *d = chip2controller(chip);
struct gpio_controller __iomem *g = d->regs;
__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
@@ -262,7 +266,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
{
- struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+ struct davinci_gpio *d = chip2controller(chip);
if (d->irq_base >= 0)
return d->irq_base + offset;
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 24/34] Davinci: gpio - structs and functions renamed
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (22 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 23/34] Davinci: gpio - minor cleanup Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 25/34] Davinci: gpio - register layout invariant inlines Kevin Hilman
` (9 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
Renamed gpio types to something more sensible:
struct gpio_controller --> struct davinci_gpio_regs
struct davinci_gpio --> struct davinci_gpio_controller
gpio2controller() --> gpio2regs()
irq2controller() --> irq2regs()
This change also moves davinci_gpio_controller definition to gpio.h.
Eventually, the gpio registers structure will be moved to gpio.c and no longer
a common cross-soc definition.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/gpio.c | 50 +++++++++++++----------------
arch/arm/mach-davinci/include/mach/gpio.h | 14 ++++++--
2 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 93f7c68..c77683c 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -22,28 +22,22 @@
static DEFINE_SPINLOCK(gpio_lock);
-struct davinci_gpio {
- struct gpio_chip chip;
- struct gpio_controller __iomem *regs;
- int irq_base;
-};
-
#define chip2controller(chip) \
- container_of(chip, struct davinci_gpio, chip)
+ container_of(chip, struct davinci_gpio_controller, chip)
-static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
+static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
/* create a non-inlined version */
-static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
+static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
{
return __gpio_to_controller(gpio);
}
-static inline struct gpio_controller __iomem *irq2controller(int irq)
+static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
{
- struct gpio_controller __iomem *g;
+ struct davinci_gpio_regs __iomem *g;
- g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq);
+ g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
return g;
}
@@ -60,8 +54,8 @@ static int __init davinci_gpio_irq_setup(void);
static inline int __davinci_direction(struct gpio_chip *chip,
unsigned offset, bool out, int value)
{
- struct davinci_gpio *d = chip2controller(chip);
- struct gpio_controller __iomem *g = d->regs;
+ struct davinci_gpio_controller *d = chip2controller(chip);
+ struct davinci_gpio_regs __iomem *g = d->regs;
u32 temp;
u32 mask = 1 << offset;
@@ -99,8 +93,8 @@ davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
*/
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
- struct davinci_gpio *d = chip2controller(chip);
- struct gpio_controller __iomem *g = d->regs;
+ struct davinci_gpio_controller *d = chip2controller(chip);
+ struct davinci_gpio_regs __iomem *g = d->regs;
return (1 << offset) & __raw_readl(&g->in_data);
}
@@ -111,8 +105,8 @@ static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
- struct davinci_gpio *d = chip2controller(chip);
- struct gpio_controller __iomem *g = d->regs;
+ struct davinci_gpio_controller *d = chip2controller(chip);
+ struct davinci_gpio_regs __iomem *g = d->regs;
__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
}
@@ -150,7 +144,7 @@ static int __init davinci_gpio_setup(void)
if (chips[i].chip.ngpio > 32)
chips[i].chip.ngpio = 32;
- chips[i].regs = gpio2controller(base);
+ chips[i].regs = gpio2regs(base);
gpiochip_add(&chips[i].chip);
}
@@ -174,7 +168,7 @@ pure_initcall(davinci_gpio_setup);
static void gpio_irq_disable(unsigned irq)
{
- struct gpio_controller __iomem *g = irq2controller(irq);
+ struct davinci_gpio_regs __iomem *g = irq2regs(irq);
u32 mask = (u32) get_irq_data(irq);
__raw_writel(mask, &g->clr_falling);
@@ -183,7 +177,7 @@ static void gpio_irq_disable(unsigned irq)
static void gpio_irq_enable(unsigned irq)
{
- struct gpio_controller __iomem *g = irq2controller(irq);
+ struct davinci_gpio_regs __iomem *g = irq2regs(irq);
u32 mask = (u32) get_irq_data(irq);
unsigned status = irq_desc[irq].status;
@@ -199,7 +193,7 @@ static void gpio_irq_enable(unsigned irq)
static int gpio_irq_type(unsigned irq, unsigned trigger)
{
- struct gpio_controller __iomem *g = irq2controller(irq);
+ struct davinci_gpio_regs __iomem *g = irq2regs(irq);
u32 mask = (u32) get_irq_data(irq);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -228,7 +222,7 @@ static struct irq_chip gpio_irqchip = {
static void
gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
- struct gpio_controller __iomem *g = irq2controller(irq);
+ struct davinci_gpio_regs __iomem *g = irq2regs(irq);
u32 mask = 0xffff;
/* we only care about one bank */
@@ -266,7 +260,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
{
- struct davinci_gpio *d = chip2controller(chip);
+ struct davinci_gpio_controller *d = chip2controller(chip);
if (d->irq_base >= 0)
return d->irq_base + offset;
@@ -289,7 +283,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
{
- struct gpio_controller __iomem *g = irq2controller(irq);
+ struct davinci_gpio_regs __iomem *g = irq2regs(irq);
u32 mask = (u32) get_irq_data(irq);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -318,7 +312,7 @@ static int __init davinci_gpio_irq_setup(void)
u32 binten = 0;
unsigned ngpio, bank_irq;
struct davinci_soc_info *soc_info = &davinci_soc_info;
- struct gpio_controller __iomem *g;
+ struct davinci_gpio_regs __iomem *g;
ngpio = soc_info->gpio_num;
@@ -367,7 +361,7 @@ static int __init davinci_gpio_irq_setup(void)
gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
/* default trigger: both edges */
- g = gpio2controller(0);
+ g = gpio2regs(0);
__raw_writel(~0, &g->set_falling);
__raw_writel(~0, &g->set_rising);
@@ -392,7 +386,7 @@ static int __init davinci_gpio_irq_setup(void)
unsigned i;
/* disabled by default, enabled only as needed */
- g = gpio2controller(gpio);
+ g = gpio2regs(gpio);
__raw_writel(~0, &g->clr_falling);
__raw_writel(~0, &g->clr_rising);
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 0099e6e..bdab001 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -45,7 +45,7 @@
/* Convert GPIO signal to GPIO pin number */
#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio))
-struct gpio_controller {
+struct davinci_gpio_regs {
u32 dir;
u32 out_data;
u32 set_data;
@@ -58,6 +58,12 @@ struct gpio_controller {
u32 intstat;
};
+struct davinci_gpio_controller {
+ struct davinci_gpio_regs __iomem *regs;
+ struct gpio_chip chip;
+ int irq_base;
+};
+
/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
* with constant parameters; or in outlined code they execute at runtime.
*
@@ -67,7 +73,7 @@ struct gpio_controller {
*
* These are NOT part of the cross-platform GPIO interface
*/
-static inline struct gpio_controller __iomem *
+static inline struct davinci_gpio_regs __iomem *
__gpio_to_controller(unsigned gpio)
{
void __iomem *ptr;
@@ -102,7 +108,7 @@ static inline u32 __gpio_mask(unsigned gpio)
static inline void gpio_set_value(unsigned gpio, int value)
{
if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
- struct gpio_controller __iomem *g;
+ struct davinci_gpio_regs __iomem *g;
u32 mask;
g = __gpio_to_controller(gpio);
@@ -128,7 +134,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
*/
static inline int gpio_get_value(unsigned gpio)
{
- struct gpio_controller __iomem *g;
+ struct davinci_gpio_regs __iomem *g;
if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
return __gpio_get_value(gpio);
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 25/34] Davinci: gpio - register layout invariant inlines
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (23 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 24/34] Davinci: gpio - structs and functions renamed Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 26/34] Davinci: gpio - controller type support Kevin Hilman
` (8 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
This patch renders the inlined gpio accessors in gpio.h independent of the
underlying controller's register layout. This is done by including three new
fields in davinci_gpio_controller to hold the addresses of the set, clear, and
in data registers.
Other changes:
1. davinci_gpio_regs structure definition moved to gpio.c. This structure is
no longer common across all davinci socs (davinci_gpio_controller is).
2. controller base address calculation code (gpio2controller()) moved to
gpio.c as this was no longer necessary for the inline implementation.
3. modified inline range checks to use davinci_soc_info.gpio_num instead of
DAVINCI_N_GPIO.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/gpio.c | 41 ++++++++++++++++-
arch/arm/mach-davinci/include/mach/common.h | 4 ++
arch/arm/mach-davinci/include/mach/gpio.h | 65 +++++++++-----------------
3 files changed, 65 insertions(+), 45 deletions(-)
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index c77683c..d241b4f 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -20,6 +20,19 @@
#include <asm/mach/irq.h>
+struct davinci_gpio_regs {
+ u32 dir;
+ u32 out_data;
+ u32 set_data;
+ u32 clr_data;
+ u32 in_data;
+ u32 set_rising;
+ u32 clr_rising;
+ u32 set_falling;
+ u32 clr_falling;
+ u32 intstat;
+};
+
static DEFINE_SPINLOCK(gpio_lock);
#define chip2controller(chip) \
@@ -27,10 +40,24 @@ static DEFINE_SPINLOCK(gpio_lock);
static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
-/* create a non-inlined version */
static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
{
- return __gpio_to_controller(gpio);
+ void __iomem *ptr;
+ void __iomem *base = davinci_soc_info.gpio_base;
+
+ if (gpio < 32 * 1)
+ ptr = base + 0x10;
+ else if (gpio < 32 * 2)
+ ptr = base + 0x38;
+ else if (gpio < 32 * 3)
+ ptr = base + 0x60;
+ else if (gpio < 32 * 4)
+ ptr = base + 0x88;
+ else if (gpio < 32 * 5)
+ ptr = base + 0xb0;
+ else
+ ptr = NULL;
+ return ptr;
}
static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
@@ -116,6 +143,7 @@ static int __init davinci_gpio_setup(void)
int i, base;
unsigned ngpio;
struct davinci_soc_info *soc_info = &davinci_soc_info;
+ struct davinci_gpio_regs *regs;
/*
* The gpio banks conceptually expose a segmented bitmap,
@@ -144,11 +172,18 @@ static int __init davinci_gpio_setup(void)
if (chips[i].chip.ngpio > 32)
chips[i].chip.ngpio = 32;
- chips[i].regs = gpio2regs(base);
+ regs = gpio2regs(base);
+ chips[i].regs = regs;
+ chips[i].set_data = ®s->set_data;
+ chips[i].clr_data = ®s->clr_data;
+ chips[i].in_data = ®s->in_data;
gpiochip_add(&chips[i].chip);
}
+ soc_info->gpio_ctlrs = chips;
+ soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
+
davinci_gpio_irq_setup();
return 0;
}
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 884dc72..1d72883 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -37,6 +37,8 @@ struct davinci_timer_info {
unsigned int clocksource_id;
};
+struct davinci_gpio_controller;
+
/* SoC specific init support */
struct davinci_soc_info {
struct map_desc *io_desc;
@@ -61,6 +63,8 @@ struct davinci_soc_info {
unsigned gpio_num;
unsigned gpio_irq;
unsigned gpio_unbanked;
+ struct davinci_gpio_controller *gpio_ctlrs;
+ int gpio_ctlrs_num;
struct platform_device *serial_dev;
struct emac_platform_data *emac_pdata;
dma_addr_t sram_dma;
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index bdab001..82591d0 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -45,23 +45,13 @@
/* Convert GPIO signal to GPIO pin number */
#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio))
-struct davinci_gpio_regs {
- u32 dir;
- u32 out_data;
- u32 set_data;
- u32 clr_data;
- u32 in_data;
- u32 set_rising;
- u32 clr_rising;
- u32 set_falling;
- u32 clr_falling;
- u32 intstat;
-};
-
struct davinci_gpio_controller {
- struct davinci_gpio_regs __iomem *regs;
struct gpio_chip chip;
int irq_base;
+ void __iomem *regs;
+ void __iomem *set_data;
+ void __iomem *clr_data;
+ void __iomem *in_data;
};
/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
@@ -73,25 +63,16 @@ struct davinci_gpio_controller {
*
* These are NOT part of the cross-platform GPIO interface
*/
-static inline struct davinci_gpio_regs __iomem *
+static inline struct davinci_gpio_controller *
__gpio_to_controller(unsigned gpio)
{
- void __iomem *ptr;
- void __iomem *base = davinci_soc_info.gpio_base;
-
- if (gpio < 32 * 1)
- ptr = base + 0x10;
- else if (gpio < 32 * 2)
- ptr = base + 0x38;
- else if (gpio < 32 * 3)
- ptr = base + 0x60;
- else if (gpio < 32 * 4)
- ptr = base + 0x88;
- else if (gpio < 32 * 5)
- ptr = base + 0xb0;
- else
- ptr = NULL;
- return ptr;
+ struct davinci_gpio_controller *ctlrs = davinci_soc_info.gpio_ctlrs;
+ int index = gpio / 32;
+
+ if (!ctlrs || index >= davinci_soc_info.gpio_ctlrs_num)
+ return NULL;
+
+ return ctlrs + index;
}
static inline u32 __gpio_mask(unsigned gpio)
@@ -107,16 +88,16 @@ static inline u32 __gpio_mask(unsigned gpio)
*/
static inline void gpio_set_value(unsigned gpio, int value)
{
- if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
- struct davinci_gpio_regs __iomem *g;
- u32 mask;
+ if (__builtin_constant_p(value) && gpio < davinci_soc_info.gpio_num) {
+ struct davinci_gpio_controller *ctlr;
+ u32 mask;
- g = __gpio_to_controller(gpio);
+ ctlr = __gpio_to_controller(gpio);
mask = __gpio_mask(gpio);
if (value)
- __raw_writel(mask, &g->set_data);
+ __raw_writel(mask, ctlr->set_data);
else
- __raw_writel(mask, &g->clr_data);
+ __raw_writel(mask, ctlr->clr_data);
return;
}
@@ -134,18 +115,18 @@ static inline void gpio_set_value(unsigned gpio, int value)
*/
static inline int gpio_get_value(unsigned gpio)
{
- struct davinci_gpio_regs __iomem *g;
+ struct davinci_gpio_controller *ctlr;
- if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
+ if (!__builtin_constant_p(gpio) || gpio >= davinci_soc_info.gpio_num)
return __gpio_get_value(gpio);
- g = __gpio_to_controller(gpio);
- return __gpio_mask(gpio) & __raw_readl(&g->in_data);
+ ctlr = __gpio_to_controller(gpio);
+ return __gpio_mask(gpio) & __raw_readl(ctlr->in_data);
}
static inline int gpio_cansleep(unsigned gpio)
{
- if (__builtin_constant_p(gpio) && gpio < DAVINCI_N_GPIO)
+ if (__builtin_constant_p(gpio) && gpio < davinci_soc_info.gpio_num)
return 0;
else
return __gpio_cansleep(gpio);
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 26/34] Davinci: gpio - controller type support
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (24 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 25/34] Davinci: gpio - register layout invariant inlines Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 27/34] Davinci: gpio - fine grained locking Kevin Hilman
` (7 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
This patch allows for gpio controllers that deviate from those found on
traditional davinci socs. davinci_soc_info has an added field to indicate the
soc-specific gpio controller type. The gpio initialization code then bails
out if necessary.
More elements (tnetv107x) to be added later into enum davinci_gpio_type.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/da830.c | 2 ++
arch/arm/mach-davinci/da850.c | 2 ++
arch/arm/mach-davinci/dm355.c | 1 +
arch/arm/mach-davinci/dm365.c | 1 +
arch/arm/mach-davinci/dm644x.c | 1 +
arch/arm/mach-davinci/dm646x.c | 1 +
arch/arm/mach-davinci/gpio.c | 3 +++
arch/arm/mach-davinci/include/mach/common.h | 1 +
arch/arm/mach-davinci/include/mach/gpio.h | 4 ++++
9 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 122e61a..68e5233 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -19,6 +19,7 @@
#include <mach/common.h>
#include <mach/time.h>
#include <mach/da8xx.h>
+#include <mach/gpio.h>
#include "clock.h"
#include "mux.h"
@@ -1199,6 +1200,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
.intc_irq_prios = da830_default_priorities,
.intc_irq_num = DA830_N_CP_INTC_IRQ,
.timer_info = &da830_timer_info,
+ .gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
.gpio_num = 128,
.gpio_irq = IRQ_DA8XX_GPIO0,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index d0fd756..8aefcff 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -27,6 +27,7 @@
#include <mach/da8xx.h>
#include <mach/cpufreq.h>
#include <mach/pm.h>
+#include <mach/gpio.h>
#include "clock.h"
#include "mux.h"
@@ -1084,6 +1085,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
.intc_irq_prios = da850_default_priorities,
.intc_irq_num = DA850_N_CP_INTC_IRQ,
.timer_info = &da850_timer_info,
+ .gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
.gpio_num = 144,
.gpio_irq = IRQ_DA8XX_GPIO0,
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 5efce70..f9a54ff 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -859,6 +859,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
.intc_irq_prios = dm355_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm355_timer_info,
+ .gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
.gpio_num = 104,
.gpio_irq = IRQ_DM355_GPIOBNK0,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 1ee3fc8..0566675 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1064,6 +1064,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
.intc_irq_prios = dm365_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm365_timer_info,
+ .gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
.gpio_num = 104,
.gpio_irq = IRQ_DM365_GPIO0,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 23cbe9d..4af349e 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -748,6 +748,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
.intc_irq_prios = dm644x_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm644x_timer_info,
+ .gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
.gpio_num = 71,
.gpio_irq = IRQ_GPIOBNK0,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index a0b3739..bdb1ace 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -832,6 +832,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
.intc_irq_prios = dm646x_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm646x_timer_info,
+ .gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
.gpio_num = 43, /* Only 33 usable */
.gpio_irq = IRQ_DM646X_GPIOBNK0,
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index d241b4f..e422cd3 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -145,6 +145,9 @@ static int __init davinci_gpio_setup(void)
struct davinci_soc_info *soc_info = &davinci_soc_info;
struct davinci_gpio_regs *regs;
+ if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
+ return 0;
+
/*
* The gpio banks conceptually expose a segmented bitmap,
* and "ngpio" is one more than the largest zero-based
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 1d72883..8ffef5b 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -59,6 +59,7 @@ struct davinci_soc_info {
u8 *intc_irq_prios;
unsigned long intc_irq_num;
struct davinci_timer_info *timer_info;
+ int gpio_type;
void __iomem *gpio_base;
unsigned gpio_num;
unsigned gpio_irq;
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 82591d0..9a71a26 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -21,6 +21,10 @@
#define DAVINCI_GPIO_BASE 0x01C67000
+enum davinci_gpio_type {
+ GPIO_TYPE_DAVINCI = 0,
+};
+
/*
* basic gpio routines
*
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 27/34] Davinci: gpio - fine grained locking
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (25 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 26/34] Davinci: gpio - controller type support Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 28/34] Davinci: eliminate pinmux offset verbosity Kevin Hilman
` (6 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
This patch eliminates the global gpio_lock, and implements a per-controller
lock instead. This also switches to irqsave/irqrestore locks in case gpios
are manipulated in isr.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/gpio.c | 9 +++++----
arch/arm/mach-davinci/include/mach/gpio.h | 3 +++
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index e422cd3..b62d5e2 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -33,8 +33,6 @@ struct davinci_gpio_regs {
u32 intstat;
};
-static DEFINE_SPINLOCK(gpio_lock);
-
#define chip2controller(chip) \
container_of(chip, struct davinci_gpio_controller, chip)
@@ -83,10 +81,11 @@ static inline int __davinci_direction(struct gpio_chip *chip,
{
struct davinci_gpio_controller *d = chip2controller(chip);
struct davinci_gpio_regs __iomem *g = d->regs;
+ unsigned long flags;
u32 temp;
u32 mask = 1 << offset;
- spin_lock(&gpio_lock);
+ spin_lock_irqsave(&d->lock, flags);
temp = __raw_readl(&g->dir);
if (out) {
temp &= ~mask;
@@ -95,7 +94,7 @@ static inline int __davinci_direction(struct gpio_chip *chip,
temp |= mask;
}
__raw_writel(temp, &g->dir);
- spin_unlock(&gpio_lock);
+ spin_unlock_irqrestore(&d->lock, flags);
return 0;
}
@@ -175,6 +174,8 @@ static int __init davinci_gpio_setup(void)
if (chips[i].chip.ngpio > 32)
chips[i].chip.ngpio = 32;
+ spin_lock_init(&chips[i].lock);
+
regs = gpio2regs(base);
chips[i].regs = regs;
chips[i].set_data = ®s->set_data;
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 9a71a26..504cc18 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -14,6 +14,8 @@
#define __DAVINCI_GPIO_H
#include <linux/io.h>
+#include <linux/spinlock.h>
+
#include <asm-generic/gpio.h>
#include <mach/irqs.h>
@@ -52,6 +54,7 @@ enum davinci_gpio_type {
struct davinci_gpio_controller {
struct gpio_chip chip;
int irq_base;
+ spinlock_t lock;
void __iomem *regs;
void __iomem *set_data;
void __iomem *clr_data;
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 28/34] Davinci: eliminate pinmux offset verbosity
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (26 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 27/34] Davinci: gpio - fine grained locking Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 29/34] Davinci: watchdog reset separation across socs Kevin Hilman
` (5 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
Pinmux registers are sequential, and do not need to be enumerated out as they
currently are. This reduces code volume and keeps things simple.
If some future SoC comes up with a discontiguous register map, PINMUX() can
then be expanded with local token pasting.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/dm355.c | 5 -----
arch/arm/mach-davinci/dm365.c | 5 -----
arch/arm/mach-davinci/dm644x.c | 3 ---
arch/arm/mach-davinci/dm646x.c | 3 ---
arch/arm/mach-davinci/gpio.c | 6 +-----
arch/arm/mach-davinci/include/mach/da8xx.h | 21 ---------------------
arch/arm/mach-davinci/include/mach/mux.h | 2 ++
arch/arm/mach-davinci/mux.h | 2 +-
8 files changed, 4 insertions(+), 43 deletions(-)
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index f9a54ff..f91e9a1 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -450,11 +450,6 @@ void __init dm355_init_spi0(unsigned chipselect_mask,
/*----------------------------------------------------------------------*/
-#define PINMUX0 0x00
-#define PINMUX1 0x04
-#define PINMUX2 0x08
-#define PINMUX3 0x0c
-#define PINMUX4 0x10
#define INTMUX 0x18
#define EVTMUX 0x1c
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0566675..f2b1d93 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -467,11 +467,6 @@ static struct clk_lookup dm365_clks[] = {
/*----------------------------------------------------------------------*/
-#define PINMUX0 0x00
-#define PINMUX1 0x04
-#define PINMUX2 0x08
-#define PINMUX3 0x0c
-#define PINMUX4 0x10
#define INTMUX 0x18
#define EVTMUX 0x1c
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 4af349e..85c88ec 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -350,9 +350,6 @@ static struct platform_device dm644x_emac_device = {
.resource = dm644x_emac_resources,
};
-#define PINMUX0 0x00
-#define PINMUX1 0x04
-
/*
* Device specific mux setup
*
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index bdb1ace..a8189c9 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -401,9 +401,6 @@ static struct platform_device dm646x_emac_device = {
.resource = dm646x_emac_resources,
};
-#define PINMUX0 0x00
-#define PINMUX1 0x04
-
/*
* Device specific mux setup
*
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index b62d5e2..2efb446 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -71,11 +71,7 @@ static int __init davinci_gpio_irq_setup(void);
/*--------------------------------------------------------------------------*/
-/*
- * board setup code *MUST* set PINMUX0 and PINMUX1 as
- * needed, and enable the GPIO clock.
- */
-
+/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
static inline int __davinci_direction(struct gpio_chip *chip,
unsigned offset, bool out, int value)
{
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 33471c9..dbb4ebe 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -64,27 +64,6 @@ extern void __iomem *da8xx_syscfg1_base;
#define DA8XX_DDR2_CTL_BASE 0xb0000000
#define DA8XX_ARM_RAM_BASE 0xffff0000
-#define PINMUX0 0x00
-#define PINMUX1 0x04
-#define PINMUX2 0x08
-#define PINMUX3 0x0c
-#define PINMUX4 0x10
-#define PINMUX5 0x14
-#define PINMUX6 0x18
-#define PINMUX7 0x1c
-#define PINMUX8 0x20
-#define PINMUX9 0x24
-#define PINMUX10 0x28
-#define PINMUX11 0x2c
-#define PINMUX12 0x30
-#define PINMUX13 0x34
-#define PINMUX14 0x38
-#define PINMUX15 0x3c
-#define PINMUX16 0x40
-#define PINMUX17 0x44
-#define PINMUX18 0x48
-#define PINMUX19 0x4c
-
void __init da830_init(void);
void __init da850_init(void);
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 923debe..743dbd2 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -1174,6 +1174,8 @@ enum davinci_tnetv107x_index {
TNETV107X_TDM0_RX,
};
+#define PINMUX(x) (4 * (x))
+
#ifdef CONFIG_DAVINCI_MUX
/* setup pin muxing */
extern int davinci_cfg_reg(unsigned long reg_cfg);
diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h
index adc8694..5aad1e7 100644
--- a/arch/arm/mach-davinci/mux.h
+++ b/arch/arm/mach-davinci/mux.h
@@ -20,7 +20,7 @@
.name = #desc, \
.debug = dbg, \
.mux_reg_name = "PINMUX"#muxreg, \
- .mux_reg = PINMUX##muxreg, \
+ .mux_reg = PINMUX(muxreg), \
.mask_offset = mode_offset, \
.mask = mode_mask, \
.mode = mux_mode, \
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 29/34] Davinci: watchdog reset separation across socs
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (27 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 28/34] Davinci: eliminate pinmux offset verbosity Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 30/34] Davinci: serial - remove unnecessary define Kevin Hilman
` (4 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
The earlier watchdog reset mechanism had a couple of limitations. First, it
embedded a reference to "davinci_wdt_device" inside common code. This
forced all derived platforms (da8xx and tnetv107x) to define such a device.
This also would have caused problems in including multiple socs in a single
build due to symbol redefinition.
With this patch, davinci_watchdog_reset() now takes the platform device as an
argument. The davinci_soc_info struct has been extended to include a reset
function and a watchdog platform_device. arch_reset() then uses these
elements to reset the system in a SoC specific fashion.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/clock.h | 1 +
arch/arm/mach-davinci/common.c | 3 +++
arch/arm/mach-davinci/da830.c | 1 +
arch/arm/mach-davinci/da850.c | 1 +
arch/arm/mach-davinci/devices-da8xx.c | 4 ++--
arch/arm/mach-davinci/dm355.c | 1 +
arch/arm/mach-davinci/dm365.c | 1 +
arch/arm/mach-davinci/dm644x.c | 1 +
arch/arm/mach-davinci/dm646x.c | 1 +
arch/arm/mach-davinci/include/mach/common.h | 2 ++
arch/arm/mach-davinci/include/mach/da8xx.h | 2 ++
arch/arm/mach-davinci/include/mach/system.h | 5 +++--
arch/arm/mach-davinci/time.c | 9 ++++++---
13 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index ce26015..01e3648 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -120,6 +120,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
unsigned int mult, unsigned int postdiv);
extern struct platform_device davinci_wdt_device;
+extern void davinci_watchdog_reset(struct platform_device *);
#endif
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 94f27cb..f8221c5 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -77,6 +77,9 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
local_flush_tlb_all();
flush_cache_all();
+ if (!davinci_soc_info.reset)
+ davinci_soc_info.reset = davinci_watchdog_reset;
+
/*
* We want to check CPU revision early for cpu_is_xxxx() macros.
* IO space mapping must be initialized before we can do that.
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 68e5233..83879f8 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1206,6 +1206,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
.gpio_irq = IRQ_DA8XX_GPIO0,
.serial_dev = &da8xx_serial_device,
.emac_pdata = &da8xx_emac_pdata,
+ .reset_device = &da8xx_wdt_device,
};
void __init da830_init(void)
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 8aefcff..2b6dd59 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1093,6 +1093,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
.emac_pdata = &da8xx_emac_pdata,
.sram_dma = DA8XX_ARM_RAM_BASE,
.sram_len = SZ_8K,
+ .reset_device = &da8xx_wdt_device,
};
void __init da850_init(void)
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 0a96791..67a6fbc 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -326,7 +326,7 @@ static struct resource da8xx_watchdog_resources[] = {
},
};
-struct platform_device davinci_wdt_device = {
+struct platform_device da8xx_wdt_device = {
.name = "watchdog",
.id = -1,
.num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
@@ -335,7 +335,7 @@ struct platform_device davinci_wdt_device = {
int __init da8xx_register_watchdog(void)
{
- return platform_device_register(&davinci_wdt_device);
+ return platform_device_register(&da8xx_wdt_device);
}
static struct resource da8xx_emac_resources[] = {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index f91e9a1..0c62a68 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -861,6 +861,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
.serial_dev = &dm355_serial_device,
.sram_dma = 0x00010000,
.sram_len = SZ_32K,
+ .reset_device = &davinci_wdt_device,
};
void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index f2b1d93..ed76450 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1068,6 +1068,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
.emac_pdata = &dm365_emac_pdata,
.sram_dma = 0x00010000,
.sram_len = SZ_32K,
+ .reset_device = &davinci_wdt_device,
};
void __init dm365_init_asp(struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 85c88ec..7f36c22 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -753,6 +753,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
.emac_pdata = &dm644x_emac_pdata,
.sram_dma = 0x00008000,
.sram_len = SZ_16K,
+ .reset_device = &davinci_wdt_device,
};
void __init dm644x_init_asp(struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index a8189c9..8dd0afe 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -837,6 +837,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
.emac_pdata = &dm646x_emac_pdata,
.sram_dma = 0x10010000,
.sram_len = SZ_32K,
+ .reset_device = &davinci_wdt_device,
};
void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 8ffef5b..a58bd88 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -70,6 +70,8 @@ struct davinci_soc_info {
struct emac_platform_data *emac_pdata;
dma_addr_t sram_dma;
unsigned sram_len;
+ struct platform_device *reset_device;
+ void (*reset)(struct platform_device *);
};
extern struct davinci_soc_info davinci_soc_info;
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index dbb4ebe..1b31a9a 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -87,6 +87,8 @@ extern struct emac_platform_data da8xx_emac_pdata;
extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
+extern struct platform_device da8xx_wdt_device;
+
extern const short da830_emif25_pins[];
extern const short da830_spi0_pins[];
extern const short da830_spi1_pins[];
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
index 5a7d758..e65629c 100644
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ b/arch/arm/mach-davinci/include/mach/system.h
@@ -11,7 +11,7 @@
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
-extern void davinci_watchdog_reset(void);
+#include <mach/common.h>
static inline void arch_idle(void)
{
@@ -20,7 +20,8 @@ static inline void arch_idle(void)
static inline void arch_reset(char mode, const char *cmd)
{
- davinci_watchdog_reset();
+ if (davinci_soc_info.reset)
+ davinci_soc_info.reset(davinci_soc_info.reset_device);
}
#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index b21f763..e5c598a 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -399,13 +399,16 @@ struct sys_timer davinci_timer = {
/* reset board using watchdog timer */
-void davinci_watchdog_reset(void)
+void davinci_watchdog_reset(struct platform_device *pdev)
{
u32 tgcr, wdtcr;
- struct platform_device *pdev = &davinci_wdt_device;
- void __iomem *base = IO_ADDRESS(pdev->resource[0].start);
+ void __iomem *base;
struct clk *wd_clk;
+ base = ioremap(pdev->resource[0].start, SZ_4K);
+ if (WARN_ON(!base))
+ return;
+
wd_clk = clk_get(&pdev->dev, NULL);
if (WARN_ON(IS_ERR(wd_clk)))
return;
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 30/34] Davinci: serial - remove unnecessary define
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (28 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 29/34] Davinci: watchdog reset separation across socs Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 31/34] Davinci: serial - use ioremap() Kevin Hilman
` (3 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
The uart pdata array is already terminated by a zero flag field.
This patch reuses this terminator and eliminates DAVINCI_MAX_NR_UARTS
definition. This way, future platforms can have different number of uarts
initialized via davinci_serial_init().
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/include/mach/serial.h | 1 -
arch/arm/mach-davinci/serial.c | 2 +-
2 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index a584697..f6c4f34 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -13,7 +13,6 @@
#include <mach/hardware.h>
-#define DAVINCI_MAX_NR_UARTS 3
#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 7ce5ba0..709e1a9 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -77,7 +77,7 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
* Make sure the serial ports are muxed on at this point.
* You have to mux them off in device drivers later on if not needed.
*/
- for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++, p++) {
+ for (i = 0; p->flags; i++, p++) {
if (!(info->enabled_uarts & (1 << i)))
continue;
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 31/34] Davinci: serial - use ioremap()
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (29 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 30/34] Davinci: serial - remove unnecessary define Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 32/34] Davinci: serial - conditional reset via pwremu Kevin Hilman
` (2 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
This patch implements davinci serial cleanups towards having this code
reusable on tnetv107x.
The change reuses the platform data membase field to hold the remapped space.
By disabling the UPF_IOREMAP flag in the platform data, we prevent
the 8250 driver from repeating the ioremap.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/serial.c | 32 +++++++++++++++++++++++++-------
1 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 709e1a9..81af42c 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -35,14 +35,20 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
int offset)
{
offset <<= up->regshift;
- return (unsigned int)__raw_readl(IO_ADDRESS(up->mapbase) + offset);
+
+ WARN_ONCE(!up->membase, "unmapped read: uart[%d]\n", offset);
+
+ return (unsigned int)__raw_readl(up->membase + offset);
}
static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
int value)
{
offset <<= p->regshift;
- __raw_writel(value, IO_ADDRESS(p->mapbase) + offset);
+
+ WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset);
+
+ __raw_writel(value, p->membase + offset);
}
static void __init davinci_serial_reset(struct plat_serial8250_port *p)
@@ -83,14 +89,26 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
sprintf(name, "uart%d", i);
uart_clk = clk_get(dev, name);
- if (IS_ERR(uart_clk))
+ if (IS_ERR(uart_clk)) {
printk(KERN_ERR "%s:%d: failed to get UART%d clock\n",
__func__, __LINE__, i);
- else {
- clk_enable(uart_clk);
- p->uartclk = clk_get_rate(uart_clk);
- davinci_serial_reset(p);
+ continue;
}
+
+ clk_enable(uart_clk);
+ p->uartclk = clk_get_rate(uart_clk);
+
+ if (!p->membase && p->mapbase) {
+ p->membase = ioremap(p->mapbase, SZ_4K);
+
+ if (p->membase)
+ p->flags &= ~UPF_IOREMAP;
+ else
+ pr_err("uart regs ioremap failed\n");
+ }
+
+ if (p->membase)
+ davinci_serial_reset(p);
}
return platform_device_register(soc_info->serial_dev);
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 32/34] Davinci: serial - conditional reset via pwremu
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (30 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 31/34] Davinci: serial - use ioremap() Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 33/34] davinci: edma: use a more intuitive name for edma_info Kevin Hilman
2010-05-06 23:24 ` [PATCH 34/34] davinci: edma: fix coding style issue related to usage of braces Kevin Hilman
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Cyril Chemparathy <cyril@ti.com>
With this patch, AR7 type uart ports are not reset via pwremu registers. This
allows davinci_serial_init() reuse on tnetv107x soc.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/serial.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 81af42c..1875740 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -107,7 +107,7 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
pr_err("uart regs ioremap failed\n");
}
- if (p->membase)
+ if (p->membase && p->type != PORT_AR7)
davinci_serial_reset(p);
}
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 33/34] davinci: edma: use a more intuitive name for edma_info
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (31 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 32/34] Davinci: serial - conditional reset via pwremu Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
2010-05-06 23:24 ` [PATCH 34/34] davinci: edma: fix coding style issue related to usage of braces Kevin Hilman
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Sekhar Nori <nsekhar@ti.com>
'edma_info' structure inside the edma driver represents
a single instance of edma channel controller. Call it
'edma_cc' instead. This also avoids readers confusing
it with an instance of edma_soc_info structre which
carries the platform data for a single channel controller
instance.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/dma.c | 158 +++++++++++++++++++++----------------------
1 files changed, 77 insertions(+), 81 deletions(-)
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 0bf290b..b705089 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -243,7 +243,7 @@ struct edma {
} intr_data[EDMA_MAX_DMACH];
};
-static struct edma *edma_info[EDMA_MAX_CC];
+static struct edma *edma_cc[EDMA_MAX_CC];
static int arch_num_cc;
/* dummy param set used to (re)initialize parameter RAM slots */
@@ -261,7 +261,7 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
/* default to low priority queue */
if (queue_no == EVENTQ_DEFAULT)
- queue_no = edma_info[ctlr]->default_queue;
+ queue_no = edma_cc[ctlr]->default_queue;
queue_no &= 7;
edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
@@ -315,8 +315,8 @@ setup_dma_interrupt(unsigned lch,
(1 << (lch & 0x1f)));
}
- edma_info[ctlr]->intr_data[lch].callback = callback;
- edma_info[ctlr]->intr_data[lch].data = data;
+ edma_cc[ctlr]->intr_data[lch].callback = callback;
+ edma_cc[ctlr]->intr_data[lch].data = data;
if (callback) {
edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
@@ -328,11 +328,10 @@ setup_dma_interrupt(unsigned lch,
static int irq2ctlr(int irq)
{
- if (irq >= edma_info[0]->irq_res_start &&
- irq <= edma_info[0]->irq_res_end)
+ if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
return 0;
- else if (irq >= edma_info[1]->irq_res_start &&
- irq <= edma_info[1]->irq_res_end)
+ else if (irq >= edma_cc[1]->irq_res_start &&
+ irq <= edma_cc[1]->irq_res_end)
return 1;
return -1;
@@ -377,10 +376,10 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
/* Clear the corresponding IPR bits */
edma_shadow0_write_array(ctlr, SH_ICR, j,
(1 << i));
- if (edma_info[ctlr]->intr_data[k].callback) {
- edma_info[ctlr]->intr_data[k].callback(
+ if (edma_cc[ctlr]->intr_data[k].callback) {
+ edma_cc[ctlr]->intr_data[k].callback(
k, DMA_COMPLETE,
- edma_info[ctlr]->intr_data[k].
+ edma_cc[ctlr]->intr_data[k].
data);
}
}
@@ -433,12 +432,12 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
/* Clear any SER */
edma_shadow0_write_array(ctlr, SH_SECR,
j, (1 << i));
- if (edma_info[ctlr]->intr_data[k].
+ if (edma_cc[ctlr]->intr_data[k].
callback) {
- edma_info[ctlr]->intr_data[k].
+ edma_cc[ctlr]->intr_data[k].
callback(k,
DMA_CC_ERROR,
- edma_info[ctlr]->intr_data
+ edma_cc[ctlr]->intr_data
[k].data);
}
}
@@ -514,9 +513,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
int stop_slot = start_slot;
DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
- for (i = start_slot; i < edma_info[ctlr]->num_slots; ++i) {
+ for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
j = EDMA_CHAN_SLOT(i);
- if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) {
+ if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
/* Record our current beginning slot */
if (count == num_slots)
stop_slot = i;
@@ -543,12 +542,12 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
* of contiguous parameter RAM slots but do not find the exact number
* requested as we may reach the total number of parameter RAM slots
*/
- if (i == edma_info[ctlr]->num_slots)
+ if (i == edma_cc[ctlr]->num_slots)
stop_slot = i;
for (j = start_slot; j < stop_slot; j++)
if (test_bit(j, tmp_inuse))
- clear_bit(j, edma_info[ctlr]->edma_inuse);
+ clear_bit(j, edma_cc[ctlr]->edma_inuse);
if (count)
return -EBUSY;
@@ -570,7 +569,7 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
(int)pdev->resource[i].start >= 0) {
ctlr = EDMA_CTLR(pdev->resource[i].start);
clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
- edma_info[ctlr]->edma_unused);
+ edma_cc[ctlr]->edma_unused);
}
}
@@ -644,14 +643,13 @@ int edma_alloc_channel(int channel,
for (i = 0; i < arch_num_cc; i++) {
channel = 0;
for (;;) {
- channel = find_next_bit(edma_info[i]->
- edma_unused,
- edma_info[i]->num_channels,
+ channel = find_next_bit(edma_cc[i]->edma_unused,
+ edma_cc[i]->num_channels,
channel);
- if (channel == edma_info[i]->num_channels)
+ if (channel == edma_cc[i]->num_channels)
break;
if (!test_and_set_bit(channel,
- edma_info[i]->edma_inuse)) {
+ edma_cc[i]->edma_inuse)) {
done = 1;
ctlr = i;
break;
@@ -663,9 +661,9 @@ int edma_alloc_channel(int channel,
}
if (!done)
return -ENOMEM;
- } else if (channel >= edma_info[ctlr]->num_channels) {
+ } else if (channel >= edma_cc[ctlr]->num_channels) {
return -EINVAL;
- } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) {
+ } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
return -EBUSY;
}
@@ -706,7 +704,7 @@ void edma_free_channel(unsigned channel)
ctlr = EDMA_CTLR(channel);
channel = EDMA_CHAN_SLOT(channel);
- if (channel >= edma_info[ctlr]->num_channels)
+ if (channel >= edma_cc[ctlr]->num_channels)
return;
setup_dma_interrupt(channel, NULL, NULL);
@@ -714,7 +712,7 @@ void edma_free_channel(unsigned channel)
memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
&dummy_paramset, PARM_SIZE);
- clear_bit(channel, edma_info[ctlr]->edma_inuse);
+ clear_bit(channel, edma_cc[ctlr]->edma_inuse);
}
EXPORT_SYMBOL(edma_free_channel);
@@ -738,20 +736,19 @@ int edma_alloc_slot(unsigned ctlr, int slot)
slot = EDMA_CHAN_SLOT(slot);
if (slot < 0) {
- slot = edma_info[ctlr]->num_channels;
+ slot = edma_cc[ctlr]->num_channels;
for (;;) {
- slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse,
- edma_info[ctlr]->num_slots, slot);
- if (slot == edma_info[ctlr]->num_slots)
+ slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
+ edma_cc[ctlr]->num_slots, slot);
+ if (slot == edma_cc[ctlr]->num_slots)
return -ENOMEM;
- if (!test_and_set_bit(slot,
- edma_info[ctlr]->edma_inuse))
+ if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
break;
}
- } else if (slot < edma_info[ctlr]->num_channels ||
- slot >= edma_info[ctlr]->num_slots) {
+ } else if (slot < edma_cc[ctlr]->num_channels ||
+ slot >= edma_cc[ctlr]->num_slots) {
return -EINVAL;
- } else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) {
+ } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
return -EBUSY;
}
@@ -777,13 +774,13 @@ void edma_free_slot(unsigned slot)
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
- if (slot < edma_info[ctlr]->num_channels ||
- slot >= edma_info[ctlr]->num_slots)
+ if (slot < edma_cc[ctlr]->num_channels ||
+ slot >= edma_cc[ctlr]->num_slots)
return;
memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
&dummy_paramset, PARM_SIZE);
- clear_bit(slot, edma_info[ctlr]->edma_inuse);
+ clear_bit(slot, edma_cc[ctlr]->edma_inuse);
}
EXPORT_SYMBOL(edma_free_slot);
@@ -821,8 +818,8 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
* of slots
*/
if ((id != EDMA_CONT_PARAMS_ANY) &&
- (slot < edma_info[ctlr]->num_channels ||
- slot >= edma_info[ctlr]->num_slots))
+ (slot < edma_cc[ctlr]->num_channels ||
+ slot >= edma_cc[ctlr]->num_slots))
return -EINVAL;
/*
@@ -831,13 +828,13 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
* channels
*/
if (count < 1 || count >
- (edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels))
+ (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
return -EINVAL;
switch (id) {
case EDMA_CONT_PARAMS_ANY:
return reserve_contiguous_slots(ctlr, id, count,
- edma_info[ctlr]->num_channels);
+ edma_cc[ctlr]->num_channels);
case EDMA_CONT_PARAMS_FIXED_EXACT:
case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
return reserve_contiguous_slots(ctlr, id, count, slot);
@@ -869,8 +866,8 @@ int edma_free_cont_slots(unsigned slot, int count)
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
- if (slot < edma_info[ctlr]->num_channels ||
- slot >= edma_info[ctlr]->num_slots ||
+ if (slot < edma_cc[ctlr]->num_channels ||
+ slot >= edma_cc[ctlr]->num_slots ||
count < 1)
return -EINVAL;
@@ -880,7 +877,7 @@ int edma_free_cont_slots(unsigned slot, int count)
memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
&dummy_paramset, PARM_SIZE);
- clear_bit(slot_to_free, edma_info[ctlr]->edma_inuse);
+ clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
}
return 0;
@@ -910,7 +907,7 @@ void edma_set_src(unsigned slot, dma_addr_t src_port,
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
- if (slot < edma_info[ctlr]->num_slots) {
+ if (slot < edma_cc[ctlr]->num_slots) {
unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
if (mode) {
@@ -948,7 +945,7 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port,
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
- if (slot < edma_info[ctlr]->num_slots) {
+ if (slot < edma_cc[ctlr]->num_slots) {
unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
if (mode) {
@@ -1008,7 +1005,7 @@ void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
- if (slot < edma_info[ctlr]->num_slots) {
+ if (slot < edma_cc[ctlr]->num_slots) {
edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
0xffff0000, src_bidx);
edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
@@ -1034,7 +1031,7 @@ void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
- if (slot < edma_info[ctlr]->num_slots) {
+ if (slot < edma_cc[ctlr]->num_slots) {
edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
0x0000ffff, dest_bidx << 16);
edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
@@ -1081,7 +1078,7 @@ void edma_set_transfer_params(unsigned slot,
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
- if (slot < edma_info[ctlr]->num_slots) {
+ if (slot < edma_cc[ctlr]->num_slots) {
edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
0x0000ffff, bcnt_rld << 16);
if (sync_mode == ASYNC)
@@ -1111,9 +1108,9 @@ void edma_link(unsigned from, unsigned to)
ctlr_to = EDMA_CTLR(to);
to = EDMA_CHAN_SLOT(to);
- if (from >= edma_info[ctlr_from]->num_slots)
+ if (from >= edma_cc[ctlr_from]->num_slots)
return;
- if (to >= edma_info[ctlr_to]->num_slots)
+ if (to >= edma_cc[ctlr_to]->num_slots)
return;
edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
PARM_OFFSET(to));
@@ -1134,7 +1131,7 @@ void edma_unlink(unsigned from)
ctlr = EDMA_CTLR(from);
from = EDMA_CHAN_SLOT(from);
- if (from >= edma_info[ctlr]->num_slots)
+ if (from >= edma_cc[ctlr]->num_slots)
return;
edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
}
@@ -1161,7 +1158,7 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param)
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
- if (slot >= edma_info[ctlr]->num_slots)
+ if (slot >= edma_cc[ctlr]->num_slots)
return;
memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
PARM_SIZE);
@@ -1183,7 +1180,7 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param)
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
- if (slot >= edma_info[ctlr]->num_slots)
+ if (slot >= edma_cc[ctlr]->num_slots)
return;
memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
PARM_SIZE);
@@ -1208,7 +1205,7 @@ void edma_pause(unsigned channel)
ctlr = EDMA_CTLR(channel);
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_info[ctlr]->num_channels) {
+ if (channel < edma_cc[ctlr]->num_channels) {
unsigned int mask = (1 << (channel & 0x1f));
edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
@@ -1229,7 +1226,7 @@ void edma_resume(unsigned channel)
ctlr = EDMA_CTLR(channel);
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_info[ctlr]->num_channels) {
+ if (channel < edma_cc[ctlr]->num_channels) {
unsigned int mask = (1 << (channel & 0x1f));
edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
@@ -1255,12 +1252,12 @@ int edma_start(unsigned channel)
ctlr = EDMA_CTLR(channel);
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_info[ctlr]->num_channels) {
+ if (channel < edma_cc[ctlr]->num_channels) {
int j = channel >> 5;
unsigned int mask = (1 << (channel & 0x1f));
/* EDMA channels without event association */
- if (test_bit(channel, edma_info[ctlr]->edma_unused)) {
+ if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
pr_debug("EDMA: ESR%d %08x\n", j,
edma_shadow0_read_array(ctlr, SH_ESR, j));
edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
@@ -1301,7 +1298,7 @@ void edma_stop(unsigned channel)
ctlr = EDMA_CTLR(channel);
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_info[ctlr]->num_channels) {
+ if (channel < edma_cc[ctlr]->num_channels) {
int j = channel >> 5;
unsigned int mask = (1 << (channel & 0x1f));
@@ -1340,7 +1337,7 @@ void edma_clean_channel(unsigned channel)
ctlr = EDMA_CTLR(channel);
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_info[ctlr]->num_channels) {
+ if (channel < edma_cc[ctlr]->num_channels) {
int j = (channel >> 5);
unsigned int mask = 1 << (channel & 0x1f);
@@ -1368,7 +1365,7 @@ void edma_clear_event(unsigned channel)
ctlr = EDMA_CTLR(channel);
channel = EDMA_CHAN_SLOT(channel);
- if (channel >= edma_info[ctlr]->num_channels)
+ if (channel >= edma_cc[ctlr]->num_channels)
return;
if (channel < 32)
edma_write(ctlr, EDMA_ECR, 1 << channel);
@@ -1423,38 +1420,37 @@ static int __init edma_probe(struct platform_device *pdev)
goto fail1;
}
- edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
- if (!edma_info[j]) {
+ edma_cc[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
+ if (!edma_cc[j]) {
status = -ENOMEM;
goto fail1;
}
- memset(edma_info[j], 0, sizeof(struct edma));
+ memset(edma_cc[j], 0, sizeof(struct edma));
- edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel,
+ edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel,
EDMA_MAX_DMACH);
- edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot,
+ edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot,
EDMA_MAX_PARAMENTRY);
- edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc,
- EDMA_MAX_CC);
+ edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC);
- edma_info[j]->default_queue = info[j].default_queue;
- if (!edma_info[j]->default_queue)
- edma_info[j]->default_queue = EVENTQ_1;
+ edma_cc[j]->default_queue = info[j].default_queue;
+ if (!edma_cc[j]->default_queue)
+ edma_cc[j]->default_queue = EVENTQ_1;
dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
edmacc_regs_base[j]);
- for (i = 0; i < edma_info[j]->num_slots; i++)
+ for (i = 0; i < edma_cc[j]->num_slots; i++)
memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
&dummy_paramset, PARM_SIZE);
/* Mark all channels as unused */
- memset(edma_info[j]->edma_unused, 0xff,
- sizeof(edma_info[j]->edma_unused));
+ memset(edma_cc[j]->edma_unused, 0xff,
+ sizeof(edma_cc[j]->edma_unused));
sprintf(irq_name, "edma%d", j);
irq[j] = platform_get_irq_byname(pdev, irq_name);
- edma_info[j]->irq_res_start = irq[j];
+ edma_cc[j]->irq_res_start = irq[j];
status = request_irq(irq[j], dma_irq_handler, 0, "edma",
&pdev->dev);
if (status < 0) {
@@ -1465,7 +1461,7 @@ static int __init edma_probe(struct platform_device *pdev)
sprintf(irq_name, "edma%d_err", j);
err_irq[j] = platform_get_irq_byname(pdev, irq_name);
- edma_info[j]->irq_res_end = err_irq[j];
+ edma_cc[j]->irq_res_end = err_irq[j];
status = request_irq(err_irq[j], dma_ccerr_handler, 0,
"edma_error", &pdev->dev);
if (status < 0) {
@@ -1478,7 +1474,7 @@ static int __init edma_probe(struct platform_device *pdev)
* specified. This way, long transfers on the low priority queue
* started by the codec engine will not cause audio defects.
*/
- for (i = 0; i < edma_info[j]->num_channels; i++)
+ for (i = 0; i < edma_cc[j]->num_channels; i++)
map_dmach_queue(j, i, EVENTQ_1);
queue_tc_mapping = info[j].queue_tc_mapping;
@@ -1541,7 +1537,7 @@ fail1:
release_mem_region(r[i]->start, len[i]);
if (edmacc_regs_base[i])
iounmap(edmacc_regs_base[i]);
- kfree(edma_info[i]);
+ kfree(edma_cc[i]);
}
return status;
}
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 34/34] davinci: edma: fix coding style issue related to usage of braces
2010-05-06 23:23 [PATCH 00/34] davinci updates for 2.6.35 Kevin Hilman
` (32 preceding siblings ...)
2010-05-06 23:24 ` [PATCH 33/34] davinci: edma: use a more intuitive name for edma_info Kevin Hilman
@ 2010-05-06 23:24 ` Kevin Hilman
33 siblings, 0 replies; 38+ messages in thread
From: Kevin Hilman @ 2010-05-06 23:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Sekhar Nori <nsekhar@ti.com>
In the edma driver, there are couple of instances where braces
are used for a single statement 'if' construct.
There are other instances where 'else' part of the if-else construct
does not use braces even if the 'if' part is a multi-line statement.
This patch fixes both.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-davinci/dma.c | 15 +++++++--------
1 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index b705089..cc5fcda 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -310,10 +310,9 @@ setup_dma_interrupt(unsigned lch,
ctlr = EDMA_CTLR(lch);
lch = EDMA_CHAN_SLOT(lch);
- if (!callback) {
+ if (!callback)
edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
(1 << (lch & 0x1f)));
- }
edma_cc[ctlr]->intr_data[lch].callback = callback;
edma_cc[ctlr]->intr_data[lch].data = data;
@@ -376,12 +375,11 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
/* Clear the corresponding IPR bits */
edma_shadow0_write_array(ctlr, SH_ICR, j,
(1 << i));
- if (edma_cc[ctlr]->intr_data[k].callback) {
+ if (edma_cc[ctlr]->intr_data[k].callback)
edma_cc[ctlr]->intr_data[k].callback(
k, DMA_COMPLETE,
edma_cc[ctlr]->intr_data[k].
data);
- }
}
}
cnt++;
@@ -473,9 +471,8 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
&& (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
&& (edma_read(ctlr, EDMA_QEMR) == 0)
- && (edma_read(ctlr, EDMA_CCERR) == 0)) {
+ && (edma_read(ctlr, EDMA_CCERR) == 0))
break;
- }
cnt++;
if (cnt > 10)
break;
@@ -531,8 +528,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
stop_slot = i;
break;
- } else
+ } else {
count = num_slots;
+ }
}
}
@@ -1402,8 +1400,9 @@ static int __init edma_probe(struct platform_device *pdev)
break;
else
return -ENODEV;
- } else
+ } else {
found = 1;
+ }
len[j] = resource_size(r[j]);
--
1.7.0.2
^ permalink raw reply related [flat|nested] 38+ messages in thread