PIPT cache handling on s5pv210 chip

[linux@arm.linux.org.uk (Russell King - ARM Linux)]

On Fri, May 14, 2010 at 08:34:14PM +0900, Kukjin Kim wrote:
> In case a driver starts the Memory_To_Peripheral DMA operation with the
> memory area allotted by __vmalloc(,,no-cacheable), the driver can face some
> problems caused by cache victims.

That's its own lookout - all the time that there's the kernel mapping
present, the cache can be loaded with data via that mapping - and being
PIPT, that means the data _could_ be hit by accesses via the __vmalloc
mapping.

As I've already explained, __vmalloc() with differing memory types on
ARMv6 and above is unpredictable, period.  The same is true for different
sharability settings for the same physical memory.  No amount of
discussing will change this; it's a fact of the hardware.  If you
create them, your system will have unpredictable behaviour.

With different cache attributes, it's unpredictable to the word of the
architecture spec, and eventually it will become unpredictable according
to the hardware as well.

So the message is: using __vmalloc() with _any_ differing attributes
from the main memory mapping is unpredictable and must not be used on
ARM.