[PATCH v3 0/7] Patches/fixes for 2.6.35

[PATCH v3 0/7] Patches/fixes for 2.6.35

[Catalin Marinas]

Hi,

Just reposting these patches as they contain some bug-fixes and should
get in before 2.6.35 is released.

>From my previous posts, I removed the PL310 lock optimisation patch
(there are some discussions on optimising the range operations for large
memory blocks and these would be faster as background All operations).

If there are no further comments to these patches, I'll send them to the
patch system.

Thanks.


Catalin Marinas (7):
      ARM: Align machine_desc.phys_io to a 1MB section
      ARM: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds
      ARM: The v6_dma_inv_range() function must preserve data on SMP
      ARM: Add a config option for the ARM11MPCore DMA cache maintenance workaround
      ARM: Add support for the MOVW/MOVT relocations in Thumb-2
      ARM: Remove dummy loads from the original relocation address
      ARM: Do not compile the Thumb-2 module relocations on an ARM kernel


 arch/arm/include/asm/elf.h |    2 ++
 arch/arm/kernel/head.S     |    2 ++
 arch/arm/kernel/module.c   |   34 ++++++++++++++++++++++++++++++++++
 arch/arm/mm/Kconfig        |   19 +++++++++++++++++++
 arch/arm/mm/cache-v6.S     |   18 ++++++++++++++----
 arch/arm/mm/dma-mapping.c  |    2 ++
 6 files changed, 73 insertions(+), 4 deletions(-)

-- 
Catalin

[PATCH v3 1/7] ARM: Align machine_desc.phys_io to a 1MB section

[Catalin Marinas]

Platforms like RealView don't pass a section-aligned pointer via the
machine_desc structure. This patch aligns the pointer in the
__create_page_tables function. Reported by Tony Thompson.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/kernel/head.S |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..82ea924 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -302,6 +302,8 @@ __create_page_tables:
 	movhi	r3, #0x0800
 	add	r6, r0, r3
 	ldr	r3, [r8, #MACHINFO_PHYSIO]
+	mov	r3, r3, lsr #20			@ 1MB-aligned address
+	mov	r3, r3, lsl #20
 	orr	r3, r3, r7
 1:	str	r3, [r0], #4
 	add	r3, r3, #1 << 20

[PATCH v3 2/7] ARM: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds

[Catalin Marinas]

This macro is not defined when !CONFIG_MMU.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/mm/dma-mapping.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 13fa536..c4de90f 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -25,6 +25,7 @@
 #include <asm/sizes.h>
 
 /* Sanity check size */
+#ifdef CONFIG_MMU
 #if (CONSISTENT_DMA_SIZE % SZ_2M)
 #error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
 #endif
@@ -32,6 +33,7 @@
 #define CONSISTENT_OFFSET(x)	(((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
 #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
 #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
+#endif
 
 static u64 get_coherent_dma_mask(struct device *dev)
 {

[PATCH v3 3/7] ARM: The v6_dma_inv_range() function must preserve data on SMP

[Catalin Marinas]

A recent patch for DMA cache maintenance on ARM11MPCore added a write
for ownership trick to the v6_dma_inv_range() function. Such operation
destroys data already present in the buffer. However, this function is
used with with dma_sync_single_for_device() which is supposed to
preserve the existing data transfered into the buffer. This patch adds a
combination of read/write for ownership to preserve the original data.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Ronen Shitrit <rshitrit@marvell.com>
---
 arch/arm/mm/cache-v6.S |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index e46ecd8..332b48c 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -212,7 +212,8 @@ v6_dma_inv_range:
 #endif
 1:
 #ifdef CONFIG_SMP
-	str	r0, [r0]			@ write for ownership
+	ldr	r2, [r0]			@ read for ownership
+	str	r2, [r0]			@ write for ownership
 #endif
 #ifdef HARVARD_CACHE
 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D line

[PATCH v3 4/7] ARM: Add a config option for the ARM11MPCore DMA cache maintenance workaround

[Catalin Marinas]

Commit f4d6477f introduced a workaround for the lack of hardware
broadcasting of the cache maintenance operations on ARM11MPCore.
However, the workaround is only valid on CPUs that do not do speculative
loads into the D-cache.

This patch adds a Kconfig option with the corresponding help to make the
above clear. When the DMA_CACHE_RWFO option is disabled, the kernel
behaviour is that prior to the f4d6477f commit. This also allows ARMv6
UP processors with speculative loads to work correctly.

For other processors, a different workaround may be needed.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ronen Shitrit <rshitrit@marvell.com>
---
 arch/arm/mm/Kconfig    |   19 +++++++++++++++++++
 arch/arm/mm/cache-v6.S |   15 ++++++++++++---
 2 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 346ae14..fc1b2fa 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -735,6 +735,25 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
 	  Forget about fast user space cmpxchg support.
 	  It is just not possible.
 
+config DMA_CACHE_RWFO
+	bool "Enable read/write for ownership DMA cache maintenance"
+	depends on CPU_V6 && SMP
+	default y
+	help
+	  The Snoop Control Unit on ARM11MPCore does not detect the
+	  cache maintenance operations and the dma_{map,unmap}_area()
+	  functions may leave stale cache entries on other CPUs. By
+	  enabling this option, Read or Write For Ownership in the ARMv6
+	  DMA cache maintenance functions is performed. These LDR/STR
+	  instructions change the cache line state to shared or modified
+	  so that the cache operation has the desired effect.
+
+	  Note that the workaround is only valid on processors that do
+	  not perform speculative loads into the D-cache. For such
+	  processors, if cache maintenance operations are not broadcast
+	  in hardware, other workarounds are needed (e.g. cache
+	  maintenance broadcasting in software via FIQ).
+
 config OUTER_CACHE
 	bool
 
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 332b48c..86aa689 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -211,7 +211,7 @@ v6_dma_inv_range:
 	mcrne	p15, 0, r1, c7, c15, 1		@ clean & invalidate unified line
 #endif
 1:
-#ifdef CONFIG_SMP
+#ifdef CONFIG_DMA_CACHE_RWFO
 	ldr	r2, [r0]			@ read for ownership
 	str	r2, [r0]			@ write for ownership
 #endif
@@ -235,7 +235,7 @@ v6_dma_inv_range:
 v6_dma_clean_range:
 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
-#ifdef CONFIG_SMP
+#ifdef CONFIG_DMA_CACHE_RWFO
 	ldr	r2, [r0]			@ read for ownership
 #endif
 #ifdef HARVARD_CACHE
@@ -258,7 +258,7 @@ v6_dma_clean_range:
 ENTRY(v6_dma_flush_range)
 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
-#ifdef CONFIG_SMP
+#ifdef CONFIG_DMA_CACHE_RWFO
 	ldr	r2, [r0]			@ read for ownership
 	str	r2, [r0]			@ write for ownership
 #endif
@@ -284,9 +284,13 @@ ENTRY(v6_dma_map_area)
 	add	r1, r1, r0
 	teq	r2, #DMA_FROM_DEVICE
 	beq	v6_dma_inv_range
+#ifndef CONFIG_DMA_CACHE_RWFO
+	b	v6_dma_clean_range
+#else
 	teq	r2, #DMA_TO_DEVICE
 	beq	v6_dma_clean_range
 	b	v6_dma_flush_range
+#endif
 ENDPROC(v6_dma_map_area)
 
 /*
@@ -296,6 +300,11 @@ ENDPROC(v6_dma_map_area)
  *	- dir	- DMA direction
  */
 ENTRY(v6_dma_unmap_area)
+#ifndef CONFIG_DMA_CACHE_RWFO
+	add	r1, r1, r0
+	teq	r2, #DMA_TO_DEVICE
+	bne	v6_dma_inv_range
+#endif
 	mov	pc, lr
 ENDPROC(v6_dma_unmap_area)
 

[PATCH v3 5/7] ARM: Add support for the MOVW/MOVT relocations in Thumb-2

[Catalin Marinas]

The patch adds handling case for the R_ARM_THM_MOVW_ABS_NC and
R_ARM_THM_MOVT_ABS relocations in arch/arm/kernel/module.c. Such
relocations may appear in Thumb-2 compiled kernel modules.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Kyungmin Park <kmpark@infradead.org>
---
 arch/arm/include/asm/elf.h |    2 ++
 arch/arm/kernel/module.c   |   32 ++++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 51662fe..4d0e730 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -59,6 +59,8 @@ typedef struct user_fp elf_fpregset_t;
 
 #define R_ARM_THM_CALL		10
 #define R_ARM_THM_JUMP24	30
+#define R_ARM_THM_MOVW_ABS_NC	47
+#define R_ARM_THM_MOVT_ABS	48
 
 /*
  * These are used to set parameters in the core dumps.
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index c628bdf..ae3c804 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -237,6 +237,38 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 			lower = *(u16 *)(loc + 2);
 			break;
 
+		case R_ARM_THM_MOVW_ABS_NC:
+		case R_ARM_THM_MOVT_ABS:
+			upper = *(u16 *)loc;
+			lower = *(u16 *)(loc + 2);
+
+			/*
+			 * MOVT/MOVW instructions encoding in Thumb-2:
+			 *
+			 * i	= upper[10]
+			 * imm4	= upper[3:0]
+			 * imm3	= lower[14:12]
+			 * imm8	= lower[7:0]
+			 *
+			 * imm16 = imm4:i:imm3:imm8
+			 */
+			offset = ((upper & 0x000f) << 12) |
+				((upper & 0x0400) << 1) |
+				((lower & 0x7000) >> 4) | (lower & 0x00ff);
+			offset = (offset ^ 0x8000) - 0x8000;
+			offset += sym->st_value;
+
+			if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS)
+				offset >>= 16;
+
+			*(u16 *)loc = (u16)((upper & 0xfbf0) |
+					    ((offset & 0xf000) >> 12) |
+					    ((offset & 0x0800) >> 1));
+			*(u16 *)(loc + 2) = (u16)((lower & 0x8f00) |
+						  ((offset & 0x0700) << 4) |
+						  (offset & 0x00ff));
+			break;
+
 		default:
 			printk(KERN_ERR "%s: unknown relocation: %u\n",
 			       module->name, ELF32_R_TYPE(rel->r_info));

[PATCH v3 6/7] ARM: Remove dummy loads from the original relocation address

[Catalin Marinas]

Reading back the upper and lower values in the R_ARM_THM_CALL and
R_ARM_THM_JUMP24 case was introduced by a previous commit but they are
not needed.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/kernel/module.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index ae3c804..aab7fca 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -233,8 +233,6 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 			*(u16 *)(loc + 2) = (u16)((lower & 0xd000) |
 						  (j1 << 13) | (j2 << 11) |
 						  ((offset >> 1) & 0x07ff));
-			upper = *(u16 *)loc;
-			lower = *(u16 *)(loc + 2);
 			break;
 
 		case R_ARM_THM_MOVW_ABS_NC:

[PATCH v3 7/7] ARM: Do not compile the Thumb-2 module relocations on an ARM kernel

[Catalin Marinas]

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/kernel/module.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index aab7fca..6b46058 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -102,7 +102,9 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 		unsigned long loc;
 		Elf32_Sym *sym;
 		s32 offset;
+#ifdef CONFIG_THUMB2_KERNEL
 		u32 upper, lower, sign, j1, j2;
+#endif
 
 		offset = ELF32_R_SYM(rel->r_info);
 		if (offset < 0 || offset > (symsec->sh_size / sizeof(Elf32_Sym))) {
@@ -185,6 +187,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 					(offset & 0x0fff);
 			break;
 
+#ifdef CONFIG_THUMB2_KERNEL
 		case R_ARM_THM_CALL:
 		case R_ARM_THM_JUMP24:
 			upper = *(u16 *)loc;
@@ -266,6 +269,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 						  ((offset & 0x0700) << 4) |
 						  (offset & 0x00ff));
 			break;
+#endif
 
 		default:
 			printk(KERN_ERR "%s: unknown relocation: %u\n",

[PATCH v3 2/7] ARM: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds

[Russell King - ARM Linux]

On Mon, Jun 21, 2010 at 10:13:36AM +0100, Catalin Marinas wrote:
> This macro is not defined when !CONFIG_MMU.

Just move the definitions into the !CONFIG_MMU section.  No need for
any more ifdefs.

[PATCH v3 7/7] ARM: Do not compile the Thumb-2 module relocations on an ARM kernel

[Russell King - ARM Linux]

On Mon, Jun 21, 2010 at 10:14:04AM +0100, Catalin Marinas wrote:
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Commit message?  What is the reasoning behind this change?

It'd be useful for those who don't know anything about T2 to have
some such information about this change.

[PATCH v3 1/7] ARM: Align machine_desc.phys_io to a 1MB section

[Russell King - ARM Linux]

On Mon, Jun 21, 2010 at 10:13:31AM +0100, Catalin Marinas wrote:
> Platforms like RealView don't pass a section-aligned pointer via the
> machine_desc structure. This patch aligns the pointer in the
> __create_page_tables function. Reported by Tony Thompson.

I still say this is the wrong way.  As I've said before, please fix it
at the machine_desc initialization point.  If you want, pass it as the
section frame number itself (address >> 20) rather than the address to
allow for more addressing space.

[PATCH v3 7/7] ARM: Do not compile the Thumb-2 modulerelocations on an ARM kernel

[Catalin Marinas]

On Mon, 2010-06-21 at 10:26 +0100, Russell King - ARM Linux wrote:
> On Mon, Jun 21, 2010 at 10:14:04AM +0100, Catalin Marinas wrote:
> > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> 
> Commit message?  What is the reasoning behind this change?
> 
> It'd be useful for those who don't know anything about T2 to have
> some such information about this change.

It looks like I forgot to write a description. The reason is just to
avoid extra code to be compiled in when you don't really need to handle
such relocations (i.e. ARM-only kernel). Do you think it's not worth?

-- 
Catalin

[PATCH v3 7/7] ARM: Do not compile the Thumb-2 modulerelocations on an ARM kernel

[Russell King - ARM Linux]

On Mon, Jun 21, 2010 at 10:37:12AM +0100, Catalin Marinas wrote:
> On Mon, 2010-06-21 at 10:26 +0100, Russell King - ARM Linux wrote:
> > On Mon, Jun 21, 2010 at 10:14:04AM +0100, Catalin Marinas wrote:
> > > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> > 
> > Commit message?  What is the reasoning behind this change?
> > 
> > It'd be useful for those who don't know anything about T2 to have
> > some such information about this change.
> 
> It looks like I forgot to write a description. The reason is just to
> avoid extra code to be compiled in when you don't really need to handle
> such relocations (i.e. ARM-only kernel). Do you think it's not worth?

I think its worth giving other people the information they need to
understand the change if they review the patch.

[PATCH v3 2/7] ARM: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds

[Catalin Marinas]

On Mon, 2010-06-21 at 10:23 +0100, Russell King - ARM Linux wrote:
> On Mon, Jun 21, 2010 at 10:13:36AM +0100, Catalin Marinas wrote:
> > This macro is not defined when !CONFIG_MMU.
> 
> Just move the definitions into the !CONFIG_MMU section.  No need for
> any more ifdefs.

Done.


ARM: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds

From: Catalin Marinas <catalin.marinas@arm.com>

This macro is not defined when !CONFIG_MMU so this patch moves the
CONSISTENT_* definitions to the CONFIG_MMU section.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/mm/dma-mapping.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 13fa536..9e7742f 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -24,15 +24,6 @@
 #include <asm/tlbflush.h>
 #include <asm/sizes.h>
 
-/* Sanity check size */
-#if (CONSISTENT_DMA_SIZE % SZ_2M)
-#error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
-#endif
-
-#define CONSISTENT_OFFSET(x)	(((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
-#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
-#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
-
 static u64 get_coherent_dma_mask(struct device *dev)
 {
 	u64 mask = ISA_DMA_THRESHOLD;
@@ -123,6 +114,15 @@ static void __dma_free_buffer(struct page *page, size_t size)
 }
 
 #ifdef CONFIG_MMU
+/* Sanity check size */
+#if (CONSISTENT_DMA_SIZE % SZ_2M)
+#error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
+#endif
+
+#define CONSISTENT_OFFSET(x)	(((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
+#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
+#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
+
 /*
  * These are the page tables (2MB each) covering uncached, DMA consistent allocations
  */

-- 
Catalin

[PATCH v3 1/7] ARM: Align machine_desc.phys_io to a 1MB section

[Catalin Marinas]

On Mon, 2010-06-21 at 10:35 +0100, Russell King - ARM Linux wrote:
> On Mon, Jun 21, 2010 at 10:13:31AM +0100, Catalin Marinas wrote:
> > Platforms like RealView don't pass a section-aligned pointer via the
> > machine_desc structure. This patch aligns the pointer in the
> > __create_page_tables function. Reported by Tony Thompson.
> 
> I still say this is the wrong way.  As I've said before, please fix it
> at the machine_desc initialization point.  

This requirement doesn't seem to be well documented and platforms don't
follow it (e.g. RealView and VExpress). Since it's the head.S code
responsible for this temporary mapping, the platform code wouldn't need
to know whether sections or pages or something else are used to map it.
But io_pg_offst already makes the assumption about sections.

> If you want, pass it as the
> section frame number itself (address >> 20) rather than the address to
> allow for more addressing space.

I would rather go for a PFN to allow more addressing space (but doesn't
solve the section alignment).

For now, I'll send a couple of patches to fix RealView and VExpress
boards.

-- 
Catalin

[PATCH v3 1/7] ARM: Align machine_desc.phys_io to a 1MB section

[Russell King - ARM Linux]

On Mon, Jun 21, 2010 at 11:05:49AM +0100, Catalin Marinas wrote:
> On Mon, 2010-06-21 at 10:35 +0100, Russell King - ARM Linux wrote:
> > On Mon, Jun 21, 2010 at 10:13:31AM +0100, Catalin Marinas wrote:
> > > Platforms like RealView don't pass a section-aligned pointer via the
> > > machine_desc structure. This patch aligns the pointer in the
> > > __create_page_tables function. Reported by Tony Thompson.
> > 
> > I still say this is the wrong way.  As I've said before, please fix it
> > at the machine_desc initialization point.  
> 
> This requirement doesn't seem to be well documented and platforms don't
> follow it (e.g. RealView and VExpress). Since it's the head.S code
> responsible for this temporary mapping, the platform code wouldn't need
> to know whether sections or pages or something else are used to map it.
> But io_pg_offst already makes the assumption about sections.

We're never going to map it using sections - using pages implies a
way to allocate 2nd level page tables, and we don't have any memory
allocators which can work this early.

> > If you want, pass it as the
> > section frame number itself (address >> 20) rather than the address to
> > allow for more addressing space.
> 
> I would rather go for a PFN to allow more addressing space (but doesn't
> solve the section alignment).

PFNs don't solve the problem you've brought up - might as well stick
with what we have in that case.