From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/4] ARM: Use lazy cache flushing on ARMv7 SMP systems
Date: Mon, 21 Jun 2010 10:38:56 +0100 [thread overview]
Message-ID: <20100621093856.GF7702@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <20100621092029.23136.39916.stgit@e102109-lin.cambridge.arm.com>
On Mon, Jun 21, 2010 at 10:20:29AM +0100, Catalin Marinas wrote:
> ARMv7 processors like Cortex-A9 broadcast the cache maintenance
> operations in hardware. This patch allows the
> flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode
> similar to the UP case.
No. We know that this trick can't be used on SMP, because update_mmu_cache
is called after the PTE has been established and the page has become
visible to other CPUs in the system.
So this optimization must remain disabled on SMP for correctness.
next prev parent reply other threads:[~2010-06-21 9:38 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-06-21 9:20 [PATCH v3 0/4] Patches for -next Catalin Marinas
2010-06-21 9:20 ` [PATCH v3 1/4] ARM: Remove the domain switching on ARMv6k/v7 CPUs Catalin Marinas
2010-06-21 9:20 ` [PATCH v3 2/4] ARM: Use lazy cache flushing on ARMv7 SMP systems Catalin Marinas
2010-06-21 9:38 ` Russell King - ARM Linux [this message]
2010-06-21 9:42 ` [PATCH v3 2/4] ARM: Use lazy cache flushing on ARMv7 SMPsystems Catalin Marinas
2010-06-21 9:20 ` [PATCH v3 3/4] ARM: Assume new page cache pages have dirty D-cache Catalin Marinas
2010-06-21 9:20 ` [PATCH v3 4/4] ARM: Synchronise the I and D caches via set_pte_at() on SMP systems Catalin Marinas
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