From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: About cachetype on ARMv7
Date: Wed, 7 Jul 2010 08:49:43 +0100 [thread overview]
Message-ID: <20100707074943.GA21884@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <013501cb1d6a$47682ea0$d6388be0$%kim@samsung.com>
On Wed, Jul 07, 2010 at 09:20:57AM +0900, Kukjin Kim wrote:
> > The requirements for N is such the CPU visible conditions which qualify a
> > cache as being VIPT non-aliasing also satisfy PIPT - and a non-aliasing
> > VIPT cache has the same properties as a PIPT cache.
>
> Thanks for your reply :-)
>
> You mean PIPT is the same as VIPT non-aliasing.
No, because that's not the case - they are different at the hardware
level. At the software level, they can be treated the same though.
> Hmm..there is no need to show exactly cachetype in the kernel boot message?
The boot message shows how the kernel drives the cache, not what the
actual cache is - which is far more informative about what the kernel
is doing.
We can find out what the hardware is by looking in specification docs;
we don't need the kernel to tell us that.
next prev parent reply other threads:[~2010-07-07 7:49 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-07-05 11:21 About cachetype on ARMv7 Kukjin Kim
2010-07-05 14:17 ` Russell King - ARM Linux
2010-07-07 0:20 ` Kukjin Kim
2010-07-07 7:49 ` Russell King - ARM Linux [this message]
2010-07-08 0:52 ` Kukjin Kim
2010-07-08 8:08 ` Russell King - ARM Linux
2010-07-08 10:18 ` Kukjin Kim
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