From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 3/3] ARM: Add barriers to the I/O accessors if ARM_DMA_MEM_BUFFERABLE
Date: Fri, 9 Jul 2010 13:16:29 +0100 [thread overview]
Message-ID: <20100709121629.GE22845@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <1278675696.11895.37.camel@e102109-lin.cambridge.arm.com>
On Fri, Jul 09, 2010 at 12:41:36PM +0100, Catalin Marinas wrote:
> This part requires a small change. It looks like the e1000e driver
> doesn't like the do {...} while (0) constructs in the write*() accessors
> (the E1000_WRITE_REG_ARRAY macro). Thanks to Giuseppe for finding this.
Hmm. I think those additional parens in drivers/net/e1000e/hw.h should
be killed off instead. They aren't serving any useful purpose.
In fact, this is potentially dangerous - it causes write[bwl]() not to
be 'void' - in that if you do use write[bwl]() in an expression that
wants its return value, write[bwl]() will generate a read. (While you
might not use the value, you're relying on the compiler being able to
spot that you're not using the value.)
Keeping the do { } while() there prevents write[bwl]() being used as
an expression, and therefore avoids nasty surprises when the compiler
decides to read the register after writing.
next prev parent reply other threads:[~2010-07-09 12:16 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-07-09 11:07 [PATCH v2 0/3] Ordered I/O accessors Catalin Marinas
2010-07-09 11:08 ` [PATCH v2 1/3] ARM: Introduce *_relaxed() " Catalin Marinas
2010-07-09 16:08 ` Arnd Bergmann
2010-07-09 16:53 ` Catalin Marinas
2010-07-09 17:17 ` Arnd Bergmann
2010-07-09 18:24 ` Russell King - ARM Linux
2010-07-09 19:30 ` Arnd Bergmann
2010-07-09 22:31 ` Catalin Marinas
2010-07-12 11:39 ` Arnd Bergmann
2010-07-12 11:50 ` Jamie Lokier
2010-07-12 11:53 ` Catalin Marinas
2010-07-12 12:46 ` Jamie Lokier
2010-07-13 15:21 ` Catalin Marinas
2010-07-12 12:00 ` Catalin Marinas
2010-07-09 11:08 ` [PATCH v2 2/3] ARM: Convert L2x0 to use the IO relaxed operations for cache sync Catalin Marinas
2010-07-09 11:08 ` [PATCH v2 3/3] ARM: Add barriers to the I/O accessors if ARM_DMA_MEM_BUFFERABLE Catalin Marinas
2010-07-09 11:41 ` Catalin Marinas
2010-07-09 12:16 ` Russell King - ARM Linux [this message]
2010-07-09 13:02 ` [PATCH v2 3/3] ARM: Add barriers to the I/O accessors ifARM_DMA_MEM_BUFFERABLE Catalin Marinas
2010-07-09 14:21 ` [PATCH v2 3/3] ARM: Add barriers to the I/O accessorsifARM_DMA_MEM_BUFFERABLE Catalin Marinas
2010-07-09 14:34 ` Russell King - ARM Linux
2010-07-09 15:02 ` [PATCH v2 3/3] ARM: Add barriers to the I/OaccessorsifARM_DMA_MEM_BUFFERABLE Catalin Marinas
2010-07-09 11:29 ` [PATCH v2 0/3] Ordered I/O accessors Russell King - ARM Linux
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