From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: Memory type used for ioremap
Date: Fri, 9 Jul 2010 13:48:50 +0100 [thread overview]
Message-ID: <20100709124850.GH22845@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <2A3DCF3DA181AD40BDE86A3150B27B6B030E181724@dbde02.ent.ti.com>
On Fri, Jul 09, 2010 at 07:46:31AM +0530, Pedanekar, Hemant wrote:
> I have few doubts regarding the memory type configured when we call
> ioremap for mapping a region (e.g., on-chip peripheral MMRs):
What's a MMR?
> Please note that this is regarding Cortx A8.
>
> After examining 2nd level page descriptor, I see that the memory
> type configured for ioremapped region (as per TEX[2:0]=1 and CB=0)
That is correct. TEX=001 C=0 B=0.
> is "Outer and Inner Non-cacheable - Normal".
I think that's where you're wrong. TEX=001 C=0 B=0 is device memory.
On ARMv6 with fixed TEX values, this is described in the architecture
reference manual, and is 'shared device'. On ARMv7 (which Cortex A8 is)
with TEX remapping, we arrange for this bit combination to be 'device'
and the shared-ness of the mapping depends on the S bit.
next prev parent reply other threads:[~2010-07-09 12:48 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-07-09 2:16 Memory type used for ioremap Pedanekar, Hemant
2010-07-09 12:11 ` Catalin Marinas
2010-07-09 14:02 ` Pedanekar, Hemant
2010-07-09 14:14 ` Russell King - ARM Linux
2010-07-09 17:25 ` Pedanekar, Hemant
2010-08-03 17:54 ` Pedanekar, Hemant
2010-08-04 4:46 ` Shilimkar, Santosh
2010-08-04 12:01 ` Pedanekar, Hemant
2010-08-04 12:05 ` Shilimkar, Santosh
2010-08-11 12:55 ` Pedanekar, Hemant
2010-08-11 13:03 ` Shilimkar, Santosh
2010-08-11 14:58 ` Pedanekar, Hemant
2010-08-11 20:38 ` Russell King - ARM Linux
2010-08-12 6:18 ` Shilimkar, Santosh
2010-07-09 12:48 ` Russell King - ARM Linux [this message]
2010-07-09 15:41 ` Pedanekar, Hemant
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