* amba clcd clock/timing check mismatch
@ 2010-08-16 22:54 Kevin Wells
2010-08-16 23:31 ` Russell King - ARM Linux
0 siblings, 1 reply; 5+ messages in thread
From: Kevin Wells @ 2010-08-16 22:54 UTC (permalink / raw)
To: linux-arm-kernel
^ permalink raw reply [flat|nested] 5+ messages in thread
* amba clcd clock/timing check mismatch
2010-08-16 22:54 amba clcd clock/timing check mismatch Kevin Wells
@ 2010-08-16 23:31 ` Russell King - ARM Linux
2010-08-17 17:27 ` Kevin Wells
0 siblings, 1 reply; 5+ messages in thread
From: Russell King - ARM Linux @ 2010-08-16 23:31 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Aug 16, 2010 at 03:54:47PM -0700, Kevin Wells wrote:
> >From the include/linux/amba/clcd.h file, in the clcdfb_check() function...
>
> #define CHECK(e,l,h) (var->e < l || var->e > h)
> if (CHECK(right_margin, (5+1), 256) || /* back porch */
> CHECK(left_margin, (5+1), 256) || /* front porch */
> CHECK(hsync_len, (5+1), 256) ||
> var->xres > 4096 ||
>
> These 4 checks don't match the actual values that can be
> generated by the CLCD controller. The minimum values for left
> and right horizontal porch and HSYNC width can go down to
> 1 clock.
Not quite - these restrictions deal with the restrictions for DMA
timing for STN panels as specified in the CLCD documentation -
clcdfb_check doesn't deal with the differences between STN and
active panels.
So it's not as simple as just reducing these down to allowing 1 clock
- that'd break STN panels.
> The maximum x resolution for the pl11x devices is 1024 pixels.
Yes, you seem to be right here.
^ permalink raw reply [flat|nested] 5+ messages in thread
* amba clcd clock/timing check mismatch
2010-08-16 23:31 ` Russell King - ARM Linux
@ 2010-08-17 17:27 ` Kevin Wells
2010-08-19 0:23 ` Kevin Wells
0 siblings, 1 reply; 5+ messages in thread
From: Kevin Wells @ 2010-08-17 17:27 UTC (permalink / raw)
To: linux-arm-kernel
>> >From the include/linux/amba/clcd.h file, in the clcdfb_check() function...
>>
>> #define CHECK(e,l,h) (var->e < l || var->e > h)
>> ? ? ? if (CHECK(right_margin, (5+1), 256) || ?/* back porch */
>> ? ? ? ? ? CHECK(left_margin, (5+1), 256) || ? /* front porch */
>> ? ? ? ? ? CHECK(hsync_len, (5+1), 256) ||
>> ? ? ? ? ? var->xres > 4096 ||
>>
>> These 4 checks don't match the actual values that can be
>> generated by the CLCD controller. The minimum values for left
>> and right horizontal porch and HSYNC width can go down to
>> 1 clock.
>
> Not quite - these restrictions deal with the restrictions for DMA
> timing for STN panels as specified in the CLCD documentation -
> clcdfb_check doesn't deal with the differences between STN and
> active panels.
>
> So it's not as simple as just reducing these down to allowing 1 clock
> - that'd break STN panels.
>
I didn't realize those limits were for STN. With TFT HS width at 5 clocks,
the check fails on my board, I'll have to create a variant of this function
on the phy3250 platform.
>> The maximum x resolution for the pl11x devices is 1024 pixels.
>
> Yes, you seem to be right here.
>
It's probably not worth a patch unless something changes elsewhere
in clcd.h.
^ permalink raw reply [flat|nested] 5+ messages in thread
* amba clcd clock/timing check mismatch
2010-08-17 17:27 ` Kevin Wells
@ 2010-08-19 0:23 ` Kevin Wells
2010-08-19 9:06 ` Russell King - ARM Linux
0 siblings, 1 reply; 5+ messages in thread
From: Kevin Wells @ 2010-08-19 0:23 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Aug 17, 2010 at 10:27 AM, Kevin Wells <wellsk40@gmail.com> wrote:
>>> >From the include/linux/amba/clcd.h file, in the clcdfb_check() function...
>>>
>>> #define CHECK(e,l,h) (var->e < l || var->e > h)
>>> ? ? ? if (CHECK(right_margin, (5+1), 256) || ?/* back porch */
>>> ? ? ? ? ? CHECK(left_margin, (5+1), 256) || ? /* front porch */
>>> ? ? ? ? ? CHECK(hsync_len, (5+1), 256) ||
>>> ? ? ? ? ? var->xres > 4096 ||
>>>
>>> These 4 checks don't match the actual values that can be
>>> generated by the CLCD controller. The minimum values for left
>>> and right horizontal porch and HSYNC width can go down to
>>> 1 clock.
>>
>> Not quite - these restrictions deal with the restrictions for DMA
>> timing for STN panels as specified in the CLCD documentation -
>> clcdfb_check doesn't deal with the differences between STN and
>> active panels.
>>
>> So it's not as simple as just reducing these down to allowing 1 clock
>> - that'd break STN panels.
>>
>
> I didn't realize those limits were for STN. With TFT HS width at 5 clocks,
> the check fails on my board, I'll have to create a variant of this function
> on the phy3250 platform.
>
if (CHECK(right_margin, (5+1), 256) || /* back porch */
CHECK(left_margin, (5+1), 256) || /* front porch */
CHECK(hsync_len, (5+1), 256) ||
var->xres > 4096 ||
The hsync_len has a minimum value of (3+1) on the pl11x and TFT panels
can go as low as 2 clocks on HSW and HBP.
For TFT panels, HBP and HSW can go as low as 2 clocks.
I think the limits should be fixed in clcd.h for STN and another variant added
for TFT. Will this work?
>>> The maximum x resolution for the pl11x devices is 1024 pixels.
>>
>> Yes, you seem to be right here.
>>
>
> It's probably not worth a patch unless something changes elsewhere
> in clcd.h.
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* amba clcd clock/timing check mismatch
2010-08-19 0:23 ` Kevin Wells
@ 2010-08-19 9:06 ` Russell King - ARM Linux
0 siblings, 0 replies; 5+ messages in thread
From: Russell King - ARM Linux @ 2010-08-19 9:06 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Aug 18, 2010 at 05:23:56PM -0700, Kevin Wells wrote:
> On Tue, Aug 17, 2010 at 10:27 AM, Kevin Wells <wellsk40@gmail.com> wrote:
> >>> >From the include/linux/amba/clcd.h file, in the clcdfb_check() function...
> >>>
> >>> #define CHECK(e,l,h) (var->e < l || var->e > h)
> >>> ? ? ? if (CHECK(right_margin, (5+1), 256) || ?/* back porch */
> >>> ? ? ? ? ? CHECK(left_margin, (5+1), 256) || ? /* front porch */
> >>> ? ? ? ? ? CHECK(hsync_len, (5+1), 256) ||
> >>> ? ? ? ? ? var->xres > 4096 ||
> >>>
> >>> These 4 checks don't match the actual values that can be
> >>> generated by the CLCD controller. The minimum values for left
> >>> and right horizontal porch and HSYNC width can go down to
> >>> 1 clock.
> >>
> >> Not quite - these restrictions deal with the restrictions for DMA
> >> timing for STN panels as specified in the CLCD documentation -
> >> clcdfb_check doesn't deal with the differences between STN and
> >> active panels.
> >>
> >> So it's not as simple as just reducing these down to allowing 1 clock
> >> - that'd break STN panels.
> >>
> >
> > I didn't realize those limits were for STN. With TFT HS width at 5 clocks,
> > the check fails on my board, I'll have to create a variant of this function
> > on the phy3250 platform.
> >
>
> if (CHECK(right_margin, (5+1), 256) || /* back porch */
> CHECK(left_margin, (5+1), 256) || /* front porch */
> CHECK(hsync_len, (5+1), 256) ||
> var->xres > 4096 ||
>
> The hsync_len has a minimum value of (3+1) on the pl11x and TFT panels
> can go as low as 2 clocks on HSW and HBP.
>
> For TFT panels, HBP and HSW can go as low as 2 clocks.
>
> I think the limits should be fixed in clcd.h for STN and another variant added
> for TFT. Will this work?
We do have a flag which indicates what type of panel is connected - we
could use that to select the minimum requirements to test in this
function.
^ permalink raw reply [flat|nested] 5+ messages in thread
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2010-08-16 22:54 amba clcd clock/timing check mismatch Kevin Wells
2010-08-16 23:31 ` Russell King - ARM Linux
2010-08-17 17:27 ` Kevin Wells
2010-08-19 0:23 ` Kevin Wells
2010-08-19 9:06 ` Russell King - ARM Linux
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