* [PATCH 00/14] omap sram, omap4 control module and es2.0 support
@ 2010-09-17 9:47 Santosh Shilimkar
2010-09-17 9:47 ` [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries Santosh Shilimkar
` (2 more replies)
0 siblings, 3 replies; 52+ messages in thread
From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw)
To: linux-arm-kernel
This is consolidated patch series targetted for 2.6.37 merge window.
All of these patches have been already posted/reviewed on the list.
The series contains
- SRAM mapping fixes to avoid speculative aborts
- omap4 control module support
- Fixes for omap4 HS/GP detection
- omap4 es2.0 fixes. MMC and ethernet fixes are queued in respective
trees
Boot tested with omap3_defconfig on
- OMAP4430 SPP
- OMAP4 Panda
- OMAP4 Blaze
- OMAP3430 SDP
The following changes since commit 03a7ab083e4d619136d6f07ce70fa9de0bc436fc:
Linus Torvalds (1):
Merge git://git.kernel.org/.../sfrench/cifs-2.6
are available in the git repository at:
git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base.git omap_for_2.6.37
David Anders (1):
omap4: Panda: Add DEBUG_LL support
Santosh Shilimkar (11):
ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries
omap: Map only available sram memory
davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE
omap4: control: Add ctrl_pad_base to omap_globals
omap4: control: Add accessor api's for pad control module
omap4: control: Add the register definition headers
omap4: control: Fix the control module register accesses
omap4: Update id.c and cpu.h for es2.0
omap4: Fix silicon version detection for early samples
omap4: l2x0: Fix init parameter for es2.0
omap4: Fix bootup crash observed with higher CPU clocks
Vikram Pandita (2):
omap: sram: fix is_sram_locked check
omap4: sram: Fix start address
arch/arm/mach-davinci/dm355.c | 3 +-
arch/arm/mach-davinci/dm365.c | 3 +-
arch/arm/mach-davinci/dm644x.c | 3 +-
arch/arm/mach-davinci/dm646x.c | 3 +-
arch/arm/mach-omap2/control.c | 25 +
arch/arm/mach-omap2/hsmmc.c | 67 +-
arch/arm/mach-omap2/id.c | 40 +-
.../include/mach/ctrl_module_core_44xx.h | 391 ++++++
.../include/mach/ctrl_module_pad_core_44xx.h | 1409 ++++++++++++++++++++
.../include/mach/ctrl_module_pad_wkup_44xx.h | 236 ++++
.../include/mach/ctrl_module_wkup_44xx.h | 92 ++
arch/arm/mach-omap2/omap4-common.c | 10 +-
arch/arm/mm/mmu.c | 17 +-
arch/arm/plat-omap/common.c | 3 +-
arch/arm/plat-omap/dmtimer.c | 2 +-
arch/arm/plat-omap/include/plat/common.h | 1 +
arch/arm/plat-omap/include/plat/control.h | 31 +-
arch/arm/plat-omap/include/plat/cpu.h | 5 +-
arch/arm/plat-omap/include/plat/uncompress.h | 1 +
arch/arm/plat-omap/sram.c | 38 +-
20 files changed, 2271 insertions(+), 109 deletions(-)
create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
^ permalink raw reply [flat|nested] 52+ messages in thread* [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries 2010-09-17 9:47 [PATCH 00/14] omap sram, omap4 control module and es2.0 support Santosh Shilimkar @ 2010-09-17 9:47 ` Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 02/14] omap: Map only available sram memory Santosh Shilimkar ` (2 more replies) 2010-09-17 15:06 ` [PATCH 00/14] omap sram, omap4 control module and es2.0 support Bryan Wu 2010-09-17 17:50 ` Paul Walmsley 2 siblings, 3 replies; 52+ messages in thread From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw) To: linux-arm-kernel This patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED types so that at boot-up, we can map memories outside system memory at page level granularity Previously the mapping was limiting to section level, which creates unnecessary addiotional mapping for which physical memory may not present. On the newer ARM with speculation, this is dangerous and can result in untraceable aborts. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Russell King <linux@arm.linux.org.uk> --- arch/arm/mm/mmu.c | 17 +++++++++++++++-- 1 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 6e1c4f6..3e986a6 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -246,6 +246,9 @@ static struct mem_type mem_types[] = { .domain = DOMAIN_USER, }, [MT_MEMORY] = { + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | + L_PTE_USER | L_PTE_EXEC, + .prot_l1 = PMD_TYPE_TABLE, .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, .domain = DOMAIN_KERNEL, }, @@ -254,6 +257,9 @@ static struct mem_type mem_types[] = { .domain = DOMAIN_KERNEL, }, [MT_MEMORY_NONCACHED] = { + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | + L_PTE_USER | L_PTE_EXEC | L_PTE_MT_BUFFERABLE, + .prot_l1 = PMD_TYPE_TABLE, .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, .domain = DOMAIN_KERNEL, }, @@ -411,9 +417,12 @@ static void __init build_mem_type_table(void) * Enable CPU-specific coherency if supported. * (Only available on XSC3 at the moment.) */ - if (arch_is_coherent() && cpu_is_xsc3()) + if (arch_is_coherent() && cpu_is_xsc3()) { mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; - + mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; + mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; + mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; + } /* * ARMv6 and above have extended page tables. */ @@ -438,7 +447,9 @@ static void __init build_mem_type_table(void) mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; + mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; + mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; #endif } @@ -475,6 +486,8 @@ static void __init build_mem_type_table(void) mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; + mem_types[MT_MEMORY].prot_pte |= kern_pgprot; + mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; mem_types[MT_ROM].prot_sect |= cp->pmd; switch (cp->pmd) { -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 02/14] omap: Map only available sram memory 2010-09-17 9:47 ` [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries Santosh Shilimkar @ 2010-09-17 9:47 ` Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 03/14] davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE Santosh Shilimkar ` (2 more replies) 2010-09-17 16:41 ` [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries Tony Lindgren 2010-09-29 14:51 ` Catalin Marinas 2 siblings, 3 replies; 52+ messages in thread From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw) To: linux-arm-kernel Currently we map 1 MB section while setting up SRAM on OMAPs. The actual physcal OCM RAM available on OMAP SOCs is in order of KBs. This patch maps only available sram and removes some non necessary cpu_is_xxx checks. On the newer ARMs with speculation, this is dangerous and can result in untraceable aborts. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> --- arch/arm/plat-omap/sram.c | 25 +++++-------------------- 1 files changed, 5 insertions(+), 20 deletions(-) diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 226b2e8..10b3b4c 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -220,20 +220,7 @@ void __init omap_map_sram(void) if (omap_sram_size == 0) return; - if (cpu_is_omap24xx()) { - omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA; - - base = OMAP2_SRAM_PA; - base = ROUND_DOWN(base, PAGE_SIZE); - omap_sram_io_desc[0].pfn = __phys_to_pfn(base); - } - if (cpu_is_omap34xx()) { - omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA; - base = OMAP3_SRAM_PA; - base = ROUND_DOWN(base, PAGE_SIZE); - omap_sram_io_desc[0].pfn = __phys_to_pfn(base); - /* * SRAM must be marked as non-cached on OMAP3 since the * CORE DPLL M2 divider change code (in SRAM) runs with the @@ -244,13 +231,11 @@ void __init omap_map_sram(void) omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED; } - if (cpu_is_omap44xx()) { - omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA; - base = OMAP4_SRAM_PA; - base = ROUND_DOWN(base, PAGE_SIZE); - omap_sram_io_desc[0].pfn = __phys_to_pfn(base); - } - omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */ + omap_sram_io_desc[0].virtual = omap_sram_base; + base = omap_sram_start; + base = ROUND_DOWN(base, PAGE_SIZE); + omap_sram_io_desc[0].pfn = __phys_to_pfn(base); + omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE); iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n", -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 03/14] davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE 2010-09-17 9:47 ` [PATCH 02/14] omap: Map only available sram memory Santosh Shilimkar @ 2010-09-17 9:47 ` Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 04/14] omap4: control: Add ctrl_pad_base to omap_globals Santosh Shilimkar 2010-09-17 10:16 ` [PATCH 03/14] davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE Russell King - ARM Linux 2010-09-17 10:15 ` [PATCH 02/14] omap: Map only available sram memory Russell King - ARM Linux 2010-10-01 20:15 ` Grazvydas Ignotas 2 siblings, 2 replies; 52+ messages in thread From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw) To: linux-arm-kernel On Davinci SRAM is mapped as MT_DEVICE becasue of the section mapping pre-requisite instead of intended MT_MEMORY_NONCACHED Since the section mapping limitation gets fixed with first patch in this series, the MT_MEMORY_NONCACHED can be used now. Have not tested this, so somebody with Davinci hardware can try this out Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> --- arch/arm/mach-davinci/dm355.c | 3 +-- arch/arm/mach-davinci/dm365.c | 3 +-- arch/arm/mach-davinci/dm644x.c | 3 +-- arch/arm/mach-davinci/dm646x.c | 3 +-- 4 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 3d996b6..9be261b 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -769,8 +769,7 @@ static struct map_desc dm355_io_desc[] = { .virtual = SRAM_VIRT, .pfn = __phys_to_pfn(0x00010000), .length = SZ_32K, - /* MT_MEMORY_NONCACHED requires supersection alignment */ - .type = MT_DEVICE, + .type = MT_MEMORY_NONCACHED, }, }; diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 6b6f4c6..7781e35 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -969,8 +969,7 @@ static struct map_desc dm365_io_desc[] = { .virtual = SRAM_VIRT, .pfn = __phys_to_pfn(0x00010000), .length = SZ_32K, - /* MT_MEMORY_NONCACHED requires supersection alignment */ - .type = MT_DEVICE, + .type = MT_MEMORY_NONCACHED, }, }; diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 40fec31..5e5b0a7 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -653,8 +653,7 @@ static struct map_desc dm644x_io_desc[] = { .virtual = SRAM_VIRT, .pfn = __phys_to_pfn(0x00008000), .length = SZ_16K, - /* MT_MEMORY_NONCACHED requires supersection alignment */ - .type = MT_DEVICE, + .type = MT_MEMORY_NONCACHED, }, }; diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index e4a3df1..26e8a9c 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -737,8 +737,7 @@ static struct map_desc dm646x_io_desc[] = { .virtual = SRAM_VIRT, .pfn = __phys_to_pfn(0x00010000), .length = SZ_32K, - /* MT_MEMORY_NONCACHED requires supersection alignment */ - .type = MT_DEVICE, + .type = MT_MEMORY_NONCACHED, }, }; -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 04/14] omap4: control: Add ctrl_pad_base to omap_globals 2010-09-17 9:47 ` [PATCH 03/14] davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE Santosh Shilimkar @ 2010-09-17 9:47 ` Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 05/14] omap4: control: Add accessor api's for pad control module Santosh Shilimkar 2010-09-17 10:16 ` [PATCH 03/14] davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE Russell King - ARM Linux 1 sibling, 1 reply; 52+ messages in thread From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw) To: linux-arm-kernel On omap4 control module is divided in four IP blocks. - CTRL_MODULE_CORE 0x4a002000 - CTRL_MODULE_PAD_CORE 0x4a100000 - CTRL_MODULE_WKUP 0x4a30c000 - CTRL_MODULE_PAD_WKUP 0x4a31e000 Addressing all the modules with single base address is not possible considering 16 bit offsets. The mux code manages the pad core and pad wakeup related base address inside the mux framework. For other usage only control core and control pad bases are necessary. So this patch maps only needed pad control base address which is used by device drivers and infrastructure code The main control core base is still kept same in this patch to keep git-bisect working. This will be fixed in the relevant patch in this series. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> --- arch/arm/mach-omap2/control.c | 7 +++++++ arch/arm/plat-omap/common.c | 3 ++- arch/arm/plat-omap/include/plat/common.h | 1 + 3 files changed, 10 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index a8d20ee..99c0eb6 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -25,6 +25,7 @@ #include "sdrc.h" static void __iomem *omap2_ctrl_base; +static void __iomem *omap4_ctrl_pad_base; #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) struct omap3_scratchpad { @@ -145,6 +146,12 @@ void __init omap2_set_globals_control(struct omap_globals *omap2_globals) omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K); WARN_ON(!omap2_ctrl_base); } + + /* Static mapping, never released */ + if (omap2_globals->ctrl_pad) { + omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K); + WARN_ON(!omap4_ctrl_pad_base); + } } void __iomem *omap_ctrl_base_get(void) diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 3008e71..480718b 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -336,7 +336,8 @@ void __init omap3_map_io(void) static struct omap_globals omap4_globals = { .class = OMAP443X_CLASS, .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), - .ctrl = OMAP443X_CTRL_BASE, + .ctrl = OMAP443X_CTRL_BASE, /* FIXME: Move this to control core */ + .ctrl_pad = OMAP443X_CTRL_BASE, .prm = OMAP4430_PRM_BASE, .cm = OMAP4430_CM_BASE, .cm2 = OMAP4430_CM2_BASE, diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 9776b41..7cd0180 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -47,6 +47,7 @@ struct omap_globals { unsigned long sdrc; /* SDRAM Controller */ unsigned long sms; /* SDRAM Memory Scheduler */ unsigned long ctrl; /* System Control Module */ + unsigned long ctrl_pad; /* PAD Control Module */ unsigned long prm; /* Power and Reset Management */ unsigned long cm; /* Clock Management */ unsigned long cm2; -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 05/14] omap4: control: Add accessor api's for pad control module 2010-09-17 9:47 ` [PATCH 04/14] omap4: control: Add ctrl_pad_base to omap_globals Santosh Shilimkar @ 2010-09-17 9:47 ` Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 06/14] omap4: control: Add the register definition headers Santosh Shilimkar 2010-09-17 10:17 ` [PATCH 05/14] omap4: control: Add accessor api's for pad control module Menon, Nishanth 0 siblings, 2 replies; 52+ messages in thread From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw) To: linux-arm-kernel On OMAP4 control pad are not addressable from control core base. So the common omap_ctrl_read/write APIs breaks Hence export separate APIs to manage the omap4 pad control registers. This APIs will work only for OMAP4 Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> --- arch/arm/mach-omap2/control.c | 18 ++++++++++++++++++ arch/arm/plat-omap/include/plat/control.h | 4 ++++ 2 files changed, 22 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 99c0eb6..4ace2d1 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -138,6 +138,7 @@ static struct omap3_control_regs control_context; #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) +#define OMAP_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) void __init omap2_set_globals_control(struct omap_globals *omap2_globals) { @@ -189,6 +190,23 @@ void omap_ctrl_writel(u32 val, u16 offset) __raw_writel(val, OMAP_CTRL_REGADDR(offset)); } +/* + * On OMAP4 control pad are not addressable from control + * core base. So the common omap_ctrl_read/write APIs breaks + * Hence export separate APIs to manage the omap4 pad control + * registers. This APIs will work only for OMAP4 + */ + +u32 omap4_ctrl_pad_readl(u16 offset) +{ + return __raw_readl(OMAP_CTRL_PAD_REGADDR(offset)); +} + +void omap4_ctrl_pad_writel(u32 val, u16 offset) +{ + __raw_writel(val, OMAP_CTRL_PAD_REGADDR(offset)); +} + #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) /* * Clears the scratchpad contents in case of cold boot- diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h index 131bf40..2916b7e 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/plat-omap/include/plat/control.h @@ -354,9 +354,11 @@ extern void __iomem *omap_ctrl_base_get(void); extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); extern u32 omap_ctrl_readl(u16 offset); +extern u32 omap4_ctrl_pad_readl(u16 offset); extern void omap_ctrl_writeb(u8 val, u16 offset); extern void omap_ctrl_writew(u16 val, u16 offset); extern void omap_ctrl_writel(u32 val, u16 offset); +extern void omap4_ctrl_pad_writel(u32 val, u16 offset); extern void omap3_save_scratchpad_contents(void); extern void omap3_clear_scratchpad_contents(void); @@ -371,9 +373,11 @@ extern void omap3_control_restore_context(void); #define omap_ctrl_readb(x) 0 #define omap_ctrl_readw(x) 0 #define omap_ctrl_readl(x) 0 +#define omap4_ctrl_pad_readl(x) 0 #define omap_ctrl_writeb(x, y) WARN_ON(1) #define omap_ctrl_writew(x, y) WARN_ON(1) #define omap_ctrl_writel(x, y) WARN_ON(1) +#define omap4_ctrl_pad_writel(x, y) WARN_ON(1) #endif #endif /* __ASSEMBLY__ */ -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 06/14] omap4: control: Add the register definition headers 2010-09-17 9:47 ` [PATCH 05/14] omap4: control: Add accessor api's for pad control module Santosh Shilimkar @ 2010-09-17 9:47 ` Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 07/14] omap4: control: Fix the control module register accesses Santosh Shilimkar 2010-09-17 10:17 ` [PATCH 05/14] omap4: control: Add accessor api's for pad control module Menon, Nishanth 1 sibling, 1 reply; 52+ messages in thread From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw) To: linux-arm-kernel On OMAP4, control module is divided into 4 separate IPs - OMAP44XX_CTRL_MODULE_CORE - OMAP44XX_CTRL_MODULE_PAD_CORE - OMAP44XX_CTRL_MODULE_WKUP - OMAP44XX_CTRL_MODULE_PAD_WKUP This patch adds all the omap4 control module register data and includes them in the common control.h The register data is autogenerated from the codebase thanks to Benoit Cousson efforts Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> --- .../include/mach/ctrl_module_core_44xx.h | 391 ++++++ .../include/mach/ctrl_module_pad_core_44xx.h | 1409 ++++++++++++++++++++ .../include/mach/ctrl_module_pad_wkup_44xx.h | 236 ++++ .../include/mach/ctrl_module_wkup_44xx.h | 92 ++ arch/arm/plat-omap/include/plat/control.h | 4 + 5 files changed, 2132 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h new file mode 100644 index 0000000..2f7ac70 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h @@ -0,0 +1,391 @@ +/* + * OMAP44xx CTRL_MODULE_CORE registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson at ti.com) + * Santosh Shilimkar (santosh.shilimkar at ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap at vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H + + +/* Base address */ +#define OMAP4_CTRL_MODULE_CORE 0x4a002000 + +/* Registers offset */ +#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000 +#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004 +#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200 +#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 +#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 +#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 +#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 +#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 +#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 +#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324 +#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328 +#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c +#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330 +#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334 +#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c +#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340 +#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350 +#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400 +#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408 +#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c +#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430 +#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434 +#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438 +#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440 +#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444 +#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448 +#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c +#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450 +#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc + +/* Registers shifts and masks */ + +/* IP_REVISION */ +#define OMAP4_IP_REV_SCHEME_SHIFT 30 +#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) +#define OMAP4_IP_REV_FUNC_SHIFT 16 +#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) +#define OMAP4_IP_REV_RTL_SHIFT 11 +#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) +#define OMAP4_IP_REV_MAJOR_SHIFT 8 +#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) +#define OMAP4_IP_REV_CUSTOM_SHIFT 6 +#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) +#define OMAP4_IP_REV_MINOR_SHIFT 0 +#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) + +/* IP_HWINFO */ +#define OMAP4_IP_HWINFO_SHIFT 0 +#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) + +/* IP_SYSCONFIG */ +#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 +#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) + +/* STD_FUSE_DIE_ID_0 */ +#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0 +#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0) + +/* ID_CODE */ +#define OMAP4_STD_FUSE_IDCODE_SHIFT 0 +#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0) + +/* STD_FUSE_DIE_ID_1 */ +#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0 +#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0) + +/* STD_FUSE_DIE_ID_2 */ +#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0 +#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0) + +/* STD_FUSE_DIE_ID_3 */ +#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0 +#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0) + +/* STD_FUSE_PROD_ID_0 */ +#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0 +#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0) + +/* STD_FUSE_PROD_ID_1 */ +#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0 +#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0) + +/* STD_FUSE_USB_CONF */ +#define OMAP4_USB_PROD_ID_SHIFT 16 +#define OMAP4_USB_PROD_ID_MASK (0xffff << 16) +#define OMAP4_USB_VENDOR_ID_SHIFT 0 +#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0) + +/* STD_FUSE_OPP_VDD_WKUP */ +#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0 +#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0) + +/* STD_FUSE_OPP_BGAP */ +#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0 +#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0) + +/* STD_FUSE_OPP_DPLL_0 */ +#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0 +#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0) + +/* STD_FUSE_OPP_DPLL_1 */ +#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0 +#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0) + +/* STATUS */ +#define OMAP4_ATTILA_CONF_SHIFT 11 +#define OMAP4_ATTILA_CONF_MASK (0x3 << 11) +#define OMAP4_DEVICE_TYPE_SHIFT 8 +#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8) +#define OMAP4_SYS_BOOT_SHIFT 0 +#define OMAP4_SYS_BOOT_MASK (0xff << 0) + +/* DEV_CONF */ +#define OMAP4_DEV_CONF_SHIFT 1 +#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1) +#define OMAP4_USBPHY_PD_SHIFT 0 +#define OMAP4_USBPHY_PD_MASK (1 << 0) + +/* LDOVBB_IVA_VOLTAGE_CTRL */ +#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21 +#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16 +#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5 +#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0 +#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0) + +/* LDOVBB_MPU_VOLTAGE_CTRL */ +#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21 +#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16 +#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5 +#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0 +#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0) + +/* LDOSRAM_IVA_VOLTAGE_CTRL */ +#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21 +#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16 +#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5 +#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0 +#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0) + +/* LDOSRAM_MPU_VOLTAGE_CTRL */ +#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21 +#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16 +#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5 +#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0 +#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0) + +/* LDOSRAM_CORE_VOLTAGE_CTRL */ +#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21 +#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16 +#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5 +#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0 +#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0) + +/* TEMP_SENSOR */ +#define OMAP4_BGAP_TEMPSOFF_SHIFT 12 +#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12) +#define OMAP4_BGAP_TSHUT_SHIFT 11 +#define OMAP4_BGAP_TSHUT_MASK (1 << 11) +#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10 +#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10) +#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9 +#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9) +#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8 +#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8) +#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0 +#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0) + +/* DPLL_NWELL_TRIM_0 */ +#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29 +#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) +#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24 +#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24) +#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23 +#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) +#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18 +#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18) +#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17 +#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) +#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12 +#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12) +#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11 +#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) +#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6 +#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6) +#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5 +#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) +#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0 +#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0) + +/* DPLL_NWELL_TRIM_1 */ +#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29 +#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) +#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24 +#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24) +#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23 +#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) +#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18 +#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18) +#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17 +#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) +#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12 +#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12) +#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11 +#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) +#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6 +#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6) +#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5 +#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) +#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0 +#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0) + +/* USBOTGHS_CONTROL */ +#define OMAP4_DISCHRGVBUS_SHIFT 8 +#define OMAP4_DISCHRGVBUS_MASK (1 << 8) +#define OMAP4_CHRGVBUS_SHIFT 7 +#define OMAP4_CHRGVBUS_MASK (1 << 7) +#define OMAP4_DRVVBUS_SHIFT 6 +#define OMAP4_DRVVBUS_MASK (1 << 6) +#define OMAP4_IDPULLUP_SHIFT 5 +#define OMAP4_IDPULLUP_MASK (1 << 5) +#define OMAP4_IDDIG_SHIFT 4 +#define OMAP4_IDDIG_MASK (1 << 4) +#define OMAP4_SESSEND_SHIFT 3 +#define OMAP4_SESSEND_MASK (1 << 3) +#define OMAP4_VBUSVALID_SHIFT 2 +#define OMAP4_VBUSVALID_MASK (1 << 2) +#define OMAP4_BVALID_SHIFT 1 +#define OMAP4_BVALID_MASK (1 << 1) +#define OMAP4_AVALID_SHIFT 0 +#define OMAP4_AVALID_MASK (1 << 0) + +/* DSS_CONTROL */ +#define OMAP4_DSS_MUX6_SELECT_SHIFT 0 +#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0) + +/* HWOBS_CONTROL */ +#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3 +#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3) +#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2 +#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2) +#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1 +#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1) +#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0 +#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0) + +/* DEBOBS_FINAL_MUX_SEL */ +#define OMAP4_SELECT_SHIFT 0 +#define OMAP4_SELECT_MASK (0xffffffff << 0) + +/* DEBOBS_MMR_MPU */ +#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0 +#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0) + +/* CONF_SDMA_REQ_SEL0 */ +#define OMAP4_MULT_SHIFT 0 +#define OMAP4_MULT_MASK (0x7f << 0) + +/* CONF_CLK_SEL0 */ +#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0 +#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0) + +/* CONF_CLK_SEL1 */ +#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0 +#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0) + +/* CONF_CLK_SEL2 */ +#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0 +#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0) + +/* CONF_DPLL_FREQLOCK_SEL */ +#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0 +#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0) + +/* CONF_DPLL_TINITZ_SEL */ +#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0 +#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0) + +/* CONF_DPLL_PHASELOCK_SEL */ +#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0 +#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0) + +/* CONF_DEBUG_SEL_TST_0 */ +#define OMAP4_MODE_SHIFT 0 +#define OMAP4_MODE_MASK (0xf << 0) + +#endif diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h new file mode 100644 index 0000000..c88420d --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h @@ -0,0 +1,1409 @@ +/* + * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson at ti.com) + * Santosh Shilimkar (santosh.shilimkar at ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap at vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H + + +/* Base address */ +#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000 + +/* Registers offset */ +#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000 +#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004 +#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c +#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660 +#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664 +#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c + +/* Registers shifts and masks */ + +/* IP_REVISION */ +#define OMAP4_IP_REV_SCHEME_SHIFT 30 +#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) +#define OMAP4_IP_REV_FUNC_SHIFT 16 +#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) +#define OMAP4_IP_REV_RTL_SHIFT 11 +#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) +#define OMAP4_IP_REV_MAJOR_SHIFT 8 +#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) +#define OMAP4_IP_REV_CUSTOM_SHIFT 6 +#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) +#define OMAP4_IP_REV_MINOR_SHIFT 0 +#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) + +/* IP_HWINFO */ +#define OMAP4_IP_HWINFO_SHIFT 0 +#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) + +/* IP_SYSCONFIG */ +#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 +#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) + +/* PADCONF_WAKEUPEVENT_0 */ +#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_1 */ +#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_2 */ +#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_3 */ +#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_4 */ +#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_5 */ +#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_6 */ +#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* CONTROL_PADCONF_GLOBAL */ +#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31 +#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31) + +/* CONTROL_PADCONF_MODE */ +#define OMAP4_VDDS_DV_BANK0_SHIFT 31 +#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31) +#define OMAP4_VDDS_DV_BANK1_SHIFT 30 +#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30) +#define OMAP4_VDDS_DV_BANK3_SHIFT 29 +#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29) +#define OMAP4_VDDS_DV_BANK4_SHIFT 28 +#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28) +#define OMAP4_VDDS_DV_BANK5_SHIFT 27 +#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27) +#define OMAP4_VDDS_DV_BANK6_SHIFT 26 +#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26) +#define OMAP4_VDDS_DV_C2C_SHIFT 25 +#define OMAP4_VDDS_DV_C2C_MASK (1 << 25) +#define OMAP4_VDDS_DV_CAM_SHIFT 24 +#define OMAP4_VDDS_DV_CAM_MASK (1 << 24) +#define OMAP4_VDDS_DV_GPMC_SHIFT 23 +#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23) +#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22 +#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22) + +/* CONTROL_SMART1IO_PADCONF_0 */ +#define OMAP4_ABE_DR0_SC_SHIFT 30 +#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30) +#define OMAP4_CAM_DR0_SC_SHIFT 28 +#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28) +#define OMAP4_FREF_DR2_SC_SHIFT 26 +#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26) +#define OMAP4_FREF_DR3_SC_SHIFT 24 +#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24) +#define OMAP4_GPIO_DR8_SC_SHIFT 22 +#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22) +#define OMAP4_GPIO_DR9_SC_SHIFT 20 +#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20) +#define OMAP4_GPMC_DR2_SC_SHIFT 18 +#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18) +#define OMAP4_GPMC_DR3_SC_SHIFT 16 +#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16) +#define OMAP4_GPMC_DR6_SC_SHIFT 14 +#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14) +#define OMAP4_HDMI_DR0_SC_SHIFT 12 +#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12) +#define OMAP4_MCSPI1_DR0_SC_SHIFT 10 +#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10) +#define OMAP4_UART1_DR0_SC_SHIFT 8 +#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8) +#define OMAP4_UART3_DR0_SC_SHIFT 6 +#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6) +#define OMAP4_UART3_DR1_SC_SHIFT 4 +#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4) +#define OMAP4_UNIPRO_DR0_SC_SHIFT 2 +#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2) +#define OMAP4_UNIPRO_DR1_SC_SHIFT 0 +#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0) + +/* CONTROL_SMART1IO_PADCONF_1 */ +#define OMAP4_ABE_DR0_LB_SHIFT 30 +#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30) +#define OMAP4_CAM_DR0_LB_SHIFT 28 +#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28) +#define OMAP4_FREF_DR2_LB_SHIFT 26 +#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26) +#define OMAP4_FREF_DR3_LB_SHIFT 24 +#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24) +#define OMAP4_GPIO_DR8_LB_SHIFT 22 +#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22) +#define OMAP4_GPIO_DR9_LB_SHIFT 20 +#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20) +#define OMAP4_GPMC_DR2_LB_SHIFT 18 +#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18) +#define OMAP4_GPMC_DR3_LB_SHIFT 16 +#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16) +#define OMAP4_GPMC_DR6_LB_SHIFT 14 +#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14) +#define OMAP4_HDMI_DR0_LB_SHIFT 12 +#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12) +#define OMAP4_MCSPI1_DR0_LB_SHIFT 10 +#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10) +#define OMAP4_UART1_DR0_LB_SHIFT 8 +#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8) +#define OMAP4_UART3_DR0_LB_SHIFT 6 +#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6) +#define OMAP4_UART3_DR1_LB_SHIFT 4 +#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4) +#define OMAP4_UNIPRO_DR0_LB_SHIFT 2 +#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2) +#define OMAP4_UNIPRO_DR1_LB_SHIFT 0 +#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0) + +/* CONTROL_SMART2IO_PADCONF_0 */ +#define OMAP4_C2C_DR0_LB_SHIFT 31 +#define OMAP4_C2C_DR0_LB_MASK (1 << 31) +#define OMAP4_DPM_DR1_LB_SHIFT 30 +#define OMAP4_DPM_DR1_LB_MASK (1 << 30) +#define OMAP4_DPM_DR2_LB_SHIFT 29 +#define OMAP4_DPM_DR2_LB_MASK (1 << 29) +#define OMAP4_DPM_DR3_LB_SHIFT 28 +#define OMAP4_DPM_DR3_LB_MASK (1 << 28) +#define OMAP4_GPIO_DR0_LB_SHIFT 27 +#define OMAP4_GPIO_DR0_LB_MASK (1 << 27) +#define OMAP4_GPIO_DR1_LB_SHIFT 26 +#define OMAP4_GPIO_DR1_LB_MASK (1 << 26) +#define OMAP4_GPIO_DR10_LB_SHIFT 25 +#define OMAP4_GPIO_DR10_LB_MASK (1 << 25) +#define OMAP4_GPIO_DR2_LB_SHIFT 24 +#define OMAP4_GPIO_DR2_LB_MASK (1 << 24) +#define OMAP4_GPMC_DR0_LB_SHIFT 23 +#define OMAP4_GPMC_DR0_LB_MASK (1 << 23) +#define OMAP4_GPMC_DR1_LB_SHIFT 22 +#define OMAP4_GPMC_DR1_LB_MASK (1 << 22) +#define OMAP4_GPMC_DR4_LB_SHIFT 21 +#define OMAP4_GPMC_DR4_LB_MASK (1 << 21) +#define OMAP4_GPMC_DR5_LB_SHIFT 20 +#define OMAP4_GPMC_DR5_LB_MASK (1 << 20) +#define OMAP4_GPMC_DR7_LB_SHIFT 19 +#define OMAP4_GPMC_DR7_LB_MASK (1 << 19) +#define OMAP4_HSI2_DR0_LB_SHIFT 18 +#define OMAP4_HSI2_DR0_LB_MASK (1 << 18) +#define OMAP4_HSI2_DR1_LB_SHIFT 17 +#define OMAP4_HSI2_DR1_LB_MASK (1 << 17) +#define OMAP4_HSI2_DR2_LB_SHIFT 16 +#define OMAP4_HSI2_DR2_LB_MASK (1 << 16) +#define OMAP4_KPD_DR0_LB_SHIFT 15 +#define OMAP4_KPD_DR0_LB_MASK (1 << 15) +#define OMAP4_KPD_DR1_LB_SHIFT 14 +#define OMAP4_KPD_DR1_LB_MASK (1 << 14) +#define OMAP4_PDM_DR0_LB_SHIFT 13 +#define OMAP4_PDM_DR0_LB_MASK (1 << 13) +#define OMAP4_SDMMC2_DR0_LB_SHIFT 12 +#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12) +#define OMAP4_SDMMC3_DR0_LB_SHIFT 11 +#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11) +#define OMAP4_SDMMC4_DR0_LB_SHIFT 10 +#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10) +#define OMAP4_SDMMC4_DR1_LB_SHIFT 9 +#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9) +#define OMAP4_SPI3_DR0_LB_SHIFT 8 +#define OMAP4_SPI3_DR0_LB_MASK (1 << 8) +#define OMAP4_SPI3_DR1_LB_SHIFT 7 +#define OMAP4_SPI3_DR1_LB_MASK (1 << 7) +#define OMAP4_UART3_DR2_LB_SHIFT 6 +#define OMAP4_UART3_DR2_LB_MASK (1 << 6) +#define OMAP4_UART3_DR3_LB_SHIFT 5 +#define OMAP4_UART3_DR3_LB_MASK (1 << 5) +#define OMAP4_UART3_DR4_LB_SHIFT 4 +#define OMAP4_UART3_DR4_LB_MASK (1 << 4) +#define OMAP4_UART3_DR5_LB_SHIFT 3 +#define OMAP4_UART3_DR5_LB_MASK (1 << 3) +#define OMAP4_USBA0_DR1_LB_SHIFT 2 +#define OMAP4_USBA0_DR1_LB_MASK (1 << 2) +#define OMAP4_USBA_DR2_LB_SHIFT 1 +#define OMAP4_USBA_DR2_LB_MASK (1 << 1) + +/* CONTROL_SMART2IO_PADCONF_1 */ +#define OMAP4_USBB1_DR0_LB_SHIFT 31 +#define OMAP4_USBB1_DR0_LB_MASK (1 << 31) +#define OMAP4_USBB2_DR0_LB_SHIFT 30 +#define OMAP4_USBB2_DR0_LB_MASK (1 << 30) +#define OMAP4_USBA0_DR0_LB_SHIFT 29 +#define OMAP4_USBA0_DR0_LB_MASK (1 << 29) + +/* CONTROL_SMART3IO_PADCONF_0 */ +#define OMAP4_DMIC_DR0_MB_SHIFT 30 +#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30) +#define OMAP4_GPIO_DR3_MB_SHIFT 28 +#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28) +#define OMAP4_GPIO_DR4_MB_SHIFT 26 +#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26) +#define OMAP4_GPIO_DR5_MB_SHIFT 24 +#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24) +#define OMAP4_GPIO_DR6_MB_SHIFT 22 +#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22) +#define OMAP4_HSI_DR1_MB_SHIFT 20 +#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20) +#define OMAP4_HSI_DR2_MB_SHIFT 18 +#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18) +#define OMAP4_HSI_DR3_MB_SHIFT 16 +#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16) +#define OMAP4_MCBSP2_DR0_MB_SHIFT 14 +#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14) +#define OMAP4_MCSPI4_DR0_MB_SHIFT 12 +#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12) +#define OMAP4_MCSPI4_DR1_MB_SHIFT 10 +#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10) +#define OMAP4_SDMMC3_DR0_MB_SHIFT 8 +#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8) +#define OMAP4_SPI2_DR0_MB_SHIFT 0 +#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0) + +/* CONTROL_SMART3IO_PADCONF_1 */ +#define OMAP4_SPI2_DR1_MB_SHIFT 30 +#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30) +#define OMAP4_SPI2_DR2_MB_SHIFT 28 +#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28) +#define OMAP4_UART2_DR0_MB_SHIFT 26 +#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26) +#define OMAP4_UART2_DR1_MB_SHIFT 24 +#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24) +#define OMAP4_UART4_DR0_MB_SHIFT 22 +#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22) +#define OMAP4_HSI_DR0_MB_SHIFT 20 +#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20) + +/* CONTROL_SMART3IO_PADCONF_2 */ +#define OMAP4_DMIC_DR0_LB_SHIFT 31 +#define OMAP4_DMIC_DR0_LB_MASK (1 << 31) +#define OMAP4_GPIO_DR3_LB_SHIFT 30 +#define OMAP4_GPIO_DR3_LB_MASK (1 << 30) +#define OMAP4_GPIO_DR4_LB_SHIFT 29 +#define OMAP4_GPIO_DR4_LB_MASK (1 << 29) +#define OMAP4_GPIO_DR5_LB_SHIFT 28 +#define OMAP4_GPIO_DR5_LB_MASK (1 << 28) +#define OMAP4_GPIO_DR6_LB_SHIFT 27 +#define OMAP4_GPIO_DR6_LB_MASK (1 << 27) +#define OMAP4_HSI_DR1_LB_SHIFT 26 +#define OMAP4_HSI_DR1_LB_MASK (1 << 26) +#define OMAP4_HSI_DR2_LB_SHIFT 25 +#define OMAP4_HSI_DR2_LB_MASK (1 << 25) +#define OMAP4_HSI_DR3_LB_SHIFT 24 +#define OMAP4_HSI_DR3_LB_MASK (1 << 24) +#define OMAP4_MCBSP2_DR0_LB_SHIFT 23 +#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23) +#define OMAP4_MCSPI4_DR0_LB_SHIFT 22 +#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22) +#define OMAP4_MCSPI4_DR1_LB_SHIFT 21 +#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21) +#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18 +#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18) +#define OMAP4_SPI2_DR0_LB_SHIFT 16 +#define OMAP4_SPI2_DR0_LB_MASK (1 << 16) +#define OMAP4_SPI2_DR1_LB_SHIFT 15 +#define OMAP4_SPI2_DR1_LB_MASK (1 << 15) +#define OMAP4_SPI2_DR2_LB_SHIFT 14 +#define OMAP4_SPI2_DR2_LB_MASK (1 << 14) +#define OMAP4_UART2_DR0_LB_SHIFT 13 +#define OMAP4_UART2_DR0_LB_MASK (1 << 13) +#define OMAP4_UART2_DR1_LB_SHIFT 12 +#define OMAP4_UART2_DR1_LB_MASK (1 << 12) +#define OMAP4_UART4_DR0_LB_SHIFT 11 +#define OMAP4_UART4_DR0_LB_MASK (1 << 11) +#define OMAP4_HSI_DR0_LB_SHIFT 10 +#define OMAP4_HSI_DR0_LB_MASK (1 << 10) + +/* CONTROL_USBB_HSIC */ +#define OMAP4_USBB2_DR1_SR_SHIFT 30 +#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30) +#define OMAP4_USBB2_DR1_I_SHIFT 27 +#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27) +#define OMAP4_USBB1_DR1_SR_SHIFT 25 +#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25) +#define OMAP4_USBB1_DR1_I_SHIFT 22 +#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22) +#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20 +#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20) +#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18 +#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18) +#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16 +#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16) +#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14 +#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14) +#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13 +#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13) +#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11 +#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11) +#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10 +#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10) +#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8 +#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8) +#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7 +#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7) +#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5 +#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5) +#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4 +#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4) +#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2 +#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2) + +/* CONTROL_SLIMBUS */ +#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30 +#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30) +#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28 +#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28) +#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26 +#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26) +#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24 +#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24) +#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22 +#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22) +#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20 +#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20) +#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19 +#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19) +#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18 +#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18) + +/* CONTROL_PBIASLITE */ +#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31 +#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31) +#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30 +#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30) +#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29 +#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29) +#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28 +#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28) +#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27 +#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27) +#define OMAP4_MMC1_PWRDNZ_SHIFT 26 +#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26) +#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25 +#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25) +#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24 +#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24) +#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23 +#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23) +#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22 +#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22) +#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21 +#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21) +#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20 +#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20) + +/* CONTROL_I2C_0 */ +#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31 +#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31) +#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29 +#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29) +#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28 +#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28) +#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27 +#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27) +#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25 +#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25) +#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24 +#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24) +#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23 +#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23) +#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21 +#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21) +#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20 +#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20) +#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19 +#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19) +#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17 +#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17) +#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16 +#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16) +#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15 +#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15) +#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13 +#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13) +#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12 +#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12) +#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11 +#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11) +#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9 +#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9) +#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8 +#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8) +#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7 +#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7) +#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5 +#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5) +#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4 +#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4) +#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3 +#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3) +#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1 +#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1) +#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0 +#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0) + +/* CONTROL_CAMERA_RX */ +#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31 +#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31) +#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29 +#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29) +#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24 +#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24) +#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22 +#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22) +#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21 +#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21) +#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19 +#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19) +#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18 +#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18) +#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16 +#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16) + +/* CONTROL_AVDAC */ +#define OMAP4_AVDAC_ACEN_SHIFT 31 +#define OMAP4_AVDAC_ACEN_MASK (1 << 31) +#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30 +#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30) +#define OMAP4_AVDAC_INPUTINV_SHIFT 29 +#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29) +#define OMAP4_AVDAC_CTL_SHIFT 13 +#define OMAP4_AVDAC_CTL_MASK (0xffff << 13) +#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12 +#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12) + +/* CONTROL_HDMI_TX_PHY */ +#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31 +#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31) +#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30 +#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30) +#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29 +#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29) +#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28 +#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28) + +/* CONTROL_MMC2 */ +#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31 +#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31) + +/* CONTROL_DSIPHY */ +#define OMAP4_DSI2_LANEENABLE_SHIFT 29 +#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) +#define OMAP4_DSI1_LANEENABLE_SHIFT 24 +#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) +#define OMAP4_DSI1_PIPD_SHIFT 19 +#define OMAP4_DSI1_PIPD_MASK (0x1f << 19) +#define OMAP4_DSI2_PIPD_SHIFT 14 +#define OMAP4_DSI2_PIPD_MASK (0x1f << 14) + +/* CONTROL_MCBSPLP */ +#define OMAP4_ALBCTRLRX_FSX_SHIFT 31 +#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31) +#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30 +#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30) +#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29 +#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29) + +/* CONTROL_USB2PHYCORE */ +#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31 +#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31) +#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30 +#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30) +#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29 +#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29) +#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28 +#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28) +#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27 +#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27) +#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26 +#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26) +#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25 +#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25) +#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24 +#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24) +#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21 +#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21) +#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20 +#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20) +#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19 +#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19) +#define OMAP4_USB2PHY_DATADET_SHIFT 18 +#define OMAP4_USB2PHY_DATADET_MASK (1 << 18) +#define OMAP4_USB2PHY_SINKONDP_SHIFT 17 +#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17) +#define OMAP4_USB2PHY_SRCONDM_SHIFT 16 +#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16) +#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15 +#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15) +#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14 +#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14) +#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13 +#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13) +#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12 +#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12) +#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11 +#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11) +#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10 +#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10) +#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9 +#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9) +#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8 +#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8) +#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7 +#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7) +#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6 +#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6) +#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5 +#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5) + +/* CONTROL_I2C_1 */ +#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31 +#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31) +#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29 +#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29) +#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28 +#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28) +#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27 +#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27) +#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25 +#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25) +#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24 +#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24) +#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23 +#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23) +#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22 +#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22) +#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21 +#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21) +#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20 +#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20) + +/* CONTROL_MMC1 */ +#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31 +#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31) +#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30 +#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30) +#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29 +#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29) +#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28 +#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28) +#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27 +#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27) +#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26 +#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26) +#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25 +#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25) +#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24 +#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24) +#define OMAP4_USB_FD_CDEN_SHIFT 23 +#define OMAP4_USB_FD_CDEN_MASK (1 << 23) +#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22 +#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22) +#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21 +#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21) + +/* CONTROL_HSI */ +#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31 +#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31) +#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30 +#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30) +#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29 +#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29) +#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28 +#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28) + +/* CONTROL_USB */ +#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31 +#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31) +#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30 +#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30) + +/* CONTROL_HDQ */ +#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31 +#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31) + +/* CONTROL_LPDDR2IO1_0 */ +#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30 +#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27 +#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25 +#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22 +#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19 +#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17 +#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14 +#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11 +#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9 +#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9) +#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6 +#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6) +#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3 +#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3) +#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1 +#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1) + +/* CONTROL_LPDDR2IO1_1 */ +#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30 +#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27 +#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25 +#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22 +#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19 +#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17 +#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14 +#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11 +#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9 +#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9) +#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6 +#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6) +#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3 +#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3) +#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1 +#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1) + +/* CONTROL_LPDDR2IO1_2 */ +#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30 +#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27 +#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25 +#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22 +#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19 +#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17 +#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14 +#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11 +#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9 +#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9) + +/* CONTROL_LPDDR2IO1_3 */ +#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31 +#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31) +#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30 +#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30) +#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29 +#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29) +#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28 +#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28) +#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27 +#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27) +#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26 +#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26) +#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25 +#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25) +#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24 +#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24) +#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23 +#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23) +#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22 +#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22) +#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21 +#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21) +#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20 +#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20) +#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19 +#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19) +#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18 +#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18) +#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17 +#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17) +#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16 +#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16) +#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15 +#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15) +#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14 +#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14) +#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13 +#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13) +#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12 +#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12) + +/* CONTROL_LPDDR2IO2_0 */ +#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30 +#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27 +#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25 +#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22 +#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19 +#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17 +#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14 +#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11 +#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9 +#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9) +#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6 +#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6) +#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3 +#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3) +#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1 +#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1) + +/* CONTROL_LPDDR2IO2_1 */ +#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30 +#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27 +#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25 +#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22 +#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19 +#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17 +#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14 +#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11 +#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9 +#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9) +#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6 +#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6) +#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3 +#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3) +#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1 +#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1) + +/* CONTROL_LPDDR2IO2_2 */ +#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30 +#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27 +#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25 +#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22 +#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19 +#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17 +#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14 +#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11 +#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9 +#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9) + +/* CONTROL_LPDDR2IO2_3 */ +#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31 +#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31) +#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30 +#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30) +#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29 +#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29) +#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28 +#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28) +#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27 +#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27) +#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26 +#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26) +#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25 +#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25) +#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24 +#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24) +#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23 +#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23) +#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22 +#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22) +#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21 +#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21) +#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20 +#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20) +#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19 +#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19) +#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18 +#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18) +#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17 +#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17) +#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16 +#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16) +#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15 +#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15) +#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14 +#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14) +#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13 +#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13) +#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12 +#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12) + +/* CONTROL_BUS_HOLD */ +#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31 +#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31) +#define OMAP4_MCSPI1_CS3_EN_SHIFT 30 +#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30) + +/* CONTROL_C2C */ +#define OMAP4_MIRROR_MODE_EN_SHIFT 31 +#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31) +#define OMAP4_C2C_SPARE_SHIFT 24 +#define OMAP4_C2C_SPARE_MASK (0x7f << 24) + +/* CORE_CONTROL_SPARE_RW */ +#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0 +#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0) + +/* CORE_CONTROL_SPARE_R */ +#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0 +#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0) + +/* CORE_CONTROL_SPARE_R_C0 */ +#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31 +#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31) +#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30 +#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30) +#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29 +#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29) +#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28 +#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28) +#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27 +#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27) +#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26 +#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26) +#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25 +#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25) +#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24 +#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24) + +/* CONTROL_EFUSE_1 */ +#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24 +#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24) +#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16 +#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16) +#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8 +#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8) +#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0 +#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0) + +/* CONTROL_EFUSE_2 */ +#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31 +#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31) +#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30 +#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30) +#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29 +#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29) +#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28 +#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28) +#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27 +#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27) +#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26 +#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26) +#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25 +#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25) +#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24 +#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24) +#define OMAP4_LPDDR2_PTV_N1_SHIFT 23 +#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23) +#define OMAP4_LPDDR2_PTV_N2_SHIFT 22 +#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22) +#define OMAP4_LPDDR2_PTV_N3_SHIFT 21 +#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21) +#define OMAP4_LPDDR2_PTV_N4_SHIFT 20 +#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20) +#define OMAP4_LPDDR2_PTV_N5_SHIFT 19 +#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19) +#define OMAP4_LPDDR2_PTV_P1_SHIFT 18 +#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18) +#define OMAP4_LPDDR2_PTV_P2_SHIFT 17 +#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17) +#define OMAP4_LPDDR2_PTV_P3_SHIFT 16 +#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16) +#define OMAP4_LPDDR2_PTV_P4_SHIFT 15 +#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15) +#define OMAP4_LPDDR2_PTV_P5_SHIFT 14 +#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14) + +/* CONTROL_EFUSE_3 */ +#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24 +#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24) +#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16 +#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16) +#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8 +#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8) +#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0 +#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0) + +/* CONTROL_EFUSE_4 */ +#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24 +#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24) +#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16 +#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16) +#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8 +#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8) +#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0 +#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0) + +#endif diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h new file mode 100644 index 0000000..17c9b37 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h @@ -0,0 +1,236 @@ +/* + * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson at ti.com) + * Santosh Shilimkar (santosh.shilimkar at ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap at vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H + + +/* Base address */ +#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000 + +/* Registers offset */ +#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000 +#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004 +#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010 +#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c +#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614 +#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618 +#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c + +/* Registers shifts and masks */ + +/* IP_REVISION */ +#define OMAP4_IP_REV_SCHEME_SHIFT 30 +#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) +#define OMAP4_IP_REV_FUNC_SHIFT 16 +#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) +#define OMAP4_IP_REV_RTL_SHIFT 11 +#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) +#define OMAP4_IP_REV_MAJOR_SHIFT 8 +#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) +#define OMAP4_IP_REV_CUSTOM_SHIFT 6 +#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) +#define OMAP4_IP_REV_MINOR_SHIFT 0 +#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) + +/* IP_HWINFO */ +#define OMAP4_IP_HWINFO_SHIFT 0 +#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) + +/* IP_SYSCONFIG */ +#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 +#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) + +/* PADCONF_WAKEUPEVENT_0 */ +#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* CONTROL_SMART1NOPMIO_PADCONF_0 */ +#define OMAP4_FREF_DR0_SC_SHIFT 30 +#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30) +#define OMAP4_FREF_DR1_SC_SHIFT 28 +#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28) +#define OMAP4_FREF_DR4_SC_SHIFT 26 +#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26) +#define OMAP4_FREF_DR5_SC_SHIFT 24 +#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24) +#define OMAP4_FREF_DR6_SC_SHIFT 22 +#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22) +#define OMAP4_FREF_DR7_SC_SHIFT 20 +#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20) +#define OMAP4_GPIO_DR7_SC_SHIFT 18 +#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18) +#define OMAP4_DPM_DR0_SC_SHIFT 14 +#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14) +#define OMAP4_SIM_DR0_SC_SHIFT 12 +#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12) + +/* CONTROL_SMART1NOPMIO_PADCONF_1 */ +#define OMAP4_FREF_DR0_LB_SHIFT 30 +#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30) +#define OMAP4_FREF_DR1_LB_SHIFT 28 +#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28) +#define OMAP4_FREF_DR4_LB_SHIFT 26 +#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26) +#define OMAP4_FREF_DR5_LB_SHIFT 24 +#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24) +#define OMAP4_FREF_DR6_LB_SHIFT 22 +#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22) +#define OMAP4_FREF_DR7_LB_SHIFT 20 +#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20) +#define OMAP4_GPIO_DR7_LB_SHIFT 18 +#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18) +#define OMAP4_DPM_DR0_LB_SHIFT 14 +#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14) +#define OMAP4_SIM_DR0_LB_SHIFT 12 +#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12) + +/* CONTROL_PADCONF_MODE */ +#define OMAP4_VDDS_DV_FREF_SHIFT 31 +#define OMAP4_VDDS_DV_FREF_MASK (1 << 31) +#define OMAP4_VDDS_DV_BANK2_SHIFT 30 +#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30) + +/* CONTROL_XTAL_OSCILLATOR */ +#define OMAP4_OSCILLATOR_BOOST_SHIFT 31 +#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31) +#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30 +#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30) + +/* CONTROL_USIMIO */ +#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31 +#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31) +#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29 +#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29) +#define OMAP4_USIM_PWRDNZ_SHIFT 28 +#define OMAP4_USIM_PWRDNZ_MASK (1 << 28) + +/* CONTROL_I2C_2 */ +#define OMAP4_SR_SDA_GLFENB_SHIFT 31 +#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31) +#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29 +#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29) +#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28 +#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28) +#define OMAP4_SR_SCL_GLFENB_SHIFT 27 +#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27) +#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25 +#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25) +#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24 +#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24) + +/* CONTROL_JTAG */ +#define OMAP4_JTAG_NTRST_EN_SHIFT 31 +#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31) +#define OMAP4_JTAG_TCK_EN_SHIFT 30 +#define OMAP4_JTAG_TCK_EN_MASK (1 << 30) +#define OMAP4_JTAG_RTCK_EN_SHIFT 29 +#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29) +#define OMAP4_JTAG_TDI_EN_SHIFT 28 +#define OMAP4_JTAG_TDI_EN_MASK (1 << 28) +#define OMAP4_JTAG_TDO_EN_SHIFT 27 +#define OMAP4_JTAG_TDO_EN_MASK (1 << 27) + +/* CONTROL_SYS */ +#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31 +#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31) + +/* WKUP_CONTROL_SPARE_RW */ +#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0 +#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0) + +/* WKUP_CONTROL_SPARE_R */ +#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0 +#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0) + +/* WKUP_CONTROL_SPARE_R_C0 */ +#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31 +#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31) +#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30 +#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30) +#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29 +#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29) +#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28 +#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28) +#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27 +#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27) +#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26 +#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26) +#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25 +#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25) +#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24 +#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24) + +#endif diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h new file mode 100644 index 0000000..a0af9ba --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h @@ -0,0 +1,92 @@ +/* + * OMAP44xx CTRL_MODULE_WKUP registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson at ti.com) + * Santosh Shilimkar (santosh.shilimkar at ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H + + +/* Base address */ +#define OMAP4_CTRL_MODULE_WKUP 0x4a30c000 + +/* Registers offset */ +#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000 +#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004 +#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6 0x0478 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7 0x047c +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8 0x0480 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9 0x0484 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10 0x0488 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11 0x048c +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12 0x0490 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13 0x0494 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14 0x0498 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15 0x049c +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16 0x04a0 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17 0x04a4 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18 0x04a8 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19 0x04ac +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20 0x04b0 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21 0x04b4 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22 0x04b8 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23 0x04bc +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24 0x04c0 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25 0x04c4 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26 0x04c8 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27 0x04cc +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28 0x04d0 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29 0x04d4 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30 0x04d8 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31 0x04dc + +/* Registers shifts and masks */ + +/* IP_REVISION */ +#define OMAP4_IP_REV_SCHEME_SHIFT 30 +#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) +#define OMAP4_IP_REV_FUNC_SHIFT 16 +#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) +#define OMAP4_IP_REV_RTL_SHIFT 11 +#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) +#define OMAP4_IP_REV_MAJOR_SHIFT 8 +#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) +#define OMAP4_IP_REV_CUSTOM_SHIFT 6 +#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) +#define OMAP4_IP_REV_MINOR_SHIFT 0 +#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) + +/* IP_HWINFO */ +#define OMAP4_IP_HWINFO_SHIFT 0 +#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) + +/* IP_SYSCONFIG */ +#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 +#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) + +/* CONF_DEBUG_SEL_TST_0 */ +#define OMAP4_WKUP_MODE_SHIFT 0 +#define OMAP4_WKUP_MODE_MASK (1 << 0) + +#endif diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h index 2916b7e..f571af7 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/plat-omap/include/plat/control.h @@ -17,6 +17,10 @@ #define __ASM_ARCH_CONTROL_H #include <mach/io.h> +#include <mach/ctrl_module_core_44xx.h> +#include <mach/ctrl_module_wkup_44xx.h> +#include <mach/ctrl_module_pad_core_44xx.h> +#include <mach/ctrl_module_pad_wkup_44xx.h> #ifndef __ASSEMBLY__ #define OMAP242X_CTRL_REGADDR(reg) \ -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 07/14] omap4: control: Fix the control module register accesses 2010-09-17 9:47 ` [PATCH 06/14] omap4: control: Add the register definition headers Santosh Shilimkar @ 2010-09-17 9:47 ` Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 08/14] omap: sram: fix is_sram_locked check Santosh Shilimkar 0 siblings, 1 reply; 52+ messages in thread From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw) To: linux-arm-kernel This patch has multiple fixes together. To ensure that git bisect work across commits, all changes are clubbed together 1. Move the common control base address to control core 2. Remove the manually coeded defines and use the ones from headers. 3. Fix the the status register define in id.c for OMAP4 4. Fix all the register define in hsmmc.c 5. Use the control pad accessor API for omap4 hsmmc register accesses Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> --- arch/arm/mach-omap2/hsmmc.c | 67 +++++++++++++++------------- arch/arm/mach-omap2/id.c | 2 +- arch/arm/plat-omap/common.c | 2 +- arch/arm/plat-omap/include/plat/control.h | 23 ---------- 4 files changed, 38 insertions(+), 56 deletions(-) diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index c8f647b..87bdb7b 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -135,10 +135,11 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, * * FIXME handle VMMC1A as needed ... */ - reg = omap_ctrl_readl(control_pbias_offset); - reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | - OMAP4_USBC1_ICUSB_PWRDNZ); - omap_ctrl_writel(reg, control_pbias_offset); + reg = omap4_ctrl_pad_readl(control_pbias_offset); + reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | + OMAP4_MMC1_PWRDNZ_MASK | + OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + omap4_ctrl_pad_writel(reg, control_pbias_offset); } static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, @@ -147,30 +148,33 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, u32 reg; if (power_on) { - reg = omap_ctrl_readl(control_pbias_offset); - reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ; + reg = omap4_ctrl_pad_readl(control_pbias_offset); + reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; if ((1 << vdd) <= MMC_VDD_165_195) - reg &= ~OMAP4_MMC1_PBIASLITE_VMODE; + reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; else - reg |= OMAP4_MMC1_PBIASLITE_VMODE; - reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | - OMAP4_USBC1_ICUSB_PWRDNZ); - omap_ctrl_writel(reg, control_pbias_offset); + reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; + reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | + OMAP4_MMC1_PWRDNZ_MASK | + OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + omap4_ctrl_pad_writel(reg, control_pbias_offset); /* 4 microsec delay for comparator to generate an error*/ udelay(4); - reg = omap_ctrl_readl(control_pbias_offset); - if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) { + reg = omap4_ctrl_pad_readl(control_pbias_offset); + if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { pr_err("Pbias Voltage is not same as LDO\n"); /* Caution : On VMODE_ERROR Power Down MMC IO */ - reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ); - omap_ctrl_writel(reg, control_pbias_offset); + reg &= ~(OMAP4_MMC1_PWRDNZ_MASK | + OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + omap4_ctrl_pad_writel(reg, control_pbias_offset); } } else { - reg = omap_ctrl_readl(control_pbias_offset); - reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | - OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ | - OMAP4_USBC1_ICUSB_PWRDNZ); - omap_ctrl_writel(reg, control_pbias_offset); + reg = omap4_ctrl_pad_readl(control_pbias_offset); + reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | + OMAP4_MMC1_PWRDNZ_MASK | + OMAP4_MMC1_PBIASLITE_VMODE_MASK | + OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + omap4_ctrl_pad_writel(reg, control_pbias_offset); } } @@ -218,17 +222,18 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } } else { - control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE; - control_mmc1 = OMAP44XX_CONTROL_MMC1; - reg = omap_ctrl_readl(control_mmc1); - reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 | - OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1); - reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 | - OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3); - reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL | - OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL | - OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL); - omap_ctrl_writel(reg, control_mmc1); + control_pbias_offset = + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; + control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; + reg = omap4_ctrl_pad_readl(control_mmc1); + reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | + OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); + reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | + OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); + reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| + OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | + OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); + omap4_ctrl_pad_writel(reg, control_mmc1); } for (c = controllers; c->mmc; c++) { diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 9a879f9..4808bc9 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -60,7 +60,7 @@ int omap_type(void) } else if (cpu_is_omap34xx()) { val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); } else if (cpu_is_omap44xx()) { - val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS); + val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); } else { pr_err("Cannot detect omap type!\n"); goto out; diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 480718b..7d668b3 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -336,7 +336,7 @@ void __init omap3_map_io(void) static struct omap_globals omap4_globals = { .class = OMAP443X_CLASS, .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), - .ctrl = OMAP443X_CTRL_BASE, /* FIXME: Move this to control core */ + .ctrl = OMAP443X_SCM_BASE, .ctrl_pad = OMAP443X_CTRL_BASE, .prm = OMAP4430_PRM_BASE, .cm = OMAP4430_CM_BASE, diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h index f571af7..19c9b2a 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/plat-omap/include/plat/control.h @@ -208,12 +208,6 @@ #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 -/* 44xx control status register offset */ -#define OMAP44XX_CONTROL_STATUS 0x2c4 - -/* 44xx-only CONTROL_GENERAL register offsets */ -#define OMAP44XX_CONTROL_MMC1 0x628 -#define OMAP44XX_CONTROL_PBIAS_LITE 0x600 /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. @@ -259,23 +253,6 @@ #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) #define OMAP2_PBIASLITEVMODE0 (1 << 0) -/* CONTROL_PBIAS_LITE bits for OMAP4 */ -#define OMAP4_MMC1_PWRDNZ (1 << 26) -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25) -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24) -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23) -#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22) -#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21) -#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20) - -#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31) -#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30) -#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29) -#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28) -#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27) -#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26) -#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25) - /* CONTROL_PROG_IO1 bits */ #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 08/14] omap: sram: fix is_sram_locked check 2010-09-17 9:47 ` [PATCH 07/14] omap4: control: Fix the control module register accesses Santosh Shilimkar @ 2010-09-17 9:47 ` Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 09/14] omap4: sram: Fix start address Santosh Shilimkar 0 siblings, 1 reply; 52+ messages in thread From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw) To: linux-arm-kernel From: Vikram Pandita <vikram.pandita@ti.com> For OMAP24xx/34xx/44xx: omap_type() returns the correct type: OMAP2_DEVICE_TYPE_TEST OMAP2_DEVICE_TYPE_EMU OMAP2_DEVICE_TYPE_SEC OMAP2_DEVICE_TYPE_GP OMAP2_DEVICE_TYPE_BAD In current implementation there are two problems: Problem 1: For 34xx, the current if check will never return true. Problem 2: For 24xx the correct type check should be with omap_type() function Verified by checking the TRM 24xx for CONTROL_STATUS register bits Signed-off-by: Vikram Pandita <vikram.pandita@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> --- arch/arm/plat-omap/sram.c | 11 +---------- 1 files changed, 1 insertions(+), 10 deletions(-) diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 10b3b4c..1faaa6e 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -93,16 +93,7 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, */ static int is_sram_locked(void) { - int type = 0; - - if (cpu_is_omap44xx()) - /* Not yet supported */ - return 0; - - if (cpu_is_omap242x()) - type = omap_rev() & OMAP2_DEVICETYPE_MASK; - - if (type == GP_DEVICE) { + if (OMAP2_DEVICE_TYPE_GP == omap_type()) { /* RAMFW: R/W access to all initiators for all qualifier sets */ if (cpu_is_omap242x()) { __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 09/14] omap4: sram: Fix start address 2010-09-17 9:47 ` [PATCH 08/14] omap: sram: fix is_sram_locked check Santosh Shilimkar @ 2010-09-17 9:47 ` Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 10/14] omap4: Update id.c and cpu.h for es2.0 Santosh Shilimkar 0 siblings, 1 reply; 52+ messages in thread From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw) To: linux-arm-kernel From: Vikram Pandita <vikram.pandita@ti.com> On OMAP4 there is no need to have SRAM_BOOTLOADER_SZ provision Hence put this macro under CONFIG_ARCH_OMAP2PLUS check Signed-off-by: Vikram Pandita <vikram.pandita@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> --- arch/arm/plat-omap/sram.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 1faaa6e..33ee6b8 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -53,7 +53,7 @@ #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) #define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2PLUS) #define SRAM_BOOTLOADER_SZ 0x00 #else #define SRAM_BOOTLOADER_SZ 0x80 -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 10/14] omap4: Update id.c and cpu.h for es2.0 2010-09-17 9:47 ` [PATCH 09/14] omap4: sram: Fix start address Santosh Shilimkar @ 2010-09-17 9:47 ` Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 11/14] omap4: Fix silicon version detection for early samples Santosh Shilimkar 0 siblings, 1 reply; 52+ messages in thread From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw) To: linux-arm-kernel This patch updates the id.c and cpu.h files to support omap4 ES2.0 silicon detection. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> --- arch/arm/mach-omap2/id.c | 29 ++++++++++++++++++++++------- arch/arm/plat-omap/include/plat/cpu.h | 5 ++++- 2 files changed, 26 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 4808bc9..ae70ae9 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -298,7 +298,6 @@ static void __init omap4_check_revision(void) u32 idcode; u16 hawkeye; u8 rev; - char *rev_name = "ES1.0"; /* * The IC rev detection is done with hawkeye and rev. @@ -309,14 +308,30 @@ static void __init omap4_check_revision(void) hawkeye = (idcode >> 12) & 0xffff; rev = (idcode >> 28) & 0xff; - if ((hawkeye == 0xb852) && (rev == 0x0)) { - omap_revision = OMAP4430_REV_ES1_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES1; - pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); - return; + switch (hawkeye) { + case 0xb852: + switch (rev) { + case 0: + omap_revision = OMAP4430_REV_ES1_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES1; + break; + case 1: + omap_revision = OMAP4430_REV_ES2_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES2; + break; + default: + omap_revision = OMAP4430_REV_ES2_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES2; + } + break; + default: + /* Unknown default to latest silicon rev as default*/ + omap_revision = OMAP4430_REV_ES2_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES2; } - pr_err("Unknown OMAP4 CPU id\n"); + pr_info("OMAP%04x ES%d.0\n", + omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1); } #define OMAP3_SHOW_FEATURE(feat) \ diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 2e2ae53..9b38e4b 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -391,6 +391,7 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP443X_CLASS 0x44300044 #define OMAP4430_REV_ES1_0 0x44300044 +#define OMAP4430_REV_ES2_0 0x44301044 /* * omap_chip bits @@ -417,10 +418,12 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP4430ES1 (1 << 8) #define CHIP_IS_OMAP3630ES1_1 (1 << 9) #define CHIP_IS_OMAP3630ES1_2 (1 << 10) +#define CHIP_IS_OMAP4430ES2 (1 << 11) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) -#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1) +#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ + CHIP_IS_OMAP4430ES2) /* * "GE" here represents "greater than or equal to" in terms of ES -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 11/14] omap4: Fix silicon version detection for early samples 2010-09-17 9:47 ` [PATCH 10/14] omap4: Update id.c and cpu.h for es2.0 Santosh Shilimkar @ 2010-09-17 9:47 ` Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 12/14] omap4: l2x0: Fix init parameter for es2.0 Santosh Shilimkar 2010-09-17 10:18 ` [PATCH 11/14] omap4: Fix silicon version detection for early samples Menon, Nishanth 0 siblings, 2 replies; 52+ messages in thread From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw) To: linux-arm-kernel Few initial omap4 es2 samples IDCODE is same as es1. This patch uses ARM cpuid register to detect the ES version for such samples Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> --- arch/arm/mach-omap2/id.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index ae70ae9..0412233 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -308,6 +308,15 @@ static void __init omap4_check_revision(void) hawkeye = (idcode >> 12) & 0xffff; rev = (idcode >> 28) & 0xff; + /* + * Few initial ES2.0 samples IDCODE is same as ES1.0 + * Use ARM register to detect the correct ES version + */ + if (!rev) { + idcode = read_cpuid(CPUID_ID); + rev = (idcode & 0xf) - 1; + } + switch (hawkeye) { case 0xb852: switch (rev) { -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 12/14] omap4: l2x0: Fix init parameter for es2.0 2010-09-17 9:47 ` [PATCH 11/14] omap4: Fix silicon version detection for early samples Santosh Shilimkar @ 2010-09-17 9:47 ` Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 13/14] omap4: Panda: Add DEBUG_LL support Santosh Shilimkar 2010-09-17 10:18 ` [PATCH 11/14] omap4: Fix silicon version detection for early samples Menon, Nishanth 1 sibling, 1 reply; 52+ messages in thread From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw) To: linux-arm-kernel On ES2.0 the L2 cache init parameter ineeds to be changed to take care of cache size. The cache size is 1MB on ES2.0 vs 512KB on ES1.0 This patch fixes the init parameter to update the same using dynamic cpu version check Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> --- arch/arm/mach-omap2/omap4-common.c | 10 +++++++--- 1 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 13dc979..923f9f5 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -61,10 +61,14 @@ static int __init omap_l2_cache_init(void) omap_smc1(0x102, 0x1); /* - * 32KB way size, 16-way associativity, - * parity disabled + * 16-way associativity, parity disabled + * Way size - 32KB (es1.0) + * Way size - 64KB (es2.0 +) */ - l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); + if (omap_rev() == OMAP4430_REV_ES1_0) + l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); + else + l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff); return 0; } -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 13/14] omap4: Panda: Add DEBUG_LL support 2010-09-17 9:47 ` [PATCH 12/14] omap4: l2x0: Fix init parameter for es2.0 Santosh Shilimkar @ 2010-09-17 9:47 ` Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU clocks Santosh Shilimkar 0 siblings, 1 reply; 52+ messages in thread From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw) To: linux-arm-kernel From: David Anders <x0132446@ti.com> Add support for use of DEBUG_LL for use with PandaBoard. Signed-off-by: David Anders <x0132446@ti.com> --- arch/arm/plat-omap/include/plat/uncompress.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index ddf723b..57dffa7 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -153,6 +153,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* omap4 based boards using UART3 */ DEBUG_LL_OMAP4(3, omap_4430sdp); + DEBUG_LL_OMAP4(3, omap4_panda); /* zoom2/3 external uart */ DEBUG_LL_ZOOM(omap_zoom2); -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU clocks 2010-09-17 9:47 ` [PATCH 13/14] omap4: Panda: Add DEBUG_LL support Santosh Shilimkar @ 2010-09-17 9:47 ` Santosh Shilimkar 2010-09-17 10:14 ` Menon, Nishanth 0 siblings, 1 reply; 52+ messages in thread From: Santosh Shilimkar @ 2010-09-17 9:47 UTC (permalink / raw) To: linux-arm-kernel This patch is temporary fix to below crash. This is observed when CPU is clocked more than 600 MHz. Unhandled fault: imprecise external abort (0x1406) at 0xbf9ef65c Internal error: : 1406 [#1] PREEMPT SMP last sysfs file: Modules linked in: CPU: 0 Not tainted (2.6.36-rc3+ #18) PC is at kernel_thread_helper+0x0/0x14 LR is at kernel_thread_helper+0x0/0x14 pc : [<c003ce14>] lr : [<c003ce14>] psr: 00000093 sp : dc83bff8 ip : 00000000 fp : 00000000 r10: 00000000 r9 : 00000000 r8 : 00000000 r7 : 00000013 r6 : c003ce28 r5 : c008935c r4 : 00000000 r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : 00000000 Flags: nzcv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c53c7f Table: 8000404a DAC: 00000017 Process swapper (pid: 2, stack limit = 0xdc83a2f0) Stack: (0xdc83bff8 to 0xdc83c000) bfe0: 00000000 ffffffff [<c003ce14>] (kernel_thread_helper+0x0/0x14) from [<fffffffe>] (0xfffffffe) Code: c03a0ba3 c03a5fcb c045c880 c0394035 (eb017701) ---[ end trace 1b75b31a2719ed1c ]--- The timer hwmod adaptation will eventually fix it in a proper way. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> --- arch/arm/plat-omap/dmtimer.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 44bafda..1d706cf 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -581,7 +581,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) * When the functional clock disappears, too quick writes seem * to cause an abort. XXX Is this still necessary? */ - __delay(150000); + __delay(300000); return ret; } -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU clocks 2010-09-17 9:47 ` [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU clocks Santosh Shilimkar @ 2010-09-17 10:14 ` Menon, Nishanth 2010-09-17 10:16 ` Shilimkar, Santosh 2010-09-17 10:37 ` Felipe Balbi 0 siblings, 2 replies; 52+ messages in thread From: Menon, Nishanth @ 2010-09-17 10:14 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap- > owner at vger.kernel.org] On Behalf Of Shilimkar, Santosh > Sent: Friday, September 17, 2010 4:48 AM > To: linux-omap at vger.kernel.org > Cc: linux-arm-kernel at lists.infradead.org; Shilimkar, Santosh; Nayak, > Rajendra > Subject: [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU > clocks > > This patch is temporary fix to below crash. This is observed when > CPU is clocked more than 600 MHz. > > Unhandled fault: imprecise external abort (0x1406) at 0xbf9ef65c > Internal error: : 1406 [#1] PREEMPT SMP > last sysfs file: > Modules linked in: > CPU: 0 Not tainted (2.6.36-rc3+ #18) > PC is at kernel_thread_helper+0x0/0x14 > LR is at kernel_thread_helper+0x0/0x14 > pc : [<c003ce14>] lr : [<c003ce14>] psr: 00000093 > sp : dc83bff8 ip : 00000000 fp : 00000000 > r10: 00000000 r9 : 00000000 r8 : 00000000 > r7 : 00000013 r6 : c003ce28 r5 : c008935c r4 : 00000000 > r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : 00000000 > Flags: nzcv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel > Control: 10c53c7f Table: 8000404a DAC: 00000017 > Process swapper (pid: 2, stack limit = 0xdc83a2f0) > Stack: (0xdc83bff8 to 0xdc83c000) > bfe0: 00000000 ffffffff > [<c003ce14>] (kernel_thread_helper+0x0/0x14) from [<fffffffe>] > (0xfffffffe) > Code: c03a0ba3 c03a5fcb c045c880 c0394035 (eb017701) > ---[ end trace 1b75b31a2719ed1c ]--- > > The timer hwmod adaptation will eventually fix it in a proper way. > > Signed-off-by: Rajendra Nayak <rnayak@ti.com> > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > --- > arch/arm/plat-omap/dmtimer.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c > index 44bafda..1d706cf 100644 > --- a/arch/arm/plat-omap/dmtimer.c > +++ b/arch/arm/plat-omap/dmtimer.c > @@ -581,7 +581,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer > *timer, int source) > * When the functional clock disappears, too quick writes seem > * to cause an abort. XXX Is this still necessary? > */ > - __delay(150000); > + __delay(300000); What is the rationale for this increase? Lets say we have a CPU bumped up to 1GHz or something will we have weird numbers again? Regards, Nishanth Menon ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU clocks 2010-09-17 10:14 ` Menon, Nishanth @ 2010-09-17 10:16 ` Shilimkar, Santosh 2010-09-17 10:27 ` Menon, Nishanth 2010-09-17 10:37 ` Felipe Balbi 1 sibling, 1 reply; 52+ messages in thread From: Shilimkar, Santosh @ 2010-09-17 10:16 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Menon, Nishanth > Sent: Friday, September 17, 2010 3:45 PM > To: Shilimkar, Santosh; linux-omap at vger.kernel.org > Cc: linux-arm-kernel at lists.infradead.org; Nayak, Rajendra > Subject: RE: [PATCH 14/14] omap4: Fix bootup crash observed with higher > CPU clocks > > > -----Original Message----- > > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap- > > owner at vger.kernel.org] On Behalf Of Shilimkar, Santosh > > Sent: Friday, September 17, 2010 4:48 AM > > To: linux-omap at vger.kernel.org > > Cc: linux-arm-kernel at lists.infradead.org; Shilimkar, Santosh; Nayak, > > Rajendra > > Subject: [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU > > clocks > > > > This patch is temporary fix to below crash. This is observed when > > CPU is clocked more than 600 MHz. > > > > Unhandled fault: imprecise external abort (0x1406) at 0xbf9ef65c > > Internal error: : 1406 [#1] PREEMPT SMP > > last sysfs file: > > Modules linked in: > > CPU: 0 Not tainted (2.6.36-rc3+ #18) > > PC is at kernel_thread_helper+0x0/0x14 > > LR is at kernel_thread_helper+0x0/0x14 > > pc : [<c003ce14>] lr : [<c003ce14>] psr: 00000093 > > sp : dc83bff8 ip : 00000000 fp : 00000000 > > r10: 00000000 r9 : 00000000 r8 : 00000000 > > r7 : 00000013 r6 : c003ce28 r5 : c008935c r4 : 00000000 > > r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : 00000000 > > Flags: nzcv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel > > Control: 10c53c7f Table: 8000404a DAC: 00000017 > > Process swapper (pid: 2, stack limit = 0xdc83a2f0) > > Stack: (0xdc83bff8 to 0xdc83c000) > > bfe0: 00000000 ffffffff > > [<c003ce14>] (kernel_thread_helper+0x0/0x14) from [<fffffffe>] > > (0xfffffffe) > > Code: c03a0ba3 c03a5fcb c045c880 c0394035 (eb017701) > > ---[ end trace 1b75b31a2719ed1c ]--- > > > > The timer hwmod adaptation will eventually fix it in a proper way. > > > > Signed-off-by: Rajendra Nayak <rnayak@ti.com> > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > > --- > > arch/arm/plat-omap/dmtimer.c | 2 +- > > 1 files changed, 1 insertions(+), 1 deletions(-) > > > > diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c > > index 44bafda..1d706cf 100644 > > --- a/arch/arm/plat-omap/dmtimer.c > > +++ b/arch/arm/plat-omap/dmtimer.c > > @@ -581,7 +581,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer > > *timer, int source) > > * When the functional clock disappears, too quick writes seem > > * to cause an abort. XXX Is this still necessary? > > */ > > - __delay(150000); > > + __delay(300000); > What is the rationale for this increase? Lets say we have a CPU bumped up > to 1GHz or something will we have weird numbers again? > This is the max what we need at any clock speed. As mentioned in commit "The timer hwmod adaptation will eventually fix it in a proper way" Regards, Santosh ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU clocks 2010-09-17 10:16 ` Shilimkar, Santosh @ 2010-09-17 10:27 ` Menon, Nishanth 2010-09-17 10:30 ` Shilimkar, Santosh 0 siblings, 1 reply; 52+ messages in thread From: Menon, Nishanth @ 2010-09-17 10:27 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Shilimkar, Santosh > Sent: Friday, September 17, 2010 5:17 AM [..] > > > -----Original Message----- > > > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap- > > > owner at vger.kernel.org] On Behalf Of Shilimkar, Santosh > > > Sent: Friday, September 17, 2010 4:48 AM [...] > > > --- > > > arch/arm/plat-omap/dmtimer.c | 2 +- > > > 1 files changed, 1 insertions(+), 1 deletions(-) > > > > > > diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat- > omap/dmtimer.c > > > index 44bafda..1d706cf 100644 > > > --- a/arch/arm/plat-omap/dmtimer.c > > > +++ b/arch/arm/plat-omap/dmtimer.c > > > @@ -581,7 +581,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer > > > *timer, int source) > > > * When the functional clock disappears, too quick writes seem > > > * to cause an abort. XXX Is this still necessary? > > > */ > > > - __delay(150000); > > > + __delay(300000); > > What is the rationale for this increase? Lets say we have a CPU bumped > up > > to 1GHz or something will we have weird numbers again? > > > This is the max what we need at any clock speed. As mentioned in commit > "The timer hwmod adaptation will eventually fix it in a proper way" Okay.. taking your word for it ;) PS: hard coded numbers + delays makes the red blue and white lights in my head to go off..(it even makes the siren sound too) ;) Regards, Nishanth Menon ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU clocks 2010-09-17 10:27 ` Menon, Nishanth @ 2010-09-17 10:30 ` Shilimkar, Santosh 2010-09-17 10:41 ` Felipe Balbi 0 siblings, 1 reply; 52+ messages in thread From: Shilimkar, Santosh @ 2010-09-17 10:30 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Menon, Nishanth > Sent: Friday, September 17, 2010 3:57 PM > To: Shilimkar, Santosh; linux-omap at vger.kernel.org > Cc: linux-arm-kernel at lists.infradead.org; Nayak, Rajendra > Subject: RE: [PATCH 14/14] omap4: Fix bootup crash observed with higher > CPU clocks > > > -----Original Message----- > > From: Shilimkar, Santosh > > Sent: Friday, September 17, 2010 5:17 AM > [..] > > > > -----Original Message----- > > > > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap- > > > > owner at vger.kernel.org] On Behalf Of Shilimkar, Santosh > > > > Sent: Friday, September 17, 2010 4:48 AM > > [...] > > > > --- > > > > arch/arm/plat-omap/dmtimer.c | 2 +- > > > > 1 files changed, 1 insertions(+), 1 deletions(-) > > > > > > > > diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat- > > omap/dmtimer.c > > > > index 44bafda..1d706cf 100644 > > > > --- a/arch/arm/plat-omap/dmtimer.c > > > > +++ b/arch/arm/plat-omap/dmtimer.c > > > > @@ -581,7 +581,7 @@ int omap_dm_timer_set_source(struct > omap_dm_timer > > > > *timer, int source) > > > > * When the functional clock disappears, too quick writes seem > > > > * to cause an abort. XXX Is this still necessary? > > > > */ > > > > - __delay(150000); > > > > + __delay(300000); > > > What is the rationale for this increase? Lets say we have a CPU bumped > > up > > > to 1GHz or something will we have weird numbers again? > > > > > This is the max what we need at any clock speed. As mentioned in commit > > "The timer hwmod adaptation will eventually fix it in a proper way" > > Okay.. taking your word for it ;) > This one I will ensure. > PS: hard coded numbers + delays makes the red blue and white lights in my > head to go off..(it even makes the siren sound too) ;) > Second your thought. Infact I wasn't ok to push this patch to start with but it's needed till the timer hwmod gets merged Regards, Santosh ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU clocks 2010-09-17 10:30 ` Shilimkar, Santosh @ 2010-09-17 10:41 ` Felipe Balbi 2010-09-17 11:17 ` Shilimkar, Santosh 0 siblings, 1 reply; 52+ messages in thread From: Felipe Balbi @ 2010-09-17 10:41 UTC (permalink / raw) To: linux-arm-kernel hi, On Fri, Sep 17, 2010 at 05:30:30AM -0500, Shilimkar, Santosh wrote: >Second your thought. Infact I wasn't ok to push this patch to start >with but it's needed till the timer hwmod gets merged to me, it just looks like "omap_test_timeout()" is timing out and that function is omap_dm_timer_set_source() is returning with a still-disabled clock. could you check if you get "cm: Module associated with clock gpt<blablabla> didn't enabled in 100000 tries" message on your dmesg ?? -- balbi ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU clocks 2010-09-17 10:41 ` Felipe Balbi @ 2010-09-17 11:17 ` Shilimkar, Santosh 2010-09-17 11:19 ` Felipe Balbi 0 siblings, 1 reply; 52+ messages in thread From: Shilimkar, Santosh @ 2010-09-17 11:17 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Balbi, Felipe > Sent: Friday, September 17, 2010 4:12 PM > To: Shilimkar, Santosh > Cc: Menon, Nishanth; linux-omap at vger.kernel.org; linux-arm- > kernel at lists.infradead.org; Nayak, Rajendra > Subject: Re: [PATCH 14/14] omap4: Fix bootup crash observed with higher > CPU clocks > > hi, > > On Fri, Sep 17, 2010 at 05:30:30AM -0500, Shilimkar, Santosh wrote: > >Second your thought. Infact I wasn't ok to push this patch to start > >with but it's needed till the timer hwmod gets merged > > to me, it just looks like "omap_test_timeout()" is timing out and that > function is omap_dm_timer_set_source() is returning with a > still-disabled clock. > > could you check if you get "cm: Module associated with clock > gpt<blablabla> didn't enabled in 100000 tries" message on your dmesg ?? > On OMAP4 specifically, the wait IDLEST support isn't there in the clock framework. This is taken care now in hwmod framework. With that we see that we don't need this delay anymore. The delay change is there for some time. May be there were issue with wait IDLEST. Regards, Santosh ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU clocks 2010-09-17 11:17 ` Shilimkar, Santosh @ 2010-09-17 11:19 ` Felipe Balbi 2010-09-17 11:24 ` Shilimkar, Santosh 0 siblings, 1 reply; 52+ messages in thread From: Felipe Balbi @ 2010-09-17 11:19 UTC (permalink / raw) To: linux-arm-kernel Hi, On Fri, Sep 17, 2010 at 06:17:47AM -0500, Shilimkar, Santosh wrote: >On OMAP4 specifically, the wait IDLEST support isn't there in the >clock framework. This is taken care now in hwmod framework. With >that we see that we don't need this delay anymore. > >The delay change is there for some time. May be there were issue >with wait IDLEST. ok, I see. Kevin, any plans to remove this hack ? -- balbi ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU clocks 2010-09-17 11:19 ` Felipe Balbi @ 2010-09-17 11:24 ` Shilimkar, Santosh 0 siblings, 0 replies; 52+ messages in thread From: Shilimkar, Santosh @ 2010-09-17 11:24 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Balbi, Felipe > Sent: Friday, September 17, 2010 4:49 PM > To: Shilimkar, Santosh > Cc: Balbi, Felipe; Menon, Nishanth; linux-omap at vger.kernel.org; linux-arm- > kernel at lists.infradead.org; Nayak, Rajendra; Kevin Hilman > Subject: Re: [PATCH 14/14] omap4: Fix bootup crash observed with higher > CPU clocks > > Hi, > > On Fri, Sep 17, 2010 at 06:17:47AM -0500, Shilimkar, Santosh wrote: > >On OMAP4 specifically, the wait IDLEST support isn't there in the > >clock framework. This is taken care now in hwmod framework. With > >that we see that we don't need this delay anymore. > > > >The delay change is there for some time. May be there were issue > >with wait IDLEST. > > ok, I see. > > Kevin, any plans to remove this hack ? > It's removed already in the timer hwmod series which is getting developed in parallel. Regards, ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU clocks 2010-09-17 10:14 ` Menon, Nishanth 2010-09-17 10:16 ` Shilimkar, Santosh @ 2010-09-17 10:37 ` Felipe Balbi 1 sibling, 0 replies; 52+ messages in thread From: Felipe Balbi @ 2010-09-17 10:37 UTC (permalink / raw) To: linux-arm-kernel Hi, On Fri, Sep 17, 2010 at 05:14:59AM -0500, Menon, Nishanth wrote: >> @@ -581,7 +581,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer >> *timer, int source) >> * When the functional clock disappears, too quick writes seem >> * to cause an abort. XXX Is this still necessary? >> */ >> - __delay(150000); >> + __delay(300000); >What is the rationale for this increase? Lets say we have a CPU bumped >up to 1GHz or something will we have weird numbers again? yeah, I thought the _omap2_module_wait_ready() should handle that ?? -- balbi ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 11/14] omap4: Fix silicon version detection for early samples 2010-09-17 9:47 ` [PATCH 11/14] omap4: Fix silicon version detection for early samples Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 12/14] omap4: l2x0: Fix init parameter for es2.0 Santosh Shilimkar @ 2010-09-17 10:18 ` Menon, Nishanth 2010-09-17 10:23 ` Shilimkar, Santosh 1 sibling, 1 reply; 52+ messages in thread From: Menon, Nishanth @ 2010-09-17 10:18 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap- > owner at vger.kernel.org] On Behalf Of Shilimkar, Santosh > Sent: Friday, September 17, 2010 4:48 AM [..] > diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c > index ae70ae9..0412233 100644 > --- a/arch/arm/mach-omap2/id.c > +++ b/arch/arm/mach-omap2/id.c > @@ -308,6 +308,15 @@ static void __init omap4_check_revision(void) > hawkeye = (idcode >> 12) & 0xffff; > rev = (idcode >> 28) & 0xff; > > + /* > + * Few initial ES2.0 samples IDCODE is same as ES1.0 > + * Use ARM register to detect the correct ES version > + */ > + if (!rev) { > + idcode = read_cpuid(CPUID_ID); > + rev = (idcode & 0xf) - 1; > + } > + Squash this to patch 10? Regards, Nishanth Menon ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 11/14] omap4: Fix silicon version detection for early samples 2010-09-17 10:18 ` [PATCH 11/14] omap4: Fix silicon version detection for early samples Menon, Nishanth @ 2010-09-17 10:23 ` Shilimkar, Santosh 0 siblings, 0 replies; 52+ messages in thread From: Shilimkar, Santosh @ 2010-09-17 10:23 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Menon, Nishanth > Sent: Friday, September 17, 2010 3:48 PM > To: Shilimkar, Santosh; linux-omap at vger.kernel.org > Cc: linux-arm-kernel at lists.infradead.org > Subject: RE: [PATCH 11/14] omap4: Fix silicon version detection for early > samples > > > -----Original Message----- > > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap- > > owner at vger.kernel.org] On Behalf Of Shilimkar, Santosh > > Sent: Friday, September 17, 2010 4:48 AM > > [..] > > > diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c > > index ae70ae9..0412233 100644 > > --- a/arch/arm/mach-omap2/id.c > > +++ b/arch/arm/mach-omap2/id.c > > @@ -308,6 +308,15 @@ static void __init omap4_check_revision(void) > > hawkeye = (idcode >> 12) & 0xffff; > > rev = (idcode >> 28) & 0xff; > > > > + /* > > + * Few initial ES2.0 samples IDCODE is same as ES1.0 > > + * Use ARM register to detect the correct ES version > > + */ > > + if (!rev) { > > + idcode = read_cpuid(CPUID_ID); > > + rev = (idcode & 0xf) - 1; > > + } > > + > > Squash this to patch 10? > Actually this was kind of temporary patch and was suppose to be reverted later and hence I kept it separate. Felipe, benoit suggested to have this change anyways considering it's just one check. http://www.mail-archive.com/linux-omap at vger.kernel.org/msg34521.html But now I think we can fold this into id patch itself. Will fold it into patch 10. Regards, Santosh ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 05/14] omap4: control: Add accessor api's for pad control module 2010-09-17 9:47 ` [PATCH 05/14] omap4: control: Add accessor api's for pad control module Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 06/14] omap4: control: Add the register definition headers Santosh Shilimkar @ 2010-09-17 10:17 ` Menon, Nishanth 1 sibling, 0 replies; 52+ messages in thread From: Menon, Nishanth @ 2010-09-17 10:17 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap- > owner at vger.kernel.org] On Behalf Of Santosh Shilimkar > Sent: Friday, September 17, 2010 4:48 AM > > On OMAP4 control pad are not addressable from control > core base. So the common omap_ctrl_read/write APIs breaks > Hence export separate APIs to manage the omap4 pad control > registers. > > This APIs will work only for OMAP4 Cosmetic comment below: > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > --- > arch/arm/mach-omap2/control.c | 18 ++++++++++++++++++ > arch/arm/plat-omap/include/plat/control.h | 4 ++++ > 2 files changed, 22 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c > index 99c0eb6..4ace2d1 100644 > --- a/arch/arm/mach-omap2/control.c > +++ b/arch/arm/mach-omap2/control.c > @@ -138,6 +138,7 @@ static struct omap3_control_regs control_context; > #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ > > #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) > +#define OMAP_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) s/ OMAP_CTRL_PAD_REGADDR/OMAP4_CTRL_PAD_REGADDR ? [...] Regards, Nishanth Menon ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 03/14] davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE 2010-09-17 9:47 ` [PATCH 03/14] davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 04/14] omap4: control: Add ctrl_pad_base to omap_globals Santosh Shilimkar @ 2010-09-17 10:16 ` Russell King - ARM Linux 2010-09-17 10:18 ` Shilimkar, Santosh 1 sibling, 1 reply; 52+ messages in thread From: Russell King - ARM Linux @ 2010-09-17 10:16 UTC (permalink / raw) To: linux-arm-kernel On Fri, Sep 17, 2010 at 03:17:47PM +0530, Santosh Shilimkar wrote: > On Davinci SRAM is mapped as MT_DEVICE becasue of the section > mapping pre-requisite instead of intended MT_MEMORY_NONCACHED > > Since the section mapping limitation gets fixed with first > patch in this series, the MT_MEMORY_NONCACHED can be used now. > > Have not tested this, so somebody with Davinci hardware can > try this out Is this still true? ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 03/14] davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE 2010-09-17 10:16 ` [PATCH 03/14] davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE Russell King - ARM Linux @ 2010-09-17 10:18 ` Shilimkar, Santosh 0 siblings, 0 replies; 52+ messages in thread From: Shilimkar, Santosh @ 2010-09-17 10:18 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk] > Sent: Friday, September 17, 2010 3:46 PM > To: Shilimkar, Santosh > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org > Subject: Re: [PATCH 03/14] davinci: map sram using MT_MEMORY_NONCACHED > instead of MT_DEVICE > > On Fri, Sep 17, 2010 at 03:17:47PM +0530, Santosh Shilimkar wrote: > > On Davinci SRAM is mapped as MT_DEVICE becasue of the section > > mapping pre-requisite instead of intended MT_MEMORY_NONCACHED > > > > Since the section mapping limitation gets fixed with first > > patch in this series, the MT_MEMORY_NONCACHED can be used now. > > > > Have not tested this, so somebody with Davinci hardware can > > try this out > > Is this still true? No it's not anymore.. It's already tested on Davinci by Kevin. I missed to remove that ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 02/14] omap: Map only available sram memory 2010-09-17 9:47 ` [PATCH 02/14] omap: Map only available sram memory Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 03/14] davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE Santosh Shilimkar @ 2010-09-17 10:15 ` Russell King - ARM Linux 2010-09-17 11:11 ` Shilimkar, Santosh 2010-10-01 20:15 ` Grazvydas Ignotas 2 siblings, 1 reply; 52+ messages in thread From: Russell King - ARM Linux @ 2010-09-17 10:15 UTC (permalink / raw) To: linux-arm-kernel On Fri, Sep 17, 2010 at 03:17:46PM +0530, Santosh Shilimkar wrote: > Currently we map 1 MB section while setting up SRAM on OMAPs. > The actual physcal OCM RAM available on OMAP SOCs is in order physical > of KBs. This patch maps only available sram and removes some > non necessary cpu_is_xxx checks. > > On the newer ARMs with speculation, this is dangerous and can > result in untraceable aborts. "this" should be expanded (otherwise it is unclear whether it refers to the original code or the new code.) ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 02/14] omap: Map only available sram memory 2010-09-17 10:15 ` [PATCH 02/14] omap: Map only available sram memory Russell King - ARM Linux @ 2010-09-17 11:11 ` Shilimkar, Santosh 0 siblings, 0 replies; 52+ messages in thread From: Shilimkar, Santosh @ 2010-09-17 11:11 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk] > Sent: Friday, September 17, 2010 3:46 PM > To: Shilimkar, Santosh > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org > Subject: Re: [PATCH 02/14] omap: Map only available sram memory > > On Fri, Sep 17, 2010 at 03:17:46PM +0530, Santosh Shilimkar wrote: > > Currently we map 1 MB section while setting up SRAM on OMAPs. > > The actual physcal OCM RAM available on OMAP SOCs is in order > > physical > > > of KBs. This patch maps only available sram and removes some > > non necessary cpu_is_xxx checks. > > > > On the newer ARMs with speculation, this is dangerous and can > > result in untraceable aborts. > > "this" should be expanded (otherwise it is unclear whether it refers to > the original code or the new code.) Will fix the change log as below. omap: Map only available sram memory Currently we map 1 MB section while setting up SRAM on OMAPs Regardless of the actual memory. The physical OCM RAM available on OMAP SOCs is in order of KBs. This patch maps only available sram and cleans up some un-necessary cpu_is_xxx checks. Mapping un-available or non-accessible(secure) memory on the newer ARM processor is dangerous. Because ARM CPUs can now speculatively prefetch, we should avoid mapping any no-existing or secure memory. ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 02/14] omap: Map only available sram memory 2010-09-17 9:47 ` [PATCH 02/14] omap: Map only available sram memory Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 03/14] davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE Santosh Shilimkar 2010-09-17 10:15 ` [PATCH 02/14] omap: Map only available sram memory Russell King - ARM Linux @ 2010-10-01 20:15 ` Grazvydas Ignotas 2010-10-01 22:53 ` Tony Lindgren 2 siblings, 1 reply; 52+ messages in thread From: Grazvydas Ignotas @ 2010-10-01 20:15 UTC (permalink / raw) To: linux-arm-kernel On Fri, Sep 17, 2010 at 12:47 PM, Santosh Shilimkar <santosh.shilimkar@ti.com> wrote: > Currently we map 1 MB section while setting up SRAM on OMAPs. > The actual physcal OCM RAM available on OMAP SOCs is in order > of KBs. This patch maps only available sram and removes some > non necessary cpu_is_xxx checks. > > On the newer ARMs with speculation, this is dangerous and can > result in untraceable aborts. > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> This hangs OMAP3 pandora: [ 0.000000] Linux version 2.6.36-rc6-next-20101001-00002-ge76bb53-dirty (notaz at pixelinis) (gcc version 4.3.3 (Sourcery G++ Lite 2009q1-20 [ 0.000000] CPU: ARMv7 Processor [411fc082] revision 2 (ARMv7), cr=10c53c7f [ 0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache [ 0.000000] Machine: Pandora Handheld Console [ 0.000000] Ignoring unrecognised tag 0x54410008 [ 0.000000] bootconsole [earlycon0] enabled [ 0.000000] Reserving 6422528 bytes SDRAM for VRAM [ 0.000000] Memory policy: ECC disabled, Data cache writeback [ 0.000000] OMAP3430/3530 ES2.1 (l2cache iva sgx neon isp ) [ 0.000000] SRAM: Mapped pa 0x40200000 to va 0xfe400000 size: 0x10000 (stuck here) reverting this fixes the problem. > --- > ?arch/arm/plat-omap/sram.c | ? 25 +++++-------------------- > ?1 files changed, 5 insertions(+), 20 deletions(-) > > diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c > index 226b2e8..10b3b4c 100644 > --- a/arch/arm/plat-omap/sram.c > +++ b/arch/arm/plat-omap/sram.c > @@ -220,20 +220,7 @@ void __init omap_map_sram(void) > ? ? ? ?if (omap_sram_size == 0) > ? ? ? ? ? ? ? ?return; > > - ? ? ? if (cpu_is_omap24xx()) { > - ? ? ? ? ? ? ? omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA; > - > - ? ? ? ? ? ? ? base = OMAP2_SRAM_PA; > - ? ? ? ? ? ? ? base = ROUND_DOWN(base, PAGE_SIZE); > - ? ? ? ? ? ? ? omap_sram_io_desc[0].pfn = __phys_to_pfn(base); > - ? ? ? } > - > ? ? ? ?if (cpu_is_omap34xx()) { > - ? ? ? ? ? ? ? omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA; > - ? ? ? ? ? ? ? base = OMAP3_SRAM_PA; > - ? ? ? ? ? ? ? base = ROUND_DOWN(base, PAGE_SIZE); > - ? ? ? ? ? ? ? omap_sram_io_desc[0].pfn = __phys_to_pfn(base); > - > ? ? ? ? ? ? ? ?/* > ? ? ? ? ? ? ? ? * SRAM must be marked as non-cached on OMAP3 since the > ? ? ? ? ? ? ? ? * CORE DPLL M2 divider change code (in SRAM) runs with the > @@ -244,13 +231,11 @@ void __init omap_map_sram(void) > ? ? ? ? ? ? ? ?omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED; > ? ? ? ?} > > - ? ? ? if (cpu_is_omap44xx()) { > - ? ? ? ? ? ? ? omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA; > - ? ? ? ? ? ? ? base = OMAP4_SRAM_PA; > - ? ? ? ? ? ? ? base = ROUND_DOWN(base, PAGE_SIZE); > - ? ? ? ? ? ? ? omap_sram_io_desc[0].pfn = __phys_to_pfn(base); > - ? ? ? } > - ? ? ? omap_sram_io_desc[0].length = 1024 * 1024; ? ? ?/* Use section desc */ > + ? ? ? omap_sram_io_desc[0].virtual = omap_sram_base; > + ? ? ? base = omap_sram_start; > + ? ? ? base = ROUND_DOWN(base, PAGE_SIZE); > + ? ? ? omap_sram_io_desc[0].pfn = __phys_to_pfn(base); > + ? ? ? omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE); > ? ? ? ?iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); > > ? ? ? ?printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n", > -- > 1.6.0.4 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-omap" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at ?http://vger.kernel.org/majordomo-info.html > ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 02/14] omap: Map only available sram memory 2010-10-01 20:15 ` Grazvydas Ignotas @ 2010-10-01 22:53 ` Tony Lindgren 2010-10-02 7:49 ` Shilimkar, Santosh 0 siblings, 1 reply; 52+ messages in thread From: Tony Lindgren @ 2010-10-01 22:53 UTC (permalink / raw) To: linux-arm-kernel * Grazvydas Ignotas <notasas@gmail.com> [101001 13:07]: > On Fri, Sep 17, 2010 at 12:47 PM, Santosh Shilimkar > <santosh.shilimkar@ti.com> wrote: > > Currently we map 1 MB section while setting up SRAM on OMAPs. > > The actual physcal OCM RAM available on OMAP SOCs is in order > > of KBs. This patch maps only available sram and removes some > > non necessary cpu_is_xxx checks. > > > > On the newer ARMs with speculation, this is dangerous and can > > result in untraceable aborts. > > > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > > This hangs OMAP3 pandora: > > [ 0.000000] Linux version > 2.6.36-rc6-next-20101001-00002-ge76bb53-dirty (notaz at pixelinis) (gcc > version 4.3.3 (Sourcery G++ Lite 2009q1-20 > [ 0.000000] CPU: ARMv7 Processor [411fc082] revision 2 (ARMv7), cr=10c53c7f > [ 0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing > instruction cache > [ 0.000000] Machine: Pandora Handheld Console > [ 0.000000] Ignoring unrecognised tag 0x54410008 > [ 0.000000] bootconsole [earlycon0] enabled > [ 0.000000] Reserving 6422528 bytes SDRAM for VRAM > [ 0.000000] Memory policy: ECC disabled, Data cache writeback > [ 0.000000] OMAP3430/3530 ES2.1 (l2cache iva sgx neon isp ) > [ 0.000000] SRAM: Mapped pa 0x40200000 to va 0xfe400000 size: 0x10000 > (stuck here) > > reverting this fixes the problem. Hmm, boots fine here with overo. Any idea what in this patch breaks pandora? Tony ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 02/14] omap: Map only available sram memory 2010-10-01 22:53 ` Tony Lindgren @ 2010-10-02 7:49 ` Shilimkar, Santosh 2010-10-04 9:03 ` Grazvydas Ignotas 0 siblings, 1 reply; 52+ messages in thread From: Shilimkar, Santosh @ 2010-10-02 7:49 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Tony Lindgren [mailto:tony at atomide.com] > Sent: Saturday, October 02, 2010 4:23 AM > To: Grazvydas Ignotas > Cc: Shilimkar, Santosh; linux-omap at vger.kernel.org; linux-arm- > kernel at lists.infradead.org; Russell King - ARM Linux > Subject: Re: [PATCH 02/14] omap: Map only available sram memory > > * Grazvydas Ignotas <notasas@gmail.com> [101001 13:07]: > > On Fri, Sep 17, 2010 at 12:47 PM, Santosh Shilimkar > > <santosh.shilimkar@ti.com> wrote: > > > Currently we map 1 MB section while setting up SRAM on OMAPs. > > > The actual physcal OCM RAM available on OMAP SOCs is in order > > > of KBs. This patch maps only available sram and removes some > > > non necessary cpu_is_xxx checks. > > > > > > On the newer ARMs with speculation, this is dangerous and can > > > result in untraceable aborts. > > > > > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > > > > This hangs OMAP3 pandora: > > > > [ 0.000000] Linux version > > 2.6.36-rc6-next-20101001-00002-ge76bb53-dirty (notaz at pixelinis) (gcc > > version 4.3.3 (Sourcery G++ Lite 2009q1-20 > > [ 0.000000] CPU: ARMv7 Processor [411fc082] revision 2 (ARMv7), > cr=10c53c7f > > [ 0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing > > instruction cache > > [ 0.000000] Machine: Pandora Handheld Console > > [ 0.000000] Ignoring unrecognised tag 0x54410008 > > [ 0.000000] bootconsole [earlycon0] enabled > > [ 0.000000] Reserving 6422528 bytes SDRAM for VRAM > > [ 0.000000] Memory policy: ECC disabled, Data cache writeback > > [ 0.000000] OMAP3430/3530 ES2.1 (l2cache iva sgx neon isp ) > > [ 0.000000] SRAM: Mapped pa 0x40200000 to va 0xfe400000 size: 0x10000 > > (stuck here) > > > > reverting this fixes the problem. > > Hmm, boots fine here with overo. Any idea what in this patch breaks > pandora? > The change in this patch is not board dependent really. Have tested this on 3430SDP. Pandora is OMAP3 based, right ? Regards, Santosh ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 02/14] omap: Map only available sram memory 2010-10-02 7:49 ` Shilimkar, Santosh @ 2010-10-04 9:03 ` Grazvydas Ignotas 2010-10-04 9:38 ` Shilimkar, Santosh 0 siblings, 1 reply; 52+ messages in thread From: Grazvydas Ignotas @ 2010-10-04 9:03 UTC (permalink / raw) To: linux-arm-kernel >> > >> > This hangs OMAP3 pandora: >> > >> > [ ? ?0.000000] Linux version >> > 2.6.36-rc6-next-20101001-00002-ge76bb53-dirty (notaz at pixelinis) (gcc >> > version 4.3.3 (Sourcery G++ Lite 2009q1-20 >> > [ ? ?0.000000] CPU: ARMv7 Processor [411fc082] revision 2 (ARMv7), >> cr=10c53c7f >> > [ ? ?0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing >> > instruction cache >> > [ ? ?0.000000] Machine: Pandora Handheld Console >> > [ ? ?0.000000] Ignoring unrecognised tag 0x54410008 >> > [ ? ?0.000000] bootconsole [earlycon0] enabled >> > [ ? ?0.000000] Reserving 6422528 bytes SDRAM for VRAM >> > [ ? ?0.000000] Memory policy: ECC disabled, Data cache writeback >> > [ ? ?0.000000] OMAP3430/3530 ES2.1 (l2cache iva sgx neon isp ) >> > [ ? ?0.000000] SRAM: Mapped pa 0x40200000 to va 0xfe400000 size: 0x10000 >> > (stuck here) >> > >> > reverting this fixes the problem. >> >> Hmm, boots fine here with overo. Any idea what in this patch breaks >> pandora? >> > The change in this patch is not board dependent really. Have tested this > on 3430SDP. Pandora is OMAP3 based, right ? OMAP3530 ES2.1, also tried on friend's beagleboard b5 (also ES2.1) and it has the same problem. Maybe it's because of older Cortex A8 used there, or I'm missing some errata workaround in defconfig. BTW, hacking the size to 1M on top of your patch fixes the problem too: base = omap_sram_start; base = ROUND_DOWN(base, PAGE_SIZE); omap_sram_io_desc[0].pfn = __phys_to_pfn(base); - omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE); + omap_sram_io_desc[0].length = 0x100000; iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 02/14] omap: Map only available sram memory 2010-10-04 9:03 ` Grazvydas Ignotas @ 2010-10-04 9:38 ` Shilimkar, Santosh 2010-10-04 13:24 ` Shilimkar, Santosh 0 siblings, 1 reply; 52+ messages in thread From: Shilimkar, Santosh @ 2010-10-04 9:38 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Grazvydas Ignotas [mailto:notasas at gmail.com] > Sent: Monday, October 04, 2010 2:34 PM > To: Shilimkar, Santosh > Cc: Tony Lindgren; linux-omap at vger.kernel.org; linux-arm- > kernel at lists.infradead.org; Russell King - ARM Linux > Subject: Re: [PATCH 02/14] omap: Map only available sram memory > > >> > > >> > This hangs OMAP3 pandora: > >> > > >> > [ ? ?0.000000] Linux version > >> > 2.6.36-rc6-next-20101001-00002-ge76bb53-dirty (notaz at pixelinis) (gcc > >> > version 4.3.3 (Sourcery G++ Lite 2009q1-20 > >> > [ ? ?0.000000] CPU: ARMv7 Processor [411fc082] revision 2 (ARMv7), > >> cr=10c53c7f > >> > [ ? ?0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing > >> > instruction cache > >> > [ ? ?0.000000] Machine: Pandora Handheld Console > >> > [ ? ?0.000000] Ignoring unrecognised tag 0x54410008 > >> > [ ? ?0.000000] bootconsole [earlycon0] enabled > >> > [ ? ?0.000000] Reserving 6422528 bytes SDRAM for VRAM > >> > [ ? ?0.000000] Memory policy: ECC disabled, Data cache writeback > >> > [ ? ?0.000000] OMAP3430/3530 ES2.1 (l2cache iva sgx neon isp ) > >> > [ ? ?0.000000] SRAM: Mapped pa 0x40200000 to va 0xfe400000 size: > 0x10000 > >> > (stuck here) > >> > > >> > reverting this fixes the problem. > >> > >> Hmm, boots fine here with overo. Any idea what in this patch breaks > >> pandora? > >> > > The change in this patch is not board dependent really. Have tested this > > on 3430SDP. Pandora is OMAP3 based, right ? > > OMAP3530 ES2.1, also tried on friend's beagleboard b5 (also ES2.1) and > it has the same problem. Maybe it's because of older Cortex A8 used > there, or I'm missing some errata workaround in defconfig. > > BTW, hacking the size to 1M on top of your patch fixes the problem too: > > base = omap_sram_start; > base = ROUND_DOWN(base, PAGE_SIZE); > omap_sram_io_desc[0].pfn = __phys_to_pfn(base); > - omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, > PAGE_SIZE); > + omap_sram_io_desc[0].length = 0x100000; This is the exact reason this patch is created :) So that you map only available memory instead of 1 MB > iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 02/14] omap: Map only available sram memory 2010-10-04 9:38 ` Shilimkar, Santosh @ 2010-10-04 13:24 ` Shilimkar, Santosh 2010-10-04 23:44 ` Grazvydas Ignotas 0 siblings, 1 reply; 52+ messages in thread From: Shilimkar, Santosh @ 2010-10-04 13:24 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap- > owner at vger.kernel.org] On Behalf Of Shilimkar, Santosh > Sent: Monday, October 04, 2010 3:08 PM > To: Grazvydas Ignotas > Cc: Tony Lindgren; linux-omap at vger.kernel.org; linux-arm- > kernel at lists.infradead.org; Russell King - ARM Linux > Subject: RE: [PATCH 02/14] omap: Map only available sram memory > > > -----Original Message----- > > From: Grazvydas Ignotas [mailto:notasas at gmail.com] > > Sent: Monday, October 04, 2010 2:34 PM > > To: Shilimkar, Santosh > > Cc: Tony Lindgren; linux-omap at vger.kernel.org; linux-arm- > > kernel at lists.infradead.org; Russell King - ARM Linux > > Subject: Re: [PATCH 02/14] omap: Map only available sram memory > > > > >> > > > >> > This hangs OMAP3 pandora: > > >> > > > >> > [ ? ?0.000000] Linux version > > >> > 2.6.36-rc6-next-20101001-00002-ge76bb53-dirty (notaz at pixelinis) > (gcc > > >> > version 4.3.3 (Sourcery G++ Lite 2009q1-20 > > >> > [ ? ?0.000000] CPU: ARMv7 Processor [411fc082] revision 2 (ARMv7), > > >> cr=10c53c7f > > >> > [ ? ?0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing > > >> > instruction cache > > >> > [ ? ?0.000000] Machine: Pandora Handheld Console > > >> > [ ? ?0.000000] Ignoring unrecognised tag 0x54410008 > > >> > [ ? ?0.000000] bootconsole [earlycon0] enabled > > >> > [ ? ?0.000000] Reserving 6422528 bytes SDRAM for VRAM > > >> > [ ? ?0.000000] Memory policy: ECC disabled, Data cache writeback > > >> > [ ? ?0.000000] OMAP3430/3530 ES2.1 (l2cache iva sgx neon isp ) > > >> > [ ? ?0.000000] SRAM: Mapped pa 0x40200000 to va 0xfe400000 size: > > 0x10000 > > >> > (stuck here) > > >> > > > >> > reverting this fixes the problem. > > >> > > >> Hmm, boots fine here with overo. Any idea what in this patch breaks > > >> pandora? > > >> > > > The change in this patch is not board dependent really. Have tested > this > > > on 3430SDP. Pandora is OMAP3 based, right ? > > > > OMAP3530 ES2.1, also tried on friend's beagleboard b5 (also ES2.1) and > > it has the same problem. Maybe it's because of older Cortex A8 used > > there, or I'm missing some errata workaround in defconfig. > > > > BTW, hacking the size to 1M on top of your patch fixes the problem too: > > > > base = omap_sram_start; > > base = ROUND_DOWN(base, PAGE_SIZE); > > omap_sram_io_desc[0].pfn = __phys_to_pfn(base); > > - omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, > > PAGE_SIZE); > > + omap_sram_io_desc[0].length = 0x100000; > This is the exact reason this patch is created :) > So that you map only available memory instead of 1 MB > > iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); Just booted latest mainline where this patch is already merged and my OMAP3630 boots fine ## Booting image at 80300000 ... Image Name: Linux-2.6.36-rc6-00086-gd4e8aa3 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3242124 Bytes = 3.1 MB Load Address: 80008000 Entry Point: 80008000 Verifying Checksum ... OK OK Starting kernel ... Uncompressing Linux... done, booting the kernel. [ 0.000000] Linux version 2.6.36-rc6-00086-gd4e8aa3 (a0393909 at a0393909-desktop) (gcc version 4.4.1 (Sourcery G++ Lite 2010q1-202) ) #1 Mon Oct 4 18:27:30 IST 2010 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7f [ 0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache [ 0.000000] Machine: OMAP Zoom3 board [ 0.000000] Memory policy: ECC disabled, Data cache writeback [ 0.000000] OMAP3630 ES1.0 (l2cache iva sgx neon isp 192mhz_clk ) [ 0.000000] SRAM: Mapped pa 0x40208000 to va 0xfe408000 size: 0x8000 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 [ 0.000000] Kernel command line: root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=172.24.190.46:/ubuntu/nfs-share/omap3_next/,nolock,tcp,rsize=4096,wsize=4096 ip=dhcp earlyprintk [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes) [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) [ 0.000000] Memory: 128MB = 128MB total [ 0.000000] Memory: 116148k/116148k available, 14924k reserved, 0K highmem [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) [ 0.000000] DMA : 0xffc00000 - 0xffe00000 ( 2 MB) [ 0.000000] vmalloc : 0xc8800000 - 0xf8000000 ( 760 MB) [ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) [ 0.000000] modules : 0xbf000000 - 0xc0000000 ( 16 MB) [ 0.000000] .init : 0xc0008000 - 0xc0047000 ( 252 kB) [ 0.000000] .text : 0xc0047000 - 0xc05e9000 (5768 kB) [ 0.000000] .data : 0xc0612000 - 0xc07e2900 (1859 kB) [ 0.000000] Hierarchical RCU implementation. [ 0.000000] RCU-based detection of stalled CPUs is disabled. [ 0.000000] Verbose stalled-CPUs detection is disabled. [ 0.000000] NR_IRQS:402 [ 0.000000] Clocking rate (Crystal/Core/MPU): 26.0/400/600 MHz [ 0.000000] (null): Could not get uart4_ick [ 0.000000] (null): Could not get uart4_fck [ 0.000000] Reprogramming SDRC clock to 400000000 Hz [ 0.000000] GPMC revision 5.0 [ 0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts [ 0.000000] Total of 96 interrupts on 1 active controller [ 0.000000] Could not get gpios_ick [ 0.000000] Could not get gpios_fck ---- Looks like for you " is_sram_locked" function is failing. There was a patch in my series from Vikram which was fixing this API. Do you have this patch applied when you are trying this out ? http://www.spinics.net/linux/lists/arm-kernel/msg98697.html Regards, Santosh ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 02/14] omap: Map only available sram memory 2010-10-04 13:24 ` Shilimkar, Santosh @ 2010-10-04 23:44 ` Grazvydas Ignotas 2010-10-05 0:34 ` Tony Lindgren 2010-10-05 5:15 ` Shilimkar, Santosh 0 siblings, 2 replies; 52+ messages in thread From: Grazvydas Ignotas @ 2010-10-04 23:44 UTC (permalink / raw) To: linux-arm-kernel > Looks like for you " is_sram_locked" function is failing. There was a patch > in my series from Vikram which was fixing this API. > > Do you have this patch applied when you are trying this out ? > http://www.spinics.net/linux/lists/arm-kernel/msg98697.html Well it looks like this only happens on linux-next (was using next-20101001 version) with this defconfig: http://notaz.gp2x.de/misc/pnd/config_next_101001_2 this has yours and Vikram's patch you mentioned in. Using omap2plus_defconfig on linux-next or this "bad" defconfig on linux-omap boots fine, strange. ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 02/14] omap: Map only available sram memory 2010-10-04 23:44 ` Grazvydas Ignotas @ 2010-10-05 0:34 ` Tony Lindgren 2010-10-05 0:36 ` Tony Lindgren 2010-10-05 5:15 ` Shilimkar, Santosh 1 sibling, 1 reply; 52+ messages in thread From: Tony Lindgren @ 2010-10-05 0:34 UTC (permalink / raw) To: linux-arm-kernel * Grazvydas Ignotas <notasas@gmail.com> [101004 16:35]: > > Looks like for you " is_sram_locked" function is failing. There was a patch > > in my series from Vikram which was fixing this API. > > > > Do you have this patch applied when you are trying this out ? > > http://www.spinics.net/linux/lists/arm-kernel/msg98697.html > > Well it looks like this only happens on linux-next (was using > next-20101001 version) with this defconfig: > http://notaz.gp2x.de/misc/pnd/config_next_101001_2 > > this has yours and Vikram's patch you mentioned in. Using > omap2plus_defconfig on linux-next or this "bad" defconfig on > linux-omap boots fine, strange. Maybe you need to disable CONFIG_SMP still in for-next? At least one patch is still missing there, that's the TLB broadcast patch we have in omap-testing and sitting in Russell's patch system. Regards, Tony ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 02/14] omap: Map only available sram memory 2010-10-05 0:34 ` Tony Lindgren @ 2010-10-05 0:36 ` Tony Lindgren 0 siblings, 0 replies; 52+ messages in thread From: Tony Lindgren @ 2010-10-05 0:36 UTC (permalink / raw) To: linux-arm-kernel * Tony Lindgren <tony@atomide.com> [101004 17:26]: > * Grazvydas Ignotas <notasas@gmail.com> [101004 16:35]: > > > Looks like for you " is_sram_locked" function is failing. There was a patch > > > in my series from Vikram which was fixing this API. > > > > > > Do you have this patch applied when you are trying this out ? > > > http://www.spinics.net/linux/lists/arm-kernel/msg98697.html > > > > Well it looks like this only happens on linux-next (was using > > next-20101001 version) with this defconfig: > > http://notaz.gp2x.de/misc/pnd/config_next_101001_2 > > > > this has yours and Vikram's patch you mentioned in. Using > > omap2plus_defconfig on linux-next or this "bad" defconfig on > > linux-omap boots fine, strange. > > Maybe you need to disable CONFIG_SMP still in for-next? > > At least one patch is still missing there, that's the TLB > broadcast patch we have in omap-testing and sitting in > Russell's patch system. Hmm, no CONFIG_SMP at least in the config above.. Must be something else then. Tony ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 02/14] omap: Map only available sram memory 2010-10-04 23:44 ` Grazvydas Ignotas 2010-10-05 0:34 ` Tony Lindgren @ 2010-10-05 5:15 ` Shilimkar, Santosh 1 sibling, 0 replies; 52+ messages in thread From: Shilimkar, Santosh @ 2010-10-05 5:15 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Grazvydas Ignotas [mailto:notasas at gmail.com] > Sent: Tuesday, October 05, 2010 5:14 AM > To: Shilimkar, Santosh > Cc: Tony Lindgren; linux-omap at vger.kernel.org; linux-arm- > kernel at lists.infradead.org; Russell King - ARM Linux > Subject: Re: [PATCH 02/14] omap: Map only available sram memory > > > Looks like for you " is_sram_locked" function is failing. There was a > patch > > in my series from Vikram which was fixing this API. > > > > Do you have this patch applied when you are trying this out ? > > http://www.spinics.net/linux/lists/arm-kernel/msg98697.html > > Well it looks like this only happens on linux-next (was using > next-20101001 version) with this defconfig: > http://notaz.gp2x.de/misc/pnd/config_next_101001_2 > > this has yours and Vikram's patch you mentioned in. Using > omap2plus_defconfig on linux-next or this "bad" defconfig on > linux-omap boots fine, strange. Indeed strange. At least good to know that omap2plus_defconfig on linux-next is booting fine. ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries 2010-09-17 9:47 ` [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 02/14] omap: Map only available sram memory Santosh Shilimkar @ 2010-09-17 16:41 ` Tony Lindgren 2010-09-29 14:51 ` Catalin Marinas 2 siblings, 0 replies; 52+ messages in thread From: Tony Lindgren @ 2010-09-17 16:41 UTC (permalink / raw) To: linux-arm-kernel * Santosh Shilimkar <santosh.shilimkar@ti.com> [100917 02:40]: > This patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED > types so that at boot-up, we can map memories outside system memory > at page level granularity > > Previously the mapping was limiting to section level, which creates > unnecessary addiotional mapping for which physical memory may not Minor typo here, it should be "additional". Tony ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries 2010-09-17 9:47 ` [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 02/14] omap: Map only available sram memory Santosh Shilimkar 2010-09-17 16:41 ` [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries Tony Lindgren @ 2010-09-29 14:51 ` Catalin Marinas 2010-09-29 15:01 ` Shilimkar, Santosh 2010-09-29 15:02 ` Russell King - ARM Linux 2 siblings, 2 replies; 52+ messages in thread From: Catalin Marinas @ 2010-09-29 14:51 UTC (permalink / raw) To: linux-arm-kernel Hi Santosh, Santosh Shilimkar <santosh.shilimkar@ti.com> wrote: > This patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED > types so that at boot-up, we can map memories outside system memory > at page level granularity > > Previously the mapping was limiting to section level, which creates > unnecessary addiotional mapping for which physical memory may not > present. On the newer ARM with speculation, this is dangerous and can > result in untraceable aborts. > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > Reviewed-by: Russell King <linux@arm.linux.org.uk> > --- > arch/arm/mm/mmu.c | 17 +++++++++++++++-- > 1 files changed, 15 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c > index 6e1c4f6..3e986a6 100644 > --- a/arch/arm/mm/mmu.c > +++ b/arch/arm/mm/mmu.c > @@ -246,6 +246,9 @@ static struct mem_type mem_types[] = { > .domain = DOMAIN_USER, > }, > [MT_MEMORY] = { > + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | > + L_PTE_USER | L_PTE_EXEC, > + .prot_l1 = PMD_TYPE_TABLE, Just a quick question - does this need to have L_PTE_USER? Is it read-only or it needs L_PTE_WRITE as well? Thanks. -- Catalin ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries 2010-09-29 14:51 ` Catalin Marinas @ 2010-09-29 15:01 ` Shilimkar, Santosh 2010-09-29 15:02 ` Russell King - ARM Linux 1 sibling, 0 replies; 52+ messages in thread From: Shilimkar, Santosh @ 2010-09-29 15:01 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Catalin Marinas [mailto:catalin.marinas at arm.com] > Sent: Wednesday, September 29, 2010 8:21 PM > To: Shilimkar, Santosh > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org > Subject: Re: [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and > MT_MEMORY_NONCACHED L1 entries > > Hi Santosh, > > Santosh Shilimkar <santosh.shilimkar@ti.com> wrote: > > This patch populates the L1 entries for MT_MEMORY and > MT_MEMORY_NONCACHED > > types so that at boot-up, we can map memories outside system memory > > at page level granularity > > > > Previously the mapping was limiting to section level, which creates > > unnecessary addiotional mapping for which physical memory may not > > present. On the newer ARM with speculation, this is dangerous and can > > result in untraceable aborts. > > > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > > Reviewed-by: Russell King <linux@arm.linux.org.uk> > > --- > > arch/arm/mm/mmu.c | 17 +++++++++++++++-- > > 1 files changed, 15 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c > > index 6e1c4f6..3e986a6 100644 > > --- a/arch/arm/mm/mmu.c > > +++ b/arch/arm/mm/mmu.c > > @@ -246,6 +246,9 @@ static struct mem_type mem_types[] = { > > .domain = DOMAIN_USER, > > }, > > [MT_MEMORY] = { > > + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | > > + L_PTE_USER | L_PTE_EXEC, > > + .prot_l1 = PMD_TYPE_TABLE, > > Just a quick question - does this need to have L_PTE_USER? Is it > read-only or it needs L_PTE_WRITE as well? > I think you are right. It should have "L_PTE_WRITE" as well. Regards, Santosh ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries 2010-09-29 14:51 ` Catalin Marinas 2010-09-29 15:01 ` Shilimkar, Santosh @ 2010-09-29 15:02 ` Russell King - ARM Linux 1 sibling, 0 replies; 52+ messages in thread From: Russell King - ARM Linux @ 2010-09-29 15:02 UTC (permalink / raw) To: linux-arm-kernel On Wed, Sep 29, 2010 at 03:51:21PM +0100, Catalin Marinas wrote: > Hi Santosh, > > Santosh Shilimkar <santosh.shilimkar@ti.com> wrote: > > This patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED > > types so that at boot-up, we can map memories outside system memory > > at page level granularity > > > > Previously the mapping was limiting to section level, which creates > > unnecessary addiotional mapping for which physical memory may not > > present. On the newer ARM with speculation, this is dangerous and can > > result in untraceable aborts. > > > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > > Reviewed-by: Russell King <linux@arm.linux.org.uk> > > --- > > arch/arm/mm/mmu.c | 17 +++++++++++++++-- > > 1 files changed, 15 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c > > index 6e1c4f6..3e986a6 100644 > > --- a/arch/arm/mm/mmu.c > > +++ b/arch/arm/mm/mmu.c > > @@ -246,6 +246,9 @@ static struct mem_type mem_types[] = { > > .domain = DOMAIN_USER, > > }, > > [MT_MEMORY] = { > > + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | > > + L_PTE_USER | L_PTE_EXEC, > > + .prot_l1 = PMD_TYPE_TABLE, > > Just a quick question - does this need to have L_PTE_USER? Is it > read-only or it needs L_PTE_WRITE as well? Eek. It should not have L_PTE_USER or else it will be accessible to userspace. ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 00/14] omap sram, omap4 control module and es2.0 support 2010-09-17 9:47 [PATCH 00/14] omap sram, omap4 control module and es2.0 support Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries Santosh Shilimkar @ 2010-09-17 15:06 ` Bryan Wu 2010-09-17 15:10 ` Shilimkar, Santosh 2010-09-17 17:50 ` Paul Walmsley 2 siblings, 1 reply; 52+ messages in thread From: Bryan Wu @ 2010-09-17 15:06 UTC (permalink / raw) To: linux-arm-kernel Santosh, Unfortunately, the kernel still cannot find MMC device and mount the root file system on my Panda ES2.0 8 layers board. Did we miss some patches? The Ubuntu 2.6.35 kernel boots fine. -Bryan On Fri, Sep 17, 2010 at 5:47 PM, Santosh Shilimkar <santosh.shilimkar@ti.com> wrote: > This is consolidated patch series targetted for 2.6.37 merge window. > All of these patches have been already posted/reviewed on the list. > > The series contains > ? ? ? ?- SRAM mapping fixes to avoid speculative aborts > ? ? ? ?- omap4 control module support > ? ? ? ?- Fixes for omap4 HS/GP detection > ? ? ? ?- omap4 es2.0 fixes. MMC and ethernet fixes are queued in respective > ? ? ? ? ?trees > > Boot tested with omap3_defconfig on > ? ? ? ? ? ? ? ? ? ? ? ?- OMAP4430 SPP > ? ? ? ? ? ? ? ? ? ? ? ?- OMAP4 Panda > ? ? ? ? ? ? ? ? ? ? ? ?- OMAP4 Blaze > ? ? ? ? ? ? ? ? ? ? ? ?- OMAP3430 SDP > > The following changes since commit 03a7ab083e4d619136d6f07ce70fa9de0bc436fc: > ?Linus Torvalds (1): > ? ? ? ?Merge git://git.kernel.org/.../sfrench/cifs-2.6 > > are available in the git repository at: > > ?git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base.git omap_for_2.6.37 > > David Anders (1): > ? ? ?omap4: Panda: Add DEBUG_LL support > > Santosh Shilimkar (11): > ? ? ?ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries > ? ? ?omap: Map only available sram memory > ? ? ?davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE > ? ? ?omap4: control: Add ctrl_pad_base to omap_globals > ? ? ?omap4: control: Add accessor api's for pad control module > ? ? ?omap4: control: Add the register definition headers > ? ? ?omap4: control: Fix the control module register accesses > ? ? ?omap4: Update id.c and cpu.h for es2.0 > ? ? ?omap4: Fix silicon version detection for early samples > ? ? ?omap4: l2x0: Fix init parameter for es2.0 > ? ? ?omap4: Fix bootup crash observed with higher CPU clocks > > Vikram Pandita (2): > ? ? ?omap: sram: fix is_sram_locked check > ? ? ?omap4: sram: Fix start address > > ?arch/arm/mach-davinci/dm355.c ? ? ? ? ? ? ? ? ? ? ?| ? ?3 +- > ?arch/arm/mach-davinci/dm365.c ? ? ? ? ? ? ? ? ? ? ?| ? ?3 +- > ?arch/arm/mach-davinci/dm644x.c ? ? ? ? ? ? ? ? ? ? | ? ?3 +- > ?arch/arm/mach-davinci/dm646x.c ? ? ? ? ? ? ? ? ? ? | ? ?3 +- > ?arch/arm/mach-omap2/control.c ? ? ? ? ? ? ? ? ? ? ?| ? 25 + > ?arch/arm/mach-omap2/hsmmc.c ? ? ? ? ? ? ? ? ? ? ? ?| ? 67 +- > ?arch/arm/mach-omap2/id.c ? ? ? ? ? ? ? ? ? ? ? ? ? | ? 40 +- > ?.../include/mach/ctrl_module_core_44xx.h ? ? ? ? ? | ?391 ++++++ > ?.../include/mach/ctrl_module_pad_core_44xx.h ? ? ? | 1409 ++++++++++++++++++++ > ?.../include/mach/ctrl_module_pad_wkup_44xx.h ? ? ? | ?236 ++++ > ?.../include/mach/ctrl_module_wkup_44xx.h ? ? ? ? ? | ? 92 ++ > ?arch/arm/mach-omap2/omap4-common.c ? ? ? ? ? ? ? ? | ? 10 +- > ?arch/arm/mm/mmu.c ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? 17 +- > ?arch/arm/plat-omap/common.c ? ? ? ? ? ? ? ? ? ? ? ?| ? ?3 +- > ?arch/arm/plat-omap/dmtimer.c ? ? ? ? ? ? ? ? ? ? ? | ? ?2 +- > ?arch/arm/plat-omap/include/plat/common.h ? ? ? ? ? | ? ?1 + > ?arch/arm/plat-omap/include/plat/control.h ? ? ? ? ?| ? 31 +- > ?arch/arm/plat-omap/include/plat/cpu.h ? ? ? ? ? ? ?| ? ?5 +- > ?arch/arm/plat-omap/include/plat/uncompress.h ? ? ? | ? ?1 + > ?arch/arm/plat-omap/sram.c ? ? ? ? ? ? ? ? ? ? ? ? ?| ? 38 +- > ?20 files changed, 2271 insertions(+), 109 deletions(-) > ?create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h > ?create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h > ?create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h > ?create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h > -- > To unsubscribe from this list: send the line "unsubscribe linux-omap" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at ?http://vger.kernel.org/majordomo-info.html > ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 00/14] omap sram, omap4 control module and es2.0 support 2010-09-17 15:06 ` [PATCH 00/14] omap sram, omap4 control module and es2.0 support Bryan Wu @ 2010-09-17 15:10 ` Shilimkar, Santosh 0 siblings, 0 replies; 52+ messages in thread From: Shilimkar, Santosh @ 2010-09-17 15:10 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: cooloney at gmail.com [mailto:cooloney at gmail.com] On Behalf Of Bryan Wu > Sent: Friday, September 17, 2010 8:36 PM > To: Shilimkar, Santosh > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org > Subject: Re: [PATCH 00/14] omap sram, omap4 control module and es2.0 > support > > Santosh, > > Unfortunately, the kernel still cannot find MMC device and mount the > root file system on my Panda ES2.0 8 layers board. > Did we miss some patches? The Ubuntu 2.6.35 kernel boots fine. > Use the patch posted by Madhu for MMC apart from this series http://www.mail-archive.com/linux-omap at vger.kernel.org/msg34855.html I didn't find any issues with my es2.0 Panda board. Kevin also tested his Panda where MMC worked well. Not sure what is the problem with your board, Regards, Santosh ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 00/14] omap sram, omap4 control module and es2.0 support 2010-09-17 9:47 [PATCH 00/14] omap sram, omap4 control module and es2.0 support Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries Santosh Shilimkar 2010-09-17 15:06 ` [PATCH 00/14] omap sram, omap4 control module and es2.0 support Bryan Wu @ 2010-09-17 17:50 ` Paul Walmsley 2010-09-18 7:32 ` Shilimkar, Santosh 2 siblings, 1 reply; 52+ messages in thread From: Paul Walmsley @ 2010-09-17 17:50 UTC (permalink / raw) To: linux-arm-kernel Hello Santosh On Fri, 17 Sep 2010, Santosh Shilimkar wrote: > This is consolidated patch series targetted for 2.6.37 merge window. > All of these patches have been already posted/reviewed on the list. Patch 6 is missing, could you please look into why? Also, please split all of the SCM changes out into a separate series/branch since they will be going in through my tree. Am reviewing those now. - Paul ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 00/14] omap sram, omap4 control module and es2.0 support 2010-09-17 17:50 ` Paul Walmsley @ 2010-09-18 7:32 ` Shilimkar, Santosh 2010-09-24 1:13 ` Tony Lindgren 0 siblings, 1 reply; 52+ messages in thread From: Shilimkar, Santosh @ 2010-09-18 7:32 UTC (permalink / raw) To: linux-arm-kernel -----Original Message----- > From: Paul Walmsley [mailto:paul at pwsan.com] > Sent: Friday, September 17, 2010 11:21 PM > To: Shilimkar, Santosh > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org > Subject: Re: [PATCH 00/14] omap sram, omap4 control module and es2.0 > support > > Hello Santosh > > On Fri, 17 Sep 2010, Santosh Shilimkar wrote: > > > This is consolidated patch series targetted for 2.6.37 merge window. > > All of these patches have been already posted/reviewed on the list. > > Patch 6 is missing, could you please look into why? > Mostly because of size of the patch, You can pick this from the below git link > Also, please split all of the SCM changes out into a separate > series/branch since they will be going in through my tree. Am reviewing > those now. > Ok done. I have split the series and kept scm changes on 'omap4_scm_2.6.37' head and rest on 'omap_for_2.6.37' Regards, Santosh --- The following changes since commit 03a7ab083e4d619136d6f07ce70fa9de0bc436fc: Linus Torvalds (1): Merge git://git.kernel.org/.../sfrench/cifs-2.6 are available in the git repository at: git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base.git omap4_scm_2.6.37 Santosh Shilimkar (4): omap4: control: Add ctrl_pad_base to omap_globals omap4: control: Add accessor api's for pad control module omap4: control: Add the register definition headers omap4: control: Fix the control module register accesses ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 00/14] omap sram, omap4 control module and es2.0 support 2010-09-18 7:32 ` Shilimkar, Santosh @ 2010-09-24 1:13 ` Tony Lindgren 2010-09-24 4:51 ` Shilimkar, Santosh 2010-09-24 6:42 ` Shilimkar, Santosh 0 siblings, 2 replies; 52+ messages in thread From: Tony Lindgren @ 2010-09-24 1:13 UTC (permalink / raw) To: linux-arm-kernel * Shilimkar, Santosh <santosh.shilimkar@ti.com> [100918 00:24]: > -----Original Message----- > > From: Paul Walmsley [mailto:paul at pwsan.com] > > Sent: Friday, September 17, 2010 11:21 PM > > To: Shilimkar, Santosh > > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org > > Subject: Re: [PATCH 00/14] omap sram, omap4 control module and es2.0 > > support > > > > Hello Santosh > > > > On Fri, 17 Sep 2010, Santosh Shilimkar wrote: > > > > > This is consolidated patch series targetted for 2.6.37 merge window. > > > All of these patches have been already posted/reviewed on the list. > > > > Patch 6 is missing, could you please look into why? > > > Mostly because of size of the patch, You can pick this from the > below git link > > > Also, please split all of the SCM changes out into a separate > > series/branch since they will be going in through my tree. Am reviewing > > those now. > > > Ok done. I have split the series and kept scm changes on 'omap4_scm_2.6.37' > head and rest on 'omap_for_2.6.37' Santosh, the "Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries" should get tested in the arm tree to avoid nasty surprises. Please do the following split: 1. A series for Russell to pull ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries omap: Map only available sram memory davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE You can add my Acked-by: Tony Lindgren <tony@atomide.com> to the "Map only available sram memory" patch. 2. A series for me to pull omap4: sram: Fix start address omap4: Update id.c and cpu.h for es2.0 omap4: l2x0: Fix init parameter for es2.0 omap4: Panda: Add DEBUG_LL support omap4: Fix bootup crash observed with higher CPU clocks 3. A series for Paul to pull (already in omap4_scm_2.6.37) omap4: control: Add ctrl_pad_base to omap_globals omap4: control: Add accessor api's for pad control module omap4: control: Add the register definition headers omap4: control: Fix the control module register accesses Please base them either on v2.6.35 or v2.6.36-rc5. Regards, Tony ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 00/14] omap sram, omap4 control module and es2.0 support 2010-09-24 1:13 ` Tony Lindgren @ 2010-09-24 4:51 ` Shilimkar, Santosh 2010-09-24 6:42 ` Shilimkar, Santosh 1 sibling, 0 replies; 52+ messages in thread From: Shilimkar, Santosh @ 2010-09-24 4:51 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Tony Lindgren [mailto:tony at atomide.com] > Sent: Friday, September 24, 2010 6:43 AM > To: Shilimkar, Santosh > Cc: Paul Walmsley; linux-omap at vger.kernel.org; linux-arm- > kernel at lists.infradead.org > Subject: Re: [PATCH 00/14] omap sram, omap4 control module and es2.0 > support > > * Shilimkar, Santosh <santosh.shilimkar@ti.com> [100918 00:24]: > > -----Original Message----- > > > From: Paul Walmsley [mailto:paul at pwsan.com] > > > Sent: Friday, September 17, 2010 11:21 PM > > > To: Shilimkar, Santosh > > > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org > > > Subject: Re: [PATCH 00/14] omap sram, omap4 control module and es2.0 > > > support > > > > > > Hello Santosh > > > > > > On Fri, 17 Sep 2010, Santosh Shilimkar wrote: > > > > > > > This is consolidated patch series targetted for 2.6.37 merge window. > > > > All of these patches have been already posted/reviewed on the list. > > > > > > Patch 6 is missing, could you please look into why? > > > > > Mostly because of size of the patch, You can pick this from the > > below git link > > > > > Also, please split all of the SCM changes out into a separate > > > series/branch since they will be going in through my tree. Am > reviewing > > > those now. > > > > > Ok done. I have split the series and kept scm changes on > 'omap4_scm_2.6.37' > > head and rest on 'omap_for_2.6.37' > > Santosh, the "Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries" should > get tested in the arm tree to avoid nasty surprises. Please do the > following > split: > > 1. A series for Russell to pull > ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries > omap: Map only available sram memory > davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE > > You can add my Acked-by: Tony Lindgren <tony@atomide.com> to > the "Map only available sram memory" patch. > > 2. A series for me to pull > omap4: sram: Fix start address > omap4: Update id.c and cpu.h for es2.0 > omap4: l2x0: Fix init parameter for es2.0 > omap4: Panda: Add DEBUG_LL support > omap4: Fix bootup crash observed with higher CPU clocks > > 3. A series for Paul to pull (already in omap4_scm_2.6.37) > omap4: control: Add ctrl_pad_base to omap_globals > omap4: control: Add accessor api's for pad control module > omap4: control: Add the register definition headers > omap4: control: Fix the control module register accesses > > Please base them either on v2.6.35 or v2.6.36-rc5. > Will do arrange patches as you suggested. Regards, Santosh ^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 00/14] omap sram, omap4 control module and es2.0 support 2010-09-24 1:13 ` Tony Lindgren 2010-09-24 4:51 ` Shilimkar, Santosh @ 2010-09-24 6:42 ` Shilimkar, Santosh 1 sibling, 0 replies; 52+ messages in thread From: Shilimkar, Santosh @ 2010-09-24 6:42 UTC (permalink / raw) To: linux-arm-kernel Tony, > -----Original Message----- > From: Tony Lindgren [mailto:tony at atomide.com] > Sent: Friday, September 24, 2010 6:43 AM > To: Shilimkar, Santosh > Cc: Paul Walmsley; linux-omap at vger.kernel.org; linux-arm- > kernel at lists.infradead.org > Subject: Re: [PATCH 00/14] omap sram, omap4 control module and es2.0 > support > <snip..> > Santosh, the "Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries" should > get tested in the arm tree to avoid nasty surprises. Please do the > following > split: > > 1. A series for Russell to pull > ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries > omap: Map only available sram memory > davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE > > You can add my Acked-by: Tony Lindgren <tony@atomide.com> to > the "Map only available sram memory" patch. Have submitted above three patches to RMK's patch system with your ack on the mentioned patch - patch 6407/1 - patch 6408/1 - patch 6409/1 They are also available at: git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base.git omap_for_2.6.37-rmk > > 2. A series for me to pull > omap4: sram: Fix start address > omap4: Update id.c and cpu.h for es2.0 > omap4: l2x0: Fix init parameter for es2.0 > omap4: Panda: Add DEBUG_LL support > omap4: Fix bootup crash observed with higher CPU clocks > The pull request is sent to you with patches rebased on v2.6.36-rc5 > 3. A series for Paul to pull (already in omap4_scm_2.6.37) > omap4: control: Add ctrl_pad_base to omap_globals > omap4: control: Add accessor api's for pad control module > omap4: control: Add the register definition headers > omap4: control: Fix the control module register accesses > This series is already available. I just rebased on v2.6.36-rc5 as you suggested. Regards, Santosh ^ permalink raw reply [flat|nested] 52+ messages in thread
end of thread, other threads:[~2010-10-05 5:15 UTC | newest] Thread overview: 52+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2010-09-17 9:47 [PATCH 00/14] omap sram, omap4 control module and es2.0 support Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 02/14] omap: Map only available sram memory Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 03/14] davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 04/14] omap4: control: Add ctrl_pad_base to omap_globals Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 05/14] omap4: control: Add accessor api's for pad control module Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 06/14] omap4: control: Add the register definition headers Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 07/14] omap4: control: Fix the control module register accesses Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 08/14] omap: sram: fix is_sram_locked check Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 09/14] omap4: sram: Fix start address Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 10/14] omap4: Update id.c and cpu.h for es2.0 Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 11/14] omap4: Fix silicon version detection for early samples Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 12/14] omap4: l2x0: Fix init parameter for es2.0 Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 13/14] omap4: Panda: Add DEBUG_LL support Santosh Shilimkar 2010-09-17 9:47 ` [PATCH 14/14] omap4: Fix bootup crash observed with higher CPU clocks Santosh Shilimkar 2010-09-17 10:14 ` Menon, Nishanth 2010-09-17 10:16 ` Shilimkar, Santosh 2010-09-17 10:27 ` Menon, Nishanth 2010-09-17 10:30 ` Shilimkar, Santosh 2010-09-17 10:41 ` Felipe Balbi 2010-09-17 11:17 ` Shilimkar, Santosh 2010-09-17 11:19 ` Felipe Balbi 2010-09-17 11:24 ` Shilimkar, Santosh 2010-09-17 10:37 ` Felipe Balbi 2010-09-17 10:18 ` [PATCH 11/14] omap4: Fix silicon version detection for early samples Menon, Nishanth 2010-09-17 10:23 ` Shilimkar, Santosh 2010-09-17 10:17 ` [PATCH 05/14] omap4: control: Add accessor api's for pad control module Menon, Nishanth 2010-09-17 10:16 ` [PATCH 03/14] davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE Russell King - ARM Linux 2010-09-17 10:18 ` Shilimkar, Santosh 2010-09-17 10:15 ` [PATCH 02/14] omap: Map only available sram memory Russell King - ARM Linux 2010-09-17 11:11 ` Shilimkar, Santosh 2010-10-01 20:15 ` Grazvydas Ignotas 2010-10-01 22:53 ` Tony Lindgren 2010-10-02 7:49 ` Shilimkar, Santosh 2010-10-04 9:03 ` Grazvydas Ignotas 2010-10-04 9:38 ` Shilimkar, Santosh 2010-10-04 13:24 ` Shilimkar, Santosh 2010-10-04 23:44 ` Grazvydas Ignotas 2010-10-05 0:34 ` Tony Lindgren 2010-10-05 0:36 ` Tony Lindgren 2010-10-05 5:15 ` Shilimkar, Santosh 2010-09-17 16:41 ` [PATCH 01/14] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries Tony Lindgren 2010-09-29 14:51 ` Catalin Marinas 2010-09-29 15:01 ` Shilimkar, Santosh 2010-09-29 15:02 ` Russell King - ARM Linux 2010-09-17 15:06 ` [PATCH 00/14] omap sram, omap4 control module and es2.0 support Bryan Wu 2010-09-17 15:10 ` Shilimkar, Santosh 2010-09-17 17:50 ` Paul Walmsley 2010-09-18 7:32 ` Shilimkar, Santosh 2010-09-24 1:13 ` Tony Lindgren 2010-09-24 4:51 ` Shilimkar, Santosh 2010-09-24 6:42 ` Shilimkar, Santosh
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