[PATCH 0/3] [ARM] tegra: PCI Express support

[PATCH 0/3] [ARM] tegra: PCI Express support

[Mike Rapoport]

These patches enable PCI Express support on Tegra2.
The implementation is based on original NVidia code from (1), but it
is heavily reworked to avoid custom PCI enumeration and make the code
more Linux friendly.

This implementation assumes that the PCIe subsystem is fully powered
and ungated by the bootloader.

[1] git://nv-tegra.nvidia.com/linux-2.6.git

The following changes since commit 9c03f1622af051004416dd3e24d8a0fa31e34178:
  Linus Torvalds (1):
        Merge ssh://master.kernel.org/home/hpa/tree/sec

Mike Rapoport (3):
      [ARM] tegra: add PCI Express clocks
      [ARM] tegra: add PCI Express support
      [ARM] tegra: harmony: enable PCI Express

 arch/arm/mach-tegra/Kconfig                 |    4 +
 arch/arm/mach-tegra/Makefile                |    2 +
 arch/arm/mach-tegra/board-harmony-pcie.c    |   52 ++
 arch/arm/mach-tegra/board.h                 |    1 +
 arch/arm/mach-tegra/include/mach/hardware.h |    4 +
 arch/arm/mach-tegra/pcie.c                  |  889 +++++++++++++++++++++++++++
 arch/arm/mach-tegra/tegra2_clocks.c         |   76 +++-
 7 files changed, 1025 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/mach-tegra/board-harmony-pcie.c
 create mode 100644 arch/arm/mach-tegra/pcie.c

[PATCH 1/3] [ARM] tegra: add PCI Express clocks

[Mike Rapoport]

Signed-off-by: Mike Rapoport <mike@compulab.co.il>
---
 arch/arm/mach-tegra/tegra2_clocks.c |   76 +++++++++++++++++++++++++++++++++-
 1 files changed, 73 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 4261632..44f1b81 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -92,6 +92,8 @@
 #define PLLD_MISC_DIV_RST		(1<<23)
 #define PLLD_MISC_DCCON_SHIFT		12
 
+#define PLLE_MISC_READY			(1 << 15)
+
 #define PERIPH_CLK_TO_ENB_REG(c)	((c->clk_num / 32) * 4)
 #define PERIPH_CLK_TO_ENB_SET_REG(c)	((c->clk_num / 32) * 8)
 #define PERIPH_CLK_TO_ENB_BIT(c)	(1 << (c->clk_num % 32))
@@ -356,12 +358,12 @@ static unsigned long tegra2_pll_clk_recalculate_rate(struct clk *c)
 	return c->rate;
 }
 
-static int tegra2_pll_clk_wait_for_lock(struct clk *c)
+static int tegra2_pll_clk_wait_for_bit_set(struct clk *c, int bit)
 {
 	ktime_t before;
 
 	before = ktime_get();
-	while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) {
+	while (!(clk_readl(c->reg + PLL_BASE) & bit)) {
 		if (ktime_us_delta(ktime_get(), before) > 5000) {
 			pr_err("Timed out waiting for lock bit on pll %s",
 				c->name);
@@ -414,7 +416,7 @@ static int tegra2_pll_clk_enable(struct clk *c)
 	val |= PLL_MISC_LOCK_ENABLE;
 	clk_writel(val, c->reg + PLL_MISC(c));
 
-	tegra2_pll_clk_wait_for_lock(c);
+	tegra2_pll_clk_wait_for_bit_set(c, PLL_BASE_LOCK);
 
 	return 0;
 }
@@ -754,6 +756,34 @@ static struct clk_ops tegra_clk_double_ops = {
 	.recalculate_rate	= &tegra2_clk_recalculate_rate,
 };
 
+/* PCI Express clock ops */
+static int tegra2_plle_clk_enable(struct clk *c)
+{
+	u32 val;
+
+	pr_debug("%s on clock %s\n", __func__, c->name);
+
+	if (tegra2_pll_clk_wait_for_bit_set(c, PLLE_MISC_READY))
+		return -EBUSY;
+
+	val = clk_readl(c->reg + PLL_BASE);
+	val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
+	clk_writel(val, c->reg + PLL_BASE);
+
+	return 0;
+}
+
+static struct clk_ops tegra_plle_ops = {
+	.init       = tegra2_pll_clk_init,
+	.enable     = tegra2_plle_clk_enable,
+	.set_rate   = tegra2_pll_clk_set_rate,
+};
+
+static struct clk_ops tegra_pcie_clk_ops = {
+	.enable	    = tegra2_periph_clk_enable,
+	.disable    = tegra2_periph_clk_disable,
+};
+
 /* Clock definitions */
 static struct clk tegra_clk_32k = {
 	.name = "clk_32k",
@@ -1109,6 +1139,42 @@ static struct clk tegra_clk_pclk = {
 	.ops		= &tegra_bus_ops,
 };
 
+/* PCI Express clocks */
+static struct clk_pll_table tegra_pll_e_table[] = {
+       { 12000000, 100000000,  200,  24, 1, 0 },
+};
+
+static struct clk tegra_pll_e = {
+	.name      = "pll_e",
+	.flags	   = PLL_ALT_MISC_REG,
+	.ops       = &tegra_plle_ops,
+	.input_min = 12000000,
+	.input_max = 12000000,
+	.parent    = &tegra_clk_m,
+	.reg       = 0xe8,
+	.pll_table = tegra_pll_e_table,
+};
+
+static struct clk tegra_clk_pex = {
+	.name      = "pex",
+	.flags     = PERIPH_MANUAL_RESET,
+	.ops       = &tegra_pcie_clk_ops,
+	.clk_num   = 70,
+};
+
+static struct clk tegra_clk_afi = {
+	.name      = "afi",
+	.flags     = PERIPH_MANUAL_RESET,
+	.ops       = &tegra_pcie_clk_ops,
+	.clk_num   = 72,
+};
+
+/* the pcie_xclk is required for reset of PCIE subsystem */
+static struct clk tegra_clk_pcie_xclk = {
+	.name      = "pcie_xclk",
+	.clk_num   = 74,
+};
+
 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
 	{ .input = &tegra_pll_m, .value = 0},
 	{ .input = &tegra_pll_c, .value = 1},
@@ -1315,11 +1381,15 @@ struct clk_lookup tegra_clk_lookups[] = {
 	CLK(NULL,	"pll_d_out0",	&tegra_pll_d_out0),
 	CLK(NULL,	"pll_u",	&tegra_pll_u),
 	CLK(NULL,	"pll_x",	&tegra_pll_x),
+	CLK(NULL,	"pll_e",	&tegra_pll_e),
 	CLK(NULL,	"cpu",		&tegra_clk_cpu),
 	CLK(NULL,	"sys",		&tegra_clk_sys),
 	CLK(NULL,	"hclk",		&tegra_clk_hclk),
 	CLK(NULL,	"pclk",		&tegra_clk_pclk),
 	CLK(NULL,	"clk_d",	&tegra_clk_d),
+	CLK(NULL,	"pcie_xclk",	&tegra_clk_pcie_xclk),
+	CLK(NULL,	"pex",		&tegra_clk_pex),
+	CLK(NULL,	"afi",		&tegra_clk_afi),
 };
 
 void __init tegra2_init_clocks(void)
-- 
1.6.6.2

[PATCH 2/3] [ARM] tegra: add PCI Express support

[Mike Rapoport]

Signed-off-by: Mike Rapoport <mike@compulab.co.il>
---
 arch/arm/mach-tegra/Kconfig                 |    4 +
 arch/arm/mach-tegra/Makefile                |    1 +
 arch/arm/mach-tegra/board.h                 |    1 +
 arch/arm/mach-tegra/include/mach/hardware.h |    4 +
 arch/arm/mach-tegra/pcie.c                  |  889 +++++++++++++++++++++++++++
 5 files changed, 899 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/pcie.c

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index a57713c..5f09846 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -16,6 +16,10 @@ config ARCH_TEGRA_2x_SOC
 
 endchoice
 
+config TEGRA_PCI
+	bool "PCI Express support"
+	select PCI
+
 comment "Tegra board type"
 
 config MACH_HARMONY
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 51e9370..23c9600 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clock.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
+obj-$(CONFIG_TEGRA_PCI)			+= pcie.o
 
 obj-${CONFIG_MACH_HARMONY}              += board-harmony.o
 obj-${CONFIG_MACH_HARMONY}              += board-harmony-pinmux.o
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 3d06354..0de565c 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -27,6 +27,7 @@ void __init tegra_common_init(void);
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
 void __init tegra_init_clock(void);
+int __init tegra_pcie_init(bool init_port0, bool init_port1);
 
 extern struct sys_timer tegra_timer;
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/hardware.h b/arch/arm/mach-tegra/include/mach/hardware.h
index 6014edf..76f3478 100644
--- a/arch/arm/mach-tegra/include/mach/hardware.h
+++ b/arch/arm/mach-tegra/include/mach/hardware.h
@@ -21,4 +21,8 @@
 #ifndef __MACH_TEGRA_HARDWARE_H
 #define __MACH_TEGRA_HARDWARE_H
 
+#define PCIBIOS_MIN_IO			0
+#define PCIBIOS_MIN_MEM			0
+#define pcibios_assign_all_busses()	1
+
 #endif
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
new file mode 100644
index 0000000..54cc034
--- /dev/null
+++ b/arch/arm/mach-tegra/pcie.c
@@ -0,0 +1,889 @@
+/*
+ * arch/arm/mach-tegra/pci.c
+ *
+ * PCIe host controller driver for TEGRA(2) SOCs
+ *
+ * Copyright (c) 2010, CompuLab, Ltd.
+ * Author: Mike Rapoport <mike@compulab.co.il>
+ *
+ * Based on NVIDIA PCIe driver
+ * Copyright (c) 2008-2009, NVIDIA Corporation.
+ *
+ * Bits taken from arch/arm/mach-dove/pcie.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+
+#include <asm/sizes.h>
+#include <asm/mach/pci.h>
+
+#include <mach/pinmux.h>
+#include <mach/iomap.h>
+#include <mach/clk.h>
+
+/* register definitions */
+#define AFI_OFSET	0x3800
+#define PADS_OFSET	0x3000
+#define RP0_OFFSET	0x0000
+#define RP1_OFFSET	0x1000
+
+#define AFI_AXI_BAR0_SZ	0x00
+#define AFI_AXI_BAR1_SZ	0x04
+#define AFI_AXI_BAR2_SZ	0x08
+#define AFI_AXI_BAR3_SZ	0x0c
+#define AFI_AXI_BAR4_SZ	0x10
+#define AFI_AXI_BAR5_SZ	0x14
+
+#define AFI_AXI_BAR0_START	0x18
+#define AFI_AXI_BAR1_START	0x1c
+#define AFI_AXI_BAR2_START	0x20
+#define AFI_AXI_BAR3_START	0x24
+#define AFI_AXI_BAR4_START	0x28
+#define AFI_AXI_BAR5_START	0x2c
+
+#define AFI_FPCI_BAR0	0x30
+#define AFI_FPCI_BAR1	0x34
+#define AFI_FPCI_BAR2	0x38
+#define AFI_FPCI_BAR3	0x3c
+#define AFI_FPCI_BAR4	0x40
+#define AFI_FPCI_BAR5	0x44
+
+#define AFI_CACHE_BAR0_SZ	0x48
+#define AFI_CACHE_BAR0_ST	0x4c
+#define AFI_CACHE_BAR1_SZ	0x50
+#define AFI_CACHE_BAR1_ST	0x54
+
+#define AFI_MSI_BAR_SZ		0x60
+#define AFI_MSI_FPCI_BAR_ST	0x64
+#define AFI_MSI_AXI_BAR_ST	0x68
+
+#define AFI_CONFIGURATION		0xac
+#define  AFI_CONFIGURATION_EN_FPCI	(1 << 0)
+
+#define AFI_FPCI_ERROR_MASKS	0xb0
+
+#define AFI_INTR_MASK		0xb4
+#define  AFI_INTR_MASK_INT_MASK	(1 << 0)
+#define  AFI_INTR_MASK_MSI_MASK	(1 << 8)
+
+#define AFI_INTR_CODE		0xb8
+#define  AFI_INTR_CODE_MASK	0xf
+#define  AFI_INTR_MASTER_ABORT	4
+#define  AFI_INTR_LEGACY	6
+
+#define AFI_INTR_SIGNATURE	0xbc
+#define AFI_SM_INTR_ENABLE	0xc4
+
+#define AFI_AFI_INTR_ENABLE		0xc8
+#define  AFI_INTR_EN_INI_SLVERR		(1 << 0)
+#define  AFI_INTR_EN_INI_DECERR		(1 << 1)
+#define  AFI_INTR_EN_TGT_SLVERR		(1 << 2)
+#define  AFI_INTR_EN_TGT_DECERR		(1 << 3)
+#define  AFI_INTR_EN_TGT_WRERR		(1 << 4)
+#define  AFI_INTR_EN_DFPCI_DECERR	(1 << 5)
+#define  AFI_INTR_EN_AXI_DECERR		(1 << 6)
+#define  AFI_INTR_EN_FPCI_TIMEOUT	(1 << 7)
+
+#define AFI_PCIE_CONFIG					0x0f8
+#define  AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE		(1 << 1)
+#define  AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE		(1 << 2)
+#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK	(0xf << 20)
+#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE	(0x0 << 20)
+#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL	(0x1 << 20)
+
+#define AFI_FUSE			0x104
+#define  AFI_FUSE_PCIE_T0_GEN2_DIS	(1 << 2)
+
+#define AFI_PEX0_CTRL			0x110
+#define AFI_PEX1_CTRL			0x118
+#define  AFI_PEX_CTRL_RST		(1 << 0)
+#define  AFI_PEX_CTRL_REFCLK_EN		(1 << 3)
+
+#define RP_VEND_XP	0x00000F00
+#define  RP_VEND_XP_DL_UP	(1 << 30)
+
+#define RP_LINK_CONTROL_STATUS			0x00000090
+#define  RP_LINK_CONTROL_STATUS_LINKSTAT_MASK	0x3fff0000
+
+#define PADS_CTL_SEL		0x0000009C
+
+#define PADS_CTL		0x000000A0
+#define  PADS_CTL_IDDQ_1L	(1 << 0)
+#define  PADS_CTL_TX_DATA_EN_1L	(1 << 6)
+#define  PADS_CTL_RX_DATA_EN_1L	(1 << 10)
+
+#define PADS_PLL_CTL				0x000000B8
+#define  PADS_PLL_CTL_RST_B4SM			(1 << 1)
+#define  PADS_PLL_CTL_LOCKDET			(1 << 8)
+#define  PADS_PLL_CTL_REFCLK_MASK		(0x3 << 16)
+#define  PADS_PLL_CTL_REFCLK_INTERNAL_CML	(0 << 16)
+#define  PADS_PLL_CTL_REFCLK_INTERNAL_CMOS	(1 << 16)
+#define  PADS_PLL_CTL_REFCLK_EXTERNAL		(2 << 16)
+#define  PADS_PLL_CTL_TXCLKREF_MASK		(0x1 << 20)
+#define  PADS_PLL_CTL_TXCLKREF_DIV10		(0 << 20)
+#define  PADS_PLL_CTL_TXCLKREF_DIV5		(1 << 20)
+
+/* PMC access is required for PCIE xclk (un)clamping */
+#define PMC_SCRATCH42		0x144
+#define PMC_SCRATCH42_PCX_CLAMP	(1 << 0)
+
+static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+
+#define pmc_writel(value, reg) \
+	__raw_writel(value, (u32)reg_pmc_base + (reg))
+#define pmc_readl(reg) \
+	__raw_readl((u32)reg_pmc_base + (reg))
+
+/*
+ * Tegra2 defines 1GB in the AXI address map for PCIe.
+ *
+ * That address space is split into different regions, with sizes and
+ * offsets as follows:
+ *
+ * 0x80000000 - 0x80003fff - PCI controller registers
+ * 0x80004000 - 0x80103fff - PCI configuration space
+ * 0x80104000 - 0x80203fff - PCI extended configuration space
+ * 0x80203fff - 0x803fffff - unused
+ * 0x80400000 - 0x805fffff - downstream IO
+ * 0x80600000 - 0x8fffffff - unused
+ * 0x90000000 - 0x9fffffff - non-prefetchable memory
+ * 0xa0000000 - 0xbfffffff - prefetchable memory
+ */
+#define TEGRA_PCIE_BASE		0x80000000
+
+#define PCIE_REGS_SZ		SZ_16K
+#define PCIE_CFG_OFF		PCIE_REGS_SZ
+#define PCIE_CFG_SZ		SZ_1M
+#define PCIE_EXT_CFG_OFF	(PCIE_CFG_SZ + PCIE_CFG_OFF)
+#define PCIE_EXT_CFG_SZ		SZ_1M
+#define PCIE_IOMAP_SZ		(PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
+
+#define IO_BASE_0		(TEGRA_PCIE_BASE + SZ_4M)
+#define IO_SIZE_0		SZ_1M
+#define IO_BASE_1		(IO_BASE_0 + SZ_1M)
+#define IO_SIZE_1		SZ_1M
+#define MEM_BASE_0		(TEGRA_PCIE_BASE + SZ_256M)
+#define MEM_SIZE_0		SZ_128M
+#define MEM_BASE_1		(MEM_BASE_0 + MEM_SIZE_0)
+#define MEM_SIZE_1		SZ_128M
+#define PREFETCH_MEM_BASE_0	(MEM_BASE_1 + MEM_SIZE_1)
+#define PREFETCH_MEM_SIZE_0	SZ_128M
+#define PREFETCH_MEM_BASE_1	(PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0)
+#define PREFETCH_MEM_SIZE_1	SZ_128M
+
+#define  PCIE_CONF_BUS(b)	((b) << 16)
+#define  PCIE_CONF_DEV(d)	((d) << 11)
+#define  PCIE_CONF_FUNC(f)	((f) << 8)
+#define  PCIE_CONF_REG(r)	\
+	(((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))
+
+struct tegra_pcie_port {
+	int			index;
+	u8			root_bus_nr;
+	void __iomem		*base;
+
+	bool			link_up;
+
+	char			io_space_name[16];
+	char			mem_space_name[16];
+	char			prefetch_space_name[20];
+	struct resource		res[3];
+};
+
+struct tegra_pcie_info {
+	struct tegra_pcie_port	port[2];
+	int			num_ports;
+
+	void __iomem		*regs;
+
+	struct clk		*pex_clk;
+	struct clk		*afi_clk;
+	struct clk		*pcie_xclk;
+	struct clk		*pll_e;
+};
+
+static struct tegra_pcie_info tegra_pcie;
+
+static inline void afi_writel(u32 value, unsigned long offset)
+{
+	writel(value, offset + AFI_OFSET + tegra_pcie.regs);
+}
+
+static inline u32 afi_readl(unsigned long offset)
+{
+	return readl(offset + AFI_OFSET + tegra_pcie.regs);
+}
+
+static inline void pads_writel(u32 value, unsigned long offset)
+{
+	writel(value, offset + PADS_OFSET + tegra_pcie.regs);
+}
+
+static inline u32 pads_readl(unsigned long offset)
+{
+	return readl(offset + PADS_OFSET + tegra_pcie.regs);
+}
+
+static struct tegra_pcie_port *bus_to_port(int bus)
+{
+	int i;
+
+	for (i = tegra_pcie.num_ports - 1; i >= 0; i--) {
+		int rbus = tegra_pcie.port[i].root_bus_nr;
+		if (rbus != -1 && rbus == bus)
+			break;
+	}
+
+	return i >= 0 ? tegra_pcie.port + i : NULL;
+}
+
+static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
+				int where, int size, u32 *val)
+{
+	struct tegra_pcie_port *pp = bus_to_port(bus->number);
+	void __iomem *addr;
+
+	if (pp) {
+		if (devfn != 0) {
+			*val = 0xffffffff;
+			return PCIBIOS_DEVICE_NOT_FOUND;
+		}
+
+		addr = pp->base + (where & ~0x3);
+	} else {
+		addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
+					  PCIE_CONF_DEV(PCI_SLOT(devfn)) +
+					  PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
+					  PCIE_CONF_REG(where));
+	}
+
+	*val = readl(addr);
+
+	if (size == 1)
+		*val = (*val >> (8 * (where & 3))) & 0xff;
+	else if (size == 2)
+		*val = (*val >> (8 * (where & 3))) & 0xffff;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
+				 int where, int size, u32 val)
+{
+	struct tegra_pcie_port *pp = bus_to_port(bus->number);
+	void __iomem *addr;
+
+	u32 mask;
+	u32 tmp;
+
+	if (pp) {
+		if (devfn != 0)
+			return PCIBIOS_DEVICE_NOT_FOUND;
+
+		addr = pp->base + (where & ~0x3);
+	} else {
+		addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
+					  PCIE_CONF_DEV(PCI_SLOT(devfn)) +
+					  PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
+					  PCIE_CONF_REG(where));
+	}
+
+	if (size == 4) {
+		writel(val, addr);
+		return PCIBIOS_SUCCESSFUL;
+	}
+
+	if (size == 2)
+		mask = ~(0xffff << ((where & 0x3) * 8));
+	else if (size == 1)
+		mask = ~(0xff << ((where & 0x3) * 8));
+	else
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	tmp = readl(addr) & mask;
+	tmp |= val << ((where & 0x3) * 8);
+	writel(tmp, addr);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops tegra_pcie_ops = {
+	.read	= tegra_pcie_read_conf,
+	.write	= tegra_pcie_write_conf,
+};
+
+static void __devinit tegra_pcie_fixup_bridge(struct pci_dev *dev)
+{
+	u16 reg;
+
+	if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
+		pci_read_config_word(dev, PCI_COMMAND, &reg);
+		reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+			PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
+		pci_write_config_word(dev, PCI_COMMAND, reg);
+	}
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge);
+
+/* Tegra PCIE root complex wrongly reports device class */
+static void __devinit tegra_pcie_fixup_class(struct pci_dev *dev)
+{
+	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
+
+/* Tegra PCIE requires relaxed ordering */
+static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev)
+{
+	u16 val16;
+	int pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
+
+	if (pos <= 0) {
+		dev_err(&dev->dev, "skipping relaxed ordering fixup\n");
+		return;
+	}
+
+	pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16);
+	val16 |= PCI_EXP_DEVCTL_RELAX_EN;
+	pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
+
+static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+	struct tegra_pcie_port *pp;
+
+	if (nr >= tegra_pcie.num_ports)
+		return 0;
+
+	pp = tegra_pcie.port + nr;
+	pp->root_bus_nr = sys->busnr;
+
+	/*
+	 * IORESOURCE_IO
+	 */
+	snprintf(pp->io_space_name, sizeof(pp->io_space_name),
+		 "PCIe %d I/O", pp->index);
+	pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
+	pp->res[0].name = pp->io_space_name;
+	if (pp->index == 0) {
+		pp->res[0].start = IO_BASE_0;
+		pp->res[0].end = pp->res[0].start + IO_SIZE_0 - 1;
+	} else {
+		pp->res[0].start = IO_BASE_1;
+		pp->res[0].end = pp->res[0].start + IO_SIZE_1 - 1;
+	}
+	pp->res[0].flags = IORESOURCE_IO;
+	if (request_resource(&ioport_resource, &pp->res[0]))
+		panic("Request PCIe IO resource failed\n");
+	sys->resource[0] = &pp->res[0];
+	sys->io_offset  = pp->res[nr].start;
+
+	/*
+	 * IORESOURCE_MEM
+	 */
+	snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
+		 "PCIe %d MEM", pp->index);
+	pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
+	pp->res[1].name = pp->mem_space_name;
+	if (pp->index == 0) {
+		pp->res[1].start = MEM_BASE_0;
+		pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1;
+	} else {
+		pp->res[1].start = MEM_BASE_1;
+		pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1;
+	}
+	pp->res[1].flags = IORESOURCE_MEM;
+	if (request_resource(&iomem_resource, &pp->res[1]))
+		panic("Request PCIe Memory resource failed\n");
+	sys->resource[1] = &pp->res[1];
+
+	/*
+	 * IORESOURCE_MEM | IORESOURCE_PREFETCH
+	 */
+	snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
+		 "PCIe %d PREFETCH MEM", pp->index);
+	pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
+	pp->res[2].name = pp->prefetch_space_name;
+	if (pp->index == 0) {
+		pp->res[2].start = PREFETCH_MEM_BASE_0;
+		pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1;
+	} else {
+		pp->res[2].start = PREFETCH_MEM_BASE_1;
+		pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1;
+	}
+	pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+	if (request_resource(&iomem_resource, &pp->res[2]))
+		panic("Request PCIe Prefetch Memory resource failed\n");
+	sys->resource[2] = &pp->res[2];
+
+	return 1;
+}
+
+static int tegra_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+	return INT_PCIE_INTR;
+}
+
+static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
+						  struct pci_sys_data *sys)
+{
+	struct tegra_pcie_port *pp;
+
+	if (nr >= tegra_pcie.num_ports)
+		return 0;
+
+	pp = tegra_pcie.port + nr;
+	pp->root_bus_nr = sys->busnr;
+
+	return pci_scan_bus(sys->busnr, &tegra_pcie_ops, sys);
+}
+
+static struct hw_pci tegra_pcie_hw __initdata = {
+	.nr_controllers	= 2,
+	.setup		= tegra_pcie_setup,
+	.scan		= tegra_pcie_scan_bus,
+	.swizzle	= pci_std_swizzle,
+	.map_irq	= tegra_pcie_map_irq,
+};
+
+
+static irqreturn_t tegra_pcie_isr(int irq, void *arg)
+{
+	const char *err_msg[] = {
+		"Unknown",
+		"AXI slave error",
+		"AXI decode error",
+		"Target abort",
+		"Master abort",
+		"Invalid write",
+		"Response decoding error",
+		"AXI response decoding error",
+		"Transcation timeout",
+	};
+
+	u32 code, signature;
+
+	code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
+	signature = afi_readl(AFI_INTR_SIGNATURE);
+	afi_writel(0, AFI_INTR_CODE);
+
+	if (code == AFI_INTR_LEGACY)
+		return IRQ_NONE;
+
+	if (code >= ARRAY_SIZE(err_msg))
+		code = 0;
+
+	/*
+	 * do not pollute kernel log with master abort reports since they
+	 * happen a lot during enumeration
+	 */
+	if (code == AFI_INTR_MASTER_ABORT)
+		pr_debug("PCI: %s, signature: %08x\n", err_msg[code], signature);
+	else
+		pr_err("PCI: %s, signature: %08x\n", err_msg[code], signature);
+
+	return IRQ_HANDLED;
+}
+
+static void tegra_pcie_setup_translations(void)
+{
+	u32 fpci_bar;
+	u32 size;
+	u32 axi_address;
+
+	/* Bar 0: config Bar */
+	fpci_bar = ((u32)0xfdff << 16);
+	size = PCIE_CFG_SZ;
+	axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF;
+	afi_writel(axi_address, AFI_AXI_BAR0_START);
+	afi_writel(size >> 12, AFI_AXI_BAR0_SZ);
+	afi_writel(fpci_bar, AFI_FPCI_BAR0);
+
+	/* Bar 1: extended config Bar */
+	fpci_bar = ((u32)0xfe1 << 20);
+	size = PCIE_EXT_CFG_SZ;
+	axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF;
+	afi_writel(axi_address, AFI_AXI_BAR1_START);
+	afi_writel(size >> 12, AFI_AXI_BAR1_SZ);
+	afi_writel(fpci_bar, AFI_FPCI_BAR1);
+
+	/* Bar 2: downstream IO bar */
+	fpci_bar = ((__u32)0xfdfc << 16);
+	size = IO_SIZE_0 + IO_SIZE_1;
+	axi_address = IO_BASE_0;
+	afi_writel(axi_address, AFI_AXI_BAR2_START);
+	afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
+	afi_writel(fpci_bar, AFI_FPCI_BAR2);
+
+	/* Bar 3: prefetchable memory BAR */
+	fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1;
+	size =  PREFETCH_MEM_SIZE_0 +  PREFETCH_MEM_SIZE_1;
+	axi_address = PREFETCH_MEM_BASE_0;
+	afi_writel(axi_address, AFI_AXI_BAR3_START);
+	afi_writel(size >> 12, AFI_AXI_BAR3_SZ);
+	afi_writel(fpci_bar, AFI_FPCI_BAR3);
+
+	/* Bar 4: non prefetchable memory BAR */
+	fpci_bar = (((MEM_BASE_0 >> 12)	& 0x0FFFFFFF) << 4) | 0x1;
+	size = MEM_SIZE_0 + MEM_SIZE_1;
+	axi_address = MEM_BASE_0;
+	afi_writel(axi_address, AFI_AXI_BAR4_START);
+	afi_writel(size >> 12, AFI_AXI_BAR4_SZ);
+	afi_writel(fpci_bar, AFI_FPCI_BAR4);
+
+	/* Bar 5: NULL out the remaining BAR as it is not used */
+	fpci_bar = 0;
+	size = 0;
+	axi_address = 0;
+	afi_writel(axi_address, AFI_AXI_BAR5_START);
+	afi_writel(size >> 12, AFI_AXI_BAR5_SZ);
+	afi_writel(fpci_bar, AFI_FPCI_BAR5);
+
+	/* map all upstream transactions as uncached */
+	afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST);
+	afi_writel(0, AFI_CACHE_BAR0_SZ);
+	afi_writel(0, AFI_CACHE_BAR1_ST);
+	afi_writel(0, AFI_CACHE_BAR1_SZ);
+
+	/* No MSI */
+	afi_writel(0, AFI_MSI_FPCI_BAR_ST);
+	afi_writel(0, AFI_MSI_BAR_SZ);
+	afi_writel(0, AFI_MSI_AXI_BAR_ST);
+	afi_writel(0, AFI_MSI_BAR_SZ);
+}
+
+static void tegra_pcie_enable_controller(void)
+{
+	u32 val, reg;
+	int i;
+
+	/* Enable slot clock and pulse the reset signals */
+	for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
+		val = afi_readl(reg) |  AFI_PEX_CTRL_REFCLK_EN;
+		afi_writel(val, reg);
+		val &= ~AFI_PEX_CTRL_RST;
+		afi_writel(val, reg);
+
+		val = afi_readl(reg) | AFI_PEX_CTRL_RST;
+		afi_writel(val, reg);
+	}
+
+	/* Enable dual controller and both ports */
+	val = afi_readl(AFI_PCIE_CONFIG);
+	val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE |
+		 AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE |
+		 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK);
+	val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
+	afi_writel(val, AFI_PCIE_CONFIG);
+
+	val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS;
+	afi_writel(val, AFI_FUSE);
+
+	/* Initialze internal PHY, enable up to 16 PCIE lanes */
+	pads_writel(0x0, PADS_CTL_SEL);
+
+	/* override IDDQ to 1 on all 4 lanes */
+	val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L;
+	pads_writel(val, PADS_CTL);
+
+	/*
+	 * set up PHY PLL inputs select PLLE output as refclock,
+	 * set TX ref sel to div10 (not div5)
+	 */
+	val = pads_readl(PADS_PLL_CTL);
+	val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
+	val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10);
+	pads_writel(val, PADS_PLL_CTL);
+
+	/* take PLL out of reset  */
+	val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
+	pads_writel(val, PADS_PLL_CTL);
+
+	/*
+	 * Hack, set the clock voltage to the DEFAULT provided by hw folks.
+	 * This doesn't exist in the documentation
+	 */
+	pads_writel(0xfa5cfa5c, 0xc8);
+
+	/* Wait for the PLL to lock */
+	do {
+		val = pads_readl(PADS_PLL_CTL);
+	} while (!(val & PADS_PLL_CTL_LOCKDET));
+
+	/* turn off IDDQ override */
+	val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L;
+	pads_writel(val, PADS_CTL);
+
+	/* enable TX/RX data */
+	val = pads_readl(PADS_CTL);
+	val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
+	pads_writel(val, PADS_CTL);
+
+	/* Take the PCIe interface module out of reset */
+	tegra_periph_reset_deassert(tegra_pcie.pcie_xclk);
+
+	/* Finally enable PCIe */
+	val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI;
+	afi_writel(val, AFI_CONFIGURATION);
+
+	val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
+	       AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
+	       AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR);
+	afi_writel(val, AFI_AFI_INTR_ENABLE);
+	afi_writel(0xffffffff, AFI_SM_INTR_ENABLE);
+
+	/* FIXME: No MSI for now, only INT */
+	afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
+
+	/* Disable all execptions */
+	afi_writel(0, AFI_FPCI_ERROR_MASKS);
+
+	return;
+}
+
+static void tegra_pcie_xclk_clamp(bool clamp)
+{
+	u32 reg;
+
+	reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
+
+	if (clamp)
+		reg |= PMC_SCRATCH42_PCX_CLAMP;
+
+	pmc_writel(reg, PMC_SCRATCH42);
+}
+
+static int tegra_pcie_power_on(void)
+{
+	int err;
+
+	tegra_pcie_xclk_clamp(true);
+	tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
+	tegra_pcie_xclk_clamp(false);
+
+	clk_enable(tegra_pcie.afi_clk);
+	clk_enable(tegra_pcie.pex_clk);
+	return clk_enable(tegra_pcie.pll_e);
+}
+
+static void tegra_pcie_power_off(void)
+{
+	tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
+	tegra_periph_reset_assert(tegra_pcie.afi_clk);
+	tegra_periph_reset_assert(tegra_pcie.pex_clk);
+
+	tegra_pcie_xclk_clamp(true);
+}
+
+static int tegra_pcie_clocks_get(void)
+{
+	int err;
+
+	tegra_pcie.pex_clk = clk_get_sys(NULL, "pex");
+	if (IS_ERR(tegra_pcie.pex_clk))
+		return PTR_ERR(tegra_pcie.pex_clk);
+
+	tegra_pcie.afi_clk = clk_get_sys(NULL, "afi");
+	if (IS_ERR(tegra_pcie.afi_clk)) {
+		err = PTR_ERR(tegra_pcie.afi_clk);
+		goto err_afi_clk;
+	}
+
+	tegra_pcie.pcie_xclk = clk_get_sys(NULL, "pcie_xclk");
+	if (IS_ERR(tegra_pcie.pcie_xclk)) {
+		err =  PTR_ERR(tegra_pcie.pcie_xclk);
+		goto err_pcie_xclk;
+	}
+
+	tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e");
+	if (IS_ERR(tegra_pcie.pll_e)) {
+		err = PTR_ERR(tegra_pcie.pll_e);
+		goto err_pll_e;
+	}
+
+	return 0;
+
+err_pll_e:
+	clk_put(tegra_pcie.pcie_xclk);
+err_pcie_xclk:
+	clk_put(tegra_pcie.afi_clk);
+err_afi_clk:
+	clk_put(tegra_pcie.pex_clk);
+
+	return err;
+}
+
+static void tegra_pcie_clocks_put(void)
+{
+	clk_put(tegra_pcie.pll_e);
+	clk_put(tegra_pcie.pcie_xclk);
+	clk_put(tegra_pcie.afi_clk);
+	clk_put(tegra_pcie.pex_clk);
+}
+
+static int __init tegra_pcie_get_resources(void)
+{
+	int err;
+
+	err = tegra_pcie_clocks_get();
+	if (err) {
+		pr_err("%s: tegra_pcie_clocks_get: %d\n", __func__, err);
+		return err;
+	}
+
+	err = tegra_pcie_power_on();
+	if (err) {
+		pr_err("%s: tegra_pcie_power_on: %d\n", __func__, err);
+		goto err_pwr_on;
+	}
+
+	tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ);
+	if (tegra_pcie.regs == NULL) {
+		pr_err("tegra_pcie_setup: Failed to map the PCI/AFI regs\n");
+		goto err_reg_map;
+	}
+
+	err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
+			  IRQF_SHARED, "PCIE", &tegra_pcie);
+	if (err) {
+		pr_err("tegra_pcie_setup: Cannot register the IRQ\n");
+		goto err_irq;
+	}
+	set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
+
+	return 0;
+
+err_irq:
+	iounmap(tegra_pcie.regs);
+err_reg_map:
+	tegra_pcie_power_off();
+err_pwr_on:
+	tegra_pcie_clocks_put();
+
+	return err;
+}
+
+/*
+ * FIXME: If there are no PCIe cards attached, then calling this function
+ * can result in the increase of the bootup time as there are big timeout
+ * loops.
+ */
+#define TEGRA_PCIE_LINKUP_TIMEOUT	200	/* up to 1.2 seconds */
+static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
+				  u32 reset_reg)
+{
+	u32 reg;
+	int retries = 3;
+	int timeout;
+
+	do {
+		timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
+		while (timeout) {
+			reg = readl(pp->base + RP_VEND_XP);
+
+			if (reg & RP_VEND_XP_DL_UP)
+				break;
+
+			mdelay(1);
+			timeout--;
+		}
+
+		if (!timeout)  {
+			pr_err("PCIE: port %d: link down, retrying\n", idx);
+			goto retry;
+		}
+
+		timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
+		while (timeout) {
+			reg = readl(pp->base + RP_LINK_CONTROL_STATUS);
+
+			if (reg & 0x20000000)
+				return true;
+
+			mdelay(1);
+			timeout--;
+		}
+
+retry:
+		/* Pulse the PEX reset */
+		reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
+		afi_writel(reg, reset_reg);
+		mdelay(1);
+		reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
+		afi_writel(reg, reset_reg);
+
+		retries--;
+	} while (retries);
+
+	return false;
+}
+
+static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
+{
+	struct tegra_pcie_port *pp;
+
+	pp = tegra_pcie.port + tegra_pcie.num_ports;
+
+	pp->index = -1;
+	pp->base = tegra_pcie.regs + offset;
+	pp->link_up = tegra_pcie_check_link(pp, index, reset_reg);
+
+	if (!pp->link_up) {
+		pp->base = NULL;
+		printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index);
+		return;
+	}
+
+	tegra_pcie.num_ports++;
+	pp->index = index;
+	pp->root_bus_nr = -1;
+	memset(pp->res, 0, sizeof(pp->res));
+}
+
+int __init tegra_pcie_init(bool init_port0, bool init_port1)
+{
+	int err;
+
+	if (!(init_port0 || init_port1))
+		return -ENODEV;
+
+	err = tegra_pcie_get_resources();
+	if (err)
+		return err;
+
+	tegra_pcie_enable_controller();
+
+	/* setup the AFI address translations */
+	tegra_pcie_setup_translations();
+
+	if (init_port0)
+		tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL);
+
+	if (init_port1)
+		tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL);
+
+	pci_common_init(&tegra_pcie_hw);
+
+	return 0;
+}
-- 
1.6.6.2

[PATCH 3/3] [ARM] tegra: harmony: enable PCI Express

[Mike Rapoport]

Signed-off-by: Mike Rapoport <mike@compulab.co.il>
---
 arch/arm/mach-tegra/Makefile             |    1 +
 arch/arm/mach-tegra/board-harmony-pcie.c |   52 ++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/board-harmony-pcie.c

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 23c9600..60f73c7 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_TEGRA_PCI)			+= pcie.o
 
 obj-${CONFIG_MACH_HARMONY}              += board-harmony.o
 obj-${CONFIG_MACH_HARMONY}              += board-harmony-pinmux.o
+obj-${CONFIG_MACH_HARMONY}              += board-harmony-pcie.o
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
new file mode 100644
index 0000000..824c0a1
--- /dev/null
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -0,0 +1,52 @@
+/*
+ * arch/arm/mach-tegra/board-harmony-pcie.c
+ *
+ * Copyright (C) 2010 CompuLab, Ltd.
+ * Mike Rapoport <mike@compulab.co.il>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/pinmux.h>
+#include "board.h"
+
+#ifdef CONFIG_TEGRA_PCI
+
+static int __init harmony_pcie_init(void)
+{
+	int err;
+
+	tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_NORMAL);
+	tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_NORMAL);
+	tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_NORMAL);
+
+	err = tegra_pcie_init(true, true);
+	if (err)
+		goto err_pcie;
+
+	return 0;
+
+err_pcie:
+	tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_TRISTATE);
+	tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_TRISTATE);
+	tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_TRISTATE);
+
+	return err;
+}
+
+subsys_initcall(harmony_pcie_init);
+
+#endif
-- 
1.6.6.2

[PATCH 0/3] [ARM] tegra: PCI Express support

[Arnd Bergmann]

On Thursday 16 September 2010 18:53:33 Mike Rapoport wrote:
> These patches enable PCI Express support on Tegra2.
> The implementation is based on original NVidia code from (1), but it
> is heavily reworked to avoid custom PCI enumeration and make the code
> more Linux friendly.
> 
> This implementation assumes that the PCIe subsystem is fully powered
> and ungated by the bootloader.

The patches look good to me, but it seems that I/O space accesses are
still broken and need to be redirected to the PCI I/O range, like
the (totally untested) patch below.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
index 35edfc3..d54e384 100644
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -21,7 +21,8 @@
 #ifndef __MACH_TEGRA_IO_H
 #define __MACH_TEGRA_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
+/* Two 1MB windows */
+#define IO_SPACE_LIMIT (SZ_1M + SZ_1M - 1)
 
 /* On TEGRA, many peripherals are very closely packed in
  * two 256MB io windows (that actually only use about 64KB
@@ -69,7 +70,7 @@ void tegra_iounmap(volatile void __iomem *addr);
 
 static inline void __iomem *__io(unsigned long addr)
 {
-	return (void __iomem *)addr;
+	return addr + tegra_pcie.regs + SZ_4M;
 }
 #define __io(a)         __io(a)
 #define __mem_pci(a)    (a)

[PATCH 1/3] [ARM] tegra: add PCI Express clocks

[Colin Cross]

On Thu, Sep 16, 2010 at 9:53 AM, Mike Rapoport <mike@compulab.co.il> wrote:
> Signed-off-by: Mike Rapoport <mike@compulab.co.il>
> ---
> ?arch/arm/mach-tegra/tegra2_clocks.c | ? 76 +++++++++++++++++++++++++++++++++-
> ?1 files changed, 73 insertions(+), 3 deletions(-)

<snip>

> -static int tegra2_pll_clk_wait_for_lock(struct clk *c)
> +static int tegra2_pll_clk_wait_for_bit_set(struct clk *c, int bit)
> ?{
> ? ? ? ?ktime_t before;
>
> ? ? ? ?before = ktime_get();
> - ? ? ? while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) {
> + ? ? ? while (!(clk_readl(c->reg + PLL_BASE) & bit)) {
> ? ? ? ? ? ? ? ?if (ktime_us_delta(ktime_get(), before) > 5000) {
> ? ? ? ? ? ? ? ? ? ? ? ?pr_err("Timed out waiting for lock bit on pll %s",
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?c->name);
> @@ -414,7 +416,7 @@ static int tegra2_pll_clk_enable(struct clk *c)
> ? ? ? ?val |= PLL_MISC_LOCK_ENABLE;
> ? ? ? ?clk_writel(val, c->reg + PLL_MISC(c));
>
> - ? ? ? tegra2_pll_clk_wait_for_lock(c);
> + ? ? ? tegra2_pll_clk_wait_for_bit_set(c, PLL_BASE_LOCK);
>
> ? ? ? ?return 0;
> ?}

I've been told by Nvidia that the pll lock bits are not reliable, and
will be removing uses of tegra2_pll_clk_wait_for_lock and replacing
them with delays selected by each pll.  Can you confirm with Nvidia
that PLLE_MISC_READY works?

<snip>

> +static struct clk_ops tegra_pcie_clk_ops = {
> + ? ? ? .enable ? ? = tegra2_periph_clk_enable,
> + ? ? ? .disable ? ?= tegra2_periph_clk_disable,
> +};
Why is this needed?  Won't the regular periph ops work?

<snip>

> +static struct clk tegra_clk_pex = {
> + ? ? ? .name ? ? ?= "pex",
> + ? ? ? .flags ? ? = PERIPH_MANUAL_RESET,
> + ? ? ? .ops ? ? ? = &tegra_pcie_clk_ops,
> + ? ? ? .clk_num ? = 70,
> +};
> +
> +static struct clk tegra_clk_afi = {
> + ? ? ? .name ? ? ?= "afi",
> + ? ? ? .flags ? ? = PERIPH_MANUAL_RESET,
> + ? ? ? .ops ? ? ? = &tegra_pcie_clk_ops,
> + ? ? ? .clk_num ? = 72,
> +};
> +
> +/* the pcie_xclk is required for reset of PCIE subsystem */
> +static struct clk tegra_clk_pcie_xclk = {
> + ? ? ? .name ? ? ?= "pcie_xclk",
> + ? ? ? .clk_num ? = 74,
> +};
These should probably all be defined in the CLK_PERIPH table.

[PATCH 2/3] [ARM] tegra: add PCI Express support

[Colin Cross]

On Thu, Sep 16, 2010 at 9:53 AM, Mike Rapoport <mike@compulab.co.il> wrote:
> Signed-off-by: Mike Rapoport <mike@compulab.co.il>
> ---
> ?arch/arm/mach-tegra/Kconfig ? ? ? ? ? ? ? ? | ? ?4 +
> ?arch/arm/mach-tegra/Makefile ? ? ? ? ? ? ? ?| ? ?1 +
> ?arch/arm/mach-tegra/board.h ? ? ? ? ? ? ? ? | ? ?1 +
> ?arch/arm/mach-tegra/include/mach/hardware.h | ? ?4 +
> ?arch/arm/mach-tegra/pcie.c ? ? ? ? ? ? ? ? ?| ?889 +++++++++++++++++++++++++++
> ?5 files changed, 899 insertions(+), 0 deletions(-)
> ?create mode 100644 arch/arm/mach-tegra/pcie.c
>
<snip>

> +/* register definitions */
> +#define AFI_OFSET ? ? ?0x3800
> +#define PADS_OFSET ? ? 0x3000
OFFSET

> +#define RP0_OFFSET ? ? 0x0000
> +#define RP1_OFFSET ? ? 0x1000

<snip>

> +static void tegra_pcie_xclk_clamp(bool clamp)
> +{
> + ? ? ? u32 reg;
> +
> + ? ? ? reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
> +
> + ? ? ? if (clamp)
> + ? ? ? ? ? ? ? reg |= PMC_SCRATCH42_PCX_CLAMP;
> +
> + ? ? ? pmc_writel(reg, PMC_SCRATCH42);
> +}

Maybe add this to mach-tegra/powergate.c, to avoid having to set PMC
registers directly?

> +static int tegra_pcie_power_on(void)
> +{
> + ? ? ? int err;
> +
> + ? ? ? tegra_pcie_xclk_clamp(true);
> + ? ? ? tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
> + ? ? ? tegra_pcie_xclk_clamp(false);
> +
> + ? ? ? clk_enable(tegra_pcie.afi_clk);
> + ? ? ? clk_enable(tegra_pcie.pex_clk);
> + ? ? ? return clk_enable(tegra_pcie.pll_e);
> +}
Any reason you can't use the powergate api here too?

> +static void tegra_pcie_power_off(void)
> +{
> + ? ? ? tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
> + ? ? ? tegra_periph_reset_assert(tegra_pcie.afi_clk);
> + ? ? ? tegra_periph_reset_assert(tegra_pcie.pex_clk);
> +
> + ? ? ? tegra_pcie_xclk_clamp(true);
> +}
Can you power off the pcie partition?

[PATCH 3/3] [ARM] tegra: harmony: enable PCI Express

[Colin Cross]

On Thu, Sep 16, 2010 at 9:53 AM, Mike Rapoport <mike@compulab.co.il> wrote:
> Signed-off-by: Mike Rapoport <mike@compulab.co.il>
> ---
> ?arch/arm/mach-tegra/Makefile ? ? ? ? ? ? | ? ?1 +
> ?arch/arm/mach-tegra/board-harmony-pcie.c | ? 52 ++++++++++++++++++++++++++++++
> ?2 files changed, 53 insertions(+), 0 deletions(-)
> ?create mode 100644 arch/arm/mach-tegra/board-harmony-pcie.c
>
> diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
> new file mode 100644
> index 0000000..824c0a1
> --- /dev/null
> +++ b/arch/arm/mach-tegra/board-harmony-pcie.c

<snip>

> +static int __init harmony_pcie_init(void)
> +{
> + ? ? ? int err;
> +
> + ? ? ? tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_NORMAL);
> + ? ? ? tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_NORMAL);
> + ? ? ? tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_NORMAL);
Can these go in the main harmony pinmux table?

[PATCH 3/3] [ARM] tegra: harmony: enable PCI Express

[Mike Rapoport]

On Thu, Sep 16, 2010 at 11:44 PM, Colin Cross <ccross@google.com> wrote:
> On Thu, Sep 16, 2010 at 9:53 AM, Mike Rapoport <mike@compulab.co.il> wrote:
>> Signed-off-by: Mike Rapoport <mike@compulab.co.il>
>> ---
>> ?arch/arm/mach-tegra/Makefile ? ? ? ? ? ? | ? ?1 +
>> ?arch/arm/mach-tegra/board-harmony-pcie.c | ? 52 ++++++++++++++++++++++++++++++
>> ?2 files changed, 53 insertions(+), 0 deletions(-)
>> ?create mode 100644 arch/arm/mach-tegra/board-harmony-pcie.c
>>
>> diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
>> new file mode 100644
>> index 0000000..824c0a1
>> --- /dev/null
>> +++ b/arch/arm/mach-tegra/board-harmony-pcie.c
>
> <snip>
>
>> +static int __init harmony_pcie_init(void)
>> +{
>> + ? ? ? int err;
>> +
>> + ? ? ? tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_NORMAL);
>> + ? ? ? tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_NORMAL);
>> + ? ? ? tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_NORMAL);
> Can these go in the main harmony pinmux table?

The idea is to keep the pins in tristate unless PCIe is enabled explicitly.

> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
? ? Sincerely Yours,
? ? ? ? Mike.

[PATCH 2/3] [ARM] tegra: add PCI Express support

[Mike Rapoport]

On Thu, Sep 16, 2010 at 11:42 PM, Colin Cross <ccross@google.com> wrote:
> On Thu, Sep 16, 2010 at 9:53 AM, Mike Rapoport <mike@compulab.co.il> wrote:
>> Signed-off-by: Mike Rapoport <mike@compulab.co.il>
>> ---
>> ?arch/arm/mach-tegra/Kconfig ? ? ? ? ? ? ? ? | ? ?4 +
>> ?arch/arm/mach-tegra/Makefile ? ? ? ? ? ? ? ?| ? ?1 +
>> ?arch/arm/mach-tegra/board.h ? ? ? ? ? ? ? ? | ? ?1 +
>> ?arch/arm/mach-tegra/include/mach/hardware.h | ? ?4 +
>> ?arch/arm/mach-tegra/pcie.c ? ? ? ? ? ? ? ? ?| ?889 +++++++++++++++++++++++++++
>> ?5 files changed, 899 insertions(+), 0 deletions(-)
>> ?create mode 100644 arch/arm/mach-tegra/pcie.c
>>
> <snip>
>
>> +/* register definitions */
>> +#define AFI_OFSET ? ? ?0x3800
>> +#define PADS_OFSET ? ? 0x3000
> OFFSET

thanks, will fix

>> +#define RP0_OFFSET ? ? 0x0000
>> +#define RP1_OFFSET ? ? 0x1000
>
> <snip>
>
>> +static void tegra_pcie_xclk_clamp(bool clamp)
>> +{
>> + ? ? ? u32 reg;
>> +
>> + ? ? ? reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
>> +
>> + ? ? ? if (clamp)
>> + ? ? ? ? ? ? ? reg |= PMC_SCRATCH42_PCX_CLAMP;
>> +
>> + ? ? ? pmc_writel(reg, PMC_SCRATCH42);
>> +}
>
> Maybe add this to mach-tegra/powergate.c, to avoid having to set PMC
> registers directly?

The patch is aginst Linus' tree, that does not have powergate yet. I'd
really like to see the PCIe in 2.6.37-rc1, so I would prefer not to
depend on powergate here.
Besides, this particular bit is PCIe specific and does not fit into
generic power gating framework.
As a side note, mach-tegra/irq.c and mach-tegra/suspend*.c also have
direct access to the PMC, so probably it's worth adding
mach-tegra/pmc.h with pmc_writel/pmc_readl definitions?

>> +static int tegra_pcie_power_on(void)
>> +{
>> + ? ? ? int err;
>> +
>> + ? ? ? tegra_pcie_xclk_clamp(true);
>> + ? ? ? tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
>> + ? ? ? tegra_pcie_xclk_clamp(false);
>> +
>> + ? ? ? clk_enable(tegra_pcie.afi_clk);
>> + ? ? ? clk_enable(tegra_pcie.pex_clk);
>> + ? ? ? return clk_enable(tegra_pcie.pll_e);
>> +}
> Any reason you can't use the powergate api here too?

I cannot use the powergate api instead of what I have now, but it
won't be a problem to add it on top of current implementation.
The PCIe subsystem uses too many clocks, which leads to necessity to
have combine powergate api with direct calls to clk_{en,dis}able and
tegra_periph_reset_{de}assert.

>> +static void tegra_pcie_power_off(void)
>> +{
>> + ? ? ? tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
>> + ? ? ? tegra_periph_reset_assert(tegra_pcie.afi_clk);
>> + ? ? ? tegra_periph_reset_assert(tegra_pcie.pex_clk);
>> +
>> + ? ? ? tegra_pcie_xclk_clamp(true);
>> +}
> Can you power off the pcie partition?

Yes, but again, I prefer not to depend on powergate api. The power
gating can be easily added afterwads.

>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
? ? Sincerely Yours,
? ? ? ? Mike.

[PATCH 1/3] [ARM] tegra: add PCI Express clocks

[Mike Rapoport]

On Thu, Sep 16, 2010 at 11:27 PM, Colin Cross <ccross@google.com> wrote:
> On Thu, Sep 16, 2010 at 9:53 AM, Mike Rapoport <mike@compulab.co.il> wrote:
>> Signed-off-by: Mike Rapoport <mike@compulab.co.il>
>> ---
>> ?arch/arm/mach-tegra/tegra2_clocks.c | ? 76 +++++++++++++++++++++++++++++++++-
>> ?1 files changed, 73 insertions(+), 3 deletions(-)
>
> <snip>
>
>> -static int tegra2_pll_clk_wait_for_lock(struct clk *c)
>> +static int tegra2_pll_clk_wait_for_bit_set(struct clk *c, int bit)
>> ?{
>> ? ? ? ?ktime_t before;
>>
>> ? ? ? ?before = ktime_get();
>> - ? ? ? while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) {
>> + ? ? ? while (!(clk_readl(c->reg + PLL_BASE) & bit)) {
>> ? ? ? ? ? ? ? ?if (ktime_us_delta(ktime_get(), before) > 5000) {
>> ? ? ? ? ? ? ? ? ? ? ? ?pr_err("Timed out waiting for lock bit on pll %s",
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?c->name);
>> @@ -414,7 +416,7 @@ static int tegra2_pll_clk_enable(struct clk *c)
>> ? ? ? ?val |= PLL_MISC_LOCK_ENABLE;
>> ? ? ? ?clk_writel(val, c->reg + PLL_MISC(c));
>>
>> - ? ? ? tegra2_pll_clk_wait_for_lock(c);
>> + ? ? ? tegra2_pll_clk_wait_for_bit_set(c, PLL_BASE_LOCK);
>>
>> ? ? ? ?return 0;
>> ?}
>
> I've been told by Nvidia that the pll lock bits are not reliable, and
> will be removing uses of tegra2_pll_clk_wait_for_lock and replacing
> them with delays selected by each pll. ?Can you confirm with Nvidia
> that PLLE_MISC_READY works?

I'll try to get a confirmation from NVidia....

[PATCH 1/3] [ARM] tegra: add PCI Express clocks

[Mogambo Park]

Good evening Mike Rapport,

 Are there is some datasheet/TRM availability for Nvidia Tegra chip ?
Please say me if yes and where.

thanks

On Fri, Sep 17, 2010 at 1:53 AM, Mike Rapoport <mike@compulab.co.il> wrote:
> Signed-off-by: Mike Rapoport <mike@compulab.co.il>
> ---
> ?arch/arm/mach-tegra/tegra2_clocks.c | ? 76 +++++++++++++++++++++++++++++++++-
> ?1 files changed, 73 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
> index 4261632..44f1b81 100644
> --- a/arch/arm/mach-tegra/tegra2_clocks.c
> +++ b/arch/arm/mach-tegra/tegra2_clocks.c
> @@ -92,6 +92,8 @@
> ?#define PLLD_MISC_DIV_RST ? ? ? ? ? ? ?(1<<23)
> ?#define PLLD_MISC_DCCON_SHIFT ? ? ? ? ?12
>
> +#define PLLE_MISC_READY ? ? ? ? ? ? ? ? ? ? ? ?(1 << 15)
> +
> ?#define PERIPH_CLK_TO_ENB_REG(c) ? ? ? ((c->clk_num / 32) * 4)
> ?#define PERIPH_CLK_TO_ENB_SET_REG(c) ? ((c->clk_num / 32) * 8)
> ?#define PERIPH_CLK_TO_ENB_BIT(c) ? ? ? (1 << (c->clk_num % 32))
> @@ -356,12 +358,12 @@ static unsigned long tegra2_pll_clk_recalculate_rate(struct clk *c)
> ? ? ? ?return c->rate;
> ?}
>
> -static int tegra2_pll_clk_wait_for_lock(struct clk *c)
> +static int tegra2_pll_clk_wait_for_bit_set(struct clk *c, int bit)
> ?{
> ? ? ? ?ktime_t before;
>
> ? ? ? ?before = ktime_get();
> - ? ? ? while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) {
> + ? ? ? while (!(clk_readl(c->reg + PLL_BASE) & bit)) {
> ? ? ? ? ? ? ? ?if (ktime_us_delta(ktime_get(), before) > 5000) {
> ? ? ? ? ? ? ? ? ? ? ? ?pr_err("Timed out waiting for lock bit on pll %s",
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?c->name);
> @@ -414,7 +416,7 @@ static int tegra2_pll_clk_enable(struct clk *c)
> ? ? ? ?val |= PLL_MISC_LOCK_ENABLE;
> ? ? ? ?clk_writel(val, c->reg + PLL_MISC(c));
>
> - ? ? ? tegra2_pll_clk_wait_for_lock(c);
> + ? ? ? tegra2_pll_clk_wait_for_bit_set(c, PLL_BASE_LOCK);
>
> ? ? ? ?return 0;
> ?}
> @@ -754,6 +756,34 @@ static struct clk_ops tegra_clk_double_ops = {
> ? ? ? ?.recalculate_rate ? ? ? = &tegra2_clk_recalculate_rate,
> ?};
>
> +/* PCI Express clock ops */
> +static int tegra2_plle_clk_enable(struct clk *c)
> +{
> + ? ? ? u32 val;
> +
> + ? ? ? pr_debug("%s on clock %s\n", __func__, c->name);
> +
> + ? ? ? if (tegra2_pll_clk_wait_for_bit_set(c, PLLE_MISC_READY))
> + ? ? ? ? ? ? ? return -EBUSY;
> +
> + ? ? ? val = clk_readl(c->reg + PLL_BASE);
> + ? ? ? val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
> + ? ? ? clk_writel(val, c->reg + PLL_BASE);
> +
> + ? ? ? return 0;
> +}
> +
> +static struct clk_ops tegra_plle_ops = {
> + ? ? ? .init ? ? ? = tegra2_pll_clk_init,
> + ? ? ? .enable ? ? = tegra2_plle_clk_enable,
> + ? ? ? .set_rate ? = tegra2_pll_clk_set_rate,
> +};
> +
> +static struct clk_ops tegra_pcie_clk_ops = {
> + ? ? ? .enable ? ? = tegra2_periph_clk_enable,
> + ? ? ? .disable ? ?= tegra2_periph_clk_disable,
> +};
> +
> ?/* Clock definitions */
> ?static struct clk tegra_clk_32k = {
> ? ? ? ?.name = "clk_32k",
> @@ -1109,6 +1139,42 @@ static struct clk tegra_clk_pclk = {
> ? ? ? ?.ops ? ? ? ? ? ?= &tegra_bus_ops,
> ?};
>
> +/* PCI Express clocks */
> +static struct clk_pll_table tegra_pll_e_table[] = {
> + ? ? ? { 12000000, 100000000, ?200, ?24, 1, 0 },
> +};
> +
> +static struct clk tegra_pll_e = {
> + ? ? ? .name ? ? ?= "pll_e",
> + ? ? ? .flags ? ? = PLL_ALT_MISC_REG,
> + ? ? ? .ops ? ? ? = &tegra_plle_ops,
> + ? ? ? .input_min = 12000000,
> + ? ? ? .input_max = 12000000,
> + ? ? ? .parent ? ?= &tegra_clk_m,
> + ? ? ? .reg ? ? ? = 0xe8,
> + ? ? ? .pll_table = tegra_pll_e_table,
> +};
> +
> +static struct clk tegra_clk_pex = {
> + ? ? ? .name ? ? ?= "pex",
> + ? ? ? .flags ? ? = PERIPH_MANUAL_RESET,
> + ? ? ? .ops ? ? ? = &tegra_pcie_clk_ops,
> + ? ? ? .clk_num ? = 70,
> +};
> +
> +static struct clk tegra_clk_afi = {
> + ? ? ? .name ? ? ?= "afi",
> + ? ? ? .flags ? ? = PERIPH_MANUAL_RESET,
> + ? ? ? .ops ? ? ? = &tegra_pcie_clk_ops,
> + ? ? ? .clk_num ? = 72,
> +};
> +
> +/* the pcie_xclk is required for reset of PCIE subsystem */
> +static struct clk tegra_clk_pcie_xclk = {
> + ? ? ? .name ? ? ?= "pcie_xclk",
> + ? ? ? .clk_num ? = 74,
> +};
> +
> ?static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
> ? ? ? ?{ .input = &tegra_pll_m, .value = 0},
> ? ? ? ?{ .input = &tegra_pll_c, .value = 1},
> @@ -1315,11 +1381,15 @@ struct clk_lookup tegra_clk_lookups[] = {
> ? ? ? ?CLK(NULL, ? ? ? "pll_d_out0", ? &tegra_pll_d_out0),
> ? ? ? ?CLK(NULL, ? ? ? "pll_u", ? ? ? ?&tegra_pll_u),
> ? ? ? ?CLK(NULL, ? ? ? "pll_x", ? ? ? ?&tegra_pll_x),
> + ? ? ? CLK(NULL, ? ? ? "pll_e", ? ? ? ?&tegra_pll_e),
> ? ? ? ?CLK(NULL, ? ? ? "cpu", ? ? ? ? ?&tegra_clk_cpu),
> ? ? ? ?CLK(NULL, ? ? ? "sys", ? ? ? ? ?&tegra_clk_sys),
> ? ? ? ?CLK(NULL, ? ? ? "hclk", ? ? ? ? &tegra_clk_hclk),
> ? ? ? ?CLK(NULL, ? ? ? "pclk", ? ? ? ? &tegra_clk_pclk),
> ? ? ? ?CLK(NULL, ? ? ? "clk_d", ? ? ? ?&tegra_clk_d),
> + ? ? ? CLK(NULL, ? ? ? "pcie_xclk", ? ?&tegra_clk_pcie_xclk),
> + ? ? ? CLK(NULL, ? ? ? "pex", ? ? ? ? ?&tegra_clk_pex),
> + ? ? ? CLK(NULL, ? ? ? "afi", ? ? ? ? ?&tegra_clk_afi),
> ?};
>
> ?void __init tegra2_init_clocks(void)
> --
> 1.6.6.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

[PATCH 1/3] [ARM] tegra: add PCI Express clocks

[Gary King]

> On Thu, Sep 16, 2010 at 11:27 PM, Colin Cross <ccross@google.com> wrote:
>> On Thu, Sep 16, 2010 at 9:53 AM, Mike Rapoport <mike@compulab.co.il> wrote:

<snip>

>> I've been told by Nvidia that the pll lock bits are not reliable, and
>> will be removing uses of tegra2_pll_clk_wait_for_lock and replacing
>> them with delays selected by each pll.  Can you confirm with Nvidia
>> that PLLE_MISC_READY works?

> I'll try to get a confirmation from NVidia....
> From what I've seen during testing the PLLE_MISC_READY works. When I
> used loops that counted udelay(1) I've noticed that the
> PLLE_MISC_READY is set after up to 3usecs.

All of the PLL lock bits in Tegra 2 are unreliable.

The safe way to ensure that PLLE is stable is to wait 1ms after changing it.

>> <snip>
>>
>>> +static struct clk_ops tegra_pcie_clk_ops = {
>>> +       .enable     = tegra2_periph_clk_enable,
>>> +       .disable    = tegra2_periph_clk_disable,
>>> +};
>> Why is this needed?  Won't the regular periph ops work?
>
> They didn't. I haven't found anything about what feeds these clocks,
> can they change rate, what clock can be their parent and if there is
> any muxing options for these clocks.

You can follow the example used by the csi and isp clocks, which also
only support enable and disable. give the PCI clocks a single-choice parent
mux (like mux_clk_m), flags = 0, reg = 0, and a dummy max_rate.

- Gary

[PATCH 1/3] [ARM] tegra: add PCI Express clocks

[Mike Rapoport]

Mogambo Park wrote:
> Good evening Mike Rapport,
> 
>  Are there is some datasheet/TRM availability for Nvidia Tegra chip ?
> Please say me if yes and where.

The Tegra docs are available only under NDA.

> 
> thanks
> 
> On Fri, Sep 17, 2010 at 1:53 AM, Mike Rapoport <mike@compulab.co.il> wrote:
>> Signed-off-by: Mike Rapoport <mike@compulab.co.il>
>> ---
>>  arch/arm/mach-tegra/tegra2_clocks.c |   76 +++++++++++++++++++++++++++++++++-
>>  1 files changed, 73 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
>> index 4261632..44f1b81 100644
>> --- a/arch/arm/mach-tegra/tegra2_clocks.c
>> +++ b/arch/arm/mach-tegra/tegra2_clocks.c
>> @@ -92,6 +92,8 @@
>>  #define PLLD_MISC_DIV_RST              (1<<23)
>>  #define PLLD_MISC_DCCON_SHIFT          12
>>
>> +#define PLLE_MISC_READY                        (1 << 15)
>> +
>>  #define PERIPH_CLK_TO_ENB_REG(c)       ((c->clk_num / 32) * 4)
>>  #define PERIPH_CLK_TO_ENB_SET_REG(c)   ((c->clk_num / 32) * 8)
>>  #define PERIPH_CLK_TO_ENB_BIT(c)       (1 << (c->clk_num % 32))
>> @@ -356,12 +358,12 @@ static unsigned long tegra2_pll_clk_recalculate_rate(struct clk *c)
>>        return c->rate;
>>  }
>>
>> -static int tegra2_pll_clk_wait_for_lock(struct clk *c)
>> +static int tegra2_pll_clk_wait_for_bit_set(struct clk *c, int bit)
>>  {
>>        ktime_t before;
>>
>>        before = ktime_get();
>> -       while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) {
>> +       while (!(clk_readl(c->reg + PLL_BASE) & bit)) {
>>                if (ktime_us_delta(ktime_get(), before) > 5000) {
>>                        pr_err("Timed out waiting for lock bit on pll %s",
>>                                c->name);
>> @@ -414,7 +416,7 @@ static int tegra2_pll_clk_enable(struct clk *c)
>>        val |= PLL_MISC_LOCK_ENABLE;
>>        clk_writel(val, c->reg + PLL_MISC(c));
>>
>> -       tegra2_pll_clk_wait_for_lock(c);
>> +       tegra2_pll_clk_wait_for_bit_set(c, PLL_BASE_LOCK);
>>
>>        return 0;
>>  }
>> @@ -754,6 +756,34 @@ static struct clk_ops tegra_clk_double_ops = {
>>        .recalculate_rate       = &tegra2_clk_recalculate_rate,
>>  };
>>
>> +/* PCI Express clock ops */
>> +static int tegra2_plle_clk_enable(struct clk *c)
>> +{
>> +       u32 val;
>> +
>> +       pr_debug("%s on clock %s\n", __func__, c->name);
>> +
>> +       if (tegra2_pll_clk_wait_for_bit_set(c, PLLE_MISC_READY))
>> +               return -EBUSY;
>> +
>> +       val = clk_readl(c->reg + PLL_BASE);
>> +       val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
>> +       clk_writel(val, c->reg + PLL_BASE);
>> +
>> +       return 0;
>> +}
>> +
>> +static struct clk_ops tegra_plle_ops = {
>> +       .init       = tegra2_pll_clk_init,
>> +       .enable     = tegra2_plle_clk_enable,
>> +       .set_rate   = tegra2_pll_clk_set_rate,
>> +};
>> +
>> +static struct clk_ops tegra_pcie_clk_ops = {
>> +       .enable     = tegra2_periph_clk_enable,
>> +       .disable    = tegra2_periph_clk_disable,
>> +};
>> +
>>  /* Clock definitions */
>>  static struct clk tegra_clk_32k = {
>>        .name = "clk_32k",
>> @@ -1109,6 +1139,42 @@ static struct clk tegra_clk_pclk = {
>>        .ops            = &tegra_bus_ops,
>>  };
>>
>> +/* PCI Express clocks */
>> +static struct clk_pll_table tegra_pll_e_table[] = {
>> +       { 12000000, 100000000,  200,  24, 1, 0 },
>> +};
>> +
>> +static struct clk tegra_pll_e = {
>> +       .name      = "pll_e",
>> +       .flags     = PLL_ALT_MISC_REG,
>> +       .ops       = &tegra_plle_ops,
>> +       .input_min = 12000000,
>> +       .input_max = 12000000,
>> +       .parent    = &tegra_clk_m,
>> +       .reg       = 0xe8,
>> +       .pll_table = tegra_pll_e_table,
>> +};
>> +
>> +static struct clk tegra_clk_pex = {
>> +       .name      = "pex",
>> +       .flags     = PERIPH_MANUAL_RESET,
>> +       .ops       = &tegra_pcie_clk_ops,
>> +       .clk_num   = 70,
>> +};
>> +
>> +static struct clk tegra_clk_afi = {
>> +       .name      = "afi",
>> +       .flags     = PERIPH_MANUAL_RESET,
>> +       .ops       = &tegra_pcie_clk_ops,
>> +       .clk_num   = 72,
>> +};
>> +
>> +/* the pcie_xclk is required for reset of PCIE subsystem */
>> +static struct clk tegra_clk_pcie_xclk = {
>> +       .name      = "pcie_xclk",
>> +       .clk_num   = 74,
>> +};
>> +
>>  static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
>>        { .input = &tegra_pll_m, .value = 0},
>>        { .input = &tegra_pll_c, .value = 1},
>> @@ -1315,11 +1381,15 @@ struct clk_lookup tegra_clk_lookups[] = {
>>        CLK(NULL,       "pll_d_out0",   &tegra_pll_d_out0),
>>        CLK(NULL,       "pll_u",        &tegra_pll_u),
>>        CLK(NULL,       "pll_x",        &tegra_pll_x),
>> +       CLK(NULL,       "pll_e",        &tegra_pll_e),
>>        CLK(NULL,       "cpu",          &tegra_clk_cpu),
>>        CLK(NULL,       "sys",          &tegra_clk_sys),
>>        CLK(NULL,       "hclk",         &tegra_clk_hclk),
>>        CLK(NULL,       "pclk",         &tegra_clk_pclk),
>>        CLK(NULL,       "clk_d",        &tegra_clk_d),
>> +       CLK(NULL,       "pcie_xclk",    &tegra_clk_pcie_xclk),
>> +       CLK(NULL,       "pex",          &tegra_clk_pex),
>> +       CLK(NULL,       "afi",          &tegra_clk_afi),
>>  };
>>
>>  void __init tegra2_init_clocks(void)
>> --
>> 1.6.6.2
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>


-- 
Sincerely yours,
Mike.

[PATCH 1/3] [ARM] tegra: add PCI Express clocks

[Mike Rapoport]

Gary King wrote:
>> On Thu, Sep 16, 2010 at 11:27 PM, Colin Cross <ccross@google.com> wrote:
>>> On Thu, Sep 16, 2010 at 9:53 AM, Mike Rapoport <mike@compulab.co.il> wrote:
> 
> <snip>
> 
>>> I've been told by Nvidia that the pll lock bits are not reliable, and
>>> will be removing uses of tegra2_pll_clk_wait_for_lock and replacing
>>> them with delays selected by each pll.  Can you confirm with Nvidia
>>> that PLLE_MISC_READY works?
> 
>> I'll try to get a confirmation from NVidia....
>> From what I've seen during testing the PLLE_MISC_READY works. When I
>> used loops that counted udelay(1) I've noticed that the
>> PLLE_MISC_READY is set after up to 3usecs.
> 
> All of the PLL lock bits in Tegra 2 are unreliable.
> 
> The safe way to ensure that PLLE is stable is to wait 1ms after changing it.

1 millisecond is a long time... Can you please elaborate about the unreliability 
of PLL lock bits?

>>> <snip>
>>>
>>>> +static struct clk_ops tegra_pcie_clk_ops = {
>>>> +       .enable     = tegra2_periph_clk_enable,
>>>> +       .disable    = tegra2_periph_clk_disable,
>>>> +};
>>> Why is this needed?  Won't the regular periph ops work?
>> They didn't. I haven't found anything about what feeds these clocks,
>> can they change rate, what clock can be their parent and if there is
>> any muxing options for these clocks.
> 
> You can follow the example used by the csi and isp clocks, which also
> only support enable and disable. give the PCI clocks a single-choice parent
> mux (like mux_clk_m), flags = 0, reg = 0, and a dummy max_rate.

Ok, I'll try.

> - Gary--
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


-- 
Sincerely yours,
Mike.

[PATCH 0/3] [ARM] tegra: PCI Express support

[Mike Rapoport]

Arnd Bergmann wrote:
> On Thursday 16 September 2010 18:53:33 Mike Rapoport wrote:
>> These patches enable PCI Express support on Tegra2.
>> The implementation is based on original NVidia code from (1), but it
>> is heavily reworked to avoid custom PCI enumeration and make the code
>> more Linux friendly.
>>
>> This implementation assumes that the PCIe subsystem is fully powered
>> and ungated by the bootloader.
> 
> The patches look good to me, but it seems that I/O space accesses are
> still broken and need to be redirected to the PCI I/O range, like
> the (totally untested) patch below.

Thanks for catching this.

> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> 
> diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
> index 35edfc3..d54e384 100644
> --- a/arch/arm/mach-tegra/include/mach/io.h
> +++ b/arch/arm/mach-tegra/include/mach/io.h
> @@ -21,7 +21,8 @@
>  #ifndef __MACH_TEGRA_IO_H
>  #define __MACH_TEGRA_IO_H
>  
> -#define IO_SPACE_LIMIT 0xffffffff
> +/* Two 1MB windows */
> +#define IO_SPACE_LIMIT (SZ_1M + SZ_1M - 1)

This would limit ioport_resource to 2M, and request_resource(&ioport_resource, 
&res) will fail because ioport_resource does not take into account that IO can 
start somewhere else than at 0.
>  
>  /* On TEGRA, many peripherals are very closely packed in
>   * two 256MB io windows (that actually only use about 64KB
> @@ -69,7 +70,7 @@ void tegra_iounmap(volatile void __iomem *addr);
>  
>  static inline void __iomem *__io(unsigned long addr)
>  {
> -	return (void __iomem *)addr;
> +	return addr + tegra_pcie.regs + SZ_4M;

I wish things were that simple :)
As far as I understand, the IO space should be mapped prior to use and __io 
should return the virtual address.
I'll add it for the next re-spin.

>  }
>  #define __io(a)         __io(a)
>  #define __mem_pci(a)    (a)


-- 
Sincerely yours,
Mike.

[PATCH 0/3] [ARM] tegra: PCI Express support

[Arnd Bergmann]

On Sunday 19 September 2010 16:07:02 Mike Rapoport wrote:
> > diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
> > index 35edfc3..d54e384 100644
> > --- a/arch/arm/mach-tegra/include/mach/io.h
> > +++ b/arch/arm/mach-tegra/include/mach/io.h
> > @@ -21,7 +21,8 @@
> >  #ifndef __MACH_TEGRA_IO_H
> >  #define __MACH_TEGRA_IO_H
> >  
> > -#define IO_SPACE_LIMIT 0xffffffff
> > +/* Two 1MB windows */
> > +#define IO_SPACE_LIMIT (SZ_1M + SZ_1M - 1)
> 
> This would limit ioport_resource to 2M, and request_resource(&ioport_resource, 
> &res) will fail because ioport_resource does not take into account that IO can 
> start somewhere else than at 0.

Normally, the ioport_resource is limited to 65536 bytes in practice,
because that's the most that many PCI cards decode.

The only reason to let the I/O window start at something other than 0 is
to leave space for legacy ISA devices, so typically the available range
is between 0x1000 and 0xffff.

I don't see that as a limitation here.

> >  /* On TEGRA, many peripherals are very closely packed in
> >   * two 256MB io windows (that actually only use about 64KB
> > @@ -69,7 +70,7 @@ void tegra_iounmap(volatile void __iomem *addr);
> >  
> >  static inline void __iomem *__io(unsigned long addr)
> >  {
> > -     return (void __iomem *)addr;
> > +     return addr + tegra_pcie.regs + SZ_4M;
> 
> I wish things were that simple :)
> As far as I understand, the IO space should be mapped prior to use and __io 
> should return the virtual address.

That's right. You already map all the PCI registers including the I/O port
mapping at initialization time, but you must not attempt to access these
during boot before that time.

You should probably mask the size as above, which I forgot:

static inline void __iomem *__io(unsigned long addr)
{
     return (addr & IO_SPACE_LIMIT) + (tegra_pcie.regs + SZ_4M);
}

Hopefully it's clearer that way, and certainly safer in case someone
passes the physical address of the I/O window into __io rather than
the offset.

	Arnd

[PATCH 0/3] [ARM] tegra: PCI Express support

[Russell King - ARM Linux]

On Sun, Sep 19, 2010 at 04:39:44PM +0200, Arnd Bergmann wrote:
> On Sunday 19 September 2010 16:07:02 Mike Rapoport wrote:
> > As far as I understand, the IO space should be mapped prior to use and __io 
> > should return the virtual address.
> 
> That's right. You already map all the PCI registers including the I/O port
> mapping at initialization time, but you must not attempt to access these
> during boot before that time.

Yes.  __io() takes the IO port address, and returns a virtual address
for the inb() et.al. macros to deference to perform the actual access.

So, for example if you have a PCI serial card inserted which appears at
0x3f8, then inb(0x3f8) should access the first register on the PCI serial
card.  As inb(0x3f8) equates to __raw_readb(__io(0x3f8)), __io(0x3f8)
must return the virtual address to access that port.

Eg, on DC21285 (footbridge) systems, the PCI IO window is at 0x7c000000
physical, mapped into 0xff000000 virtual.  So __io(0x3f8) translates to
0xff0003f8 virtual, which hits 0x7c0003f8 physical, and 0x3f8 as an IO
access on the PCI bus.

Things become a little more complicated when you have PCMCIA cards with
separate IO regions, as on SA11x0 and PXA systems.  These don't tend to
have PCI, so we adopted there to have __io() do a 1:1 translation, and
arrange for the "bus IO" address to be the actual virtual address.

[PATCH 0/3] [ARM] tegra: PCI Express support

[Mike Rapoport]

Arnd Bergmann wrote:
> On Sunday 19 September 2010 16:07:02 Mike Rapoport wrote:
>>> diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
>>> index 35edfc3..d54e384 100644
>>> --- a/arch/arm/mach-tegra/include/mach/io.h
>>> +++ b/arch/arm/mach-tegra/include/mach/io.h
>>> @@ -21,7 +21,8 @@
>>>  #ifndef __MACH_TEGRA_IO_H
>>>  #define __MACH_TEGRA_IO_H
>>>  
>>> -#define IO_SPACE_LIMIT 0xffffffff
>>> +/* Two 1MB windows */
>>> +#define IO_SPACE_LIMIT (SZ_1M + SZ_1M - 1)
>> This would limit ioport_resource to 2M, and request_resource(&ioport_resource, 
>> &res) will fail because ioport_resource does not take into account that IO can 
>> start somewhere else than at 0.
> 
> Normally, the ioport_resource is limited to 65536 bytes in practice,
> because that's the most that many PCI cards decode.
> 
> The only reason to let the I/O window start at something other than 0 is
> to leave space for legacy ISA devices, so typically the available range
> is between 0x1000 and 0xffff.
> 
> I don't see that as a limitation here.

Since ARM doesn't have special IO access instructions and all IO is memory
mapped, from the CPU perspective IO window would be at some arbitrary physical 
address. For Tegra this address can be anywhere between 0x80004000 and 
0x8fffffff. With sizes and offsets in my implementation the  IO resources would 
be defined as follows:
struct tegra_pcie_io_res[] = {
	[0] = {
		.start = 0x80400000,
		.end   = 0x804fffff,
		.flags	= IORESOURCE_IO,
	},
	[1] = {
		.start = 0x80500000,
		.end   = 0x805fffff,
		.flags	= IORESOURCE_IO,
	},
}

With IO_SPACE_LIMIT set to 2M the ioport_resource defined in kernel/resource.c 
becomes
struct resource ioport_resource = {
	.name	= "PCI IO",
	.start = 0,
	.end = 0x1fffff,
	.flags	= IORESOURCE_IO,
};

And then a call to request_resource(&ioport_resource, &tegra_pcie_io_res) fails 
because Tegra IO resources do not fit into the global ioport_resource definition.

>>>  /* On TEGRA, many peripherals are very closely packed in
>>>   * two 256MB io windows (that actually only use about 64KB
>>> @@ -69,7 +70,7 @@ void tegra_iounmap(volatile void __iomem *addr);
>>>  
>>>  static inline void __iomem *__io(unsigned long addr)
>>>  {
>>> -     return (void __iomem *)addr;
>>> +     return addr + tegra_pcie.regs + SZ_4M;
>> I wish things were that simple :)
>> As far as I understand, the IO space should be mapped prior to use and __io 
>> should return the virtual address.
> 
> That's right. You already map all the PCI registers including the I/O port
> mapping at initialization time, but you must not attempt to access these
> during boot before that time.
> 
> You should probably mask the size as above, which I forgot:
> 
> static inline void __iomem *__io(unsigned long addr)
> {
>      return (addr & IO_SPACE_LIMIT) + (tegra_pcie.regs + SZ_4M);
> }
> 
> Hopefully it's clearer that way, and certainly safer in case someone
> passes the physical address of the I/O window into __io rather than
> the offset.

I haven't mapped the IO space originally, so the __io should be something like

static inline void __iomem *__io(unsigned long addr)
{
	return tegra_pcie.io_space + addr;
}

where tegra_pcie.io_space is mapped during PCIe initialization.


> 	Arnd
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


-- 
Sincerely yours,
Mike.

[PATCH 0/3] [ARM] tegra: PCI Express support

[Russell King - ARM Linux]

On Sun, Sep 19, 2010 at 05:36:16PM +0200, Mike Rapoport wrote:
> Since ARM doesn't have special IO access instructions and all IO is memory
> mapped, from the CPU perspective IO window would be at some arbitrary 
> physical address. For Tegra this address can be anywhere between 
> 0x80004000 and 0x8fffffff. With sizes and offsets in my implementation 
> the  IO resources would be defined as follows:
> struct tegra_pcie_io_res[] = {
> 	[0] = {
> 		.start = 0x80400000,
> 		.end   = 0x804fffff,
> 		.flags	= IORESOURCE_IO,
> 	},
> 	[1] = {
> 		.start = 0x80500000,
> 		.end   = 0x805fffff,
> 		.flags	= IORESOURCE_IO,
> 	},
> }

These aren't IO resources - they're describing an area of physical
host memory, so they should be IORESOURCE_MEM.

> And then a call to request_resource(&ioport_resource, &tegra_pcie_io_res) 
> fails because Tegra IO resources do not fit into the global 
> ioport_resource definition.

And therefore they should not be registered against the ioport resource.


Think about it like this:

iomem_resource (CPU physical
address space view):
+------------+ 0x00000000
|  RAM etc   |
/            /
/            /
|            |                    ioport_resource
+------------+ 0x80400000 ------> +-----------------+ 0x00000000
|            |                    | PCI peripherals |
|            |                    |                 |
|            | 0x804003f8         +-----------------+ 0x000003f8
|            |                    | Eg, PCI serial  |
|PCI IO space| 0x804003ff         +-----------------+ 0x000003ff
|            |                    |                 |
|            |                    |                 |
|            |                    | PCI peripherals |
|            |                    |                 |
|            |                    |                 |
+------------+ 0x805fffff ------> +-----------------+ 0x001fffff
|            |
/other stuff /
/            /
|            |
+------------+ 0xffffffff

So the iomem resource tree is entirely separate from the ioport resource
tree, and the two never overlap.  The iomem resource tree represents the
physical MMIO space, and just contains a reservation for the entire block
of PCI IO space.  The ioport resource represents the entirely separate
PCI IO space resource tree.

To illustrate this better, on Footbridge, this is what you see in
/proc/iomem:
00000000-07ffffff : System RAM
  0002d000-002a9fff : Kernel text
  002aa000-002e7c77 : Kernel data
42000160-4200017f : Footbridge UART
a0000000-bfffffff : Footbridge prefetch
  a0000000-a001ffff : 0000:00:07.0
  a0020000-a003ffff : 0000:00:08.0
  a0040000-a004ffff : 0000:00:09.0
c0000000-ffffffff : Footbridge non-prefetch
  c0000000-c3ffffff : 0000:00:09.0
  c4000000-c4000fff : 0000:00:06.3
  c4001000-c400107f : 0000:00:08.0

Note that 7c000000-7c00ffff is the address range used for PCI IO accesses,
and isn't requested in the above (mainly because we never registered a
separate resource for it.)

and /proc/ioports:
0000-000f : dma1
0020-003f : pic1
0060-006f : i8042
0070-0073 : rtc_cmos
  0070-0073 : rtc0
0080-008f : dma low page
00a0-00bf : pic2
00c0-00df : dma2
01f0-01f7 : ide0
0213-0213 : ISAPnP
02f8-02ff : serial8250.0
  02f8-02ff : serial
03c0-03df : vga+
03f6-03f6 : ide0
03f8-03ff : serial8250.0
  03f8-03ff : serial
0480-048f : dma high page
0a79-0a79 : isapnp write
1000-107f : 0000:00:08.0
1080-108f : 0000:00:06.1
  1080-1087 : ide0
1090-109f : 0000:00:07.0
  1090-1097 : ide1
  1098-109f : ide2
10a0-10a7 : 0000:00:07.0
  10a0-10a7 : ide1
10a8-10af : 0000:00:07.0
  10a8-10af : ide2
10b0-10b3 : 0000:00:07.0
  10b2-10b2 : ide1
10b4-10b7 : 0000:00:07.0
  10b6-10b6 : ide2
ff00-ff7f : Footbridge

Note that IO accesses correspond to 0x7c000000 + IO address in iomem space.

[PATCH 0/3] [ARM] tegra: PCI Express support

[Arnd Bergmann]

On Sunday 19 September 2010 17:02:43 Russell King - ARM Linux wrote:
> Eg, on DC21285 (footbridge) systems, the PCI IO window is at 0x7c000000
> physical, mapped into 0xff000000 virtual.  So __io(0x3f8) translates to
> 0xff0003f8 virtual, which hits 0x7c0003f8 physical, and 0x3f8 as an IO
> access on the PCI bus.
> 
> Things become a little more complicated when you have PCMCIA cards with
> separate IO regions, as on SA11x0 and PXA systems.  These don't tend to
> have PCI, so we adopted there to have __io() do a 1:1 translation, and
> arrange for the "bus IO" address to be the actual virtual address.

Such a mapping sounds dangerous when you have device drivers trying
to access legacy ISA ports. Most of them are disabled on ARM, but
some drivers are hard to disable.

More importantly, having PCI I/O port numbers above 65536 will confuse
code like /dev/ioport, which then causes NULL pointer accesses
when accessed by a user application. Also, I would guess that it breaks
if you have PCI or PCMCIA cards that decode more than 16 bits of I/O port
addresses, because then the PCI I/O BAR gets set to a high number that
is not actually accessible inside the I/O space window.

The way we solved this on powerpc was to define a range of the virtual
address space as the I/O port window and map each bus's physical
I/O port window into a section of the virtual window.

	Arnd

[PATCH 0/3] [ARM] tegra: PCI Express support

[Russell King - ARM Linux]

On Sun, Sep 19, 2010 at 06:34:44PM +0200, Arnd Bergmann wrote:
> On Sunday 19 September 2010 17:02:43 Russell King - ARM Linux wrote:
> > Eg, on DC21285 (footbridge) systems, the PCI IO window is at 0x7c000000
> > physical, mapped into 0xff000000 virtual.  So __io(0x3f8) translates to
> > 0xff0003f8 virtual, which hits 0x7c0003f8 physical, and 0x3f8 as an IO
> > access on the PCI bus.
> > 
> > Things become a little more complicated when you have PCMCIA cards with
> > separate IO regions, as on SA11x0 and PXA systems.  These don't tend to
> > have PCI, so we adopted there to have __io() do a 1:1 translation, and
> > arrange for the "bus IO" address to be the actual virtual address.
> 
> Such a mapping sounds dangerous when you have device drivers trying
> to access legacy ISA ports. Most of them are disabled on ARM, but
> some drivers are hard to disable.

Seems reliable on SA11x0 and PXA platforms.

> More importantly, having PCI I/O port numbers above 65536 will confuse
> code like /dev/ioport, which then causes NULL pointer accesses
> when accessed by a user application. Also, I would guess that it breaks
> if you have PCI or PCMCIA cards that decode more than 16 bits of I/O port
> addresses, because then the PCI I/O BAR gets set to a high number that
> is not actually accessible inside the I/O space window.

This machine I'm using to send this email has in /proc/ioports:

90000000-9000ffff : IOP3XX PCI I/O Space
  90000000-900000ff : 0000:00:01.0
    90000000-900000ff : r8169
  90000400-900004ff : 0000:00:02.0
    90000400-900004ff : r8169
  90000800-9000081f : 0000:00:04.0
    90000800-9000081f : uhci_hcd
  90000820-9000083f : 0000:00:04.1
    90000820-9000083f : uhci_hcd
  90000840-9000084f : 0000:00:03.0
  90000850-90000857 : 0000:00:03.0
  90000858-9000085f : 0000:00:03.0
  90000860-90000863 : 0000:00:03.0
  90000864-90000867 : 0000:00:03.0

which works fine - and yes, if you insert an ISA driver it probably will
crash.  But then you can crash an x86 PC by using setserial to define
a serial port at a wrong address.

The answer to the latter issue is "don't do that then", and I'd suggest
that also goes for the "don't insert an ISA driver when the platform
doesn't support it".

But yes, in principle I agree that PCI IO space should be 0 - 0xffff
rather than having addresses assigned at the memory mapped IO address.
Unfortunately, broken hardware (bridges) sometimes gets in the way of
that.

[PATCH 0/3] [ARM] tegra: PCI Express support

[Arnd Bergmann]

On Sunday 19 September 2010 18:40:40 Russell King - ARM Linux wrote:
> which works fine - and yes, if you insert an ISA driver it probably will
> crash.  But then you can crash an x86 PC by using setserial to define
> a serial port at a wrong address.

Sure, if you build the kernel just for one machine, there is no reason
to include code that tries to access fixed I/O ports.

What I'm more worried about is that as we're moving to multi-platform
kernels you want to build for other hardware, e.g. one that has
a PC-style keyboard controller and one that has a funny mapping like that.

Normally, the driver for the keyboard controller should just access
the well-known port number and not find anything there, because PCI
devices are mapped above port 0x1000. What you get instead is a kernel
NULL pointer access.

	Arnd

[PATCH 0/3] [ARM] tegra: PCI Express support

[Mike Rapoport]

Russell King - ARM Linux wrote:
> On Sun, Sep 19, 2010 at 05:36:16PM +0200, Mike Rapoport wrote:
>> Since ARM doesn't have special IO access instructions and all IO is memory
>> mapped, from the CPU perspective IO window would be at some arbitrary 
>> physical address. For Tegra this address can be anywhere between 
>> 0x80004000 and 0x8fffffff. With sizes and offsets in my implementation 
>> the  IO resources would be defined as follows:
>> struct tegra_pcie_io_res[] = {
>> 	[0] = {
>> 		.start = 0x80400000,
>> 		.end   = 0x804fffff,
>> 		.flags	= IORESOURCE_IO,
>> 	},
>> 	[1] = {
>> 		.start = 0x80500000,
>> 		.end   = 0x805fffff,
>> 		.flags	= IORESOURCE_IO,
>> 	},
>> }
> 
> These aren't IO resources - they're describing an area of physical
> host memory, so they should be IORESOURCE_MEM.
> 
>> And then a call to request_resource(&ioport_resource, &tegra_pcie_io_res) 
>> fails because Tegra IO resources do not fit into the global 
>> ioport_resource definition.
> 
> And therefore they should not be registered against the ioport resource.
> 
> 
> Think about it like this:
> 
> iomem_resource (CPU physical
> address space view):
> +------------+ 0x00000000
> |  RAM etc   |
> /            /
> /            /
> |            |                    ioport_resource
> +------------+ 0x80400000 ------> +-----------------+ 0x00000000
> |            |                    | PCI peripherals |
> |            |                    |                 |
> |            | 0x804003f8         +-----------------+ 0x000003f8
> |            |                    | Eg, PCI serial  |
> |PCI IO space| 0x804003ff         +-----------------+ 0x000003ff
> |            |                    |                 |
> |            |                    |                 |
> |            |                    | PCI peripherals |
> |            |                    |                 |
> |            |                    |                 |
> +------------+ 0x805fffff ------> +-----------------+ 0x001fffff
> |            |
> /other stuff /
> /            /
> |            |
> +------------+ 0xffffffff
> 
> So the iomem resource tree is entirely separate from the ioport resource
> tree, and the two never overlap.  The iomem resource tree represents the
> physical MMIO space, and just contains a reservation for the entire block
> of PCI IO space.  The ioport resource represents the entirely separate
> PCI IO space resource tree.

 From what you are saying I understand that the region reservation should look like:

static struct resource res_mmio = {
	.name	= "PCI IO"
	.start	= 0x80400000,
	.end	= 0x80400000 + IO_SIZE,
	.flags	= IORESOURCE_MEM,
};

static struct resource pcie_res[] = {
	[0] = {
		.name	= "PCIe IO",
		.start	= 0x1000,
		.end	= 0x1000 + IO_SIZE - 1,
		.flags	= IORESOURCE_IO,
	},
	[1] = {
		.name	= "PCIe MEM",
		.start	= MEM_BASE,
		.end	= MEM_BASE + MEM_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
{
	request_region(&iomem_resource, &res_mmio);
	request_region(&iomem_resource, &pcie_res[1]);
	request_region(&ioport_resource, &pcie_res[0]);
	sys->resource[0] = &pcie_res[0];
	sys->resource[1] = &pcie_res[1];
}

I've used 0x1000 as IO resources start because having it 0 would cause 
pcibios_enable_device to fail.

Is the above setup reasonable enough or I'm missing something else?

> To illustrate this better, on Footbridge, this is what you see in
> /proc/iomem:
> 00000000-07ffffff : System RAM
>   0002d000-002a9fff : Kernel text
>   002aa000-002e7c77 : Kernel data
> 42000160-4200017f : Footbridge UART
> a0000000-bfffffff : Footbridge prefetch
>   a0000000-a001ffff : 0000:00:07.0
>   a0020000-a003ffff : 0000:00:08.0
>   a0040000-a004ffff : 0000:00:09.0
> c0000000-ffffffff : Footbridge non-prefetch
>   c0000000-c3ffffff : 0000:00:09.0
>   c4000000-c4000fff : 0000:00:06.3
>   c4001000-c400107f : 0000:00:08.0
> 
> Note that 7c000000-7c00ffff is the address range used for PCI IO accesses,
> and isn't requested in the above (mainly because we never registered a
> separate resource for it.)
> 
> and /proc/ioports:
> 0000-000f : dma1
> 0020-003f : pic1
> 0060-006f : i8042
> 0070-0073 : rtc_cmos
>   0070-0073 : rtc0
> 0080-008f : dma low page
> 00a0-00bf : pic2
> 00c0-00df : dma2
> 01f0-01f7 : ide0
> 0213-0213 : ISAPnP
> 02f8-02ff : serial8250.0
>   02f8-02ff : serial
> 03c0-03df : vga+
> 03f6-03f6 : ide0
> 03f8-03ff : serial8250.0
>   03f8-03ff : serial
> 0480-048f : dma high page
> 0a79-0a79 : isapnp write
> 1000-107f : 0000:00:08.0
> 1080-108f : 0000:00:06.1
>   1080-1087 : ide0
> 1090-109f : 0000:00:07.0
>   1090-1097 : ide1
>   1098-109f : ide2
> 10a0-10a7 : 0000:00:07.0
>   10a0-10a7 : ide1
> 10a8-10af : 0000:00:07.0
>   10a8-10af : ide2
> 10b0-10b3 : 0000:00:07.0
>   10b2-10b2 : ide1
> 10b4-10b7 : 0000:00:07.0
>   10b6-10b6 : ide2
> ff00-ff7f : Footbridge
> 
> Note that IO accesses correspond to 0x7c000000 + IO address in iomem space.
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


-- 
Sincerely yours,
Mike.

[PATCH 0/3] [ARM] tegra: PCI Express support

[Arnd Bergmann]

On Monday 20 September 2010, Mike Rapoport wrote:
> static struct resource pcie_res[] = {
>         [0] = {
>                 .name   = "PCIe IO",
>                 .start  = 0x1000,
>                 .end    = 0x1000 + IO_SIZE - 1,
>                 .flags  = IORESOURCE_IO,
>         },

The end should be 'IO_SIZE - 1' or IO_SPACE_LIMIT (should be the same anyway),
not '0x1000 + IO_SIZE - 1'. The reason for the 0x1000 is that the first 4096
ports are reserved for legacy ISA devices by setting PCIBIOS_MIN_IO.

The rest looks fine AFAICT.

	Arnd

[PATCH 0/3] [ARM] tegra: PCI Express support

[Russell King - ARM Linux]

On Mon, Sep 20, 2010 at 09:15:00AM +0200, Mike Rapoport wrote:
> From what you are saying I understand that the region reservation should
> look like:
>
> static struct resource res_mmio = {
> 	.name	= "PCI IO"
> 	.start	= 0x80400000,
> 	.end	= 0x80400000 + IO_SIZE,
> 	.flags	= IORESOURCE_MEM,
> };
>
> static struct resource pcie_res[] = {
> 	[0] = {
> 		.name	= "PCIe IO",
> 		.start	= 0x1000,
> 		.end	= 0x1000 + IO_SIZE - 1,
> 		.flags	= IORESOURCE_IO,
> 	},
> 	[1] = {
> 		.name	= "PCIe MEM",
> 		.start	= MEM_BASE,
> 		.end	= MEM_BASE + MEM_SIZE - 1,
> 		.flags	= IORESOURCE_MEM,
> 	},
> };
>
> static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
> {
> 	request_region(&iomem_resource, &res_mmio);
> 	request_region(&iomem_resource, &pcie_res[1]);
> 	request_region(&ioport_resource, &pcie_res[0]);
> 	sys->resource[0] = &pcie_res[0];
> 	sys->resource[1] = &pcie_res[1];
> }
>
> I've used 0x1000 as IO resources start because having it 0 would cause  
> pcibios_enable_device to fail.

More or less.  You can avoid the ioport resource (&pcie_res[0]) and
replace it with &ioport_resource if you set PCIBIOS_MIN_IO to 0x1000.
This will have the effect of preventing BARs being allocated below
0x1000.

Don't also forget to check the return value from request_region()...