[PATCH 0/5] ARM: S5PV310: Add support HSMMC for S5PV310/S5PC210

[PATCH 0/5] ARM: S5PV310: Add support HSMMC for S5PV310/S5PC210

[Jeongbae Seo]

This patch adds support HSMMC for S5PV310/S5PC210.

[PATCH 1/5] ARM: S5PV310: Add HSMMC support and SDHCI configuration
[PATCH 2/5] ARM: S5PV310: Add HSMMC support into S5PV310 and S5PC210
[PATCH 3/5] ARM: SAMSUNG: Modified to change of bus width and host caps
[PATCH 4/5] ARM: SAMSUNG: Add clock types into platform data
[PATCH 5/5] sdhci-s3c: Add support no internal clock divider in host controller

[PATCH 1/5] ARM: S5PV310: Add HSMMC support and SDHCI configuration

[Jeongbae Seo]

From: Hyuk Lee <hyuk1.lee@samsung.com>

This patch adds to support HSMMC for S5PV310 and S5PC210 and setup for
HSMMC host controller and also related GPIO.
At most 4 channel can be used at the same time.
A user can configure SDHCI data bus as 8bit or 4bit.

Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
---
 arch/arm/mach-s5pv310/Kconfig            |   39 ++++++++
 arch/arm/mach-s5pv310/Makefile           |    2 +
 arch/arm/mach-s5pv310/setup-sdhci-gpio.c |  156 ++++++++++++++++++++++++++++++
 arch/arm/mach-s5pv310/setup-sdhci.c      |   69 +++++++++++++
 4 files changed, 266 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pv310/setup-sdhci-gpio.c
 create mode 100644 arch/arm/mach-s5pv310/setup-sdhci.c

diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
index 9ac29fe..6a07968 100644
--- a/arch/arm/mach-s5pv310/Kconfig
+++ b/arch/arm/mach-s5pv310/Kconfig
@@ -25,6 +25,17 @@ config S5PV310_SETUP_I2C2
 	help
 	  Common setup code for i2c bus 2.
 
+config S5PV310_SETUP_SDHCI
+	bool
+	select S5PV310_SETUP_SDHCI_GPIO
+	help
+	  Internal helper functions for S5PV310 based SDHCI systems.
+
+config S5PV310_SETUP_SDHCI_GPIO
+	bool
+	help
+	  Common setup code for SDHCI gpio.
+
 # machine support
 
 menu "S5PC210 Machines"
@@ -33,6 +44,11 @@ config MACH_SMDKC210
 	bool "SMDKC210"
 	select CPU_S5PV310
 	select ARCH_SPARSEMEM_ENABLE
+	select S3C_DEV_HSMMC
+	select S3C_DEV_HSMMC1
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
+	select S5PV310_SETUP_SDHCI
 	help
 	  Machine support for Samsung SMDKC210
 	  S5PC210(MCP) is one of package option of S5PV310
@@ -53,9 +69,32 @@ config MACH_SMDKV310
 	bool "SMDKV310"
 	select CPU_S5PV310
 	select ARCH_SPARSEMEM_ENABLE
+	select S3C_DEV_HSMMC
+	select S3C_DEV_HSMMC1
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
+	select S5PV310_SETUP_SDHCI
 	help
 	  Machine support for Samsung SMDKV310
 
 endmenu
 
+comment "Configuration for HSMMC bus width"
+
+menu "Use 8-bit bus width"
+
+config S5PV310_SDHCI_CH0_8BIT
+	bool "Channel 0 with 8-bit bus"
+	help
+	  Support HSMMC Channel 0 8-bit bus.
+	  If selected, Channel 1 is disabled.
+
+config S5PV310_SDHCI_CH2_8BIT
+	bool "Channel 2 with 8-bit bus"
+	help
+	  Support HSMMC Channel 2 8-bit bus.
+	  If selected, Channel 3 is disabled.
+
+endmenu
+
 endif
diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
index aefb14f..c89b6b0 100644
--- a/arch/arm/mach-s5pv310/Makefile
+++ b/arch/arm/mach-s5pv310/Makefile
@@ -29,3 +29,5 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210)	+= mach-universal_c210.o
 
 obj-$(CONFIG_S5PV310_SETUP_I2C1)	+= setup-i2c1.o
 obj-$(CONFIG_S5PV310_SETUP_I2C2)	+= setup-i2c2.o
+obj-$(CONFIG_S5PV310_SETUP_SDHCI)	+= setup-sdhci.o
+obj-$(CONFIG_S5PV310_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
new file mode 100644
index 0000000..8db8c81
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
@@ -0,0 +1,156 @@
+/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+
+void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+	unsigned int gpio;
+
+	/* Set all the necessary GPK0[0:1] pins to special-function 2 */
+	for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	switch (width) {
+	case 8:
+		for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
+			/* Data pin GPK1[3:6] to special-funtion 3 */
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+
+			/* Setup Drive Strength */
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+		}
+	case 4:
+		for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) {
+			/* Data pin GPK0[3:6] to special-funtion 2 */
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+
+			/* Setup Drive Strength */
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+		}
+	default:
+		break;
+	}
+
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP);
+	}
+}
+
+void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+	unsigned int gpio;
+
+	/* Set all the necessary GPK1[0:1] pins to special-function 2 */
+	for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
+		/* Data pin GPK1[3:6] to special-function 2 */
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+
+		/* Setup Drive Strength */
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP);
+	}
+}
+
+void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+	unsigned int gpio;
+
+	/* Set all the necessary GPK2[0:1] pins to special-function 2 */
+	for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	switch (width) {
+	case 8:
+		for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
+			/* Data pin GPK3[3:6] to special-function 3 */
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+
+			/* Setup Drive Strength */
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+		}
+	case 4:
+		for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) {
+			/* Data pin GPK2[3:6] to special-function 2 */
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+
+			/* Setup Drive Strength */
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+		}
+	default:
+		break;
+	}
+
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP);
+	}
+}
+
+void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
+{
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+	unsigned int gpio;
+
+	/* Set all the necessary GPK3[0:1] pins to special-function 2 */
+	for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
+		/* Data pin GPK3[3:6] to special-function 2 */
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+
+		/* Setup Drive Strength */
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP);
+	}
+}
diff --git a/arch/arm/mach-s5pv310/setup-sdhci.c b/arch/arm/mach-s5pv310/setup-sdhci.c
new file mode 100644
index 0000000..db8358f
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-sdhci.c
@@ -0,0 +1,69 @@
+/* linux/arch/arm/mach-s5pv310/setup-sdhci.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PV310 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+
+#include <plat/regs-sdhci.h>
+
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+
+char *s5pv310_hsmmc_clksrcs[4] = {
+	[0] = NULL,
+	[1] = NULL,
+	[2] = "sclk_mmc",	/* mmc_bus */
+	[3] = NULL,
+};
+
+void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
+				  struct mmc_ios *ios, struct mmc_card *card)
+{
+	u32 ctrl2, ctrl3;
+
+	/* don't need to alter anything acording to card-type */
+
+	ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
+
+	/* select base clock source to HCLK */
+
+	ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+
+	/*
+	 * clear async mode, enable conflict mask, rx feedback ctrl, SD
+	 * clk hold and no use debounce count
+	 */
+
+	ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
+		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
+		  S3C_SDHCI_CTRL2_ENFBCLKRX |
+		  S3C_SDHCI_CTRL2_DFCNT_NONE |
+		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+
+	/* Tx and Rx feedback clock delay control */
+
+	if (ios->clock < 25 * 1000000)
+		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
+			 S3C_SDHCI_CTRL3_FCSEL2 |
+			 S3C_SDHCI_CTRL3_FCSEL1 |
+			 S3C_SDHCI_CTRL3_FCSEL0);
+	else
+		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
+
+	writel(ctrl2, r + S3C_SDHCI_CONTROL2);
+	writel(ctrl3, r + S3C_SDHCI_CONTROL3);
+}
-- 
1.6.2.5

[PATCH 2/5] ARM: S5PV310: Add HSMMC support into S5PV310 and S5PC210

[Jeongbae Seo]

From: Hyuk Lee <hyuk1.lee@samsung.com>

This patch adds to use of HSMMC on S5PV310 and S5PC210.
The HSMMC platform data like card detect, data bus width
and capability is configured.

Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
---
 arch/arm/mach-s5pv310/cpu.c                |    7 +++
 arch/arm/mach-s5pv310/mach-smdkc210.c      |   50 ++++++++++++++++++++++++
 arch/arm/mach-s5pv310/mach-smdkv310.c      |   50 ++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/sdhci.h |   57 ++++++++++++++++++++++++++++
 4 files changed, 164 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index 4add398..66beac4 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -19,6 +19,7 @@
 #include <plat/cpu.h>
 #include <plat/clock.h>
 #include <plat/s5pv310.h>
+#include <plat/sdhci.h>
 
 #include <mach/regs-irq.h>
 
@@ -83,6 +84,12 @@ static void s5pv310_idle(void)
 void __init s5pv310_map_io(void)
 {
 	iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));
+
+	/* initialize device information early */
+	s5pv310_default_sdhci0();
+	s5pv310_default_sdhci1();
+	s5pv310_default_sdhci2();
+	s5pv310_default_sdhci3();
 }
 
 void __init s5pv310_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c
index 71a3bec..e6d789f 100644
--- a/arch/arm/mach-s5pv310/mach-smdkc210.c
+++ b/arch/arm/mach-s5pv310/mach-smdkc210.c
@@ -9,6 +9,9 @@
 */
 
 #include <linux/serial_core.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -17,6 +20,8 @@
 #include <plat/regs-serial.h>
 #include <plat/s5pv310.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
 
 #include <mach/map.h>
 
@@ -65,6 +70,45 @@ static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
 	},
 };
 
+static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio		= S5PV310_GPK0(2),
+	.ext_cd_gpio_invert	= 1,
+#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio		= S5PV310_GPK0(2),
+	.ext_cd_gpio_invert	= 1,
+};
+
+static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio		= S5PV310_GPK2(2),
+	.ext_cd_gpio_invert	= 1,
+#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio		= S5PV310_GPK2(2),
+	.ext_cd_gpio_invert	= 1,
+};
+
+static struct platform_device *smdkc210_devices[] __initdata = {
+	&s3c_device_hsmmc0,
+	&s3c_device_hsmmc1,
+	&s3c_device_hsmmc2,
+	&s3c_device_hsmmc3,
+};
+
 static void __init smdkc210_map_io(void)
 {
 	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -74,9 +118,15 @@ static void __init smdkc210_map_io(void)
 
 static void __init smdkc210_machine_init(void)
 {
+	s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
+	s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
+	s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
+	s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
+
 #ifdef CONFIG_CACHE_L2X0
 	l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff);
 #endif
+	platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
 }
 
 MACHINE_START(SMDKC210, "SMDKC210")
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c
index 0d6ab77..c52b0c7 100644
--- a/arch/arm/mach-s5pv310/mach-smdkv310.c
+++ b/arch/arm/mach-s5pv310/mach-smdkv310.c
@@ -9,6 +9,9 @@
 */
 
 #include <linux/serial_core.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -17,6 +20,8 @@
 #include <plat/regs-serial.h>
 #include <plat/s5pv310.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
 
 #include <mach/map.h>
 
@@ -65,6 +70,45 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
 	},
 };
 
+static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio		= S5PV310_GPK0(2),
+	.ext_cd_gpio_invert	= 1,
+#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio		= S5PV310_GPK0(2),
+	.ext_cd_gpio_invert	= 1,
+};
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio		= S5PV310_GPK2(2),
+	.ext_cd_gpio_invert	= 1,
+#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio		= S5PV310_GPK2(2),
+	.ext_cd_gpio_invert	= 1,
+};
+
+static struct platform_device *smdkv310_devices[] __initdata = {
+	&s3c_device_hsmmc0,
+	&s3c_device_hsmmc1,
+	&s3c_device_hsmmc2,
+	&s3c_device_hsmmc3,
+};
+
 static void __init smdkv310_map_io(void)
 {
 	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -74,9 +118,15 @@ static void __init smdkv310_map_io(void)
 
 static void __init smdkv310_machine_init(void)
 {
+	s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
+	s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
+	s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
+	s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
+
 #ifdef CONFIG_CACHE_L2X0
 	l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff);
 #endif
+	platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
 }
 
 MACHINE_START(SMDKV310, "SMDKV310")
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 30844c2..d92670a 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -110,6 +110,10 @@ extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
+extern void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
 
 /* S3C64XX SDHCI setup */
 
@@ -288,4 +292,57 @@ static inline void s5pv210_default_sdhci3(void) { }
 
 #endif /* CONFIG_S5PV210_SETUP_SDHCI */
 
+/* S5PV310 SDHCI setup */
+#ifdef CONFIG_S5PV310_SETUP_SDHCI
+extern char *s5pv310_hsmmc_clksrcs[4];
+
+extern void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev,
+					   void __iomem *r,
+					   struct mmc_ios *ios,
+					   struct mmc_card *card);
+
+static inline void s5pv310_default_sdhci0(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC
+	s3c_hsmmc0_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
+	s3c_hsmmc0_def_platdata.cfg_gpio = s5pv310_setup_sdhci0_cfg_gpio;
+	s3c_hsmmc0_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+#endif
+}
+
+static inline void s5pv310_default_sdhci1(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	s3c_hsmmc1_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
+	s3c_hsmmc1_def_platdata.cfg_gpio = s5pv310_setup_sdhci1_cfg_gpio;
+	s3c_hsmmc1_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+#endif
+}
+
+static inline void s5pv310_default_sdhci2(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	s3c_hsmmc2_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
+	s3c_hsmmc2_def_platdata.cfg_gpio = s5pv310_setup_sdhci2_cfg_gpio;
+	s3c_hsmmc2_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+#endif
+}
+
+static inline void s5pv310_default_sdhci3(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	s3c_hsmmc3_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
+	s3c_hsmmc3_def_platdata.cfg_gpio = s5pv310_setup_sdhci3_cfg_gpio;
+	s3c_hsmmc3_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+#endif
+}
+
+#else
+static inline void s5pv310_default_sdhci0(void) { }
+static inline void s5pv310_default_sdhci1(void) { }
+static inline void s5pv310_default_sdhci2(void) { }
+static inline void s5pv310_default_sdhci3(void) { }
+
+#endif /* CONFIG_S5PV310_SETUP_SDHCI */
+
 #endif /* __PLAT_S3C_SDHCI_H */
-- 
1.6.2.5

[PATCH 3/5] ARM: SAMSUNG: Modified to change of bus width and host caps

[Jeongbae Seo]

From: Hyuk Lee <hyuk1.lee@samsung.com>

This patch adds to change bus width and host capability of HSMMC,
when HSMMC is only configured with another value of bus width
and host capability from default one.

Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
---
 arch/arm/plat-samsung/dev-hsmmc.c  |    5 +++--
 arch/arm/plat-samsung/dev-hsmmc1.c |    5 +++--
 arch/arm/plat-samsung/dev-hsmmc2.c |    5 +++--
 arch/arm/plat-samsung/dev-hsmmc3.c |    5 ++++-
 4 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
index 9d2be09..5b8aacb 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -59,17 +59,18 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
 {
 	struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
 
-	set->max_width = pd->max_width;
 	set->cd_type = pd->cd_type;
 	set->ext_cd_init = pd->ext_cd_init;
 	set->ext_cd_cleanup = pd->ext_cd_cleanup;
 	set->ext_cd_gpio = pd->ext_cd_gpio;
 	set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
 
+	if (pd->max_width)
+		set->max_width = pd->max_width;
 	if (pd->cfg_gpio)
 		set->cfg_gpio = pd->cfg_gpio;
 	if (pd->cfg_card)
 		set->cfg_card = pd->cfg_card;
 	if (pd->host_caps)
-		set->host_caps = pd->host_caps;
+		set->host_caps |= pd->host_caps;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
index a6c8295..9b52828 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -59,17 +59,18 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
 {
 	struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
 
-	set->max_width = pd->max_width;
 	set->cd_type = pd->cd_type;
 	set->ext_cd_init = pd->ext_cd_init;
 	set->ext_cd_cleanup = pd->ext_cd_cleanup;
 	set->ext_cd_gpio = pd->ext_cd_gpio;
 	set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
 
+	if (pd->max_width)
+		set->max_width = pd->max_width;
 	if (pd->cfg_gpio)
 		set->cfg_gpio = pd->cfg_gpio;
 	if (pd->cfg_card)
 		set->cfg_card = pd->cfg_card;
 	if (pd->host_caps)
-		set->host_caps = pd->host_caps;
+		set->host_caps |= pd->host_caps;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
index cb0d714..df9e36b 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -60,17 +60,18 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
 {
 	struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata;
 
-	set->max_width = pd->max_width;
 	set->cd_type = pd->cd_type;
 	set->ext_cd_init = pd->ext_cd_init;
 	set->ext_cd_cleanup = pd->ext_cd_cleanup;
 	set->ext_cd_gpio = pd->ext_cd_gpio;
 	set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
 
+	if (pd->max_width)
+		set->max_width = pd->max_width;
 	if (pd->cfg_gpio)
 		set->cfg_gpio = pd->cfg_gpio;
 	if (pd->cfg_card)
 		set->cfg_card = pd->cfg_card;
 	if (pd->host_caps)
-		set->host_caps = pd->host_caps;
+		set->host_caps |= pd->host_caps;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c
index 335bc35..ca80897 100644
--- a/arch/arm/plat-samsung/dev-hsmmc3.c
+++ b/arch/arm/plat-samsung/dev-hsmmc3.c
@@ -63,15 +63,18 @@ void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
 {
 	struct s3c_sdhci_platdata *set = &s3c_hsmmc3_def_platdata;
 
-	set->max_width = pd->max_width;
 	set->cd_type = pd->cd_type;
 	set->ext_cd_init = pd->ext_cd_init;
 	set->ext_cd_cleanup = pd->ext_cd_cleanup;
 	set->ext_cd_gpio = pd->ext_cd_gpio;
 	set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
 
+	if (pd->max_width)
+		set->max_width = pd->max_width;
 	if (pd->cfg_gpio)
 		set->cfg_gpio = pd->cfg_gpio;
 	if (pd->cfg_card)
 		set->cfg_card = pd->cfg_card;
+	if (pd->host_caps)
+		set->host_caps |= pd->host_caps;
 }
-- 
1.6.2.5

[PATCH 4/5] ARM: SAMSUNG: Add clock types into platform data

[Jeongbae Seo]

This patch adds clock types into platform data to support
external clock divider instead of internal clock divider.
It is defined that what kinds of clock type is used in machine.

Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
---
 arch/arm/mach-s5pv310/mach-smdkc210.c      |    4 ++++
 arch/arm/mach-s5pv310/mach-smdkv310.c      |    4 ++++
 arch/arm/plat-samsung/dev-hsmmc.c          |    3 +++
 arch/arm/plat-samsung/dev-hsmmc1.c         |    3 +++
 arch/arm/plat-samsung/dev-hsmmc2.c         |    3 +++
 arch/arm/plat-samsung/dev-hsmmc3.c         |    3 +++
 arch/arm/plat-samsung/include/plat/sdhci.h |    7 +++++++
 7 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c
index e6d789f..54947f7 100644
--- a/arch/arm/mach-s5pv310/mach-smdkc210.c
+++ b/arch/arm/mach-s5pv310/mach-smdkc210.c
@@ -74,6 +74,7 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
 	.cd_type		= S3C_SDHCI_CD_GPIO,
 	.ext_cd_gpio		= S5PV310_GPK0(2),
 	.ext_cd_gpio_invert	= 1,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
 #ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
 	.max_width		= 8,
 	.host_caps		= MMC_CAP_8_BIT_DATA,
@@ -84,12 +85,14 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
 	.cd_type		= S3C_SDHCI_CD_GPIO,
 	.ext_cd_gpio		= S5PV310_GPK0(2),
 	.ext_cd_gpio_invert	= 1,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 
 static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
 	.cd_type		= S3C_SDHCI_CD_GPIO,
 	.ext_cd_gpio		= S5PV310_GPK2(2),
 	.ext_cd_gpio_invert	= 1,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
 #ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
 	.max_width		= 8,
 	.host_caps		= MMC_CAP_8_BIT_DATA,
@@ -100,6 +103,7 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
 	.cd_type		= S3C_SDHCI_CD_GPIO,
 	.ext_cd_gpio		= S5PV310_GPK2(2),
 	.ext_cd_gpio_invert	= 1,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 
 static struct platform_device *smdkc210_devices[] __initdata = {
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c
index c52b0c7..2ec287c 100644
--- a/arch/arm/mach-s5pv310/mach-smdkv310.c
+++ b/arch/arm/mach-s5pv310/mach-smdkv310.c
@@ -74,6 +74,7 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
 	.cd_type		= S3C_SDHCI_CD_GPIO,
 	.ext_cd_gpio		= S5PV310_GPK0(2),
 	.ext_cd_gpio_invert	= 1,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
 #ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
 	.max_width		= 8,
 	.host_caps		= MMC_CAP_8_BIT_DATA,
@@ -84,12 +85,14 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
 	.cd_type		= S3C_SDHCI_CD_GPIO,
 	.ext_cd_gpio		= S5PV310_GPK0(2),
 	.ext_cd_gpio_invert	= 1,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 
 static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
 	.cd_type		= S3C_SDHCI_CD_GPIO,
 	.ext_cd_gpio		= S5PV310_GPK2(2),
 	.ext_cd_gpio_invert	= 1,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
 #ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
 	.max_width		= 8,
 	.host_caps		= MMC_CAP_8_BIT_DATA,
@@ -100,6 +103,7 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
 	.cd_type		= S3C_SDHCI_CD_GPIO,
 	.ext_cd_gpio		= S5PV310_GPK2(2),
 	.ext_cd_gpio_invert	= 1,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 
 static struct platform_device *smdkv310_devices[] __initdata = {
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
index 5b8aacb..db7a65c 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -41,6 +41,7 @@ struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
 	.max_width	= 4,
 	.host_caps	= (MMC_CAP_4_BIT_DATA |
 			   MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+	.clk_type	= S3C_SDHCI_CLK_DIV_INTERNAL,
 };
 
 struct platform_device s3c_device_hsmmc0 = {
@@ -73,4 +74,6 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
 		set->cfg_card = pd->cfg_card;
 	if (pd->host_caps)
 		set->host_caps |= pd->host_caps;
+	if (pd->clk_type)
+		set->clk_type = pd->clk_type;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
index 9b52828..2497321 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -41,6 +41,7 @@ struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
 	.max_width	= 4,
 	.host_caps	= (MMC_CAP_4_BIT_DATA |
 			   MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+	.clk_type	= S3C_SDHCI_CLK_DIV_INTERNAL,
 };
 
 struct platform_device s3c_device_hsmmc1 = {
@@ -73,4 +74,6 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
 		set->cfg_card = pd->cfg_card;
 	if (pd->host_caps)
 		set->host_caps |= pd->host_caps;
+	if (pd->clk_type)
+		set->clk_type = pd->clk_type;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
index df9e36b..f60aedb 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -42,6 +42,7 @@ struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
 	.max_width	= 4,
 	.host_caps	= (MMC_CAP_4_BIT_DATA |
 			   MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+	.clk_type	= S3C_SDHCI_CLK_DIV_INTERNAL,
 };
 
 struct platform_device s3c_device_hsmmc2 = {
@@ -74,4 +75,6 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
 		set->cfg_card = pd->cfg_card;
 	if (pd->host_caps)
 		set->host_caps |= pd->host_caps;
+	if (pd->clk_type)
+		set->clk_type = pd->clk_type;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c
index ca80897..ede776f 100644
--- a/arch/arm/plat-samsung/dev-hsmmc3.c
+++ b/arch/arm/plat-samsung/dev-hsmmc3.c
@@ -45,6 +45,7 @@ struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
 	.max_width	= 4,
 	.host_caps	= (MMC_CAP_4_BIT_DATA |
 			   MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+	.clk_type	= S3C_SDHCI_CLK_DIV_INTERNAL,
 };
 
 struct platform_device s3c_device_hsmmc3 = {
@@ -77,4 +78,6 @@ void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
 		set->cfg_card = pd->cfg_card;
 	if (pd->host_caps)
 		set->host_caps |= pd->host_caps;
+	if (pd->clk_type)
+		set->clk_type = pd->clk_type;
 }
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index d92670a..85853f8 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -28,11 +28,17 @@ enum cd_types {
 	S3C_SDHCI_CD_PERMANENT,	/* no CD line, card permanently wired to host */
 };
 
+enum clk_types {
+	S3C_SDHCI_CLK_DIV_INTERNAL,	/* use mmc internal clock divider */
+	S3C_SDHCI_CLK_DIV_EXTERNAL,	/* use external clock divider */
+};
+
 /**
  * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
  * @max_width: The maximum number of data bits supported.
  * @host_caps: Standard MMC host capabilities bit field.
  * @cd_type: Type of Card Detection method (see cd_types enum above)
+ * @clk_type: Type of clock divider method (see clk_types enum above)
  * @ext_cd_init: Initialize external card detect subsystem. Called on
  *		 sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL.
  *		 notify_func argument is a callback to the sdhci-s3c driver
@@ -59,6 +65,7 @@ struct s3c_sdhci_platdata {
 	unsigned int	max_width;
 	unsigned int	host_caps;
 	enum cd_types	cd_type;
+	enum clk_types	clk_type;
 
 	char		**clocks;	/* set of clock sources */
 
-- 
1.6.2.5

[PATCH 5/5] sdhci-s3c: Add support no internal clock divider in host controller

[Jeongbae Seo]

From: Hyuk Lee <hyuk1.lee@samsung.com>

This patch adds to support no internal clock divider in SDHCI.
The external clock divider can be used to make a proper clock
because SDHCI doesn't support internal clock divider by itself.

Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
---
 drivers/mmc/host/sdhci-s3c.c |   63 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 63 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 71ad416..6160960 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -96,6 +96,13 @@ static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
 	unsigned int rate, max;
 	int clk;
 
+	/*
+	 * There is only one clock source(sclk) if there is no clock divider
+	 * in the host controller
+	 */
+	if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
+		return clk_round_rate(ourhost->clk_bus[2], UINT_MAX);
+
 	/* note, a reset will reset the clock source */
 
 	sdhci_s3c_check_sclk(host);
@@ -130,6 +137,15 @@ static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
 	if (!clksrc)
 		return UINT_MAX;
 
+	/*
+	 * There is only one clock source(sclk) if there is no clock divider
+	 * in the host controller
+	 */
+	if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
+		rate = clk_round_rate(clksrc, wanted);
+		return wanted - rate;
+	}
+
 	rate = clk_get_rate(clksrc);
 
 	for (div = 1; div < 256; div *= 2) {
@@ -159,6 +175,7 @@ static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
 	int best_src = 0;
 	int src;
 	u32 ctrl;
+	unsigned int timeout;
 
 	/* don't bother if the clock is going off. */
 	if (clock == 0)
@@ -204,6 +221,35 @@ static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
 			(ourhost->pdata->cfg_card)(ourhost->pdev, host->ioaddr,
 						   &ios, NULL);
 	}
+
+	/*
+	 * There is only one clock source(sclk) if there is no clock divider
+	 * in the host controller
+	 */
+	if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
+		writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
+		clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
+
+		writew(SDHCI_CLOCK_INT_EN, host->ioaddr + SDHCI_CLOCK_CONTROL);
+
+		/* Wait max 20 ms */
+		timeout = 20;
+		while (!((sdhci_readw(host, SDHCI_CLOCK_CONTROL))
+			& SDHCI_CLOCK_INT_STABLE)) {
+			if (timeout == 0) {
+				printk(KERN_ERR "%s: clock never stabilised.\n"
+						, mmc_hostname(host->mmc));
+				return;
+			}
+			timeout--;
+			mdelay(1);
+		}
+
+		writew(SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_CARD_EN,
+				host->ioaddr + SDHCI_CLOCK_CONTROL);
+
+		host->clock = clock;
+	}
 }
 
 /**
@@ -221,6 +267,13 @@ static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
 	unsigned int delta, min = UINT_MAX;
 	int src;
 
+	/*
+	 * There is only one clock source(sclk) if there is no clock divider
+	 * in the host controller
+	 */
+	if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
+		return clk_round_rate(ourhost->clk_bus[2], 400000);
+
 	for (src = 0; src < MAX_BUS_CLK; src++) {
 		delta = sdhci_s3c_consider_clock(ourhost, src, 0);
 		if (delta == UINT_MAX)
@@ -425,6 +478,16 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	/* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
 	host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
 
+	/*
+	 * If controller does not have internal clock divider,
+	 * we need to use another method with setup a quirk.
+	 */
+	if (pdata->clk_type)
+		host->quirks |= SDHCI_QUIRK_NONSTANDARD_CLOCK;
+
+	if (pdata->host_caps)
+		host->mmc->caps |= pdata->host_caps;
+
 	ret = sdhci_add_host(host);
 	if (ret) {
 		dev_err(dev, "sdhci_add_host() failed\n");
-- 
1.6.2.5

[PATCH 5/5] sdhci-s3c: Add support no internal clock divider in host controller

[Kyungmin Park]

Hi,

Well there are two implementations. and no conclusion yet.
as s5pc210 don't support internal SDHCI clock, DMC overrides the
function operation itself when s5pc210. System LSI use the quirks.

Choose any one from MMC maintainer.

Thank you,
Kyungmin Park

On Thu, Sep 16, 2010 at 5:37 PM, Jeongbae Seo <jeongbae.seo@samsung.com> wrote:
> From: Hyuk Lee <hyuk1.lee@samsung.com>
>
> This patch adds to support no internal clock divider in SDHCI.
> The external clock divider can be used to make a proper clock
> because SDHCI doesn't support internal clock divider by itself.
>
> Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
> Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
> ---
> ?drivers/mmc/host/sdhci-s3c.c | ? 63 ++++++++++++++++++++++++++++++++++++++++++
> ?1 files changed, 63 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> index 71ad416..6160960 100644
> --- a/drivers/mmc/host/sdhci-s3c.c
> +++ b/drivers/mmc/host/sdhci-s3c.c
> @@ -96,6 +96,13 @@ static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
> ? ? ? ?unsigned int rate, max;
> ? ? ? ?int clk;
>
> + ? ? ? /*
> + ? ? ? ?* There is only one clock source(sclk) if there is no clock divider
> + ? ? ? ?* in the host controller
> + ? ? ? ?*/
> + ? ? ? if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
> + ? ? ? ? ? ? ? return clk_round_rate(ourhost->clk_bus[2], UINT_MAX);
No hard-coded index.
> +
> ? ? ? ?/* note, a reset will reset the clock source */
>
> ? ? ? ?sdhci_s3c_check_sclk(host);
> @@ -130,6 +137,15 @@ static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
> ? ? ? ?if (!clksrc)
> ? ? ? ? ? ? ? ?return UINT_MAX;
>
> + ? ? ? /*
> + ? ? ? ?* There is only one clock source(sclk) if there is no clock divider
> + ? ? ? ?* in the host controller
> + ? ? ? ?*/
> + ? ? ? if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
> + ? ? ? ? ? ? ? rate = clk_round_rate(clksrc, wanted);
> + ? ? ? ? ? ? ? return wanted - rate;
> + ? ? ? }
> +
> ? ? ? ?rate = clk_get_rate(clksrc);
>
> ? ? ? ?for (div = 1; div < 256; div *= 2) {
> @@ -159,6 +175,7 @@ static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
> ? ? ? ?int best_src = 0;
> ? ? ? ?int src;
> ? ? ? ?u32 ctrl;
> + ? ? ? unsigned int timeout;
>
> ? ? ? ?/* don't bother if the clock is going off. */
> ? ? ? ?if (clock == 0)
> @@ -204,6 +221,35 @@ static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
> ? ? ? ? ? ? ? ? ? ? ? ?(ourhost->pdata->cfg_card)(ourhost->pdev, host->ioaddr,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &ios, NULL);
> ? ? ? ?}
> +
> + ? ? ? /*
> + ? ? ? ?* There is only one clock source(sclk) if there is no clock divider
> + ? ? ? ?* in the host controller
> + ? ? ? ?*/
> + ? ? ? if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
> + ? ? ? ? ? ? ? writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
> + ? ? ? ? ? ? ? clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
> +
> + ? ? ? ? ? ? ? writew(SDHCI_CLOCK_INT_EN, host->ioaddr + SDHCI_CLOCK_CONTROL);
> +
> + ? ? ? ? ? ? ? /* Wait max 20 ms */
> + ? ? ? ? ? ? ? timeout = 20;
> + ? ? ? ? ? ? ? while (!((sdhci_readw(host, SDHCI_CLOCK_CONTROL))
> + ? ? ? ? ? ? ? ? ? ? ? & SDHCI_CLOCK_INT_STABLE)) {
> + ? ? ? ? ? ? ? ? ? ? ? if (timeout == 0) {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? printk(KERN_ERR "%s: clock never stabilised.\n"
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? , mmc_hostname(host->mmc));
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? return;
> + ? ? ? ? ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? ? ? ? ? timeout--;
> + ? ? ? ? ? ? ? ? ? ? ? mdelay(1);
> + ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? writew(SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_CARD_EN,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? host->ioaddr + SDHCI_CLOCK_CONTROL);
> +
> + ? ? ? ? ? ? ? host->clock = clock;
> + ? ? ? }
> ?}
>
> ?/**
> @@ -221,6 +267,13 @@ static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
> ? ? ? ?unsigned int delta, min = UINT_MAX;
> ? ? ? ?int src;
>
> + ? ? ? /*
> + ? ? ? ?* There is only one clock source(sclk) if there is no clock divider
> + ? ? ? ?* in the host controller
> + ? ? ? ?*/
> + ? ? ? if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
> + ? ? ? ? ? ? ? return clk_round_rate(ourhost->clk_bus[2], 400000);
ditto
> +
> ? ? ? ?for (src = 0; src < MAX_BUS_CLK; src++) {
> ? ? ? ? ? ? ? ?delta = sdhci_s3c_consider_clock(ourhost, src, 0);
> ? ? ? ? ? ? ? ?if (delta == UINT_MAX)
> @@ -425,6 +478,16 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
> ? ? ? ?/* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
> ? ? ? ?host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
>
> + ? ? ? /*
> + ? ? ? ?* If controller does not have internal clock divider,
> + ? ? ? ?* we need to use another method with setup a quirk.
> + ? ? ? ?*/
> + ? ? ? if (pdata->clk_type)
check the clk_type with external
> + ? ? ? ? ? ? ? host->quirks |= SDHCI_QUIRK_NONSTANDARD_CLOCK;
> +
> + ? ? ? if (pdata->host_caps)
> + ? ? ? ? ? ? ? host->mmc->caps |= pdata->host_caps;
> +
> ? ? ? ?ret = sdhci_add_host(host);
> ? ? ? ?if (ret) {
> ? ? ? ? ? ? ? ?dev_err(dev, "sdhci_add_host() failed\n");
> --
> 1.6.2.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>

[PATCH 1/5] ARM: S5PV310: Add HSMMC support and SDHCI configuration

[Kyungmin Park]

On Thu, Sep 16, 2010 at 5:36 PM, Jeongbae Seo <jeongbae.seo@samsung.com> wrote:
> From: Hyuk Lee <hyuk1.lee@samsung.com>
>
> This patch adds to support HSMMC for S5PV310 and S5PC210 and setup for
> HSMMC host controller and also related GPIO.
> At most 4 channel can be used at the same time.
> A user can configure SDHCI data bus as 8bit or 4bit.
>
> Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
> Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
> ---
> ?arch/arm/mach-s5pv310/Kconfig ? ? ? ? ? ?| ? 39 ++++++++
> ?arch/arm/mach-s5pv310/Makefile ? ? ? ? ? | ? ?2 +
> ?arch/arm/mach-s5pv310/setup-sdhci-gpio.c | ?156 ++++++++++++++++++++++++++++++
> ?arch/arm/mach-s5pv310/setup-sdhci.c ? ? ?| ? 69 +++++++++++++
> ?4 files changed, 266 insertions(+), 0 deletions(-)
> ?create mode 100644 arch/arm/mach-s5pv310/setup-sdhci-gpio.c
> ?create mode 100644 arch/arm/mach-s5pv310/setup-sdhci.c
>
> diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
> index 9ac29fe..6a07968 100644
> --- a/arch/arm/mach-s5pv310/Kconfig
> +++ b/arch/arm/mach-s5pv310/Kconfig
> @@ -25,6 +25,17 @@ config S5PV310_SETUP_I2C2
> ? ? ? ?help
> ? ? ? ? ?Common setup code for i2c bus 2.
>
> +config S5PV310_SETUP_SDHCI
> + ? ? ? bool
> + ? ? ? select S5PV310_SETUP_SDHCI_GPIO
> + ? ? ? help
> + ? ? ? ? Internal helper functions for S5PV310 based SDHCI systems.
> +
> +config S5PV310_SETUP_SDHCI_GPIO
> + ? ? ? bool
> + ? ? ? help
> + ? ? ? ? Common setup code for SDHCI gpio.
> +
> ?# machine support
>
> ?menu "S5PC210 Machines"
> @@ -33,6 +44,11 @@ config MACH_SMDKC210
> ? ? ? ?bool "SMDKC210"
> ? ? ? ?select CPU_S5PV310
> ? ? ? ?select ARCH_SPARSEMEM_ENABLE
> + ? ? ? select S3C_DEV_HSMMC
> + ? ? ? select S3C_DEV_HSMMC1
> + ? ? ? select S3C_DEV_HSMMC2
> + ? ? ? select S3C_DEV_HSMMC3
> + ? ? ? select S5PV310_SETUP_SDHCI
> ? ? ? ?help
> ? ? ? ? ?Machine support for Samsung SMDKC210
> ? ? ? ? ?S5PC210(MCP) is one of package option of S5PV310
> @@ -53,9 +69,32 @@ config MACH_SMDKV310
> ? ? ? ?bool "SMDKV310"
> ? ? ? ?select CPU_S5PV310
> ? ? ? ?select ARCH_SPARSEMEM_ENABLE
> + ? ? ? select S3C_DEV_HSMMC
> + ? ? ? select S3C_DEV_HSMMC1
> + ? ? ? select S3C_DEV_HSMMC2
> + ? ? ? select S3C_DEV_HSMMC3
> + ? ? ? select S5PV310_SETUP_SDHCI
> ? ? ? ?help
> ? ? ? ? ?Machine support for Samsung SMDKV310
>
> ?endmenu
>
> +comment "Configuration for HSMMC bus width"
> +
> +menu "Use 8-bit bus width"
> +
> +config S5PV310_SDHCI_CH0_8BIT
> + ? ? ? bool "Channel 0 with 8-bit bus"
> + ? ? ? help
> + ? ? ? ? Support HSMMC Channel 0 8-bit bus.
> + ? ? ? ? If selected, Channel 1 is disabled.
> +
> +config S5PV310_SDHCI_CH2_8BIT
> + ? ? ? bool "Channel 2 with 8-bit bus"
> + ? ? ? help
> + ? ? ? ? Support HSMMC Channel 2 8-bit bus.
> + ? ? ? ? If selected, Channel 3 is disabled.

I think it's not needed since most boards have fixed bandwith and
cfg_gpio handle it regardless these configuration.
Also we use the select state if needed, e.g., when MMC0 uses
8-buswidth then don't select MMC1.
I saw the SMDK board use this configuration. but just choose bandwidth 4 or 8.

Others good.

Thank you,
Kyungmin Park
> +
> +endmenu
> +
> ?endif
> diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
> index aefb14f..c89b6b0 100644
> --- a/arch/arm/mach-s5pv310/Makefile
> +++ b/arch/arm/mach-s5pv310/Makefile
> @@ -29,3 +29,5 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210) ? ? += mach-universal_c210.o
>
> ?obj-$(CONFIG_S5PV310_SETUP_I2C1) ? ? ? += setup-i2c1.o
> ?obj-$(CONFIG_S5PV310_SETUP_I2C2) ? ? ? += setup-i2c2.o
> +obj-$(CONFIG_S5PV310_SETUP_SDHCI) ? ? ?+= setup-sdhci.o
> +obj-$(CONFIG_S5PV310_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
> diff --git a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
> new file mode 100644
> index 0000000..8db8c81
> --- /dev/null
> +++ b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
> @@ -0,0 +1,156 @@
> +/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
> + *
> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> + * ? ? ? ? ? ? http://www.samsung.com/
> + *
> + * S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/interrupt.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <linux/gpio.h>
> +#include <linux/mmc/host.h>
> +#include <linux/mmc/card.h>
> +
> +#include <plat/gpio-cfg.h>
> +#include <plat/regs-sdhci.h>
> +#include <plat/sdhci.h>
> +
> +void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
> +{
> + ? ? ? struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
> + ? ? ? unsigned int gpio;
> +
> + ? ? ? /* Set all the necessary GPK0[0:1] pins to special-function 2 */
> + ? ? ? for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) {
> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> + ? ? ? ? ? ? ? s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> + ? ? ? }
> +
> + ? ? ? switch (width) {
> + ? ? ? case 8:
> + ? ? ? ? ? ? ? for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
> + ? ? ? ? ? ? ? ? ? ? ? /* Data pin GPK1[3:6] to special-funtion 3 */
> + ? ? ? ? ? ? ? ? ? ? ? s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
> + ? ? ? ? ? ? ? ? ? ? ? s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> +
> + ? ? ? ? ? ? ? ? ? ? ? /* Setup Drive Strength */
> + ? ? ? ? ? ? ? ? ? ? ? s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> + ? ? ? ? ? ? ? }
> + ? ? ? case 4:
> + ? ? ? ? ? ? ? for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) {
> + ? ? ? ? ? ? ? ? ? ? ? /* Data pin GPK0[3:6] to special-funtion 2 */
> + ? ? ? ? ? ? ? ? ? ? ? s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> + ? ? ? ? ? ? ? ? ? ? ? s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> +
> + ? ? ? ? ? ? ? ? ? ? ? /* Setup Drive Strength */
> + ? ? ? ? ? ? ? ? ? ? ? s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> + ? ? ? ? ? ? ? }
> + ? ? ? default:
> + ? ? ? ? ? ? ? break;
> + ? ? ? }
> +
> + ? ? ? if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2));
> + ? ? ? ? ? ? ? s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP);
> + ? ? ? }
> +}
> +
> +void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
> +{
> + ? ? ? struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
> + ? ? ? unsigned int gpio;
> +
> + ? ? ? /* Set all the necessary GPK1[0:1] pins to special-function 2 */
> + ? ? ? for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) {
> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> + ? ? ? ? ? ? ? s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> + ? ? ? }
> +
> + ? ? ? for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
> + ? ? ? ? ? ? ? /* Data pin GPK1[3:6] to special-function 2 */
> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> + ? ? ? ? ? ? ? s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> +
> + ? ? ? ? ? ? ? /* Setup Drive Strength */
> + ? ? ? ? ? ? ? s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> + ? ? ? }
> +
> + ? ? ? if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2));
> + ? ? ? ? ? ? ? s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP);
> + ? ? ? }
> +}
> +
> +void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
> +{
> + ? ? ? struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
> + ? ? ? unsigned int gpio;
> +
> + ? ? ? /* Set all the necessary GPK2[0:1] pins to special-function 2 */
> + ? ? ? for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) {
> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> + ? ? ? ? ? ? ? s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> + ? ? ? }
> +
> + ? ? ? switch (width) {
> + ? ? ? case 8:
> + ? ? ? ? ? ? ? for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
> + ? ? ? ? ? ? ? ? ? ? ? /* Data pin GPK3[3:6] to special-function 3 */
> + ? ? ? ? ? ? ? ? ? ? ? s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
> + ? ? ? ? ? ? ? ? ? ? ? s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> +
> + ? ? ? ? ? ? ? ? ? ? ? /* Setup Drive Strength */
> + ? ? ? ? ? ? ? ? ? ? ? s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> + ? ? ? ? ? ? ? }
> + ? ? ? case 4:
> + ? ? ? ? ? ? ? for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) {
> + ? ? ? ? ? ? ? ? ? ? ? /* Data pin GPK2[3:6] to special-function 2 */
> + ? ? ? ? ? ? ? ? ? ? ? s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> + ? ? ? ? ? ? ? ? ? ? ? s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> +
> + ? ? ? ? ? ? ? ? ? ? ? /* Setup Drive Strength */
> + ? ? ? ? ? ? ? ? ? ? ? s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> + ? ? ? ? ? ? ? }
> + ? ? ? default:
> + ? ? ? ? ? ? ? break;
> + ? ? ? }
> +
> + ? ? ? if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2));
> + ? ? ? ? ? ? ? s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP);
> + ? ? ? }
> +}
> +
> +void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
> +{
> + ? ? ? struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
> + ? ? ? unsigned int gpio;
> +
> + ? ? ? /* Set all the necessary GPK3[0:1] pins to special-function 2 */
> + ? ? ? for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) {
> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> + ? ? ? ? ? ? ? s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> + ? ? ? }
> +
> + ? ? ? for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
> + ? ? ? ? ? ? ? /* Data pin GPK3[3:6] to special-function 2 */
> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> + ? ? ? ? ? ? ? s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> +
> + ? ? ? ? ? ? ? /* Setup Drive Strength */
> + ? ? ? ? ? ? ? s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> + ? ? ? }
> +
> + ? ? ? if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2));
> + ? ? ? ? ? ? ? s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP);
> + ? ? ? }
> +}
> diff --git a/arch/arm/mach-s5pv310/setup-sdhci.c b/arch/arm/mach-s5pv310/setup-sdhci.c
> new file mode 100644
> index 0000000..db8358f
> --- /dev/null
> +++ b/arch/arm/mach-s5pv310/setup-sdhci.c
> @@ -0,0 +1,69 @@
> +/* linux/arch/arm/mach-s5pv310/setup-sdhci.c
> + *
> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> + * ? ? ? ? ? ? http://www.samsung.com/
> + *
> + * S5PV310 - Helper functions for settign up SDHCI device(s) (HSMMC)
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/interrupt.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#include <linux/mmc/card.h>
> +#include <linux/mmc/host.h>
> +
> +#include <plat/regs-sdhci.h>
> +
> +/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
> +
> +char *s5pv310_hsmmc_clksrcs[4] = {
> + ? ? ? [0] = NULL,
> + ? ? ? [1] = NULL,
> + ? ? ? [2] = "sclk_mmc", ? ? ? /* mmc_bus */
> + ? ? ? [3] = NULL,
> +};
> +
> +void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct mmc_ios *ios, struct mmc_card *card)
> +{
> + ? ? ? u32 ctrl2, ctrl3;
> +
> + ? ? ? /* don't need to alter anything acording to card-type */
> +
> + ? ? ? ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
> +
> + ? ? ? /* select base clock source to HCLK */
> +
> + ? ? ? ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
> +
> + ? ? ? /*
> + ? ? ? ?* clear async mode, enable conflict mask, rx feedback ctrl, SD
> + ? ? ? ?* clk hold and no use debounce count
> + ? ? ? ?*/
> +
> + ? ? ? ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
> + ? ? ? ? ? ? ? ? S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
> + ? ? ? ? ? ? ? ? S3C_SDHCI_CTRL2_ENFBCLKRX |
> + ? ? ? ? ? ? ? ? S3C_SDHCI_CTRL2_DFCNT_NONE |
> + ? ? ? ? ? ? ? ? S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
> +
> + ? ? ? /* Tx and Rx feedback clock delay control */
> +
> + ? ? ? if (ios->clock < 25 * 1000000)
> + ? ? ? ? ? ? ? ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
> + ? ? ? ? ? ? ? ? ? ? ? ?S3C_SDHCI_CTRL3_FCSEL2 |
> + ? ? ? ? ? ? ? ? ? ? ? ?S3C_SDHCI_CTRL3_FCSEL1 |
> + ? ? ? ? ? ? ? ? ? ? ? ?S3C_SDHCI_CTRL3_FCSEL0);
> + ? ? ? else
> + ? ? ? ? ? ? ? ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
> +
> + ? ? ? writel(ctrl2, r + S3C_SDHCI_CONTROL2);
> + ? ? ? writel(ctrl3, r + S3C_SDHCI_CONTROL3);
> +}
> --
> 1.6.2.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>

[PATCH 1/5] ARM: S5PV310: Add HSMMC support and SDHCI configuration

[Kukjin Kim]

Kyungmin Park wrote:
> 
> On Thu, Sep 16, 2010 at 5:36 PM, Jeongbae Seo <jeongbae.seo@samsung.com>
> wrote:
> > From: Hyuk Lee <hyuk1.lee@samsung.com>
> >
> > This patch adds to support HSMMC for S5PV310 and S5PC210 and setup for
> > HSMMC host controller and also related GPIO.
> > At most 4 channel can be used at the same time.
> > A user can configure SDHCI data bus as 8bit or 4bit.
> >
> > Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
> > Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
> > ---
> > ?arch/arm/mach-s5pv310/Kconfig ? ? ? ? ? ?| ? 39 ++++++++
> > ?arch/arm/mach-s5pv310/Makefile ? ? ? ? ? | ? ?2 +
> > ?arch/arm/mach-s5pv310/setup-sdhci-gpio.c | ?156
> ++++++++++++++++++++++++++++++
> > ?arch/arm/mach-s5pv310/setup-sdhci.c ? ? ?| ? 69 +++++++++++++
> > ?4 files changed, 266 insertions(+), 0 deletions(-)
> > ?create mode 100644 arch/arm/mach-s5pv310/setup-sdhci-gpio.c
> > ?create mode 100644 arch/arm/mach-s5pv310/setup-sdhci.c
> >
> > diff --git a/arch/arm/mach-s5pv310/Kconfig
b/arch/arm/mach-s5pv310/Kconfig
> > index 9ac29fe..6a07968 100644
> > --- a/arch/arm/mach-s5pv310/Kconfig
> > +++ b/arch/arm/mach-s5pv310/Kconfig
> > @@ -25,6 +25,17 @@ config S5PV310_SETUP_I2C2
> > ? ? ? ?help
> > ? ? ? ? ?Common setup code for i2c bus 2.
> >
> > +config S5PV310_SETUP_SDHCI
> > + ? ? ? bool
> > + ? ? ? select S5PV310_SETUP_SDHCI_GPIO
> > + ? ? ? help
> > + ? ? ? ? Internal helper functions for S5PV310 based SDHCI systems.
> > +
> > +config S5PV310_SETUP_SDHCI_GPIO
> > + ? ? ? bool
> > + ? ? ? help
> > + ? ? ? ? Common setup code for SDHCI gpio.
> > +
> > ?# machine support
> >
> > ?menu "S5PC210 Machines"
> > @@ -33,6 +44,11 @@ config MACH_SMDKC210
> > ? ? ? ?bool "SMDKC210"
> > ? ? ? ?select CPU_S5PV310
> > ? ? ? ?select ARCH_SPARSEMEM_ENABLE
> > + ? ? ? select S3C_DEV_HSMMC
> > + ? ? ? select S3C_DEV_HSMMC1
> > + ? ? ? select S3C_DEV_HSMMC2
> > + ? ? ? select S3C_DEV_HSMMC3
> > + ? ? ? select S5PV310_SETUP_SDHCI
> > ? ? ? ?help
> > ? ? ? ? ?Machine support for Samsung SMDKC210
> > ? ? ? ? ?S5PC210(MCP) is one of package option of S5PV310
> > @@ -53,9 +69,32 @@ config MACH_SMDKV310
> > ? ? ? ?bool "SMDKV310"
> > ? ? ? ?select CPU_S5PV310
> > ? ? ? ?select ARCH_SPARSEMEM_ENABLE
> > + ? ? ? select S3C_DEV_HSMMC
> > + ? ? ? select S3C_DEV_HSMMC1
> > + ? ? ? select S3C_DEV_HSMMC2
> > + ? ? ? select S3C_DEV_HSMMC3
> > + ? ? ? select S5PV310_SETUP_SDHCI
> > ? ? ? ?help
> > ? ? ? ? ?Machine support for Samsung SMDKV310
> >
> > ?endmenu
> >
> > +comment "Configuration for HSMMC bus width"
> > +
> > +menu "Use 8-bit bus width"
> > +
> > +config S5PV310_SDHCI_CH0_8BIT
> > + ? ? ? bool "Channel 0 with 8-bit bus"
> > + ? ? ? help
> > + ? ? ? ? Support HSMMC Channel 0 8-bit bus.
> > + ? ? ? ? If selected, Channel 1 is disabled.
> > +
> > +config S5PV310_SDHCI_CH2_8BIT
> > + ? ? ? bool "Channel 2 with 8-bit bus"
> > + ? ? ? help
> > + ? ? ? ? Support HSMMC Channel 2 8-bit bus.
> > + ? ? ? ? If selected, Channel 3 is disabled.
> 
> I think it's not needed since most boards have fixed bandwith and
> cfg_gpio handle it regardless these configuration.
> Also we use the select state if needed, e.g., when MMC0 uses
> 8-buswidth then don't select MMC1.
> I saw the SMDK board use this configuration. but just choose bandwidth 4
or 8.
> 
Hmm...

If it can be supported 4bit or 8bit option on each board, should be added
above configuration for selecting it.

Mr. Seo, it would be nice if you could add un-selection CH1 or CH3 when
selecting 8bit support later.

Anyway, looks ok to me now..will apply.

> Others good.
> 
(snip)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 5/5] sdhci-s3c: Add support no internal clock divider in host controller

[Kukjin Kim]

Kyungmin Park wrote:
> 
> Hi,
> 
> Well there are two implementations. and no conclusion yet.
> as s5pc210 don't support internal SDHCI clock, DMC overrides the
> function operation itself when s5pc210. System LSI use the quirks.
> 
I think, this approach is better. Because no added new quirk and no override any function operation.

Actually, used SDHCI_QUIRK_NONSTANDARD_CLOCK quirk to support SDMMC host controller of S5PV310/S5PC210 which does not have internal clock divider in it.

But need to re-submit to two separate patches which one is adding support no internal clock divider and other is adding 'pdata->host_caps' feature.

Chris, how do you think this approach?

> Choose any one from MMC maintainer.
> 
> Thank you,
> Kyungmin Park
> 
> On Thu, Sep 16, 2010 at 5:37 PM, Jeongbae Seo <jeongbae.seo@samsung.com>
> wrote:
> > From: Hyuk Lee <hyuk1.lee@samsung.com>
> >
> > This patch adds to support no internal clock divider in SDHCI.
> > The external clock divider can be used to make a proper clock
> > because SDHCI doesn't support internal clock divider by itself.
> >
> > Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
> > Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
> > ---
> >  drivers/mmc/host/sdhci-s3c.c |   63
> ++++++++++++++++++++++++++++++++++++++++++
> >  1 files changed, 63 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> > index 71ad416..6160960 100644
> > --- a/drivers/mmc/host/sdhci-s3c.c
> > +++ b/drivers/mmc/host/sdhci-s3c.c
> > @@ -96,6 +96,13 @@ static unsigned int sdhci_s3c_get_max_clk(struct
> sdhci_host *host)
> >        unsigned int rate, max;
> >        int clk;
> >
> > +       /*
> > +        * There is only one clock source(sclk) if there is no clock divider
> > +        * in the host controller
> > +        */
> > +       if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
> > +               return clk_round_rate(ourhost->clk_bus[2], UINT_MAX);
> No hard-coded index.

Always, it is #2.

(snip)

> > +       /*
> > +        * There is only one clock source(sclk) if there is no clock divider
> > +        * in the host controller
> > +        */
> > +       if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
> > +               return clk_round_rate(ourhost->clk_bus[2], 400000);
> ditto

Same.

(snip)

> > +       /*
> > +        * If controller does not have internal clock divider,
> > +        * we need to use another method with setup a quirk.
> > +        */
> > +       if (pdata->clk_type)
> check the clk_type with external

I think no need to check it.
Because in the general case, pdata->clk_type is 0, S3C_SDHCI_CLK_DIV_INTERNAL.

But if we want to add new another clock type, checking it is better...but no need now.

> > +               host->quirks |= SDHCI_QUIRK_NONSTANDARD_CLOCK;
> > +
> > +       if (pdata->host_caps)
> > +               host->mmc->caps |= pdata->host_caps;
> > +
> >        ret = sdhci_add_host(host);
> >        if (ret) {
> >                dev_err(dev, "sdhci_add_host() failed\n");
> > --

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 5/5] sdhci-s3c: Add support no internal clock divider in host controller

[Kukjin Kim]

Jeongbae Seo wrote:
> 
> From: Hyuk Lee <hyuk1.lee@samsung.com>
> 
> This patch adds to support no internal clock divider in SDHCI.
> The external clock divider can be used to make a proper clock
> because SDHCI doesn't support internal clock divider by itself.
> 
Hi,

Please add Chris Ball <cjb@laptop.org> who is a maintainer of MMC subsystem
in Cc later.

> Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
> Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
> ---
>  drivers/mmc/host/sdhci-s3c.c |   63
> ++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 63 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> index 71ad416..6160960 100644
> --- a/drivers/mmc/host/sdhci-s3c.c
> +++ b/drivers/mmc/host/sdhci-s3c.c
> @@ -96,6 +96,13 @@ static unsigned int sdhci_s3c_get_max_clk(struct
> sdhci_host *host)
>  	unsigned int rate, max;
>  	int clk;
> 
> +	/*
> +	 * There is only one clock source(sclk) if there is no clock divider
> +	 * in the host controller
> +	 */
> +	if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
> +		return clk_round_rate(ourhost->clk_bus[2], UINT_MAX);
> +
>  	/* note, a reset will reset the clock source */
> 
>  	sdhci_s3c_check_sclk(host);
> @@ -130,6 +137,15 @@ static unsigned int sdhci_s3c_consider_clock(struct
> sdhci_s3c *ourhost,
>  	if (!clksrc)
>  		return UINT_MAX;
> 
> +	/*
> +	 * There is only one clock source(sclk) if there is no clock divider
> +	 * in the host controller
> +	 */
> +	if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
> +		rate = clk_round_rate(clksrc, wanted);
> +		return wanted - rate;
> +	}
> +
>  	rate = clk_get_rate(clksrc);
> 
>  	for (div = 1; div < 256; div *= 2) {
> @@ -159,6 +175,7 @@ static void sdhci_s3c_set_clock(struct sdhci_host
*host,
> unsigned int clock)
>  	int best_src = 0;
>  	int src;
>  	u32 ctrl;
> +	unsigned int timeout;
> 
>  	/* don't bother if the clock is going off. */
>  	if (clock == 0)
> @@ -204,6 +221,35 @@ static void sdhci_s3c_set_clock(struct sdhci_host
*host,
> unsigned int clock)
>  			(ourhost->pdata->cfg_card)(ourhost->pdev, host-
> >ioaddr,
>  						   &ios, NULL);
>  	}
> +
> +	/*
> +	 * There is only one clock source(sclk) if there is no clock divider
> +	 * in the host controller
> +	 */
> +	if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
> +		writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
> +		clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
> +
> +		writew(SDHCI_CLOCK_INT_EN, host->ioaddr +
> SDHCI_CLOCK_CONTROL);
> +
> +		/* Wait max 20 ms */
> +		timeout = 20;
> +		while (!((sdhci_readw(host, SDHCI_CLOCK_CONTROL))
> +			& SDHCI_CLOCK_INT_STABLE)) {
> +			if (timeout == 0) {
> +				printk(KERN_ERR "%s: clock never
> stabilised.\n"
> +						, mmc_hostname(host-
> >mmc));
> +				return;
> +			}
> +			timeout--;
> +			mdelay(1);
> +		}
> +
> +		writew(SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_CARD_EN,
> +				host->ioaddr + SDHCI_CLOCK_CONTROL);
> +
> +		host->clock = clock;
> +	}
>  }
> 
>  /**
> @@ -221,6 +267,13 @@ static unsigned int sdhci_s3c_get_min_clock(struct
> sdhci_host *host)
>  	unsigned int delta, min = UINT_MAX;
>  	int src;
> 
> +	/*
> +	 * There is only one clock source(sclk) if there is no clock divider
> +	 * in the host controller
> +	 */
> +	if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
> +		return clk_round_rate(ourhost->clk_bus[2], 400000);
> +
>  	for (src = 0; src < MAX_BUS_CLK; src++) {
>  		delta = sdhci_s3c_consider_clock(ourhost, src, 0);
>  		if (delta == UINT_MAX)
> @@ -425,6 +478,16 @@ static int __devinit sdhci_s3c_probe(struct
> platform_device *pdev)
>  	/* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
>  	host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
> 
> +	/*
> +	 * If controller does not have internal clock divider,
> +	 * we need to use another method with setup a quirk.
> +	 */
> +	if (pdata->clk_type)
> +		host->quirks |= SDHCI_QUIRK_NONSTANDARD_CLOCK;
> +
> +	if (pdata->host_caps)
> +		host->mmc->caps |= pdata->host_caps;
> +

If you want to add above feature, please separate it...

(snip)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 5/5] sdhci-s3c: Add support no internal clock divider in host controller

[???]

Kukjin Kim wrote:

> > +	/*
> > +	 * If controller does not have internal clock divider,
> > +	 * we need to use another method with setup a quirk.
> > +	 */
> > +	if (pdata->clk_type)
> > +		host->quirks |= SDHCI_QUIRK_NONSTANDARD_CLOCK;
> > +
> > +	if (pdata->host_caps)
> > +		host->mmc->caps |= pdata->host_caps;
> > +
> 
> If you want to add above feature, please separate it...

Okay, I'll make this patch to two things.

Thanks,
Jeongbae Seo

> -----Original Message-----
> From: Kukjin Kim [mailto:kgene.kim at samsung.com]
> Sent: Friday, September 17, 2010 10:22 AM
> To: 'Jeongbae Seo'; linux-arm-kernel at lists.infradead.org; linux-samsung-
> soc at vger.kernel.org; linux-mmc at vger.kernel.org
> Cc: ben-linux at fluff.org; akpm at linux-foundation.org; 'Hyuk Lee'; 'Chris
> Ball'
> Subject: RE: [PATCH 5/5] sdhci-s3c: Add support no internal clock divider
> in host controller
> 
> Jeongbae Seo wrote:
> >
> > From: Hyuk Lee <hyuk1.lee@samsung.com>
> >
> > This patch adds to support no internal clock divider in SDHCI.
> > The external clock divider can be used to make a proper clock
> > because SDHCI doesn't support internal clock divider by itself.
> >
> Hi,
> 
> Please add Chris Ball <cjb@laptop.org> who is a maintainer of MMC
> subsystem
> in Cc later.
> 
> > Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
> > Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
> > ---
> >  drivers/mmc/host/sdhci-s3c.c |   63
> > ++++++++++++++++++++++++++++++++++++++++++
> >  1 files changed, 63 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> > index 71ad416..6160960 100644
> > --- a/drivers/mmc/host/sdhci-s3c.c
> > +++ b/drivers/mmc/host/sdhci-s3c.c
> > @@ -96,6 +96,13 @@ static unsigned int sdhci_s3c_get_max_clk(struct
> > sdhci_host *host)
> >  	unsigned int rate, max;
> >  	int clk;
> >
> > +	/*
> > +	 * There is only one clock source(sclk) if there is no clock
> divider
> > +	 * in the host controller
> > +	 */
> > +	if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
> > +		return clk_round_rate(ourhost->clk_bus[2], UINT_MAX);
> > +
> >  	/* note, a reset will reset the clock source */
> >
> >  	sdhci_s3c_check_sclk(host);
> > @@ -130,6 +137,15 @@ static unsigned int sdhci_s3c_consider_clock(struct
> > sdhci_s3c *ourhost,
> >  	if (!clksrc)
> >  		return UINT_MAX;
> >
> > +	/*
> > +	 * There is only one clock source(sclk) if there is no clock
> divider
> > +	 * in the host controller
> > +	 */
> > +	if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
> > +		rate = clk_round_rate(clksrc, wanted);
> > +		return wanted - rate;
> > +	}
> > +
> >  	rate = clk_get_rate(clksrc);
> >
> >  	for (div = 1; div < 256; div *= 2) {
> > @@ -159,6 +175,7 @@ static void sdhci_s3c_set_clock(struct sdhci_host
> *host,
> > unsigned int clock)
> >  	int best_src = 0;
> >  	int src;
> >  	u32 ctrl;
> > +	unsigned int timeout;
> >
> >  	/* don't bother if the clock is going off. */
> >  	if (clock == 0)
> > @@ -204,6 +221,35 @@ static void sdhci_s3c_set_clock(struct sdhci_host
> *host,
> > unsigned int clock)
> >  			(ourhost->pdata->cfg_card)(ourhost->pdev, host-
> > >ioaddr,
> >  						   &ios, NULL);
> >  	}
> > +
> > +	/*
> > +	 * There is only one clock source(sclk) if there is no clock
> divider
> > +	 * in the host controller
> > +	 */
> > +	if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
> > +		writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
> > +		clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
> > +
> > +		writew(SDHCI_CLOCK_INT_EN, host->ioaddr +
> > SDHCI_CLOCK_CONTROL);
> > +
> > +		/* Wait max 20 ms */
> > +		timeout = 20;
> > +		while (!((sdhci_readw(host, SDHCI_CLOCK_CONTROL))
> > +			& SDHCI_CLOCK_INT_STABLE)) {
> > +			if (timeout == 0) {
> > +				printk(KERN_ERR "%s: clock never
> > stabilised.\n"
> > +						, mmc_hostname(host-
> > >mmc));
> > +				return;
> > +			}
> > +			timeout--;
> > +			mdelay(1);
> > +		}
> > +
> > +		writew(SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_CARD_EN,
> > +				host->ioaddr + SDHCI_CLOCK_CONTROL);
> > +
> > +		host->clock = clock;
> > +	}
> >  }
> >
> >  /**
> > @@ -221,6 +267,13 @@ static unsigned int sdhci_s3c_get_min_clock(struct
> > sdhci_host *host)
> >  	unsigned int delta, min = UINT_MAX;
> >  	int src;
> >
> > +	/*
> > +	 * There is only one clock source(sclk) if there is no clock
> divider
> > +	 * in the host controller
> > +	 */
> > +	if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
> > +		return clk_round_rate(ourhost->clk_bus[2], 400000);
> > +
> >  	for (src = 0; src < MAX_BUS_CLK; src++) {
> >  		delta = sdhci_s3c_consider_clock(ourhost, src, 0);
> >  		if (delta == UINT_MAX)
> > @@ -425,6 +478,16 @@ static int __devinit sdhci_s3c_probe(struct
> > platform_device *pdev)
> >  	/* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
> >  	host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
> >
> > +	/*
> > +	 * If controller does not have internal clock divider,
> > +	 * we need to use another method with setup a quirk.
> > +	 */
> > +	if (pdata->clk_type)
> > +		host->quirks |= SDHCI_QUIRK_NONSTANDARD_CLOCK;
> > +
> > +	if (pdata->host_caps)
> > +		host->mmc->caps |= pdata->host_caps;
> > +
> 
> If you want to add above feature, please separate it...
> 
> (snip)
> 
> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 1/5] ARM: S5PV310: Add HSMMC support and SDHCI configuration

[Kyungmin Park]

On Fri, Sep 17, 2010 at 9:57 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Kyungmin Park wrote:
>>
>> On Thu, Sep 16, 2010 at 5:36 PM, Jeongbae Seo <jeongbae.seo@samsung.com>
>> wrote:
>> > From: Hyuk Lee <hyuk1.lee@samsung.com>
>> >
>> > This patch adds to support HSMMC for S5PV310 and S5PC210 and setup for
>> > HSMMC host controller and also related GPIO.
>> > At most 4 channel can be used at the same time.
>> > A user can configure SDHCI data bus as 8bit or 4bit.
>> >
>> > Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
>> > Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
>> > ---
>> > ?arch/arm/mach-s5pv310/Kconfig ? ? ? ? ? ?| ? 39 ++++++++
>> > ?arch/arm/mach-s5pv310/Makefile ? ? ? ? ? | ? ?2 +
>> > ?arch/arm/mach-s5pv310/setup-sdhci-gpio.c | ?156
>> ++++++++++++++++++++++++++++++
>> > ?arch/arm/mach-s5pv310/setup-sdhci.c ? ? ?| ? 69 +++++++++++++
>> > ?4 files changed, 266 insertions(+), 0 deletions(-)
>> > ?create mode 100644 arch/arm/mach-s5pv310/setup-sdhci-gpio.c
>> > ?create mode 100644 arch/arm/mach-s5pv310/setup-sdhci.c
>> >
>> > diff --git a/arch/arm/mach-s5pv310/Kconfig
> b/arch/arm/mach-s5pv310/Kconfig
>> > index 9ac29fe..6a07968 100644
>> > --- a/arch/arm/mach-s5pv310/Kconfig
>> > +++ b/arch/arm/mach-s5pv310/Kconfig
>> > @@ -25,6 +25,17 @@ config S5PV310_SETUP_I2C2
>> > ? ? ? ?help
>> > ? ? ? ? ?Common setup code for i2c bus 2.
>> >
>> > +config S5PV310_SETUP_SDHCI
>> > + ? ? ? bool
>> > + ? ? ? select S5PV310_SETUP_SDHCI_GPIO
>> > + ? ? ? help
>> > + ? ? ? ? Internal helper functions for S5PV310 based SDHCI systems.
>> > +
>> > +config S5PV310_SETUP_SDHCI_GPIO
>> > + ? ? ? bool
>> > + ? ? ? help
>> > + ? ? ? ? Common setup code for SDHCI gpio.
>> > +
>> > ?# machine support
>> >
>> > ?menu "S5PC210 Machines"
>> > @@ -33,6 +44,11 @@ config MACH_SMDKC210
>> > ? ? ? ?bool "SMDKC210"
>> > ? ? ? ?select CPU_S5PV310
>> > ? ? ? ?select ARCH_SPARSEMEM_ENABLE
>> > + ? ? ? select S3C_DEV_HSMMC
>> > + ? ? ? select S3C_DEV_HSMMC1
>> > + ? ? ? select S3C_DEV_HSMMC2
>> > + ? ? ? select S3C_DEV_HSMMC3
>> > + ? ? ? select S5PV310_SETUP_SDHCI
>> > ? ? ? ?help
>> > ? ? ? ? ?Machine support for Samsung SMDKC210
>> > ? ? ? ? ?S5PC210(MCP) is one of package option of S5PV310
>> > @@ -53,9 +69,32 @@ config MACH_SMDKV310
>> > ? ? ? ?bool "SMDKV310"
>> > ? ? ? ?select CPU_S5PV310
>> > ? ? ? ?select ARCH_SPARSEMEM_ENABLE
>> > + ? ? ? select S3C_DEV_HSMMC
>> > + ? ? ? select S3C_DEV_HSMMC1
>> > + ? ? ? select S3C_DEV_HSMMC2
>> > + ? ? ? select S3C_DEV_HSMMC3
>> > + ? ? ? select S5PV310_SETUP_SDHCI
>> > ? ? ? ?help
>> > ? ? ? ? ?Machine support for Samsung SMDKV310
>> >
>> > ?endmenu
>> >
>> > +comment "Configuration for HSMMC bus width"
>> > +
>> > +menu "Use 8-bit bus width"
>> > +
>> > +config S5PV310_SDHCI_CH0_8BIT
>> > + ? ? ? bool "Channel 0 with 8-bit bus"
>> > + ? ? ? help
>> > + ? ? ? ? Support HSMMC Channel 0 8-bit bus.
>> > + ? ? ? ? If selected, Channel 1 is disabled.
>> > +
>> > +config S5PV310_SDHCI_CH2_8BIT
>> > + ? ? ? bool "Channel 2 with 8-bit bus"
>> > + ? ? ? help
>> > + ? ? ? ? Support HSMMC Channel 2 8-bit bus.
>> > + ? ? ? ? If selected, Channel 3 is disabled.
>>
>> I think it's not needed since most boards have fixed bandwith and
>> cfg_gpio handle it regardless these configuration.
>> Also we use the select state if needed, e.g., when MMC0 uses
>> 8-buswidth then don't select MMC1.
>> I saw the SMDK board use this configuration. but just choose bandwidth 4
> or 8.
>>
> Hmm...
>
> If it can be supported 4bit or 8bit option on each board, should be added
> above configuration for selecting it.
why? each sdhci_cfg_gpio can configure the pins properly. each board
has each own SD/MMC. In your test board maybe can switch 4 or 8 but
most board has fixed one.

If SMDK has 8-bit just assign 8 and unselect MMC1 or 3. that's all. No
configurations.

>
> Mr. Seo, it would be nice if you could add un-selection CH1 or CH3 when
> selecting 8bit support later.
>
> Anyway, looks ok to me now..will apply.
>
>> Others good.
>>
> (snip)
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>

[PATCH 5/5] sdhci-s3c: Add support no internal clock divider in host controller

[Chris Ball]

Hi,

On Thu, Sep 16, 2010 at 06:08:28PM +0900, Kyungmin Park wrote:
> Well there are two implementations. and no conclusion yet.
> as s5pc210 don't support internal SDHCI clock, DMC overrides the
> function operation itself when s5pc210. System LSI use the quirks.
> 
> Choose any one from MMC maintainer.

Both approaches are generally acceptable for MMC, so I would want to
leave it up to the maintainer of the driver in question (which is Ben,
in this case?) to choose between them.

That said, I think my own mild preference is for Jaehoon's approach.

Thanks,

- Chris.
-- 
Chris Ball   <cjb@laptop.org>   <http://printf.net/>
One Laptop Per Child

[PATCH 5/5] sdhci-s3c: Add support no internal clock divider in host controller

[Kyungmin Park]

On Sat, Sep 18, 2010 at 12:59 AM, Chris Ball <cjb@laptop.org> wrote:
> Hi,
>
> On Thu, Sep 16, 2010 at 06:08:28PM +0900, Kyungmin Park wrote:
>> Well there are two implementations. and no conclusion yet.
>> as s5pc210 don't support internal SDHCI clock, DMC overrides the
>> function operation itself when s5pc210. System LSI use the quirks.
>>
>> Choose any one from MMC maintainer.
>
> Both approaches are generally acceptable for MMC, so I would want to
> leave it up to the maintainer of the driver in question (which is Ben,
> in this case?) to choose between them.

Hi Chris,

Did you get the opinion from Ben?

I hope this decision will be done before 2.6.37 merge windows start to
support SDHCI support on s5pc210.

Thank you,
Kyungmin Park

>
> That said, I think my own mild preference is for Jaehoon's approach.
>
> Thanks,
>
> - Chris.
> --
> Chris Ball ? <cjb@laptop.org> ? <http://printf.net/>
> One Laptop Per Child
>

[PATCH 5/5] sdhci-s3c: Add support no internal clock divider in host controller

[Chris Ball]

Hi Kyungmin, Ben,

On Thu, Sep 30, 2010 at 10:18:12AM +0900, Kyungmin Park wrote:
> On Sat, Sep 18, 2010 at 12:59 AM, Chris Ball <cjb@laptop.org> wrote:
> > Hi,
> >
> > On Thu, Sep 16, 2010 at 06:08:28PM +0900, Kyungmin Park wrote:
> >> Well there are two implementations. and no conclusion yet.
> >> as s5pc210 don't support internal SDHCI clock, DMC overrides the
> >> function operation itself when s5pc210. System LSI use the quirks.
> >>
> >> Choose any one from MMC maintainer.
> >
> > Both approaches are generally acceptable for MMC, so I would want to
> > leave it up to the maintainer of the driver in question (which is Ben,
> > in this case?) to choose between them.
> 
> Hi Chris,
> 
> Did you get the opinion from Ben?
> 
> I hope this decision will be done before 2.6.37 merge windows start to
> support SDHCI support on s5pc210.

Hm, I didn't, and Ben's been silent about the urgent sdhci-s3c patches
too.  Ben, are you just dealing with a large backlog, or are you 
interested in nominating someone else to take over sdhci-s3c?

Thanks,

- Chris.
-- 
Chris Ball   <cjb@laptop.org>   <http://printf.net/>
One Laptop Per Child

[PATCH 5/5] sdhci-s3c: Add support no internal clock divider in host controller

[Jeongbae Seo]

Chris wrote:

> Hi Kyungmin, Ben,
> 
> On Thu, Sep 30, 2010 at 10:18:12AM +0900, Kyungmin Park wrote:
> > On Sat, Sep 18, 2010 at 12:59 AM, Chris Ball <cjb@laptop.org> wrote:
> > > Hi,
> > >
> > > On Thu, Sep 16, 2010 at 06:08:28PM +0900, Kyungmin Park wrote:
> > >> Well there are two implementations. and no conclusion yet.
> > >> as s5pc210 don't support internal SDHCI clock, DMC overrides the
> > >> function operation itself when s5pc210. System LSI use the quirks.
> > >>
> > >> Choose any one from MMC maintainer.
> > >
> > > Both approaches are generally acceptable for MMC, so I would want to
> > > leave it up to the maintainer of the driver in question (which is Ben,
> > > in this case?) to choose between them.
> >
> > Hi Chris,
> >
> > Did you get the opinion from Ben?
> >
> > I hope this decision will be done before 2.6.37 merge windows start to
> > support SDHCI support on s5pc210.
> 
> Hm, I didn't, and Ben's been silent about the urgent sdhci-s3c patches
> too.  Ben, are you just dealing with a large backlog, or are you
> interested in nominating someone else to take over sdhci-s3c?

Hi Chris, Kyungmin

I'd like to let you know that Ben had reviewed and commented for
"[PATCH v2 2/2] sdhci-s3c: Add support no internal clock divider" in host
controller in 9/21. However, our response was late due to our holidays. I
made a response in 9/28 that why we use this quirk and now we're waiting for
his opinion.

Kyungmin, did you check Ben's review comments for this ? When I saw it, his
approach is just a bit different from you and me. Please let us know if you
have any idea about his comments.

Thanks,
Best Regards
Jeongbae Seo

[PATCH 5/5] sdhci-s3c: Add support no internal clock divider in host controller

[Kyungmin Park]

On Thu, Sep 30, 2010 at 2:40 PM, Jeongbae Seo <jeongbae.seo@samsung.com> wrote:
> Chris wrote:
>
>> Hi Kyungmin, Ben,
>>
>> On Thu, Sep 30, 2010 at 10:18:12AM +0900, Kyungmin Park wrote:
>> > On Sat, Sep 18, 2010 at 12:59 AM, Chris Ball <cjb@laptop.org> wrote:
>> > > Hi,
>> > >
>> > > On Thu, Sep 16, 2010 at 06:08:28PM +0900, Kyungmin Park wrote:
>> > >> Well there are two implementations. and no conclusion yet.
>> > >> as s5pc210 don't support internal SDHCI clock, DMC overrides the
>> > >> function operation itself when s5pc210. System LSI use the quirks.
>> > >>
>> > >> Choose any one from MMC maintainer.
>> > >
>> > > Both approaches are generally acceptable for MMC, so I would want to
>> > > leave it up to the maintainer of the driver in question (which is Ben,
>> > > in this case?) to choose between them.
>> >
>> > Hi Chris,
>> >
>> > Did you get the opinion from Ben?
>> >
>> > I hope this decision will be done before 2.6.37 merge windows start to
>> > support SDHCI support on s5pc210.
>>
>> Hm, I didn't, and Ben's been silent about the urgent sdhci-s3c patches
>> too. ?Ben, are you just dealing with a large backlog, or are you
>> interested in nominating someone else to take over sdhci-s3c?
>
> Hi Chris, Kyungmin
>
> I'd like to let you know that Ben had reviewed and commented for
> "[PATCH v2 2/2] sdhci-s3c: Add support no internal clock divider" in host
> controller in 9/21. However, our response was late due to our holidays. I
> made a response in 9/28 that why we use this quirk and now we're waiting for
> his opinion.
>
> Kyungmin, did you check Ben's review comments for this ? When I saw it, his
> approach is just a bit different from you and me. Please let us know if you
> have any idea about his comments.

I think he just ask "why these quirk are needed" and you already
explained it. I don't have any clue this approach.
Anyway he suggest any ideas I will check it. but no comments then no way.

Thank you,
Kyungmin Park
>
> Thanks,
> Best Regards
> Jeongbae Seo
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>

[PATCH 2/5] ARM: S5PV310: Add HSMMC support into S5PV310 and S5PC210

[Marek Szyprowski]

Hello,

I'm sorry for a late replay, I've just noticed this patch and have some comments.

On Thursday, September 16, 2010 10:37 AM Jeongbae Seo wrote:

> From: Hyuk Lee <hyuk1.lee@samsung.com>
> 
> This patch adds to use of HSMMC on S5PV310 and S5PC210.
> The HSMMC platform data like card detect, data bus width
> and capability is configured.
> 
> Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
> Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
> ---
>  arch/arm/mach-s5pv310/cpu.c                |    7 +++
>  arch/arm/mach-s5pv310/mach-smdkc210.c      |   50 ++++++++++++++++++++++++
>  arch/arm/mach-s5pv310/mach-smdkv310.c      |   50 ++++++++++++++++++++++++
>  arch/arm/plat-samsung/include/plat/sdhci.h |   57 ++++++++++++++++++++++++++++
>  4 files changed, 164 insertions(+), 0 deletions(-)

IMHO, changes to arch/arm/mach-s5pv310/{cpu.c, include/plat/sdhci.h}
should be separated from changes to board specific changes 
(arch/arm/mach-s5pv310/mach-smdk*.c), so this patch should be split
into 2 separate patches.

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center

[PATCH 1/5] ARM: S5PV310: Add HSMMC support and SDHCI configuration

[Marek Szyprowski]

Hello,

On Thursday, September 16, 2010 10:37 AM Jeongbae Seo wrote:

> From: Hyuk Lee <hyuk1.lee@samsung.com>
> 
> This patch adds to support HSMMC for S5PV310 and S5PC210 and setup for
> HSMMC host controller and also related GPIO.
> At most 4 channel can be used at the same time.
> A user can configure SDHCI data bus as 8bit or 4bit.
> 
> Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
> Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
> ---
>  arch/arm/mach-s5pv310/Kconfig            |   39 ++++++++
>  arch/arm/mach-s5pv310/Makefile           |    2 +
>  arch/arm/mach-s5pv310/setup-sdhci-gpio.c |  156 ++++++++++++++++++++++++++++++
>  arch/arm/mach-s5pv310/setup-sdhci.c      |   69 +++++++++++++
>  4 files changed, 266 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-s5pv310/setup-sdhci-gpio.c
>  create mode 100644 arch/arm/mach-s5pv310/setup-sdhci.c
> 

<snip>

> diff --git a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
> new file mode 100644
> index 0000000..8db8c81
> --- /dev/null
> +++ b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
> @@ -0,0 +1,156 @@
> +/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
> + *
> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com/
> + *
> + * S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/interrupt.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <linux/gpio.h>
> +#include <linux/mmc/host.h>
> +#include <linux/mmc/card.h>
> +
> +#include <plat/gpio-cfg.h>
> +#include <plat/regs-sdhci.h>
> +#include <plat/sdhci.h>
> +
> +void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
> +{
> +	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
> +	unsigned int gpio;
> +
> +	/* Set all the necessary GPK0[0:1] pins to special-function 2 */
> +	for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) {
> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> +	}
> +
> +	switch (width) {
> +	case 8:
> +		for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
> +			/* Data pin GPK1[3:6] to special-funtion 3 */
> +			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
> +			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> +
> +			/* Setup Drive Strength */
> +			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> +		}
> +	case 4:
> +		for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) {
> +			/* Data pin GPK0[3:6] to special-funtion 2 */
> +			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> +			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> +
> +			/* Setup Drive Strength */
> +			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> +		}
> +	default:
> +		break;
> +	}
> +
> +	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
> +		s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2));
> +		s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP);
> +	}
> +}
> +
> +void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
> +{
> +	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
> +	unsigned int gpio;
> +
> +	/* Set all the necessary GPK1[0:1] pins to special-function 2 */
> +	for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) {
> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> +	}
> +
> +	for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
> +		/* Data pin GPK1[3:6] to special-function 2 */
> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> +
> +		/* Setup Drive Strength */
> +		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> +	}
> +
> +	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
> +		s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2));
> +		s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP);
> +	}
> +}
> +
> +void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
> +{
> +	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
> +	unsigned int gpio;
> +
> +	/* Set all the necessary GPK2[0:1] pins to special-function 2 */
> +	for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) {
> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);

Lack of "s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4)" here causes problems with 
Universal C210 and external SD-card. IMHO driver strength should be set for all MMC
pins, not only for data pins like below (and do this for all MMC blocks of course). 

> +	}
> +
> +	switch (width) {
> +	case 8:
> +		for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
> +			/* Data pin GPK3[3:6] to special-function 3 */
> +			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
> +			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> +
> +			/* Setup Drive Strength */
> +			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> +		}
> +	case 4:
> +		for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) {
> +			/* Data pin GPK2[3:6] to special-function 2 */
> +			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> +			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> +
> +			/* Setup Drive Strength */
> +			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> +		}
> +	default:
> +		break;
> +	}
> +
> +	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
> +		s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2));
> +		s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP);
> +	}
> +}
> +
> +void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
> +{
> +	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
> +	unsigned int gpio;
> +
> +	/* Set all the necessary GPK3[0:1] pins to special-function 2 */
> +	for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) {
> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> +	}
> +
> +	for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
> +		/* Data pin GPK3[3:6] to special-function 2 */
> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> +
> +		/* Setup Drive Strength */
> +		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> +	}
> +
> +	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
> +		s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2));
> +		s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP);
> +	}
> +}

<snip>

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center

[PATCH 2/5] ARM: S5PV310: Add HSMMC support into S5PV310 and S5PC210

[Jeongbae Seo]

Marek Szyprowski wrote:
> Hello,
> 
> I'm sorry for a late replay, I've just noticed this patch and have some
> comments.
> 
> On Thursday, September 16, 2010 10:37 AM Jeongbae Seo wrote:
> 
> > From: Hyuk Lee <hyuk1.lee@samsung.com>
> >
> > This patch adds to use of HSMMC on S5PV310 and S5PC210.
> > The HSMMC platform data like card detect, data bus width
> > and capability is configured.
> >
> > Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
> > Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
> > ---
> >  arch/arm/mach-s5pv310/cpu.c                |    7 +++
> >  arch/arm/mach-s5pv310/mach-smdkc210.c      |   50
> ++++++++++++++++++++++++
> >  arch/arm/mach-s5pv310/mach-smdkv310.c      |   50
> ++++++++++++++++++++++++
> >  arch/arm/plat-samsung/include/plat/sdhci.h |   57
> ++++++++++++++++++++++++++++
> >  4 files changed, 164 insertions(+), 0 deletions(-)
> 
> IMHO, changes to arch/arm/mach-s5pv310/{cpu.c, include/plat/sdhci.h}
> should be separated from changes to board specific changes
> (arch/arm/mach-s5pv310/mach-smdk*.c), so this patch should be split
> into 2 separate patches.

Hi, Marek

Okay, I'll make it as two patches.
Thanks for your comments.

Best Regards
Jeongbae Seo

[PATCH 1/5] ARM: S5PV310: Add HSMMC support and SDHCI configuration

[Jeongbae Seo]

Marek Szyprowski wrote:
> Hello,
> 
> On Thursday, September 16, 2010 10:37 AM Jeongbae Seo wrote:
> 
> > From: Hyuk Lee <hyuk1.lee@samsung.com>
> >
> > This patch adds to support HSMMC for S5PV310 and S5PC210 and setup for
> > HSMMC host controller and also related GPIO.
> > At most 4 channel can be used at the same time.
> > A user can configure SDHCI data bus as 8bit or 4bit.
> >
> > Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com>
> > Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
> > ---
> >  arch/arm/mach-s5pv310/Kconfig            |   39 ++++++++
> >  arch/arm/mach-s5pv310/Makefile           |    2 +
> >  arch/arm/mach-s5pv310/setup-sdhci-gpio.c |  156
> ++++++++++++++++++++++++++++++
> >  arch/arm/mach-s5pv310/setup-sdhci.c      |   69 +++++++++++++
> >  4 files changed, 266 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/mach-s5pv310/setup-sdhci-gpio.c
> >  create mode 100644 arch/arm/mach-s5pv310/setup-sdhci.c
> >
> 
> <snip>
> 
> > diff --git a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c b/arch/arm/mach-
> s5pv310/setup-sdhci-gpio.c
> > new file mode 100644
> > index 0000000..8db8c81
> > --- /dev/null
> > +++ b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
> > @@ -0,0 +1,156 @@
> > +/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
> > + *
> > + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> > + *		http://www.samsung.com/
> > + *
> > + * S5PV310 - Helper functions for setting up SDHCI device(s) GPIO
> (HSMMC)
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > +*/
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/types.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/io.h>
> > +#include <linux/gpio.h>
> > +#include <linux/mmc/host.h>
> > +#include <linux/mmc/card.h>
> > +
> > +#include <plat/gpio-cfg.h>
> > +#include <plat/regs-sdhci.h>
> > +#include <plat/sdhci.h>
> > +
> > +void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int
> width)
> > +{
> > +	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
> > +	unsigned int gpio;
> > +
> > +	/* Set all the necessary GPK0[0:1] pins to special-function 2 */
> > +	for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) {
> > +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> > +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> > +	}
> > +
> > +	switch (width) {
> > +	case 8:
> > +		for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6);
gpio++)
> {
> > +			/* Data pin GPK1[3:6] to special-funtion 3 */
> > +			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
> > +			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> > +
> > +			/* Setup Drive Strength */
> > +			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> > +		}
> > +	case 4:
> > +		for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6);
gpio++)
> {
> > +			/* Data pin GPK0[3:6] to special-funtion 2 */
> > +			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> > +			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> > +
> > +			/* Setup Drive Strength */
> > +			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> > +		}
> > +	default:
> > +		break;
> > +	}
> > +
> > +	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
> > +		s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2));
> > +		s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP);
> > +	}
> > +}
> > +
> > +void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int
> width)
> > +{
> > +	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
> > +	unsigned int gpio;
> > +
> > +	/* Set all the necessary GPK1[0:1] pins to special-function 2 */
> > +	for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) {
> > +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> > +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> > +	}
> > +
> > +	for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
> > +		/* Data pin GPK1[3:6] to special-function 2 */
> > +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> > +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> > +
> > +		/* Setup Drive Strength */
> > +		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> > +	}
> > +
> > +	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
> > +		s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2));
> > +		s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP);
> > +	}
> > +}
> > +
> > +void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int
> width)
> > +{
> > +	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
> > +	unsigned int gpio;
> > +
> > +	/* Set all the necessary GPK2[0:1] pins to special-function 2 */
> > +	for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) {
> > +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> > +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> 
> Lack of "s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4)" here causes
> problems with
> Universal C210 and external SD-card. IMHO driver strength should be set
> for all MMC
> pins, not only for data pins like below (and do this for all MMC blocks of
> course).

Okay, if a problem can be occurred owing to the lack of driver strength,
we'd better set all MMC with driver strength. I will re-make it and thanks
for your comment.

Best Regards
Jeongbae Seo

> > +	}
> > +
> > +	switch (width) {
> > +	case 8:
> > +		for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6);
gpio++)
> {
> > +			/* Data pin GPK3[3:6] to special-function 3 */
> > +			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
> > +			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> > +
> > +			/* Setup Drive Strength */
> > +			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> > +		}
> > +	case 4:
> > +		for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6);
gpio++)
> {
> > +			/* Data pin GPK2[3:6] to special-function 2 */
> > +			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> > +			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> > +
> > +			/* Setup Drive Strength */
> > +			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> > +		}
> > +	default:
> > +		break;
> > +	}
> > +
> > +	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
> > +		s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2));
> > +		s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP);
> > +	}
> > +}
> > +
> > +void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int
> width)
> > +{
> > +	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
> > +	unsigned int gpio;
> > +
> > +	/* Set all the necessary GPK3[0:1] pins to special-function 2 */
> > +	for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) {
> > +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> > +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> > +	}
> > +
> > +	for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
> > +		/* Data pin GPK3[3:6] to special-function 2 */
> > +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> > +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
> > +
> > +		/* Setup Drive Strength */
> > +		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
> > +	}
> > +
> > +	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
> > +		s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2));
> > +		s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP);
> > +	}
> > +}
> 
> <snip>
> 
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center