From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] Fix the I-cache invalidation on ARMv6 and later CPUs
Date: Tue, 9 Nov 2010 10:38:36 +0000 [thread overview]
Message-ID: <20101109103836.GC2869@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <AANLkTikhi3znQs32Qc=ACuH0Kz-WV0xmD-4-JjQv8OqZ@mail.gmail.com>
On Tue, Nov 09, 2010 at 07:34:45PM +0900, Minchan Kim wrote:
> On Tue, Nov 9, 2010 at 7:17 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> > Note that these functions are changed slightly in 2.6.37-rc1, but we
> > still do the I-cache flushing.
> >
> > There reason is that the page being modified may already be mapped in
> > user space and may be a code page as well. The kernel may call this
>
> Yes. That's my point. We can't know code or not in that context(ie,
> flush_dcache_page).
And because we don't know, we have to assume that the page does contain
code, so we have to flush the I cache.
> In 2.6.37-rc1, we flushes icache without VM_EXEC check in set_pte_at
> which doesn't have VMA, either.
> Could we move the icache flush to update_mmu_cache again?
No. We moved it to fix a race on SMP - between the PTE being established
and the caches being coherent. Moving it later reintroduces that race
again.
next prev parent reply other threads:[~2010-11-09 10:38 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20080606114622.15520.49929.stgit@pc1117.cambridge.arm.com>
[not found] ` <AANLkTik0_0Eb8G5hEb+DGvE2BDM_mJwwF-Pt1ErTz=Lr@mail.gmail.com>
2010-11-09 5:08 ` [PATCH 1/2] Fix the I-cache invalidation on ARMv6 and later CPUs Minchan Kim
2010-11-09 10:17 ` Catalin Marinas
2010-11-09 10:34 ` Minchan Kim
2010-11-09 10:38 ` Russell King - ARM Linux [this message]
2010-11-09 10:52 ` Minchan Kim
2010-11-09 10:53 ` Russell King - ARM Linux
2010-11-09 11:04 ` Minchan Kim
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