[PATCH] ARM: Common GIC entry macro code V2

[PATCH] ARM: Common GIC entry macro code V2

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

This patch is the identical GIC demux implementation
merge V2. Instead of implementing same code over and
over simply share it in entry-macro-gic.S. The shared
code is based on the realview implementation.

Each GIC demux instance still has to setup the base address
of the controller using the get_irqnr_preamble macro. The
rest of the GIC specific code can be shared.

The omap code is excluded due to complexity and lack of
hardware - the CONFIG_SMP macros are used for multi-omap
and the omap4 case - this makes is difficult to share code.

The s5pv310 subarch is excluded due to the special "addne"
instruction in the get_irqnr_and_base macro.

The msm subarch is excluded as well since it treats PPIs
differently than other platforms and needs a different
version of the get_irqnr_and_base macro.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Srinidhi Kasagar<srinidhi.kasagar@stericsson.com>
---

 Changes since V1:
 - dropped msm as requested by Abhijeet, thank you.
 
 This patch is almost identical to 6284/1 in the RMKs patch
 tracker. The main difference is that this patch requires
 each platform to specify base address using the macro
 get_irqnr_preable. This patch includes tegra, but drops
 omap support due to multi-omap complexity.

 Thanks to Shilimkar, Santosh and Srinidhi Kasagar for feedback.

 arch/arm/include/asm/hardware/entry-macro-gic.S   |   68 +++++++++++++++++++++
 arch/arm/mach-cns3xxx/include/mach/entry-macro.S  |   61 ------------------
 arch/arm/mach-realview/include/mach/entry-macro.S |   60 ------------------
 arch/arm/mach-tegra/include/mach/entry-macro.S    |   64 -------------------
 arch/arm/mach-ux500/include/mach/entry-macro.S    |   67 --------------------
 arch/arm/mach-vexpress/include/mach/entry-macro.S |   57 -----------------
 6 files changed, 73 insertions(+), 304 deletions(-)

--- /dev/null
+++ work/arch/arm/include/asm/hardware/entry-macro-gic.S	2010-11-10 16:06:26.000000000 +0900
@@ -0,0 +1,68 @@
+/*
+ * arch/arm/include/asm/hardware/entry-macro-gic.S
+ *
+ * Low-level IRQ helper macros for GIC
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/hardware/gic.h>
+
+/*
+ * The interrupt numbering scheme is defined in the
+ * interrupt controller spec.  To wit:
+ *
+ * Interrupts 0-15 are IPI
+ * 16-28 are reserved
+ * 29-31 are local.  We allow 30 to be used for the watchdog.
+ * 32-1020 are global
+ * 1021-1022 are reserved
+ * 1023 is "spurious" (no interrupt)
+ *
+ * For now, we ignore all local interrupts so only return an interrupt if it's
+ * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
+ *
+ * A simple read from the controller will tell us the number of the highest
+ * priority enabled interrupt.  We then just need to check whether it is in the
+ * valid range for an IRQ (30-1020 inclusive).
+ */
+
+	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+	ldr     \irqstat, [\base, #GIC_CPU_INTACK]
+	/* bits 12-10 = src CPU, 9-0 = int # */
+
+	ldr	\tmp, =1021
+	bic     \irqnr, \irqstat, #0x1c00
+	cmp     \irqnr, #29
+	cmpcc	\irqnr, \irqnr
+	cmpne	\irqnr, \tmp
+	cmpcs	\irqnr, \irqnr
+	.endm
+
+/* We assume that irqstat (the raw value of the IRQ acknowledge
+ * register) is preserved from the macro above.
+ * If there is an IPI, we immediately signal end of interrupt on the
+ * controller, since this requires the original irqstat value which
+ * we won't easily be able to recreate later.
+ */
+
+	.macro test_for_ipi, irqnr, irqstat, base, tmp
+	bic	\irqnr, \irqstat, #0x1c00
+	cmp	\irqnr, #16
+	strcc	\irqstat, [\base, #GIC_CPU_EOI]
+	cmpcs	\irqnr, \irqnr
+	.endm
+
+/* As above, this assumes that irqstat and base are preserved.. */
+
+	.macro test_for_ltirq, irqnr, irqstat, base, tmp
+	bic	\irqnr, \irqstat, #0x1c00
+	mov 	\tmp, #0
+	cmp	\irqnr, #29
+	moveq	\tmp, #1
+	streq	\irqstat, [\base, #GIC_CPU_EOI]
+	cmp	\tmp, #0
+	.endm
--- 0001/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
+++ work/arch/arm/mach-cns3xxx/include/mach/entry-macro.S	2010-11-10 16:06:25.000000000 +0900
@@ -9,7 +9,7 @@
  */
 
 #include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
 
 		.macro	disable_fiq
 		.endm
@@ -21,62 +21,3 @@
 
 		.macro  arch_ret_to_user, tmp1, tmp2
 		.endm
-
-		/*
-		 * The interrupt numbering scheme is defined in the
-		 * interrupt controller spec.  To wit:
-		 *
-		 * Interrupts 0-15 are IPI
-		 * 16-28 are reserved
-		 * 29-31 are local.  We allow 30 to be used for the watchdog.
-		 * 32-1020 are global
-		 * 1021-1022 are reserved
-		 * 1023 is "spurious" (no interrupt)
-		 *
-		 * For now, we ignore all local interrupts so only return an interrupt if it's
-		 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-		 *
-		 * A simple read from the controller will tell us the number of the highest
-                 * priority enabled interrupt.  We then just need to check whether it is in the
-		 * valid range for an IRQ (30-1020 inclusive).
-		 */
-
-		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-		ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-
-		ldr	\tmp, =1021
-
-		bic     \irqnr, \irqstat, #0x1c00
-
-		cmp     \irqnr, #29
-		cmpcc	\irqnr, \irqnr
-		cmpne	\irqnr, \tmp
-		cmpcs	\irqnr, \irqnr
-
-		.endm
-
-		/* We assume that irqstat (the raw value of the IRQ acknowledge
-		 * register) is preserved from the macro above.
-		 * If there is an IPI, we immediately signal end of interrupt on the
-		 * controller, since this requires the original irqstat value which
-		 * we won't easily be able to recreate later.
-		 */
-
-		.macro test_for_ipi, irqnr, irqstat, base, tmp
-		bic	\irqnr, \irqstat, #0x1c00
-		cmp	\irqnr, #16
-		strcc	\irqstat, [\base, #GIC_CPU_EOI]
-		cmpcs	\irqnr, \irqnr
-		.endm
-
-		/* As above, this assumes that irqstat and base are preserved.. */
-
-		.macro test_for_ltirq, irqnr, irqstat, base, tmp
-		bic	\irqnr, \irqstat, #0x1c00
-		mov 	\tmp, #0
-		cmp	\irqnr, #29
-		moveq	\tmp, #1
-		streq	\irqstat, [\base, #GIC_CPU_EOI]
-		cmp	\tmp, #0
-		.endm
--- 0001/arch/arm/mach-realview/include/mach/entry-macro.S
+++ work/arch/arm/mach-realview/include/mach/entry-macro.S	2010-11-10 16:06:25.000000000 +0900
@@ -8,7 +8,7 @@
  * warranty of any kind, whether express or implied.
  */
 #include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
 
 		.macro	disable_fiq
 		.endm
@@ -21,61 +21,3 @@
 		.macro  arch_ret_to_user, tmp1, tmp2
 		.endm
 
-		/*
-		 * The interrupt numbering scheme is defined in the
-		 * interrupt controller spec.  To wit:
-		 *
-		 * Interrupts 0-15 are IPI
-		 * 16-28 are reserved
-		 * 29-31 are local.  We allow 30 to be used for the watchdog.
-		 * 32-1020 are global
-		 * 1021-1022 are reserved
-		 * 1023 is "spurious" (no interrupt)
-		 *
-		 * For now, we ignore all local interrupts so only return an interrupt if it's
-		 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-		 *
-		 * A simple read from the controller will tell us the number of the highest
-                 * priority enabled interrupt.  We then just need to check whether it is in the
-		 * valid range for an IRQ (30-1020 inclusive).
-		 */
-
-		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-		ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-
-		ldr	\tmp, =1021
-
-		bic     \irqnr, \irqstat, #0x1c00
-
-		cmp     \irqnr, #29
-		cmpcc	\irqnr, \irqnr
-		cmpne	\irqnr, \tmp
-		cmpcs	\irqnr, \irqnr
-
-		.endm
-
-		/* We assume that irqstat (the raw value of the IRQ acknowledge
-		 * register) is preserved from the macro above.
-		 * If there is an IPI, we immediately signal end of interrupt on the
-		 * controller, since this requires the original irqstat value which
-		 * we won't easily be able to recreate later.
-		 */
-
-		.macro test_for_ipi, irqnr, irqstat, base, tmp
-		bic	\irqnr, \irqstat, #0x1c00
-		cmp	\irqnr, #16
-		strcc	\irqstat, [\base, #GIC_CPU_EOI]
-		cmpcs	\irqnr, \irqnr
-		.endm
-
-		/* As above, this assumes that irqstat and base are preserved.. */
-
-		.macro test_for_ltirq, irqnr, irqstat, base, tmp
-		bic	\irqnr, \irqstat, #0x1c00
-		mov 	\tmp, #0
-		cmp	\irqnr, #29
-		moveq	\tmp, #1
-		streq	\irqstat, [\base, #GIC_CPU_EOI]
-		cmp	\tmp, #0
-		.endm
--- 0001/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ work/arch/arm/mach-tegra/include/mach/entry-macro.S	2010-11-10 16:06:25.000000000 +0900
@@ -17,7 +17,7 @@
 
 #if defined(CONFIG_ARM_GIC)
 
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
 
 	/* Uses the GIC interrupt controller built into the cpu */
 #define ICTRL_BASE (IO_CPU_VIRT + 0x100)
@@ -32,68 +32,6 @@
 
 	.macro  arch_ret_to_user, tmp1, tmp2
 	.endm
-
-	/*
-	 * The interrupt numbering scheme is defined in the
-	 * interrupt controller spec.  To wit:
-	 *
-	 * Interrupts 0-15 are IPI
-	 * 16-28 are reserved
-	 * 29-31 are local.  We allow 30 to be used for the watchdog.
-	 * 32-1020 are global
-	 * 1021-1022 are reserved
-	 * 1023 is "spurious" (no interrupt)
-	 *
-	 * For now, we ignore all local interrupts so only return an interrupt
-	 * if it's between 30 and 1020.  The test_for_ipi routine below will
-	 * pick up on IPIs.
-	 *
-	 * A simple read from the controller will tell us the number of the
-	 * highest priority enabled interrupt.  We then just need to check
-	 * whether it is in the valid range for an IRQ (30-1020 inclusive).
-	 */
-
-	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-	/* bits 12-10 = src CPU, 9-0 = int # */
-	ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-
-	ldr		\tmp, =1021
-
-	bic     \irqnr, \irqstat, #0x1c00
-
-	cmp     \irqnr, #29
-	cmpcc	\irqnr, \irqnr
-	cmpne	\irqnr, \tmp
-	cmpcs	\irqnr, \irqnr
-
-	.endm
-
-	/* We assume that irqstat (the raw value of the IRQ acknowledge
-	 * register) is preserved from the macro above.
-	 * If there is an IPI, we immediately signal end of interrupt on the
-	 * controller, since this requires the original irqstat value which
-	 * we won't easily be able to recreate later.
-	 */
-
-	.macro test_for_ipi, irqnr, irqstat, base, tmp
-	bic	\irqnr, \irqstat, #0x1c00
-	cmp	\irqnr, #16
-	strcc	\irqstat, [\base, #GIC_CPU_EOI]
-	cmpcs	\irqnr, \irqnr
-	.endm
-
-	/* As above, this assumes that irqstat and base are preserved.. */
-
-	.macro test_for_ltirq, irqnr, irqstat, base, tmp
-	bic	\irqnr, \irqstat, #0x1c00
-	mov 	\tmp, #0
-	cmp	\irqnr, #29
-	moveq	\tmp, #1
-	streq	\irqstat, [\base, #GIC_CPU_EOI]
-	cmp	\tmp, #0
-	.endm
-
 #else
 	/* legacy interrupt controller for AP16 */
 	.macro	disable_fiq
--- 0001/arch/arm/mach-ux500/include/mach/entry-macro.S
+++ work/arch/arm/mach-ux500/include/mach/entry-macro.S	2010-11-10 16:06:25.000000000 +0900
@@ -11,7 +11,7 @@
  * warranty of any kind, whether express or implied.
  */
 #include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
 
 		.macro	disable_fiq
 		.endm
@@ -22,68 +22,3 @@
 
 		.macro  arch_ret_to_user, tmp1, tmp2
 		.endm
-
-		/*
-		 * The interrupt numbering scheme is defined in the
-		 * interrupt controller spec.  To wit:
-		 *
-		 * Interrupts 0-15 are IPI
-		 * 16-28 are reserved
-		 * 29-31 are local.  We allow 30 to be used for the watchdog.
-		 * 32-1020 are global
-		 * 1021-1022 are reserved
-		 * 1023 is "spurious" (no interrupt)
-		 *
-		 * For now, we ignore all local interrupts so only return an
-		 * interrupt if it's between 30 and 1020. The test_for_ipi
-		 * routine below will pick up on IPIs.
-		 *
-		 * A simple read from the controller will tell us the number
-		 * of the highest priority enabled interrupt. We then just
-		 * need to check whether it is in the valid range for an
-		 * IRQ (30-1020 inclusive).
-		 */
-
-		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-		/* bits 12-10 = src CPU, 9-0 = int # */
-		ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-
-		ldr	\tmp, =1021
-
-		bic     \irqnr, \irqstat, #0x1c00
-
-		cmp     \irqnr, #29
-		cmpcc	\irqnr, \irqnr
-		cmpne	\irqnr, \tmp
-		cmpcs	\irqnr, \irqnr
-
-		.endm
-
-		/* We assume that irqstat (the raw value of the IRQ
-		 * acknowledge register) is preserved from the macro above.
-		 * If there is an IPI, we immediately signal end of
-		 * interrupt on the controller, since this requires the
-		 * original irqstat value which we won't easily be able
-		 * to recreate later.
-		 */
-
-		.macro test_for_ipi, irqnr, irqstat, base, tmp
-		bic	\irqnr, \irqstat, #0x1c00
-		cmp	\irqnr, #16
-		strcc	\irqstat, [\base, #GIC_CPU_EOI]
-		cmpcs	\irqnr, \irqnr
-		.endm
-
-		/* As above, this assumes that irqstat and base
-		 * are preserved..
-		 */
-
-		.macro test_for_ltirq, irqnr, irqstat, base, tmp
-		bic	\irqnr, \irqstat, #0x1c00
-		mov 	\tmp, #0
-		cmp	\irqnr, #29
-		moveq	\tmp, #1
-		streq	\irqstat, [\base, #GIC_CPU_EOI]
-		cmp	\tmp, #0
-		.endm
--- 0001/arch/arm/mach-vexpress/include/mach/entry-macro.S
+++ work/arch/arm/mach-vexpress/include/mach/entry-macro.S	2010-11-10 16:06:25.000000000 +0900
@@ -1,4 +1,4 @@
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
 
 	.macro	disable_fiq
 	.endm
@@ -10,58 +10,3 @@
 
 	.macro	arch_ret_to_user, tmp1, tmp2
 	.endm
-
-	/*
-	 * The interrupt numbering scheme is defined in the
-	 * interrupt controller spec.  To wit:
-	 *
-	 * Interrupts 0-15 are IPI
-	 * 16-28 are reserved
-	 * 29-31 are local.  We allow 30 to be used for the watchdog.
-	 * 32-1020 are global
-	 * 1021-1022 are reserved
-	 * 1023 is "spurious" (no interrupt)
-	 *
-	 * For now, we ignore all local interrupts so only return an interrupt if it's
-	 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-	 *
-	 * A simple read from the controller will tell us the number of the highest
-	 * priority enabled interrupt.  We then just need to check whether it is in the
-	 * valid range for an IRQ (30-1020 inclusive).
-	 */
-
-	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-	ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-	ldr	\tmp, =1021
-	bic     \irqnr, \irqstat, #0x1c00
-	cmp     \irqnr, #29
-	cmpcc	\irqnr, \irqnr
-	cmpne	\irqnr, \tmp
-	cmpcs	\irqnr, \irqnr
-	.endm
-
-	/* We assume that irqstat (the raw value of the IRQ acknowledge
-	 * register) is preserved from the macro above.
-	 * If there is an IPI, we immediately signal end of interrupt on the
-	 * controller, since this requires the original irqstat value which
-	 * we won't easily be able to recreate later.
-	 */
-
-	.macro test_for_ipi, irqnr, irqstat, base, tmp
-	bic	\irqnr, \irqstat, #0x1c00
-	cmp	\irqnr, #16
-	strcc	\irqstat, [\base, #GIC_CPU_EOI]
-	cmpcs	\irqnr, \irqnr
-	.endm
-
-	/* As above, this assumes that irqstat and base are preserved.. */
-
-	.macro test_for_ltirq, irqnr, irqstat, base, tmp
-	bic	\irqnr, \irqstat, #0x1c00
-	mov 	\tmp, #0
-	cmp	\irqnr, #29
-	moveq	\tmp, #1
-	streq	\irqstat, [\base, #GIC_CPU_EOI]
-	cmp	\tmp, #0
-	.endm
-

[PATCH] ARM: Common GIC entry macro code V2

[Kyungmin Park]

Hi,

Can you include the "arch/arm/mach-s5pv310/include/mach/entry-macro.S" also?

Thank you,
Kyungmin Park

On Thu, Nov 11, 2010 at 4:49 PM, Magnus Damm <magnus.damm@gmail.com> wrote:
> From: Magnus Damm <damm@opensource.se>
>
> This patch is the identical GIC demux implementation
> merge V2. Instead of implementing same code over and
> over simply share it in entry-macro-gic.S. The shared
> code is based on the realview implementation.
>
> Each GIC demux instance still has to setup the base address
> of the controller using the get_irqnr_preamble macro. The
> rest of the GIC specific code can be shared.
>
> The omap code is excluded due to complexity and lack of
> hardware - the CONFIG_SMP macros are used for multi-omap
> and the omap4 case - this makes is difficult to share code.
>
> The s5pv310 subarch is excluded due to the special "addne"
> instruction in the get_irqnr_and_base macro.
>
> The msm subarch is excluded as well since it treats PPIs
> differently than other platforms and needs a different
> version of the get_irqnr_and_base macro.
>
> Signed-off-by: Magnus Damm <damm@opensource.se>
> Acked-by: Srinidhi Kasagar<srinidhi.kasagar@stericsson.com>
> ---
>
> ?Changes since V1:
> ?- dropped msm as requested by Abhijeet, thank you.
>
> ?This patch is almost identical to 6284/1 in the RMKs patch
> ?tracker. The main difference is that this patch requires
> ?each platform to specify base address using the macro
> ?get_irqnr_preable. This patch includes tegra, but drops
> ?omap support due to multi-omap complexity.
>
> ?Thanks to Shilimkar, Santosh and Srinidhi Kasagar for feedback.
>
> ?arch/arm/include/asm/hardware/entry-macro-gic.S ? | ? 68 +++++++++++++++++++++
> ?arch/arm/mach-cns3xxx/include/mach/entry-macro.S ?| ? 61 ------------------
> ?arch/arm/mach-realview/include/mach/entry-macro.S | ? 60 ------------------
> ?arch/arm/mach-tegra/include/mach/entry-macro.S ? ?| ? 64 -------------------
> ?arch/arm/mach-ux500/include/mach/entry-macro.S ? ?| ? 67 --------------------
> ?arch/arm/mach-vexpress/include/mach/entry-macro.S | ? 57 -----------------
> ?6 files changed, 73 insertions(+), 304 deletions(-)
>
> --- /dev/null
> +++ work/arch/arm/include/asm/hardware/entry-macro-gic.S ? ? ? ?2010-11-10 16:06:26.000000000 +0900
> @@ -0,0 +1,68 @@
> +/*
> + * arch/arm/include/asm/hardware/entry-macro-gic.S
> + *
> + * Low-level IRQ helper macros for GIC
> + *
> + * This file is licensed under ?the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <asm/hardware/gic.h>
> +
> +/*
> + * The interrupt numbering scheme is defined in the
> + * interrupt controller spec. ?To wit:
> + *
> + * Interrupts 0-15 are IPI
> + * 16-28 are reserved
> + * 29-31 are local. ?We allow 30 to be used for the watchdog.
> + * 32-1020 are global
> + * 1021-1022 are reserved
> + * 1023 is "spurious" (no interrupt)
> + *
> + * For now, we ignore all local interrupts so only return an interrupt if it's
> + * between 30 and 1020. ?The test_for_ipi routine below will pick up on IPIs.
> + *
> + * A simple read from the controller will tell us the number of the highest
> + * priority enabled interrupt. ?We then just need to check whether it is in the
> + * valid range for an IRQ (30-1020 inclusive).
> + */
> +
> + ? ? ? .macro ?get_irqnr_and_base, irqnr, irqstat, base, tmp
> +
> + ? ? ? ldr ? ? \irqstat, [\base, #GIC_CPU_INTACK]
> + ? ? ? /* bits 12-10 = src CPU, 9-0 = int # */
> +
> + ? ? ? ldr ? ? \tmp, =1021
> + ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> + ? ? ? cmp ? ? \irqnr, #29
> + ? ? ? cmpcc ? \irqnr, \irqnr
> + ? ? ? cmpne ? \irqnr, \tmp
> + ? ? ? cmpcs ? \irqnr, \irqnr
> + ? ? ? .endm
> +
> +/* We assume that irqstat (the raw value of the IRQ acknowledge
> + * register) is preserved from the macro above.
> + * If there is an IPI, we immediately signal end of interrupt on the
> + * controller, since this requires the original irqstat value which
> + * we won't easily be able to recreate later.
> + */
> +
> + ? ? ? .macro test_for_ipi, irqnr, irqstat, base, tmp
> + ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> + ? ? ? cmp ? ? \irqnr, #16
> + ? ? ? strcc ? \irqstat, [\base, #GIC_CPU_EOI]
> + ? ? ? cmpcs ? \irqnr, \irqnr
> + ? ? ? .endm
> +
> +/* As above, this assumes that irqstat and base are preserved.. */
> +
> + ? ? ? .macro test_for_ltirq, irqnr, irqstat, base, tmp
> + ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> + ? ? ? mov ? ? \tmp, #0
> + ? ? ? cmp ? ? \irqnr, #29
> + ? ? ? moveq ? \tmp, #1
> + ? ? ? streq ? \irqstat, [\base, #GIC_CPU_EOI]
> + ? ? ? cmp ? ? \tmp, #0
> + ? ? ? .endm
> --- 0001/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
> +++ work/arch/arm/mach-cns3xxx/include/mach/entry-macro.S ? ? ? 2010-11-10 16:06:25.000000000 +0900
> @@ -9,7 +9,7 @@
> ?*/
>
> ?#include <mach/hardware.h>
> -#include <asm/hardware/gic.h>
> +#include <asm/hardware/entry-macro-gic.S>
>
> ? ? ? ? ? ? ? ?.macro ?disable_fiq
> ? ? ? ? ? ? ? ?.endm
> @@ -21,62 +21,3 @@
>
> ? ? ? ? ? ? ? ?.macro ?arch_ret_to_user, tmp1, tmp2
> ? ? ? ? ? ? ? ?.endm
> -
> - ? ? ? ? ? ? ? /*
> - ? ? ? ? ? ? ? ?* The interrupt numbering scheme is defined in the
> - ? ? ? ? ? ? ? ?* interrupt controller spec. ?To wit:
> - ? ? ? ? ? ? ? ?*
> - ? ? ? ? ? ? ? ?* Interrupts 0-15 are IPI
> - ? ? ? ? ? ? ? ?* 16-28 are reserved
> - ? ? ? ? ? ? ? ?* 29-31 are local. ?We allow 30 to be used for the watchdog.
> - ? ? ? ? ? ? ? ?* 32-1020 are global
> - ? ? ? ? ? ? ? ?* 1021-1022 are reserved
> - ? ? ? ? ? ? ? ?* 1023 is "spurious" (no interrupt)
> - ? ? ? ? ? ? ? ?*
> - ? ? ? ? ? ? ? ?* For now, we ignore all local interrupts so only return an interrupt if it's
> - ? ? ? ? ? ? ? ?* between 30 and 1020. ?The test_for_ipi routine below will pick up on IPIs.
> - ? ? ? ? ? ? ? ?*
> - ? ? ? ? ? ? ? ?* A simple read from the controller will tell us the number of the highest
> - ? ? ? ? ? ? ? ? * priority enabled interrupt. ?We then just need to check whether it is in the
> - ? ? ? ? ? ? ? ?* valid range for an IRQ (30-1020 inclusive).
> - ? ? ? ? ? ? ? ?*/
> -
> - ? ? ? ? ? ? ? .macro ?get_irqnr_and_base, irqnr, irqstat, base, tmp
> -
> - ? ? ? ? ? ? ? ldr ? ? \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
> -
> - ? ? ? ? ? ? ? ldr ? ? \tmp, =1021
> -
> - ? ? ? ? ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> -
> - ? ? ? ? ? ? ? cmp ? ? \irqnr, #29
> - ? ? ? ? ? ? ? cmpcc ? \irqnr, \irqnr
> - ? ? ? ? ? ? ? cmpne ? \irqnr, \tmp
> - ? ? ? ? ? ? ? cmpcs ? \irqnr, \irqnr
> -
> - ? ? ? ? ? ? ? .endm
> -
> - ? ? ? ? ? ? ? /* We assume that irqstat (the raw value of the IRQ acknowledge
> - ? ? ? ? ? ? ? ?* register) is preserved from the macro above.
> - ? ? ? ? ? ? ? ?* If there is an IPI, we immediately signal end of interrupt on the
> - ? ? ? ? ? ? ? ?* controller, since this requires the original irqstat value which
> - ? ? ? ? ? ? ? ?* we won't easily be able to recreate later.
> - ? ? ? ? ? ? ? ?*/
> -
> - ? ? ? ? ? ? ? .macro test_for_ipi, irqnr, irqstat, base, tmp
> - ? ? ? ? ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> - ? ? ? ? ? ? ? cmp ? ? \irqnr, #16
> - ? ? ? ? ? ? ? strcc ? \irqstat, [\base, #GIC_CPU_EOI]
> - ? ? ? ? ? ? ? cmpcs ? \irqnr, \irqnr
> - ? ? ? ? ? ? ? .endm
> -
> - ? ? ? ? ? ? ? /* As above, this assumes that irqstat and base are preserved.. */
> -
> - ? ? ? ? ? ? ? .macro test_for_ltirq, irqnr, irqstat, base, tmp
> - ? ? ? ? ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> - ? ? ? ? ? ? ? mov ? ? \tmp, #0
> - ? ? ? ? ? ? ? cmp ? ? \irqnr, #29
> - ? ? ? ? ? ? ? moveq ? \tmp, #1
> - ? ? ? ? ? ? ? streq ? \irqstat, [\base, #GIC_CPU_EOI]
> - ? ? ? ? ? ? ? cmp ? ? \tmp, #0
> - ? ? ? ? ? ? ? .endm
> --- 0001/arch/arm/mach-realview/include/mach/entry-macro.S
> +++ work/arch/arm/mach-realview/include/mach/entry-macro.S ? ? ?2010-11-10 16:06:25.000000000 +0900
> @@ -8,7 +8,7 @@
> ?* warranty of any kind, whether express or implied.
> ?*/
> ?#include <mach/hardware.h>
> -#include <asm/hardware/gic.h>
> +#include <asm/hardware/entry-macro-gic.S>
>
> ? ? ? ? ? ? ? ?.macro ?disable_fiq
> ? ? ? ? ? ? ? ?.endm
> @@ -21,61 +21,3 @@
> ? ? ? ? ? ? ? ?.macro ?arch_ret_to_user, tmp1, tmp2
> ? ? ? ? ? ? ? ?.endm
>
> - ? ? ? ? ? ? ? /*
> - ? ? ? ? ? ? ? ?* The interrupt numbering scheme is defined in the
> - ? ? ? ? ? ? ? ?* interrupt controller spec. ?To wit:
> - ? ? ? ? ? ? ? ?*
> - ? ? ? ? ? ? ? ?* Interrupts 0-15 are IPI
> - ? ? ? ? ? ? ? ?* 16-28 are reserved
> - ? ? ? ? ? ? ? ?* 29-31 are local. ?We allow 30 to be used for the watchdog.
> - ? ? ? ? ? ? ? ?* 32-1020 are global
> - ? ? ? ? ? ? ? ?* 1021-1022 are reserved
> - ? ? ? ? ? ? ? ?* 1023 is "spurious" (no interrupt)
> - ? ? ? ? ? ? ? ?*
> - ? ? ? ? ? ? ? ?* For now, we ignore all local interrupts so only return an interrupt if it's
> - ? ? ? ? ? ? ? ?* between 30 and 1020. ?The test_for_ipi routine below will pick up on IPIs.
> - ? ? ? ? ? ? ? ?*
> - ? ? ? ? ? ? ? ?* A simple read from the controller will tell us the number of the highest
> - ? ? ? ? ? ? ? ? * priority enabled interrupt. ?We then just need to check whether it is in the
> - ? ? ? ? ? ? ? ?* valid range for an IRQ (30-1020 inclusive).
> - ? ? ? ? ? ? ? ?*/
> -
> - ? ? ? ? ? ? ? .macro ?get_irqnr_and_base, irqnr, irqstat, base, tmp
> -
> - ? ? ? ? ? ? ? ldr ? ? \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
> -
> - ? ? ? ? ? ? ? ldr ? ? \tmp, =1021
> -
> - ? ? ? ? ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> -
> - ? ? ? ? ? ? ? cmp ? ? \irqnr, #29
> - ? ? ? ? ? ? ? cmpcc ? \irqnr, \irqnr
> - ? ? ? ? ? ? ? cmpne ? \irqnr, \tmp
> - ? ? ? ? ? ? ? cmpcs ? \irqnr, \irqnr
> -
> - ? ? ? ? ? ? ? .endm
> -
> - ? ? ? ? ? ? ? /* We assume that irqstat (the raw value of the IRQ acknowledge
> - ? ? ? ? ? ? ? ?* register) is preserved from the macro above.
> - ? ? ? ? ? ? ? ?* If there is an IPI, we immediately signal end of interrupt on the
> - ? ? ? ? ? ? ? ?* controller, since this requires the original irqstat value which
> - ? ? ? ? ? ? ? ?* we won't easily be able to recreate later.
> - ? ? ? ? ? ? ? ?*/
> -
> - ? ? ? ? ? ? ? .macro test_for_ipi, irqnr, irqstat, base, tmp
> - ? ? ? ? ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> - ? ? ? ? ? ? ? cmp ? ? \irqnr, #16
> - ? ? ? ? ? ? ? strcc ? \irqstat, [\base, #GIC_CPU_EOI]
> - ? ? ? ? ? ? ? cmpcs ? \irqnr, \irqnr
> - ? ? ? ? ? ? ? .endm
> -
> - ? ? ? ? ? ? ? /* As above, this assumes that irqstat and base are preserved.. */
> -
> - ? ? ? ? ? ? ? .macro test_for_ltirq, irqnr, irqstat, base, tmp
> - ? ? ? ? ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> - ? ? ? ? ? ? ? mov ? ? \tmp, #0
> - ? ? ? ? ? ? ? cmp ? ? \irqnr, #29
> - ? ? ? ? ? ? ? moveq ? \tmp, #1
> - ? ? ? ? ? ? ? streq ? \irqstat, [\base, #GIC_CPU_EOI]
> - ? ? ? ? ? ? ? cmp ? ? \tmp, #0
> - ? ? ? ? ? ? ? .endm
> --- 0001/arch/arm/mach-tegra/include/mach/entry-macro.S
> +++ work/arch/arm/mach-tegra/include/mach/entry-macro.S 2010-11-10 16:06:25.000000000 +0900
> @@ -17,7 +17,7 @@
>
> ?#if defined(CONFIG_ARM_GIC)
>
> -#include <asm/hardware/gic.h>
> +#include <asm/hardware/entry-macro-gic.S>
>
> ? ? ? ?/* Uses the GIC interrupt controller built into the cpu */
> ?#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
> @@ -32,68 +32,6 @@
>
> ? ? ? ?.macro ?arch_ret_to_user, tmp1, tmp2
> ? ? ? ?.endm
> -
> - ? ? ? /*
> - ? ? ? ?* The interrupt numbering scheme is defined in the
> - ? ? ? ?* interrupt controller spec. ?To wit:
> - ? ? ? ?*
> - ? ? ? ?* Interrupts 0-15 are IPI
> - ? ? ? ?* 16-28 are reserved
> - ? ? ? ?* 29-31 are local. ?We allow 30 to be used for the watchdog.
> - ? ? ? ?* 32-1020 are global
> - ? ? ? ?* 1021-1022 are reserved
> - ? ? ? ?* 1023 is "spurious" (no interrupt)
> - ? ? ? ?*
> - ? ? ? ?* For now, we ignore all local interrupts so only return an interrupt
> - ? ? ? ?* if it's between 30 and 1020. ?The test_for_ipi routine below will
> - ? ? ? ?* pick up on IPIs.
> - ? ? ? ?*
> - ? ? ? ?* A simple read from the controller will tell us the number of the
> - ? ? ? ?* highest priority enabled interrupt. ?We then just need to check
> - ? ? ? ?* whether it is in the valid range for an IRQ (30-1020 inclusive).
> - ? ? ? ?*/
> -
> - ? ? ? .macro ?get_irqnr_and_base, irqnr, irqstat, base, tmp
> -
> - ? ? ? /* bits 12-10 = src CPU, 9-0 = int # */
> - ? ? ? ldr ? ? \irqstat, [\base, #GIC_CPU_INTACK]
> -
> - ? ? ? ldr ? ? ? ? ? ? \tmp, =1021
> -
> - ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> -
> - ? ? ? cmp ? ? \irqnr, #29
> - ? ? ? cmpcc ? \irqnr, \irqnr
> - ? ? ? cmpne ? \irqnr, \tmp
> - ? ? ? cmpcs ? \irqnr, \irqnr
> -
> - ? ? ? .endm
> -
> - ? ? ? /* We assume that irqstat (the raw value of the IRQ acknowledge
> - ? ? ? ?* register) is preserved from the macro above.
> - ? ? ? ?* If there is an IPI, we immediately signal end of interrupt on the
> - ? ? ? ?* controller, since this requires the original irqstat value which
> - ? ? ? ?* we won't easily be able to recreate later.
> - ? ? ? ?*/
> -
> - ? ? ? .macro test_for_ipi, irqnr, irqstat, base, tmp
> - ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> - ? ? ? cmp ? ? \irqnr, #16
> - ? ? ? strcc ? \irqstat, [\base, #GIC_CPU_EOI]
> - ? ? ? cmpcs ? \irqnr, \irqnr
> - ? ? ? .endm
> -
> - ? ? ? /* As above, this assumes that irqstat and base are preserved.. */
> -
> - ? ? ? .macro test_for_ltirq, irqnr, irqstat, base, tmp
> - ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> - ? ? ? mov ? ? \tmp, #0
> - ? ? ? cmp ? ? \irqnr, #29
> - ? ? ? moveq ? \tmp, #1
> - ? ? ? streq ? \irqstat, [\base, #GIC_CPU_EOI]
> - ? ? ? cmp ? ? \tmp, #0
> - ? ? ? .endm
> -
> ?#else
> ? ? ? ?/* legacy interrupt controller for AP16 */
> ? ? ? ?.macro ?disable_fiq
> --- 0001/arch/arm/mach-ux500/include/mach/entry-macro.S
> +++ work/arch/arm/mach-ux500/include/mach/entry-macro.S 2010-11-10 16:06:25.000000000 +0900
> @@ -11,7 +11,7 @@
> ?* warranty of any kind, whether express or implied.
> ?*/
> ?#include <mach/hardware.h>
> -#include <asm/hardware/gic.h>
> +#include <asm/hardware/entry-macro-gic.S>
>
> ? ? ? ? ? ? ? ?.macro ?disable_fiq
> ? ? ? ? ? ? ? ?.endm
> @@ -22,68 +22,3 @@
>
> ? ? ? ? ? ? ? ?.macro ?arch_ret_to_user, tmp1, tmp2
> ? ? ? ? ? ? ? ?.endm
> -
> - ? ? ? ? ? ? ? /*
> - ? ? ? ? ? ? ? ?* The interrupt numbering scheme is defined in the
> - ? ? ? ? ? ? ? ?* interrupt controller spec. ?To wit:
> - ? ? ? ? ? ? ? ?*
> - ? ? ? ? ? ? ? ?* Interrupts 0-15 are IPI
> - ? ? ? ? ? ? ? ?* 16-28 are reserved
> - ? ? ? ? ? ? ? ?* 29-31 are local. ?We allow 30 to be used for the watchdog.
> - ? ? ? ? ? ? ? ?* 32-1020 are global
> - ? ? ? ? ? ? ? ?* 1021-1022 are reserved
> - ? ? ? ? ? ? ? ?* 1023 is "spurious" (no interrupt)
> - ? ? ? ? ? ? ? ?*
> - ? ? ? ? ? ? ? ?* For now, we ignore all local interrupts so only return an
> - ? ? ? ? ? ? ? ?* interrupt if it's between 30 and 1020. The test_for_ipi
> - ? ? ? ? ? ? ? ?* routine below will pick up on IPIs.
> - ? ? ? ? ? ? ? ?*
> - ? ? ? ? ? ? ? ?* A simple read from the controller will tell us the number
> - ? ? ? ? ? ? ? ?* of the highest priority enabled interrupt. We then just
> - ? ? ? ? ? ? ? ?* need to check whether it is in the valid range for an
> - ? ? ? ? ? ? ? ?* IRQ (30-1020 inclusive).
> - ? ? ? ? ? ? ? ?*/
> -
> - ? ? ? ? ? ? ? .macro ?get_irqnr_and_base, irqnr, irqstat, base, tmp
> -
> - ? ? ? ? ? ? ? /* bits 12-10 = src CPU, 9-0 = int # */
> - ? ? ? ? ? ? ? ldr ? ? \irqstat, [\base, #GIC_CPU_INTACK]
> -
> - ? ? ? ? ? ? ? ldr ? ? \tmp, =1021
> -
> - ? ? ? ? ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> -
> - ? ? ? ? ? ? ? cmp ? ? \irqnr, #29
> - ? ? ? ? ? ? ? cmpcc ? \irqnr, \irqnr
> - ? ? ? ? ? ? ? cmpne ? \irqnr, \tmp
> - ? ? ? ? ? ? ? cmpcs ? \irqnr, \irqnr
> -
> - ? ? ? ? ? ? ? .endm
> -
> - ? ? ? ? ? ? ? /* We assume that irqstat (the raw value of the IRQ
> - ? ? ? ? ? ? ? ?* acknowledge register) is preserved from the macro above.
> - ? ? ? ? ? ? ? ?* If there is an IPI, we immediately signal end of
> - ? ? ? ? ? ? ? ?* interrupt on the controller, since this requires the
> - ? ? ? ? ? ? ? ?* original irqstat value which we won't easily be able
> - ? ? ? ? ? ? ? ?* to recreate later.
> - ? ? ? ? ? ? ? ?*/
> -
> - ? ? ? ? ? ? ? .macro test_for_ipi, irqnr, irqstat, base, tmp
> - ? ? ? ? ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> - ? ? ? ? ? ? ? cmp ? ? \irqnr, #16
> - ? ? ? ? ? ? ? strcc ? \irqstat, [\base, #GIC_CPU_EOI]
> - ? ? ? ? ? ? ? cmpcs ? \irqnr, \irqnr
> - ? ? ? ? ? ? ? .endm
> -
> - ? ? ? ? ? ? ? /* As above, this assumes that irqstat and base
> - ? ? ? ? ? ? ? ?* are preserved..
> - ? ? ? ? ? ? ? ?*/
> -
> - ? ? ? ? ? ? ? .macro test_for_ltirq, irqnr, irqstat, base, tmp
> - ? ? ? ? ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> - ? ? ? ? ? ? ? mov ? ? \tmp, #0
> - ? ? ? ? ? ? ? cmp ? ? \irqnr, #29
> - ? ? ? ? ? ? ? moveq ? \tmp, #1
> - ? ? ? ? ? ? ? streq ? \irqstat, [\base, #GIC_CPU_EOI]
> - ? ? ? ? ? ? ? cmp ? ? \tmp, #0
> - ? ? ? ? ? ? ? .endm
> --- 0001/arch/arm/mach-vexpress/include/mach/entry-macro.S
> +++ work/arch/arm/mach-vexpress/include/mach/entry-macro.S ? ? ?2010-11-10 16:06:25.000000000 +0900
> @@ -1,4 +1,4 @@
> -#include <asm/hardware/gic.h>
> +#include <asm/hardware/entry-macro-gic.S>
>
> ? ? ? ?.macro ?disable_fiq
> ? ? ? ?.endm
> @@ -10,58 +10,3 @@
>
> ? ? ? ?.macro ?arch_ret_to_user, tmp1, tmp2
> ? ? ? ?.endm
> -
> - ? ? ? /*
> - ? ? ? ?* The interrupt numbering scheme is defined in the
> - ? ? ? ?* interrupt controller spec. ?To wit:
> - ? ? ? ?*
> - ? ? ? ?* Interrupts 0-15 are IPI
> - ? ? ? ?* 16-28 are reserved
> - ? ? ? ?* 29-31 are local. ?We allow 30 to be used for the watchdog.
> - ? ? ? ?* 32-1020 are global
> - ? ? ? ?* 1021-1022 are reserved
> - ? ? ? ?* 1023 is "spurious" (no interrupt)
> - ? ? ? ?*
> - ? ? ? ?* For now, we ignore all local interrupts so only return an interrupt if it's
> - ? ? ? ?* between 30 and 1020. ?The test_for_ipi routine below will pick up on IPIs.
> - ? ? ? ?*
> - ? ? ? ?* A simple read from the controller will tell us the number of the highest
> - ? ? ? ?* priority enabled interrupt. ?We then just need to check whether it is in the
> - ? ? ? ?* valid range for an IRQ (30-1020 inclusive).
> - ? ? ? ?*/
> -
> - ? ? ? .macro ?get_irqnr_and_base, irqnr, irqstat, base, tmp
> - ? ? ? ldr ? ? \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
> - ? ? ? ldr ? ? \tmp, =1021
> - ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> - ? ? ? cmp ? ? \irqnr, #29
> - ? ? ? cmpcc ? \irqnr, \irqnr
> - ? ? ? cmpne ? \irqnr, \tmp
> - ? ? ? cmpcs ? \irqnr, \irqnr
> - ? ? ? .endm
> -
> - ? ? ? /* We assume that irqstat (the raw value of the IRQ acknowledge
> - ? ? ? ?* register) is preserved from the macro above.
> - ? ? ? ?* If there is an IPI, we immediately signal end of interrupt on the
> - ? ? ? ?* controller, since this requires the original irqstat value which
> - ? ? ? ?* we won't easily be able to recreate later.
> - ? ? ? ?*/
> -
> - ? ? ? .macro test_for_ipi, irqnr, irqstat, base, tmp
> - ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> - ? ? ? cmp ? ? \irqnr, #16
> - ? ? ? strcc ? \irqstat, [\base, #GIC_CPU_EOI]
> - ? ? ? cmpcs ? \irqnr, \irqnr
> - ? ? ? .endm
> -
> - ? ? ? /* As above, this assumes that irqstat and base are preserved.. */
> -
> - ? ? ? .macro test_for_ltirq, irqnr, irqstat, base, tmp
> - ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> - ? ? ? mov ? ? \tmp, #0
> - ? ? ? cmp ? ? \irqnr, #29
> - ? ? ? moveq ? \tmp, #1
> - ? ? ? streq ? \irqstat, [\base, #GIC_CPU_EOI]
> - ? ? ? cmp ? ? \tmp, #0
> - ? ? ? .endm
> -
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

[PATCH] ARM: Common GIC entry macro code V2

[Kukjin Kim]

Kyungmin Park wrote:
> 
> Hi,
> 
Hi,

> Can you include the "arch/arm/mach-s5pv310/include/mach/entry-macro.S"
also?
> 
In conclusion, can't it now.
Because according to current interrupt number structure of Samsung SoCs,
irqnr macro need to add S5P_IRQ_OFFSET, 32.

Or have to add #ifdef in there...But don't like it.

> On Thu, Nov 11, 2010 at 4:49 PM, Magnus Damm <magnus.damm@gmail.com>
wrote:
> > From: Magnus Damm <damm@opensource.se>
> >
> > This patch is the identical GIC demux implementation
> > merge V2. Instead of implementing same code over and
> > over simply share it in entry-macro-gic.S. The shared
> > code is based on the realview implementation.
> >
> > Each GIC demux instance still has to setup the base address
> > of the controller using the get_irqnr_preamble macro. The
> > rest of the GIC specific code can be shared.
> >
> > The omap code is excluded due to complexity and lack of
> > hardware - the CONFIG_SMP macros are used for multi-omap
> > and the omap4 case - this makes is difficult to share code.
> >
> > The s5pv310 subarch is excluded due to the special "addne"
> > instruction in the get_irqnr_and_base macro.
> >
> > The msm subarch is excluded as well since it treats PPIs
> > differently than other platforms and needs a different
> > version of the get_irqnr_and_base macro.
> >
> > Signed-off-by: Magnus Damm <damm@opensource.se>
> > Acked-by: Srinidhi Kasagar<srinidhi.kasagar@stericsson.com>
> > ---
> >
> > ?Changes since V1:
> > ?- dropped msm as requested by Abhijeet, thank you.
> >
> > ?This patch is almost identical to 6284/1 in the RMKs patch
> > ?tracker. The main difference is that this patch requires
> > ?each platform to specify base address using the macro
> > ?get_irqnr_preable. This patch includes tegra, but drops
> > ?omap support due to multi-omap complexity.
> >
> > ?Thanks to Shilimkar, Santosh and Srinidhi Kasagar for feedback.
> >
> > ?arch/arm/include/asm/hardware/entry-macro-gic.S ? | ? 68
> +++++++++++++++++++++
> > ?arch/arm/mach-cns3xxx/include/mach/entry-macro.S ?| ? 61
-----------------
> -
> > ?arch/arm/mach-realview/include/mach/entry-macro.S | ? 60
-----------------
> -
> > ?arch/arm/mach-tegra/include/mach/entry-macro.S ? ?| ? 64
-----------------
> --
> > ?arch/arm/mach-ux500/include/mach/entry-macro.S ? ?| ? 67
-----------------
> ---
> > ?arch/arm/mach-vexpress/include/mach/entry-macro.S | ? 57
-----------------
> > ?6 files changed, 73 insertions(+), 304 deletions(-)
> >
> > --- /dev/null
> > +++ work/arch/arm/include/asm/hardware/entry-macro-gic.S ? ? ?
?2010-11-10
> 16:06:26.000000000 +0900
> > @@ -0,0 +1,68 @@
> > +/*
> > + * arch/arm/include/asm/hardware/entry-macro-gic.S
> > + *
> > + * Low-level IRQ helper macros for GIC
> > + *
> > + * This file is licensed under ?the terms of the GNU General Public
> > + * License version 2. This program is licensed "as is" without any
> > + * warranty of any kind, whether express or implied.
> > + */
> > +
> > +#include <asm/hardware/gic.h>
> > +
> > +/*
> > + * The interrupt numbering scheme is defined in the
> > + * interrupt controller spec. ?To wit:
> > + *
> > + * Interrupts 0-15 are IPI
> > + * 16-28 are reserved
> > + * 29-31 are local. ?We allow 30 to be used for the watchdog.
> > + * 32-1020 are global
> > + * 1021-1022 are reserved
> > + * 1023 is "spurious" (no interrupt)
> > + *
> > + * For now, we ignore all local interrupts so only return an interrupt
if
> it's
> > + * between 30 and 1020. ?The test_for_ipi routine below will pick up on
> IPIs.
> > + *
> > + * A simple read from the controller will tell us the number of the
> highest
> > + * priority enabled interrupt. ?We then just need to check whether it
is
> in the
> > + * valid range for an IRQ (30-1020 inclusive).
> > + */
> > +
> > + ? ? ? .macro ?get_irqnr_and_base, irqnr, irqstat, base, tmp
> > +
> > + ? ? ? ldr ? ? \irqstat, [\base, #GIC_CPU_INTACK]
> > + ? ? ? /* bits 12-10 = src CPU, 9-0 = int # */
> > +
> > + ? ? ? ldr ? ? \tmp, =1021
> > + ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> > + ? ? ? cmp ? ? \irqnr, #29
> > + ? ? ? cmpcc ? \irqnr, \irqnr
> > + ? ? ? cmpne ? \irqnr, \tmp
> > + ? ? ? cmpcs ? \irqnr, \irqnr
> > + ? ? ? .endm
> > +
> > +/* We assume that irqstat (the raw value of the IRQ acknowledge
> > + * register) is preserved from the macro above.
> > + * If there is an IPI, we immediately signal end of interrupt on the
> > + * controller, since this requires the original irqstat value which
> > + * we won't easily be able to recreate later.
> > + */
> > +
> > + ? ? ? .macro test_for_ipi, irqnr, irqstat, base, tmp
> > + ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> > + ? ? ? cmp ? ? \irqnr, #16
> > + ? ? ? strcc ? \irqstat, [\base, #GIC_CPU_EOI]
> > + ? ? ? cmpcs ? \irqnr, \irqnr
> > + ? ? ? .endm
> > +
> > +/* As above, this assumes that irqstat and base are preserved.. */
> > +
> > + ? ? ? .macro test_for_ltirq, irqnr, irqstat, base, tmp
> > + ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
> > + ? ? ? mov ? ? \tmp, #0
> > + ? ? ? cmp ? ? \irqnr, #29
> > + ? ? ? moveq ? \tmp, #1
> > + ? ? ? streq ? \irqstat, [\base, #GIC_CPU_EOI]
> > + ? ? ? cmp ? ? \tmp, #0
> > + ? ? ? .endm

(snip)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH] ARM: Common GIC entry macro code V2

[Kyungmin Park]

On Thu, Nov 11, 2010 at 6:36 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Kyungmin Park wrote:
>>
>> Hi,
>>
> Hi,
>
>> Can you include the "arch/arm/mach-s5pv310/include/mach/entry-macro.S"
> also?
>>
> In conclusion, can't it now.
> Because according to current interrupt number structure of Samsung SoCs,
> irqnr macro need to add S5P_IRQ_OFFSET, 32.
>
> Or have to add #ifdef in there...But don't like it.

I wonder why Samsung goes another way, use the common codes. if
required, modify to use the common codes.

Thank you,
Kyungmin Park

>
>> On Thu, Nov 11, 2010 at 4:49 PM, Magnus Damm <magnus.damm@gmail.com>
> wrote:
>> > From: Magnus Damm <damm@opensource.se>
>> >
>> > This patch is the identical GIC demux implementation
>> > merge V2. Instead of implementing same code over and
>> > over simply share it in entry-macro-gic.S. The shared
>> > code is based on the realview implementation.
>> >
>> > Each GIC demux instance still has to setup the base address
>> > of the controller using the get_irqnr_preamble macro. The
>> > rest of the GIC specific code can be shared.
>> >
>> > The omap code is excluded due to complexity and lack of
>> > hardware - the CONFIG_SMP macros are used for multi-omap
>> > and the omap4 case - this makes is difficult to share code.
>> >
>> > The s5pv310 subarch is excluded due to the special "addne"
>> > instruction in the get_irqnr_and_base macro.
>> >
>> > The msm subarch is excluded as well since it treats PPIs
>> > differently than other platforms and needs a different
>> > version of the get_irqnr_and_base macro.
>> >
>> > Signed-off-by: Magnus Damm <damm@opensource.se>
>> > Acked-by: Srinidhi Kasagar<srinidhi.kasagar@stericsson.com>
>> > ---
>> >
>> > ?Changes since V1:
>> > ?- dropped msm as requested by Abhijeet, thank you.
>> >
>> > ?This patch is almost identical to 6284/1 in the RMKs patch
>> > ?tracker. The main difference is that this patch requires
>> > ?each platform to specify base address using the macro
>> > ?get_irqnr_preable. This patch includes tegra, but drops
>> > ?omap support due to multi-omap complexity.
>> >
>> > ?Thanks to Shilimkar, Santosh and Srinidhi Kasagar for feedback.
>> >
>> > ?arch/arm/include/asm/hardware/entry-macro-gic.S ? | ? 68
>> +++++++++++++++++++++
>> > ?arch/arm/mach-cns3xxx/include/mach/entry-macro.S ?| ? 61
> -----------------
>> -
>> > ?arch/arm/mach-realview/include/mach/entry-macro.S | ? 60
> -----------------
>> -
>> > ?arch/arm/mach-tegra/include/mach/entry-macro.S ? ?| ? 64
> -----------------
>> --
>> > ?arch/arm/mach-ux500/include/mach/entry-macro.S ? ?| ? 67
> -----------------
>> ---
>> > ?arch/arm/mach-vexpress/include/mach/entry-macro.S | ? 57
> -----------------
>> > ?6 files changed, 73 insertions(+), 304 deletions(-)
>> >
>> > --- /dev/null
>> > +++ work/arch/arm/include/asm/hardware/entry-macro-gic.S
> ?2010-11-10
>> 16:06:26.000000000 +0900
>> > @@ -0,0 +1,68 @@
>> > +/*
>> > + * arch/arm/include/asm/hardware/entry-macro-gic.S
>> > + *
>> > + * Low-level IRQ helper macros for GIC
>> > + *
>> > + * This file is licensed under ?the terms of the GNU General Public
>> > + * License version 2. This program is licensed "as is" without any
>> > + * warranty of any kind, whether express or implied.
>> > + */
>> > +
>> > +#include <asm/hardware/gic.h>
>> > +
>> > +/*
>> > + * The interrupt numbering scheme is defined in the
>> > + * interrupt controller spec. ?To wit:
>> > + *
>> > + * Interrupts 0-15 are IPI
>> > + * 16-28 are reserved
>> > + * 29-31 are local. ?We allow 30 to be used for the watchdog.
>> > + * 32-1020 are global
>> > + * 1021-1022 are reserved
>> > + * 1023 is "spurious" (no interrupt)
>> > + *
>> > + * For now, we ignore all local interrupts so only return an interrupt
> if
>> it's
>> > + * between 30 and 1020. ?The test_for_ipi routine below will pick up on
>> IPIs.
>> > + *
>> > + * A simple read from the controller will tell us the number of the
>> highest
>> > + * priority enabled interrupt. ?We then just need to check whether it
> is
>> in the
>> > + * valid range for an IRQ (30-1020 inclusive).
>> > + */
>> > +
>> > + ? ? ? .macro ?get_irqnr_and_base, irqnr, irqstat, base, tmp
>> > +
>> > + ? ? ? ldr ? ? \irqstat, [\base, #GIC_CPU_INTACK]
>> > + ? ? ? /* bits 12-10 = src CPU, 9-0 = int # */
>> > +
>> > + ? ? ? ldr ? ? \tmp, =1021
>> > + ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
>> > + ? ? ? cmp ? ? \irqnr, #29
>> > + ? ? ? cmpcc ? \irqnr, \irqnr
>> > + ? ? ? cmpne ? \irqnr, \tmp
>> > + ? ? ? cmpcs ? \irqnr, \irqnr
>> > + ? ? ? .endm
>> > +
>> > +/* We assume that irqstat (the raw value of the IRQ acknowledge
>> > + * register) is preserved from the macro above.
>> > + * If there is an IPI, we immediately signal end of interrupt on the
>> > + * controller, since this requires the original irqstat value which
>> > + * we won't easily be able to recreate later.
>> > + */
>> > +
>> > + ? ? ? .macro test_for_ipi, irqnr, irqstat, base, tmp
>> > + ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
>> > + ? ? ? cmp ? ? \irqnr, #16
>> > + ? ? ? strcc ? \irqstat, [\base, #GIC_CPU_EOI]
>> > + ? ? ? cmpcs ? \irqnr, \irqnr
>> > + ? ? ? .endm
>> > +
>> > +/* As above, this assumes that irqstat and base are preserved.. */
>> > +
>> > + ? ? ? .macro test_for_ltirq, irqnr, irqstat, base, tmp
>> > + ? ? ? bic ? ? \irqnr, \irqstat, #0x1c00
>> > + ? ? ? mov ? ? \tmp, #0
>> > + ? ? ? cmp ? ? \irqnr, #29
>> > + ? ? ? moveq ? \tmp, #1
>> > + ? ? ? streq ? \irqstat, [\base, #GIC_CPU_EOI]
>> > + ? ? ? cmp ? ? \tmp, #0
>> > + ? ? ? .endm
>
> (snip)
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>

[PATCH] ARM: Common GIC entry macro code V2

[Magnus Damm]

On Thu, Nov 11, 2010 at 6:51 PM, Kyungmin Park <kmpark@infradead.org> wrote:
> On Thu, Nov 11, 2010 at 6:36 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
>> Kyungmin Park wrote:
>>>
>>> Can you include the "arch/arm/mach-s5pv310/include/mach/entry-macro.S"
>> also?
>>>
>> In conclusion, can't it now.
>> Because according to current interrupt number structure of Samsung SoCs,
>> irqnr macro need to add S5P_IRQ_OFFSET, 32.
>>
>> Or have to add #ifdef in there...But don't like it.
>
> I wonder why Samsung goes another way, use the common codes. if
> required, modify to use the common codes.

Yes, it would be nice if Samsung could use the common code as well. I
will however ignore this for now to focus on getting something merged
that most people can use. The Samsung bits can be dealt with
incrementally.

Thanks,

/ magnus

[PATCH] ARM: Common GIC entry macro code V2

[Daniel Walker]

On Thu, 2010-11-11 at 16:49 +0900, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
> 
> This patch is the identical GIC demux implementation
> merge V2. Instead of implementing same code over and
> over simply share it in entry-macro-gic.S. The shared
> code is based on the realview implementation.
> 
> Each GIC demux instance still has to setup the base address
> of the controller using the get_irqnr_preamble macro. The
> rest of the GIC specific code can be shared.
> 
> The omap code is excluded due to complexity and lack of
> hardware - the CONFIG_SMP macros are used for multi-omap
> and the omap4 case - this makes is difficult to share code.
> 
> The s5pv310 subarch is excluded due to the special "addne"
> instruction in the get_irqnr_and_base macro.
> 
> The msm subarch is excluded as well since it treats PPIs
> differently than other platforms and needs a different
> version of the get_irqnr_and_base macro.

I'm a little disappoint you didn't CC someone MSM related on this. Your
patch is small enough that you can CC everyone effected. Here's
get_maintainer.pl output on it,

Russell King <linux@arm.linux.org.uk>
Anton Vorontsov <avorontsov@mvista.com>
Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Linus Walleij <linus.walleij@stericsson.com>
Alessandro Rubini <rubini@unipv.it>
linux-arm-kernel at lists.infradead.org
linux-kernel at vger.kernel.org

At least those people should be getting this. Also, why can't you break
this up per sub-architecture ?

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH] ARM: Common GIC entry macro code V2

[Magnus Damm]

On Fri, Nov 12, 2010 at 5:24 AM, Daniel Walker <dwalker@codeaurora.org> wrote:
> On Thu, 2010-11-11 at 16:49 +0900, Magnus Damm wrote:
>> From: Magnus Damm <damm@opensource.se>
>>
>> This patch is the identical GIC demux implementation
>> merge V2. Instead of implementing same code over and
>> over simply share it in entry-macro-gic.S. The shared
>> code is based on the realview implementation.
>>
>> Each GIC demux instance still has to setup the base address
>> of the controller using the get_irqnr_preamble macro. The
>> rest of the GIC specific code can be shared.
>>
>> The omap code is excluded due to complexity and lack of
>> hardware - the CONFIG_SMP macros are used for multi-omap
>> and the omap4 case - this makes is difficult to share code.
>>
>> The s5pv310 subarch is excluded due to the special "addne"
>> instruction in the get_irqnr_and_base macro.
>>
>> The msm subarch is excluded as well since it treats PPIs
>> differently than other platforms and needs a different
>> version of the get_irqnr_and_base macro.
>
> I'm a little disappoint you didn't CC someone MSM related on this. Your
> patch is small enough that you can CC everyone effected. Here's
> get_maintainer.pl output on it,
>
> Russell King <linux@arm.linux.org.uk>
> Anton Vorontsov <avorontsov@mvista.com>
> Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
> Linus Walleij <linus.walleij@stericsson.com>
> Alessandro Rubini <rubini@unipv.it>
> linux-arm-kernel at lists.infradead.org
> linux-kernel at vger.kernel.org

Hi Daniel,

Sorry to disappoint you, will use get_maintainer.pl and include people
from former versions when I send out next version.

> At least those people should be getting this. Also, why can't you break
> this up per sub-architecture ?

[PATCH] ARM: Common GIC entry macro code V2

[Tony Lindgren]

Hi Magnus,

* Magnus Damm <magnus.damm@gmail.com> [101110 23:37]:
> 
> The omap code is excluded due to complexity and lack of
> hardware - the CONFIG_SMP macros are used for multi-omap
> and the omap4 case - this makes is difficult to share code.

Hmm test_for_ipi and test_for_ltirq are needed for the
SMP_ON_UP case, so I've moved those in to the MULTI_OMAP2
section.

Maybe merge the following into your original patch?

Regards,

Tony

From: Tony Lindgren <tony@atomide.com>
Date: Thu, 11 Nov 2010 16:19:44 -0800
Subject: [PATCH] ARM: Common GIC entry macro for omap

Common GIC entry macro for omap

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 06e64e1..2e358df 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -105,6 +105,35 @@ omap_irq_base:	.word	0
 9999:
 		.endm
 
+#ifdef CONFIG_SMP
+		/* We assume that irqstat (the raw value of the IRQ acknowledge
+		 * register) is preserved from the macro above.
+		 * If there is an IPI, we immediately signal end of interrupt
+		 * on the controller, since this requires the original irqstat
+		 * value which we won't easily be able to recreate later.
+		 */
+
+		.macro test_for_ipi, irqnr, irqstat, base, tmp
+		bic	\irqnr, \irqstat, #0x1c00
+		cmp	\irqnr, #16
+		it	cc
+		strcc	\irqstat, [\base, #GIC_CPU_EOI]
+		it	cs
+		cmpcs	\irqnr, \irqnr
+		.endm
+
+		/* As above, this assumes that irqstat and base are preserved */
+
+		.macro test_for_ltirq, irqnr, irqstat, base, tmp
+		bic	\irqnr, \irqstat, #0x1c00
+		mov 	\tmp, #0
+		cmp	\irqnr, #29
+		itt	eq
+		moveq	\tmp, #1
+		streq	\irqstat, [\base, #GIC_CPU_EOI]
+		cmp	\tmp, #0
+		.endm
+#endif	/* CONFIG_SMP */
 
 #else	/* MULTI_OMAP2 */
 
@@ -141,74 +170,15 @@ omap_irq_base:	.word	0
 
 
 #ifdef CONFIG_ARCH_OMAP4
+#include <asm/hardware/entry-macro-gic.S>
 
 		.macro  get_irqnr_preamble, base, tmp
 		ldr     \base, =OMAP4_IRQ_BASE
 		.endm
 
-		/*
-		 * The interrupt numbering scheme is defined in the
-		 * interrupt controller spec.  To wit:
-		 *
-		 * Interrupts 0-15 are IPI
-		 * 16-28 are reserved
-		 * 29-31 are local.  We allow 30 to be used for the watchdog.
-		 * 32-1020 are global
-		 * 1021-1022 are reserved
-		 * 1023 is "spurious" (no interrupt)
-		 *
-		 * For now, we ignore all local interrupts so only return an
-		 * interrupt if it's between 30 and 1020.  The test_for_ipi
-		 * routine below will pick up on IPIs.
-		 * A simple read from the controller will tell us the number
-		 * of the highest priority enabled interrupt.
-		 * We then just need to check whether it is in the
-		 * valid range for an IRQ (30-1020 inclusive).
-		 */
-		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-		ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-
-		ldr     \tmp, =1021
-
-		bic     \irqnr, \irqstat, #0x1c00
-
-		cmp     \irqnr, #29
-		cmpcc   \irqnr, \irqnr
-		cmpne   \irqnr, \tmp
-		cmpcs   \irqnr, \irqnr
-		.endm
 #endif
-#endif	/* MULTI_OMAP2 */
-
-#ifdef CONFIG_SMP
-		/* We assume that irqstat (the raw value of the IRQ acknowledge
-		 * register) is preserved from the macro above.
-		 * If there is an IPI, we immediately signal end of interrupt
-		 * on the controller, since this requires the original irqstat
-		 * value which we won't easily be able to recreate later.
-		 */
 
-		.macro test_for_ipi, irqnr, irqstat, base, tmp
-		bic	\irqnr, \irqstat, #0x1c00
-		cmp	\irqnr, #16
-		it	cc
-		strcc	\irqstat, [\base, #GIC_CPU_EOI]
-		it	cs
-		cmpcs	\irqnr, \irqnr
-		.endm
-
-		/* As above, this assumes that irqstat and base are preserved */
-
-		.macro test_for_ltirq, irqnr, irqstat, base, tmp
-		bic	\irqnr, \irqstat, #0x1c00
-		mov 	\tmp, #0
-		cmp	\irqnr, #29
-		itt	eq
-		moveq	\tmp, #1
-		streq	\irqstat, [\base, #GIC_CPU_EOI]
-		cmp	\tmp, #0
-		.endm
-#endif	/* CONFIG_SMP */
+#endif	/* MULTI_OMAP2 */
 
 		.macro	irq_prio_table
 		.endm

[PATCH] ARM: Common GIC entry macro code V2

[Magnus Damm]

Hi Tony,

On Fri, Nov 12, 2010 at 9:42 AM, Tony Lindgren <tony@atomide.com> wrote:
> Hi Magnus,
>
> * Magnus Damm <magnus.damm@gmail.com> [101110 23:37]:
>>
>> The omap code is excluded due to complexity and lack of
>> hardware - the CONFIG_SMP macros are used for multi-omap
>> and the omap4 case - this makes is difficult to share code.
>
> Hmm test_for_ipi and test_for_ltirq are needed for the
> SMP_ON_UP case, so I've moved those in to the MULTI_OMAP2
> section.

Looking good!

> Maybe merge the following into your original patch?

Sure, I'll include your code as a broken out patch in V3.

Thank you!

/ magnus