* [PATCH 01/07] ARM: Introduce asm/hardware/entry-macro-gic.S
2010-11-12 8:20 [PATCH 00/07] ARM: Common GIC entry macro code V3 Magnus Damm
@ 2010-11-12 8:21 ` Magnus Damm
2010-11-12 8:21 ` [PATCH 02/07] ARM: Use shared GIC entry macros on CNS3XXX Magnus Damm
` (6 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Magnus Damm @ 2010-11-12 8:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
This patch is the identical GIC demux implementation
merge V3. Instead of implementing same code over and
over simply share it in entry-macro-gic.S. The shared
code is based on the realview implementation.
Each GIC demux instance still has to setup the base address
of the controller using the get_irqnr_preamble macro. The
rest of the GIC specific code can be shared.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Srinidhi Kasagar<srinidhi.kasagar@stericsson.com>
---
Changes since V2:
- broke out patches into base + per sub-arch
arch/arm/include/asm/hardware/entry-macro-gic.S | 68 +++++++++++++++++++++++
1 file changed, 68 insertions(+)
--- /dev/null
+++ work/arch/arm/include/asm/hardware/entry-macro-gic.S 2010-11-12 15:57:05.000000000 +0900
@@ -0,0 +1,68 @@
+/*
+ * arch/arm/include/asm/hardware/entry-macro-gic.S
+ *
+ * Low-level IRQ helper macros for GIC
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/hardware/gic.h>
+
+/*
+ * The interrupt numbering scheme is defined in the
+ * interrupt controller spec. To wit:
+ *
+ * Interrupts 0-15 are IPI
+ * 16-28 are reserved
+ * 29-31 are local. We allow 30 to be used for the watchdog.
+ * 32-1020 are global
+ * 1021-1022 are reserved
+ * 1023 is "spurious" (no interrupt)
+ *
+ * For now, we ignore all local interrupts so only return an interrupt if it's
+ * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
+ *
+ * A simple read from the controller will tell us the number of the highest
+ * priority enabled interrupt. We then just need to check whether it is in the
+ * valid range for an IRQ (30-1020 inclusive).
+ */
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+ ldr \irqstat, [\base, #GIC_CPU_INTACK]
+ /* bits 12-10 = src CPU, 9-0 = int # */
+
+ ldr \tmp, =1021
+ bic \irqnr, \irqstat, #0x1c00
+ cmp \irqnr, #29
+ cmpcc \irqnr, \irqnr
+ cmpne \irqnr, \tmp
+ cmpcs \irqnr, \irqnr
+ .endm
+
+/* We assume that irqstat (the raw value of the IRQ acknowledge
+ * register) is preserved from the macro above.
+ * If there is an IPI, we immediately signal end of interrupt on the
+ * controller, since this requires the original irqstat value which
+ * we won't easily be able to recreate later.
+ */
+
+ .macro test_for_ipi, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ cmp \irqnr, #16
+ strcc \irqstat, [\base, #GIC_CPU_EOI]
+ cmpcs \irqnr, \irqnr
+ .endm
+
+/* As above, this assumes that irqstat and base are preserved.. */
+
+ .macro test_for_ltirq, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ mov \tmp, #0
+ cmp \irqnr, #29
+ moveq \tmp, #1
+ streq \irqstat, [\base, #GIC_CPU_EOI]
+ cmp \tmp, #0
+ .endm
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 02/07] ARM: Use shared GIC entry macros on CNS3XXX
2010-11-12 8:20 [PATCH 00/07] ARM: Common GIC entry macro code V3 Magnus Damm
2010-11-12 8:21 ` [PATCH 01/07] ARM: Introduce asm/hardware/entry-macro-gic.S Magnus Damm
@ 2010-11-12 8:21 ` Magnus Damm
2010-11-12 8:21 ` [PATCH 03/07] ARM: Use shared GIC entry macros on Realview Magnus Damm
` (5 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Magnus Damm @ 2010-11-12 8:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
Use the GIC demux code in asm/hardware/entry-macro-gic.S
on the CNS3XXX subarchitecture.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-cns3xxx/include/mach/entry-macro.S | 61 ----------------------
1 file changed, 1 insertion(+), 60 deletions(-)
--- 0001/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
+++ work/arch/arm/mach-cns3xxx/include/mach/entry-macro.S 2010-11-12 15:58:46.000000000 +0900
@@ -9,7 +9,7 @@
*/
#include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
.macro disable_fiq
.endm
@@ -21,62 +21,3 @@
.macro arch_ret_to_user, tmp1, tmp2
.endm
-
- /*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * For now, we ignore all local interrupts so only return an interrupt if it's
- * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
- *
- * A simple read from the controller will tell us the number of the highest
- * priority enabled interrupt. We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-
- ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-
- ldr \tmp, =1021
-
- bic \irqnr, \irqstat, #0x1c00
-
- cmp \irqnr, #29
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
-
- .endm
-
- /* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt on the
- * controller, since this requires the original irqstat value which
- * we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- cmpcs \irqnr, \irqnr
- .endm
-
- /* As above, this assumes that irqstat and base are preserved.. */
-
- .macro test_for_ltirq, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- mov \tmp, #0
- cmp \irqnr, #29
- moveq \tmp, #1
- streq \irqstat, [\base, #GIC_CPU_EOI]
- cmp \tmp, #0
- .endm
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 03/07] ARM: Use shared GIC entry macros on Realview
2010-11-12 8:20 [PATCH 00/07] ARM: Common GIC entry macro code V3 Magnus Damm
2010-11-12 8:21 ` [PATCH 01/07] ARM: Introduce asm/hardware/entry-macro-gic.S Magnus Damm
2010-11-12 8:21 ` [PATCH 02/07] ARM: Use shared GIC entry macros on CNS3XXX Magnus Damm
@ 2010-11-12 8:21 ` Magnus Damm
2010-11-12 8:21 ` [PATCH 04/07] ARM: Use shared GIC entry macros on Tegra Magnus Damm
` (4 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Magnus Damm @ 2010-11-12 8:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
Use the GIC demux code in asm/hardware/entry-macro-gic.S
on the Realview subarchitecture.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-realview/include/mach/entry-macro.S | 60 ---------------------
1 file changed, 1 insertion(+), 59 deletions(-)
--- 0001/arch/arm/mach-realview/include/mach/entry-macro.S
+++ work/arch/arm/mach-realview/include/mach/entry-macro.S 2010-11-12 15:59:57.000000000 +0900
@@ -8,7 +8,7 @@
* warranty of any kind, whether express or implied.
*/
#include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
.macro disable_fiq
.endm
@@ -21,61 +21,3 @@
.macro arch_ret_to_user, tmp1, tmp2
.endm
- /*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * For now, we ignore all local interrupts so only return an interrupt if it's
- * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
- *
- * A simple read from the controller will tell us the number of the highest
- * priority enabled interrupt. We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-
- ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-
- ldr \tmp, =1021
-
- bic \irqnr, \irqstat, #0x1c00
-
- cmp \irqnr, #29
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
-
- .endm
-
- /* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt on the
- * controller, since this requires the original irqstat value which
- * we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- cmpcs \irqnr, \irqnr
- .endm
-
- /* As above, this assumes that irqstat and base are preserved.. */
-
- .macro test_for_ltirq, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- mov \tmp, #0
- cmp \irqnr, #29
- moveq \tmp, #1
- streq \irqstat, [\base, #GIC_CPU_EOI]
- cmp \tmp, #0
- .endm
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 04/07] ARM: Use shared GIC entry macros on Tegra
2010-11-12 8:20 [PATCH 00/07] ARM: Common GIC entry macro code V3 Magnus Damm
` (2 preceding siblings ...)
2010-11-12 8:21 ` [PATCH 03/07] ARM: Use shared GIC entry macros on Realview Magnus Damm
@ 2010-11-12 8:21 ` Magnus Damm
2010-11-12 17:14 ` Olof Johansson
2010-11-12 8:21 ` [PATCH 05/07] ARM: Use shared GIC entry macros on UX500 Magnus Damm
` (3 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Magnus Damm @ 2010-11-12 8:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
Use the GIC demux code in asm/hardware/entry-macro-gic.S
on the Tegra subarchitecture.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-tegra/include/mach/entry-macro.S | 64 ------------------------
1 file changed, 1 insertion(+), 63 deletions(-)
--- 0001/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ work/arch/arm/mach-tegra/include/mach/entry-macro.S 2010-11-12 16:01:47.000000000 +0900
@@ -17,7 +17,7 @@
#if defined(CONFIG_ARM_GIC)
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
/* Uses the GIC interrupt controller built into the cpu */
#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
@@ -32,68 +32,6 @@
.macro arch_ret_to_user, tmp1, tmp2
.endm
-
- /*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * For now, we ignore all local interrupts so only return an interrupt
- * if it's between 30 and 1020. The test_for_ipi routine below will
- * pick up on IPIs.
- *
- * A simple read from the controller will tell us the number of the
- * highest priority enabled interrupt. We then just need to check
- * whether it is in the valid range for an IRQ (30-1020 inclusive).
- */
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-
- /* bits 12-10 = src CPU, 9-0 = int # */
- ldr \irqstat, [\base, #GIC_CPU_INTACK]
-
- ldr \tmp, =1021
-
- bic \irqnr, \irqstat, #0x1c00
-
- cmp \irqnr, #29
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
-
- .endm
-
- /* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt on the
- * controller, since this requires the original irqstat value which
- * we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- cmpcs \irqnr, \irqnr
- .endm
-
- /* As above, this assumes that irqstat and base are preserved.. */
-
- .macro test_for_ltirq, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- mov \tmp, #0
- cmp \irqnr, #29
- moveq \tmp, #1
- streq \irqstat, [\base, #GIC_CPU_EOI]
- cmp \tmp, #0
- .endm
-
#else
/* legacy interrupt controller for AP16 */
.macro disable_fiq
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 05/07] ARM: Use shared GIC entry macros on UX500
2010-11-12 8:20 [PATCH 00/07] ARM: Common GIC entry macro code V3 Magnus Damm
` (3 preceding siblings ...)
2010-11-12 8:21 ` [PATCH 04/07] ARM: Use shared GIC entry macros on Tegra Magnus Damm
@ 2010-11-12 8:21 ` Magnus Damm
2010-11-12 8:22 ` [PATCH 06/07] ARM: Use shared GIC entry macros on Vexpress Magnus Damm
` (2 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Magnus Damm @ 2010-11-12 8:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
Use the GIC demux code in asm/hardware/entry-macro-gic.S
on the UX500 subarchitecture.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-ux500/include/mach/entry-macro.S | 67 ------------------------
1 file changed, 1 insertion(+), 66 deletions(-)
--- 0001/arch/arm/mach-ux500/include/mach/entry-macro.S
+++ work/arch/arm/mach-ux500/include/mach/entry-macro.S 2010-11-12 16:02:32.000000000 +0900
@@ -11,7 +11,7 @@
* warranty of any kind, whether express or implied.
*/
#include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
.macro disable_fiq
.endm
@@ -22,68 +22,3 @@
.macro arch_ret_to_user, tmp1, tmp2
.endm
-
- /*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * For now, we ignore all local interrupts so only return an
- * interrupt if it's between 30 and 1020. The test_for_ipi
- * routine below will pick up on IPIs.
- *
- * A simple read from the controller will tell us the number
- * of the highest priority enabled interrupt. We then just
- * need to check whether it is in the valid range for an
- * IRQ (30-1020 inclusive).
- */
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-
- /* bits 12-10 = src CPU, 9-0 = int # */
- ldr \irqstat, [\base, #GIC_CPU_INTACK]
-
- ldr \tmp, =1021
-
- bic \irqnr, \irqstat, #0x1c00
-
- cmp \irqnr, #29
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
-
- .endm
-
- /* We assume that irqstat (the raw value of the IRQ
- * acknowledge register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of
- * interrupt on the controller, since this requires the
- * original irqstat value which we won't easily be able
- * to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- cmpcs \irqnr, \irqnr
- .endm
-
- /* As above, this assumes that irqstat and base
- * are preserved..
- */
-
- .macro test_for_ltirq, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- mov \tmp, #0
- cmp \irqnr, #29
- moveq \tmp, #1
- streq \irqstat, [\base, #GIC_CPU_EOI]
- cmp \tmp, #0
- .endm
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 06/07] ARM: Use shared GIC entry macros on Vexpress
2010-11-12 8:20 [PATCH 00/07] ARM: Common GIC entry macro code V3 Magnus Damm
` (4 preceding siblings ...)
2010-11-12 8:21 ` [PATCH 05/07] ARM: Use shared GIC entry macros on UX500 Magnus Damm
@ 2010-11-12 8:22 ` Magnus Damm
2010-11-12 8:22 ` [PATCH 07/07] ARM: Use shared GIC entry macros on OMAP Magnus Damm
2010-11-12 16:46 ` [PATCH 00/07] ARM: Common GIC entry macro code V3 Arnd Bergmann
7 siblings, 0 replies; 12+ messages in thread
From: Magnus Damm @ 2010-11-12 8:22 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
Use the GIC demux code in asm/hardware/entry-macro-gic.S
on the Versatile Express subarchitecture.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-vexpress/include/mach/entry-macro.S | 57 ---------------------
1 file changed, 1 insertion(+), 56 deletions(-)
--- 0001/arch/arm/mach-vexpress/include/mach/entry-macro.S
+++ work/arch/arm/mach-vexpress/include/mach/entry-macro.S 2010-11-12 16:03:56.000000000 +0900
@@ -1,4 +1,4 @@
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
.macro disable_fiq
.endm
@@ -10,58 +10,3 @@
.macro arch_ret_to_user, tmp1, tmp2
.endm
-
- /*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * For now, we ignore all local interrupts so only return an interrupt if it's
- * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
- *
- * A simple read from the controller will tell us the number of the highest
- * priority enabled interrupt. We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
- ldr \tmp, =1021
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #29
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
- .endm
-
- /* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt on the
- * controller, since this requires the original irqstat value which
- * we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- cmpcs \irqnr, \irqnr
- .endm
-
- /* As above, this assumes that irqstat and base are preserved.. */
-
- .macro test_for_ltirq, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- mov \tmp, #0
- cmp \irqnr, #29
- moveq \tmp, #1
- streq \irqstat, [\base, #GIC_CPU_EOI]
- cmp \tmp, #0
- .endm
-
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 07/07] ARM: Use shared GIC entry macros on OMAP
2010-11-12 8:20 [PATCH 00/07] ARM: Common GIC entry macro code V3 Magnus Damm
` (5 preceding siblings ...)
2010-11-12 8:22 ` [PATCH 06/07] ARM: Use shared GIC entry macros on Vexpress Magnus Damm
@ 2010-11-12 8:22 ` Magnus Damm
2010-11-12 8:25 ` Shilimkar, Santosh
2010-11-12 16:46 ` [PATCH 00/07] ARM: Common GIC entry macro code V3 Arnd Bergmann
7 siblings, 1 reply; 12+ messages in thread
From: Magnus Damm @ 2010-11-12 8:22 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
Common GIC entry macro for omap
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-omap2/include/mach/entry-macro.S | 92 ++++++++----------------
1 file changed, 31 insertions(+), 61 deletions(-)
--- 0001/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ work/arch/arm/mach-omap2/include/mach/entry-macro.S 2010-11-12 16:10:51.000000000 +0900
@@ -105,6 +105,35 @@ omap_irq_base: .word 0
9999:
.endm
+#ifdef CONFIG_SMP
+ /* We assume that irqstat (the raw value of the IRQ acknowledge
+ * register) is preserved from the macro above.
+ * If there is an IPI, we immediately signal end of interrupt
+ * on the controller, since this requires the original irqstat
+ * value which we won't easily be able to recreate later.
+ */
+
+ .macro test_for_ipi, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ cmp \irqnr, #16
+ it cc
+ strcc \irqstat, [\base, #GIC_CPU_EOI]
+ it cs
+ cmpcs \irqnr, \irqnr
+ .endm
+
+ /* As above, this assumes that irqstat and base are preserved */
+
+ .macro test_for_ltirq, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ mov \tmp, #0
+ cmp \irqnr, #29
+ itt eq
+ moveq \tmp, #1
+ streq \irqstat, [\base, #GIC_CPU_EOI]
+ cmp \tmp, #0
+ .endm
+#endif /* CONFIG_SMP */
#else /* MULTI_OMAP2 */
@@ -141,74 +170,15 @@ omap_irq_base: .word 0
#ifdef CONFIG_ARCH_OMAP4
+#include <asm/hardware/entry-macro-gic.S>
.macro get_irqnr_preamble, base, tmp
ldr \base, =OMAP4_IRQ_BASE
.endm
- /*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * For now, we ignore all local interrupts so only return an
- * interrupt if it's between 30 and 1020. The test_for_ipi
- * routine below will pick up on IPIs.
- * A simple read from the controller will tell us the number
- * of the highest priority enabled interrupt.
- * We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \irqstat, [\base, #GIC_CPU_INTACK]
-
- ldr \tmp, =1021
-
- bic \irqnr, \irqstat, #0x1c00
-
- cmp \irqnr, #29
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
- .endm
#endif
-#endif /* MULTI_OMAP2 */
-
-#ifdef CONFIG_SMP
- /* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt
- * on the controller, since this requires the original irqstat
- * value which we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- it cc
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- it cs
- cmpcs \irqnr, \irqnr
- .endm
-
- /* As above, this assumes that irqstat and base are preserved */
- .macro test_for_ltirq, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- mov \tmp, #0
- cmp \irqnr, #29
- itt eq
- moveq \tmp, #1
- streq \irqstat, [\base, #GIC_CPU_EOI]
- cmp \tmp, #0
- .endm
-#endif /* CONFIG_SMP */
+#endif /* MULTI_OMAP2 */
.macro irq_prio_table
.endm
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 07/07] ARM: Use shared GIC entry macros on OMAP
2010-11-12 8:22 ` [PATCH 07/07] ARM: Use shared GIC entry macros on OMAP Magnus Damm
@ 2010-11-12 8:25 ` Shilimkar, Santosh
2010-11-12 17:45 ` Tony Lindgren
0 siblings, 1 reply; 12+ messages in thread
From: Shilimkar, Santosh @ 2010-11-12 8:25 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Magnus Damm [mailto:magnus.damm at gmail.com]
> Sent: Friday, November 12, 2010 1:52 PM
> To: linux at arm.linux.org.uk
> Cc: kgene.kim at samsung.com; kmpark at infradead.org; konkers at android.com;
> tony at atomide.com; adharmap at codeaurora.org; avorontsov at mvista.com; linux-
> kernel at vger.kernel.org; srinidhikasagar at gmail.com; dwalker at codeaurora.org;
> Shilimkar, Santosh; ccross at android.com; olof at lixom.net; Magnus Damm;
> linux-arm-kernel at lists.infradead.org
> Subject: [PATCH 07/07] ARM: Use shared GIC entry macros on OMAP
>
> From: Magnus Damm <damm@opensource.se>
>
> Common GIC entry macro for omap
>
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>
> arch/arm/mach-omap2/include/mach/entry-macro.S | 92 ++++++++-----------
> -----
> 1 file changed, 31 insertions(+), 61 deletions(-)
>
> --- 0001/arch/arm/mach-omap2/include/mach/entry-macro.S
> +++ work/arch/arm/mach-omap2/include/mach/entry-macro.S 2010-11-12
> 16:10:51.000000000 +0900
> @@ -105,6 +105,35 @@ omap_irq_base: .word 0
> 9999:
> .endm
>
> +#ifdef CONFIG_SMP
> + /* We assume that irqstat (the raw value of the IRQ
> acknowledge
> + * register) is preserved from the macro above.
> + * If there is an IPI, we immediately signal end of interrupt
> + * on the controller, since this requires the original irqstat
> + * value which we won't easily be able to recreate later.
> + */
> +
> + .macro test_for_ipi, irqnr, irqstat, base, tmp
> + bic \irqnr, \irqstat, #0x1c00
> + cmp \irqnr, #16
> + it cc
> + strcc \irqstat, [\base, #GIC_CPU_EOI]
> + it cs
> + cmpcs \irqnr, \irqnr
> + .endm
> +
> + /* As above, this assumes that irqstat and base are preserved
> */
> +
> + .macro test_for_ltirq, irqnr, irqstat, base, tmp
> + bic \irqnr, \irqstat, #0x1c00
> + mov \tmp, #0
> + cmp \irqnr, #29
> + itt eq
> + moveq \tmp, #1
> + streq \irqstat, [\base, #GIC_CPU_EOI]
> + cmp \tmp, #0
> + .endm
> +#endif /* CONFIG_SMP */
>
> #else /* MULTI_OMAP2 */
>
> @@ -141,74 +170,15 @@ omap_irq_base: .word 0
>
>
> #ifdef CONFIG_ARCH_OMAP4
> +#include <asm/hardware/entry-macro-gic.S>
>
> .macro get_irqnr_preamble, base, tmp
> ldr \base, =OMAP4_IRQ_BASE
> .endm
>
> - /*
> - * The interrupt numbering scheme is defined in the
> - * interrupt controller spec. To wit:
> - *
> - * Interrupts 0-15 are IPI
> - * 16-28 are reserved
> - * 29-31 are local. We allow 30 to be used for the watchdog.
> - * 32-1020 are global
> - * 1021-1022 are reserved
> - * 1023 is "spurious" (no interrupt)
> - *
> - * For now, we ignore all local interrupts so only return an
> - * interrupt if it's between 30 and 1020. The test_for_ipi
> - * routine below will pick up on IPIs.
> - * A simple read from the controller will tell us the number
> - * of the highest priority enabled interrupt.
> - * We then just need to check whether it is in the
> - * valid range for an IRQ (30-1020 inclusive).
> - */
> - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
> - ldr \irqstat, [\base, #GIC_CPU_INTACK]
> -
> - ldr \tmp, =1021
> -
> - bic \irqnr, \irqstat, #0x1c00
> -
> - cmp \irqnr, #29
> - cmpcc \irqnr, \irqnr
> - cmpne \irqnr, \tmp
> - cmpcs \irqnr, \irqnr
> - .endm
> #endif
> -#endif /* MULTI_OMAP2 */
> -
> -#ifdef CONFIG_SMP
> - /* We assume that irqstat (the raw value of the IRQ
> acknowledge
> - * register) is preserved from the macro above.
> - * If there is an IPI, we immediately signal end of interrupt
> - * on the controller, since this requires the original irqstat
> - * value which we won't easily be able to recreate later.
> - */
> -
> - .macro test_for_ipi, irqnr, irqstat, base, tmp
> - bic \irqnr, \irqstat, #0x1c00
> - cmp \irqnr, #16
> - it cc
> - strcc \irqstat, [\base, #GIC_CPU_EOI]
> - it cs
> - cmpcs \irqnr, \irqnr
> - .endm
> -
> - /* As above, this assumes that irqstat and base are preserved
> */
>
> - .macro test_for_ltirq, irqnr, irqstat, base, tmp
> - bic \irqnr, \irqstat, #0x1c00
> - mov \tmp, #0
> - cmp \irqnr, #29
> - itt eq
> - moveq \tmp, #1
> - streq \irqstat, [\base, #GIC_CPU_EOI]
> - cmp \tmp, #0
> - .endm
> -#endif /* CONFIG_SMP */
> +#endif /* MULTI_OMAP2 */
>
> .macro irq_prio_table
> .endm
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 07/07] ARM: Use shared GIC entry macros on OMAP
2010-11-12 8:25 ` Shilimkar, Santosh
@ 2010-11-12 17:45 ` Tony Lindgren
0 siblings, 0 replies; 12+ messages in thread
From: Tony Lindgren @ 2010-11-12 17:45 UTC (permalink / raw)
To: linux-arm-kernel
* Shilimkar, Santosh <santosh.shilimkar@ti.com> [101112 00:16]:
> > -----Original Message-----
> > From: Magnus Damm [mailto:magnus.damm at gmail.com]
> > Sent: Friday, November 12, 2010 1:52 PM
> > To: linux at arm.linux.org.uk
> > Cc: kgene.kim at samsung.com; kmpark at infradead.org; konkers at android.com;
> > tony at atomide.com; adharmap at codeaurora.org; avorontsov at mvista.com; linux-
> > kernel at vger.kernel.org; srinidhikasagar at gmail.com; dwalker at codeaurora.org;
> > Shilimkar, Santosh; ccross at android.com; olof at lixom.net; Magnus Damm;
> > linux-arm-kernel at lists.infradead.org
> > Subject: [PATCH 07/07] ARM: Use shared GIC entry macros on OMAP
> >
> > From: Magnus Damm <damm@opensource.se>
> >
> > Common GIC entry macro for omap
> >
> > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > Signed-off-by: Magnus Damm <damm@opensource.se>
> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Looks like the From: field got trashed on this one assuming you're
using the patch I posted earlier :)
Tony
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 00/07] ARM: Common GIC entry macro code V3
2010-11-12 8:20 [PATCH 00/07] ARM: Common GIC entry macro code V3 Magnus Damm
` (6 preceding siblings ...)
2010-11-12 8:22 ` [PATCH 07/07] ARM: Use shared GIC entry macros on OMAP Magnus Damm
@ 2010-11-12 16:46 ` Arnd Bergmann
7 siblings, 0 replies; 12+ messages in thread
From: Arnd Bergmann @ 2010-11-12 16:46 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 12 November 2010, Magnus Damm wrote:
> ARM: Common GIC entry macro code V3
>
> [PATCH 01/07] ARM: Introduce asm/hardware/entry-macro-gic.S
> [PATCH 02/07] ARM: Use shared GIC entry macros on CNS3XXX
> [PATCH 03/07] ARM: Use shared GIC entry macros on Realview
> [PATCH 04/07] ARM: Use shared GIC entry macros on Tegra
> [PATCH 05/07] ARM: Use shared GIC entry macros on UX500
> [PATCH 06/07] ARM: Use shared GIC entry macros on Vexpress
> [PATCH 07/07] ARM: Use shared GIC entry macros on OMAP
>
> Put GIC demux code in a common place to avoid duplicated code.
>
Looks like a very nice cleanup!
Arnd
^ permalink raw reply [flat|nested] 12+ messages in thread