* [PATCH] ARM: Fix SMP_ON_UP for non ARM ltd. implementations @ 2011-01-26 23:04 Stephen Boyd 2011-01-30 12:20 ` Russell King - ARM Linux 0 siblings, 1 reply; 6+ messages in thread From: Stephen Boyd @ 2011-01-26 23:04 UTC (permalink / raw) To: linux-arm-kernel The SMP_ON_UP checks restrict the feature to ARM limited designs, when other implementers support SMP designs. Instead of checking for an ARM CPU and ARMv6/v7 just check for a v6 or v7 and then rely on the MPIDR for non ARM 11MPCore designs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> --- arch/arm/kernel/head.S | 13 +++++++++---- 1 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index f17d9a0..ede5b70 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -393,20 +393,25 @@ ENDPROC(__turn_mmu_on) #ifdef CONFIG_SMP_ON_UP __fixup_smp: mov r4, #0x00070000 - orr r3, r4, #0xff000000 @ mask 0xff070000 - orr r4, r4, #0x41000000 @ val 0x41070000 - and r0, r9, r3 - teq r0, r4 @ ARM CPU and ARMv6/v7? + and r0, r9, r4 + teq r0, r4 @ ARMv6/v7? bne __fixup_smp_on_up @ no, assume UP + orr r3, r4, #0xff000000 @ mask 0xff070000 orr r3, r3, #0x0000ff00 orr r3, r3, #0x000000f0 @ mask 0xff07fff0 + orr r4, r4, #0x41000000 @ val 0x41070000 orr r4, r4, #0x0000b000 orr r4, r4, #0x00000020 @ val 0x4107b020 and r0, r9, r3 teq r0, r4 @ ARM 11MPCore? moveq pc, lr @ yes, assume SMP + mov r4, #0x00070000 + and r0, r9, #0x000f0000 + teq r0, r4 @ ARMv6? + beq __fixup_smp_on_up @ yes, assume UP + mrc p15, 0, r0, c0, c0, 5 @ read MPIDR tst r0, #1 << 31 movne pc, lr @ bit 31 => SMP -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] ARM: Fix SMP_ON_UP for non ARM ltd. implementations 2011-01-26 23:04 [PATCH] ARM: Fix SMP_ON_UP for non ARM ltd. implementations Stephen Boyd @ 2011-01-30 12:20 ` Russell King - ARM Linux 2011-01-30 16:27 ` Will Deacon 0 siblings, 1 reply; 6+ messages in thread From: Russell King - ARM Linux @ 2011-01-30 12:20 UTC (permalink / raw) To: linux-arm-kernel On Wed, Jan 26, 2011 at 03:04:12PM -0800, Stephen Boyd wrote: > @@ -393,20 +393,25 @@ ENDPROC(__turn_mmu_on) > #ifdef CONFIG_SMP_ON_UP > __fixup_smp: > mov r4, #0x00070000 > - orr r3, r4, #0xff000000 @ mask 0xff070000 > - orr r4, r4, #0x41000000 @ val 0x41070000 > - and r0, r9, r3 > - teq r0, r4 @ ARM CPU and ARMv6/v7? > + and r0, r9, r4 > + teq r0, r4 @ ARMv6/v7? > bne __fixup_smp_on_up @ no, assume UP > > + orr r3, r4, #0xff000000 @ mask 0xff070000 > orr r3, r3, #0x0000ff00 > orr r3, r3, #0x000000f0 @ mask 0xff07fff0 > + orr r4, r4, #0x41000000 @ val 0x41070000 > orr r4, r4, #0x0000b000 > orr r4, r4, #0x00000020 @ val 0x4107b020 > and r0, r9, r3 > teq r0, r4 @ ARM 11MPCore? > moveq pc, lr @ yes, assume SMP > > + mov r4, #0x00070000 > + and r0, r9, #0x000f0000 > + teq r0, r4 @ ARMv6? > + beq __fixup_smp_on_up @ yes, assume UP > + Wouldn't it be better to check for CPUID presence first, then ARM11MPcore, and lastly preserve of MPIDR-flagged extensions? Will - can you check whether the below is correct? arch/arm/kernel/head.S | 17 +++++++---------- 1 files changed, 7 insertions(+), 10 deletions(-) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 17a97b5..f6b31c4 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -390,19 +390,16 @@ ENDPROC(__turn_mmu_on) #ifdef CONFIG_SMP_ON_UP __fixup_smp: - mov r4, #0x00070000 - orr r3, r4, #0xff000000 @ mask 0xff070000 - orr r4, r4, #0x41000000 @ val 0x41070000 - and r0, r9, r3 - teq r0, r4 @ ARM CPU and ARMv6/v7? + and r3, r9, #0x000f0000 @ architecture version + teq r3, #0x000f00000 @ CPU ID supported? bne __fixup_smp_on_up @ no, assume UP - orr r3, r3, #0x0000ff00 - orr r3, r3, #0x000000f0 @ mask 0xff07fff0 + bic r3, r9, #0x00ff0000 + bic r3, r3, #0x0000000f @ mask 0xff00fff0 + mov r4, #0x41000000 orr r4, r4, #0x0000b000 - orr r4, r4, #0x00000020 @ val 0x4107b020 - and r0, r9, r3 - teq r0, r4 @ ARM 11MPCore? + orr r4, r4, #0x00000020 @ val 0x4100b020 + teq r3, r4 @ ARM 11MPCore? moveq pc, lr @ yes, assume SMP mrc p15, 0, r0, c0, c0, 5 @ read MPIDR ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] ARM: Fix SMP_ON_UP for non ARM ltd. implementations 2011-01-30 12:20 ` Russell King - ARM Linux @ 2011-01-30 16:27 ` Will Deacon 2011-01-30 16:40 ` Russell King - ARM Linux 0 siblings, 1 reply; 6+ messages in thread From: Will Deacon @ 2011-01-30 16:27 UTC (permalink / raw) To: linux-arm-kernel Hi Russell, On Sun, 2011-01-30 at 12:20 +0000, Russell King - ARM Linux wrote: > On Wed, Jan 26, 2011 at 03:04:12PM -0800, Stephen Boyd wrote: > > @@ -393,20 +393,25 @@ ENDPROC(__turn_mmu_on) > > #ifdef CONFIG_SMP_ON_UP > > __fixup_smp: > > mov r4, #0x00070000 > > - orr r3, r4, #0xff000000 @ mask 0xff070000 > > - orr r4, r4, #0x41000000 @ val 0x41070000 > > - and r0, r9, r3 > > - teq r0, r4 @ ARM CPU and ARMv6/v7? > > + and r0, r9, r4 > > + teq r0, r4 @ ARMv6/v7? > > bne __fixup_smp_on_up @ no, assume UP > > > > + orr r3, r4, #0xff000000 @ mask 0xff070000 > > orr r3, r3, #0x0000ff00 > > orr r3, r3, #0x000000f0 @ mask 0xff07fff0 > > + orr r4, r4, #0x41000000 @ val 0x41070000 > > orr r4, r4, #0x0000b000 > > orr r4, r4, #0x00000020 @ val 0x4107b020 > > and r0, r9, r3 > > teq r0, r4 @ ARM 11MPCore? > > moveq pc, lr @ yes, assume SMP > > > > + mov r4, #0x00070000 > > + and r0, r9, #0x000f0000 > > + teq r0, r4 @ ARMv6? > > + beq __fixup_smp_on_up @ yes, assume UP > > + > > Wouldn't it be better to check for CPUID presence first, then ARM11MPcore, > and lastly preserve of MPIDR-flagged extensions? > Yes, the v6 catch-all at the end is pretty horrible. > Will - can you check whether the below is correct? > > arch/arm/kernel/head.S | 17 +++++++---------- > 1 files changed, 7 insertions(+), 10 deletions(-) > > diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S > index 17a97b5..f6b31c4 100644 > --- a/arch/arm/kernel/head.S > +++ b/arch/arm/kernel/head.S > @@ -390,19 +390,16 @@ ENDPROC(__turn_mmu_on) > > #ifdef CONFIG_SMP_ON_UP > __fixup_smp: > - mov r4, #0x00070000 > - orr r3, r4, #0xff000000 @ mask 0xff070000 > - orr r4, r4, #0x41000000 @ val 0x41070000 > - and r0, r9, r3 > - teq r0, r4 @ ARM CPU and ARMv6/v7? > + and r3, r9, #0x000f0000 @ architecture version > + teq r3, #0x000f00000 @ CPU ID supported? You've got an extra 0x0 on the end of that constant. > bne __fixup_smp_on_up @ no, assume UP > > - orr r3, r3, #0x0000ff00 > - orr r3, r3, #0x000000f0 @ mask 0xff07fff0 > + bic r3, r9, #0x00ff0000 > + bic r3, r3, #0x0000000f @ mask 0xff00fff0 > + mov r4, #0x41000000 > orr r4, r4, #0x0000b000 > - orr r4, r4, #0x00000020 @ val 0x4107b020 > - and r0, r9, r3 > - teq r0, r4 @ ARM 11MPCore? > + orr r4, r4, #0x00000020 @ val 0x4100b020 > + teq r3, r4 @ ARM 11MPCore? > moveq pc, lr @ yes, assume SMP > Yup, that looks correct to me. 11MPCore has 0xf for the architecture field so we'll end up identifying it correctly here. > mrc p15, 0, r0, c0, c0, 5 @ read MPIDR The code following this does: tst r0, #1 << 31 movne pc, lr @ bit 31 => SMP As an optimisation, we could also check that bit 30 is zero so that we patch out the SMP stuff for single-core A5/A9/A15. Up to you. With the typo fixed: Acked-by: Will Deacon <will.deacon@arm.com> Will ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] ARM: Fix SMP_ON_UP for non ARM ltd. implementations 2011-01-30 16:27 ` Will Deacon @ 2011-01-30 16:40 ` Russell King - ARM Linux 2011-01-31 10:32 ` Will Deacon 2011-01-31 21:33 ` Stephen Boyd 0 siblings, 2 replies; 6+ messages in thread From: Russell King - ARM Linux @ 2011-01-30 16:40 UTC (permalink / raw) To: linux-arm-kernel On Sun, Jan 30, 2011 at 04:27:55PM +0000, Will Deacon wrote: > > mrc p15, 0, r0, c0, c0, 5 @ read MPIDR > > > The code following this does: > > tst r0, #1 << 31 > movne pc, lr @ bit 31 => SMP > > As an optimisation, we could also check that bit 30 is zero so that > we patch out the SMP stuff for single-core A5/A9/A15. Up to you. Ok, so with that added, it becomes: arch/arm/kernel/head.S | 22 ++++++++++------------ 1 files changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index f17d9a0..c0225da 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -392,24 +392,22 @@ ENDPROC(__turn_mmu_on) #ifdef CONFIG_SMP_ON_UP __fixup_smp: - mov r4, #0x00070000 - orr r3, r4, #0xff000000 @ mask 0xff070000 - orr r4, r4, #0x41000000 @ val 0x41070000 - and r0, r9, r3 - teq r0, r4 @ ARM CPU and ARMv6/v7? + and r3, r9, #0x000f0000 @ architecture version + teq r3, #0x000f0000 @ CPU ID supported? bne __fixup_smp_on_up @ no, assume UP - orr r3, r3, #0x0000ff00 - orr r3, r3, #0x000000f0 @ mask 0xff07fff0 + bic r3, r9, #0x00ff0000 + bic r3, r3, #0x0000000f @ mask 0xff00fff0 + mov r4, #0x41000000 orr r4, r4, #0x0000b000 - orr r4, r4, #0x00000020 @ val 0x4107b020 - and r0, r9, r3 - teq r0, r4 @ ARM 11MPCore? + orr r4, r4, #0x00000020 @ val 0x4100b020 + teq r3, r4 @ ARM 11MPCore? moveq pc, lr @ yes, assume SMP mrc p15, 0, r0, c0, c0, 5 @ read MPIDR - tst r0, #1 << 31 - movne pc, lr @ bit 31 => SMP + and r0, r0, #0xc0000000 @ multiprocessing extensions and + teq r0, #0x80000000 @ not part of a uniprocessor system? + moveq pc, lr @ yes, assume SMP __fixup_smp_on_up: adr r0, 1f ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] ARM: Fix SMP_ON_UP for non ARM ltd. implementations 2011-01-30 16:40 ` Russell King - ARM Linux @ 2011-01-31 10:32 ` Will Deacon 2011-01-31 21:33 ` Stephen Boyd 1 sibling, 0 replies; 6+ messages in thread From: Will Deacon @ 2011-01-31 10:32 UTC (permalink / raw) To: linux-arm-kernel > > As an optimisation, we could also check that bit 30 is zero so that > > we patch out the SMP stuff for single-core A5/A9/A15. Up to you. > > Ok, so with that added, it becomes: > > arch/arm/kernel/head.S | 22 ++++++++++------------ > 1 files changed, 10 insertions(+), 12 deletions(-) > > diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S > index f17d9a0..c0225da 100644 > --- a/arch/arm/kernel/head.S > +++ b/arch/arm/kernel/head.S > @@ -392,24 +392,22 @@ ENDPROC(__turn_mmu_on) > > #ifdef CONFIG_SMP_ON_UP > __fixup_smp: > - mov r4, #0x00070000 > - orr r3, r4, #0xff000000 @ mask 0xff070000 > - orr r4, r4, #0x41000000 @ val 0x41070000 > - and r0, r9, r3 > - teq r0, r4 @ ARM CPU and ARMv6/v7? > + and r3, r9, #0x000f0000 @ architecture version > + teq r3, #0x000f0000 @ CPU ID supported? > bne __fixup_smp_on_up @ no, assume UP > > - orr r3, r3, #0x0000ff00 > - orr r3, r3, #0x000000f0 @ mask 0xff07fff0 > + bic r3, r9, #0x00ff0000 > + bic r3, r3, #0x0000000f @ mask 0xff00fff0 > + mov r4, #0x41000000 > orr r4, r4, #0x0000b000 > - orr r4, r4, #0x00000020 @ val 0x4107b020 > - and r0, r9, r3 > - teq r0, r4 @ ARM 11MPCore? > + orr r4, r4, #0x00000020 @ val 0x4100b020 > + teq r3, r4 @ ARM 11MPCore? > moveq pc, lr @ yes, assume SMP > > mrc p15, 0, r0, c0, c0, 5 @ read MPIDR > - tst r0, #1 << 31 > - movne pc, lr @ bit 31 => SMP > + and r0, r0, #0xc0000000 @ multiprocessing extensions and > + teq r0, #0x80000000 @ not part of a uniprocessor system? > + moveq pc, lr @ yes, assume SMP > > __fixup_smp_on_up: > adr r0, 1f That should do the trick. Acked-by: Will Deacon <will.deacon@arm.com> Thanks, Will ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] ARM: Fix SMP_ON_UP for non ARM ltd. implementations 2011-01-30 16:40 ` Russell King - ARM Linux 2011-01-31 10:32 ` Will Deacon @ 2011-01-31 21:33 ` Stephen Boyd 1 sibling, 0 replies; 6+ messages in thread From: Stephen Boyd @ 2011-01-31 21:33 UTC (permalink / raw) To: linux-arm-kernel On 01/30/2011 08:40 AM, Russell King - ARM Linux wrote: > Ok, so with that added, it becomes: > > arch/arm/kernel/head.S | 22 ++++++++++------------ > 1 files changed, 10 insertions(+), 12 deletions(-) > > diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S > index f17d9a0..c0225da 100644 > --- a/arch/arm/kernel/head.S > +++ b/arch/arm/kernel/head.S > @@ -392,24 +392,22 @@ ENDPROC(__turn_mmu_on) > > #ifdef CONFIG_SMP_ON_UP > __fixup_smp: > - mov r4, #0x00070000 > - orr r3, r4, #0xff000000 @ mask 0xff070000 > - orr r4, r4, #0x41000000 @ val 0x41070000 > - and r0, r9, r3 > - teq r0, r4 @ ARM CPU and ARMv6/v7? > + and r3, r9, #0x000f0000 @ architecture version > + teq r3, #0x000f0000 @ CPU ID supported? > bne __fixup_smp_on_up @ no, assume UP > > - orr r3, r3, #0x0000ff00 > - orr r3, r3, #0x000000f0 @ mask 0xff07fff0 > + bic r3, r9, #0x00ff0000 > + bic r3, r3, #0x0000000f @ mask 0xff00fff0 > + mov r4, #0x41000000 > orr r4, r4, #0x0000b000 > - orr r4, r4, #0x00000020 @ val 0x4107b020 > - and r0, r9, r3 > - teq r0, r4 @ ARM 11MPCore? > + orr r4, r4, #0x00000020 @ val 0x4100b020 > + teq r3, r4 @ ARM 11MPCore? > moveq pc, lr @ yes, assume SMP > > mrc p15, 0, r0, c0, c0, 5 @ read MPIDR > - tst r0, #1 << 31 > - movne pc, lr @ bit 31 => SMP > + and r0, r0, #0xc0000000 @ multiprocessing extensions and > + teq r0, #0x80000000 @ not part of a uniprocessor system? > + moveq pc, lr @ yes, assume SMP > > __fixup_smp_on_up: > adr r0, 1f Great. Looks good to me too. If I had know that ARM 11MPCore had an 0xf in the architecture bits I would have suggested this fix instead. Also, I wasn't sure if we should send fixes for EXPERIMENTAL features to the stable tree. If its appropriate, please Cc stable when the patch goes in. Reported-and-Tested-by: Stephen Boyd <sboyd@codeaurora.org> -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2011-01-31 21:33 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2011-01-26 23:04 [PATCH] ARM: Fix SMP_ON_UP for non ARM ltd. implementations Stephen Boyd 2011-01-30 12:20 ` Russell King - ARM Linux 2011-01-30 16:27 ` Will Deacon 2011-01-30 16:40 ` Russell King - ARM Linux 2011-01-31 10:32 ` Will Deacon 2011-01-31 21:33 ` Stephen Boyd
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