[PATCH RFC] ARM: MPCore v6_early_abort enhancement

[PATCH RFC] ARM: MPCore v6_early_abort enhancement

[Valentine Barshak]

SWP instruction sets bit 11 in DFSR, in case of data fault on SMP MPCore.
So v6_early_abort doesn't need erratum 326103 workaround for MPCore.
    
Signed-off-by: Valentine Barshak <vbarshak@mvista.com>

diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index f332df7..590d061 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -30,8 +30,10 @@ ENTRY(v6_early_abort)
 	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
 /*
  * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
- * The test below covers all the write situations, including Java bytecodes
+ * The test below covers all the write situations, including Java bytecodes.
+ * However SMP MPCore doesn't have this erratum.
  */
+#ifndef CONFIG_SMP
 	bic	r1, r1, #1 << 11		@ clear bit 11 of FSR
 	tst	r3, #PSR_J_BIT			@ Java?
 	movne	pc, lr
@@ -43,6 +45,7 @@ ENTRY(v6_early_abort)
 	do_ldrd_abort
 	tst	r3, #1 << 20			@ L = 0 -> write
 	orreq	r1, r1, #1 << 11		@ yes.
+#endif	/* !CONFIG_SMP */
 	mov	pc, lr
 
 

[PATCH RFC] ARM: MPCore v6_early_abort enhancement

[Russell King - ARM Linux]

On Sat, Feb 12, 2011 at 12:54:21AM +0300, Valentine Barshak wrote:
> SWP instruction sets bit 11 in DFSR, in case of data fault on SMP MPCore.
> So v6_early_abort doesn't need erratum 326103 workaround for MPCore.

NAK.  When building a SMP kernel which also supports v6 CPUs, this will
cause v6 CPUs to break.

[PATCH RFC] ARM: MPCore v6_early_abort enhancement

[George G. Davis]

Hi,

On Fri, Feb 11, 2011 at 10:38:44PM +0000, Russell King - ARM Linux wrote:
> On Sat, Feb 12, 2011 at 12:54:21AM +0300, Valentine Barshak wrote:
> > SWP instruction sets bit 11 in DFSR, in case of data fault on SMP MPCore.
> > So v6_early_abort doesn't need erratum 326103 workaround for MPCore.
> 
> NAK.  When building a SMP kernel which also supports v6 CPUs, this will
> cause v6 CPUs to break.

Since the SWP erratum only affects ARM1136 (UP) processors, how will this
break ARM11 MPCore (v6) processors?  Are you referring to unified kernels
which support both UP and SMP machines?  I reckon that's a recent feature
to be able to boot SMP kernels on UP machines.  Perhaps if that's
why you're against this, then we need to have a separate config
option to specifically enable this ARM1136 erratum workaround?  Or
at least only perform the workaround for certain processor IDs?

Thanks!

--
Regards,
George

[PATCH RFC] ARM: MPCore v6_early_abort enhancement

[Russell King - ARM Linux]

On Fri, Feb 11, 2011 at 05:53:42PM -0500, George G. Davis wrote:
> Hi,
> 
> On Fri, Feb 11, 2011 at 10:38:44PM +0000, Russell King - ARM Linux wrote:
> > On Sat, Feb 12, 2011 at 12:54:21AM +0300, Valentine Barshak wrote:
> > > SWP instruction sets bit 11 in DFSR, in case of data fault on SMP MPCore.
> > > So v6_early_abort doesn't need erratum 326103 workaround for MPCore.
> > 
> > NAK.  When building a SMP kernel which also supports v6 CPUs, this will
> > cause v6 CPUs to break.
> 
> Since the SWP erratum only affects ARM1136 (UP) processors, how will this
> break ARM11 MPCore (v6) processors?

Omitting the code will break MPcore processors.

> Are you referring to unified kernels which support both UP and SMP machines?

Of course.

> I reckon that's a recent feature to be able to boot SMP kernels on UP
> machines.

Makes no difference if it's a recent feature or not.  We're not adding
new obstacles to this when we're getting rid of them.  It's counter
productive.

> Perhaps if that's why you're against this, then we need to have a
> separate config option to specifically enable this ARM1136 erratum
> workaround?

No we don't.  Omitting the code is an optimization to what is already a
slow path which results in breakage for people.  That's why I nak'd it.