From: srinidhi.kasagar@stericsson.com (Srinidhi KASAGAR)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: errata: pl310 cache sync operation may be faulty
Date: Wed, 16 Feb 2011 11:06:58 +0530 [thread overview]
Message-ID: <20110216053657.GA17002@bnru02> (raw)
In-Reply-To: <20110215113422.GE4152@n2100.arm.linux.org.uk>
On Tue, Feb 15, 2011 at 12:34:22 +0100, Russell King - ARM Linux wrote:
> On Tue, Feb 15, 2011 at 04:48:03PM +0530, srinidhi kasagar wrote:
> > +#ifdef ARM_ERRATA_753970
> > +#define L2X0_DUMMY_REG 0x740
> > + /* write to an unmmapped register */
> > + writel_relaxed(0, base + L2X0_DUMMY_REG);
> > + cache_wait(base + L2X0_CACHE_SYNC, 1);
> > +#else
> > writel_relaxed(0, base + L2X0_CACHE_SYNC);
> > cache_wait(base + L2X0_CACHE_SYNC, 1);
> > +#endif
>
> So why wrap cache_wait() up in that horrible ifdef as well - and why not
> put the dummy register definition along side the other register definitions?
OK. In fact cache_wait need not have to be under ifdef
as this bug found only on PL310 where the sync operations
are atomic. I will send out a new patch.
srinidhi
next prev parent reply other threads:[~2011-02-16 5:36 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-02-15 11:18 [PATCH] ARM: errata: pl310 cache sync operation may be faulty srinidhi kasagar
2011-02-15 11:34 ` Russell King - ARM Linux
2011-02-16 5:36 ` Srinidhi KASAGAR [this message]
2011-02-16 6:03 ` Srinidhi KASAGAR
2011-02-16 10:32 ` Catalin Marinas
2011-02-16 12:34 ` Srinidhi KASAGAR
2011-02-16 12:36 ` Catalin Marinas
2011-02-15 16:38 ` Catalin Marinas
2011-02-16 5:08 ` Srinidhi KASAGAR
2011-02-16 10:11 ` Catalin Marinas
-- strict thread matches above, loose matches on Subject: below --
2011-02-14 11:37 srinidhi kasagar
2011-02-14 11:37 srinidhi kasagar
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