[PATCH V3 1/4] ARM: Xilinx: Adding Xilinx board support

[PATCH V3 1/4] ARM: Xilinx: Adding Xilinx board support

[John Linn]

The 1st board support is minimal to get a system up and running
on the Xilinx platform.

Signed-off-by: John Linn <john.linn@xilinx.com>
---

V3 Changes

Updates based on Russell Kings' comments
	Changed headers to update the license info and remove
	the address

	Changed the name of functions to include "xilinx" in 
	common.c and common.h

Changed the Kconfig and Makefile to use MACH_XILINX which
matches the machine registered.

V2 Changes

Updates based on Russell King's comments	
	minor cleanups
	cleaned up physical/virtual addresses in early i/o table		

Updated based on Jamie Iles's comment
	added clk_get_rate() function
	now using platform_add_devices() from platform code

 arch/arm/mach-xilinx/Kconfig       |   14 +++++
 arch/arm/mach-xilinx/Makefile      |    7 ++
 arch/arm/mach-xilinx/Makefile.boot |    3 +
 arch/arm/mach-xilinx/board_ep107.c |   82 ++++++++++++++++++++++++++
 arch/arm/mach-xilinx/common.c      |  113 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-xilinx/common.h      |   30 ++++++++++
 6 files changed, 249 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-xilinx/Kconfig
 create mode 100644 arch/arm/mach-xilinx/Makefile
 create mode 100644 arch/arm/mach-xilinx/Makefile.boot
 create mode 100644 arch/arm/mach-xilinx/board_ep107.c
 create mode 100644 arch/arm/mach-xilinx/common.c
 create mode 100644 arch/arm/mach-xilinx/common.h

diff --git a/arch/arm/mach-xilinx/Kconfig b/arch/arm/mach-xilinx/Kconfig
new file mode 100644
index 0000000..61532af
--- /dev/null
+++ b/arch/arm/mach-xilinx/Kconfig
@@ -0,0 +1,14 @@
+if ARCH_XILINX
+
+choice
+        prompt "Board Selection"
+	default MACH_XILINX
+
+config MACH_XILINX
+	bool "Xilinx EP107 Board"
+	help
+	  Select if you are using a Xilinx EP107 board.
+
+endchoice
+
+endif
diff --git a/arch/arm/mach-xilinx/Makefile b/arch/arm/mach-xilinx/Makefile
new file mode 100644
index 0000000..76e9e55
--- /dev/null
+++ b/arch/arm/mach-xilinx/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Common support
+obj-y 				:= common.o
+obj-$(CONFIG_MACH_XILINX)	+= board_ep107.o
diff --git a/arch/arm/mach-xilinx/Makefile.boot b/arch/arm/mach-xilinx/Makefile.boot
new file mode 100644
index 0000000..67039c3
--- /dev/null
+++ b/arch/arm/mach-xilinx/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y	:= 0x00008000
+params_phys-y	:= 0x00000100
+initrd_phys-y	:= 0x00800000
diff --git a/arch/arm/mach-xilinx/board_ep107.c b/arch/arm/mach-xilinx/board_ep107.c
new file mode 100644
index 0000000..a1635b5
--- /dev/null
+++ b/arch/arm/mach-xilinx/board_ep107.c
@@ -0,0 +1,82 @@
+/* arch/arm/mach-xilinx/board_ep107.c
+ *
+ * This file contains code specific to the Xilinx EP107 board.
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * based on /arch/arm/mach-realview/core.c
+ *
+ *  Copyright (C) 1999 - 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/xilinx_soc.h>
+#include <mach/irqs.h>
+#include <linux/clkdev.h>
+#include "common.h"
+
+/*
+ * Fixed clocks for now
+ */
+
+static struct clk ref50_clk = {
+	.rate	= 50000000,
+};
+
+/* Create all the platform devices for the board */
+
+static struct resource uart0[] = {
+	{
+		.start = UART0_PHYS,
+		.end = UART0_PHYS + 0xFFF,
+		.flags = IORESOURCE_MEM,
+	}, {
+		.start = IRQ_UART0,
+		.end = IRQ_UART0,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device uart_device0 = {
+	.name = "xuartpss",
+	.id = 0,
+	.dev = {
+		.platform_data = &ref50_clk.rate,
+	},
+	.resource = uart0,
+	.num_resources = ARRAY_SIZE(uart0),
+};
+
+static struct platform_device *xilinx_pdevices[] __initdata = {
+	&uart_device0,
+};
+
+/**
+ * board_ep107_init - Board specific initialization for the Xilinx EP107 board.
+ *
+ **/
+static void __init board_ep107_init(void)
+{
+	xilinx_system_init();
+	platform_add_devices(&xilinx_pdevices[0], ARRAY_SIZE(xilinx_pdevices));
+}
+
+MACHINE_START(XILINX_EP107, "Xilinx EP107")
+	.boot_params    = PHYS_OFFSET + 0x00000100,
+	.map_io         = xilinx_map_io,
+	.init_irq       = xilinx_irq_init,
+	.init_machine   = board_ep107_init,
+	.timer          = &xttcpss_sys_timer,
+MACHINE_END
diff --git a/arch/arm/mach-xilinx/common.c b/arch/arm/mach-xilinx/common.c
new file mode 100644
index 0000000..564b707
--- /dev/null
+++ b/arch/arm/mach-xilinx/common.c
@@ -0,0 +1,113 @@
+/* arch/arm/mach-xilinx/common.c
+ *
+ * This file contains common code that is intended to be used across
+ * boards so that it's not replicated.
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/cpumask.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+
+#include <asm/mach/map.h>
+#include <asm/page.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/xilinx_soc.h>
+#include <mach/clkdev.h>
+
+/*
+ * Clock function infrastructure.
+ */
+int clk_enable(struct clk *clk)
+{
+	return 0;
+}
+
+void clk_disable(struct clk *clk)
+{
+}
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+/**
+ * system_init - System specific initialization, intended to be called from
+ *			board specific initialization.
+ *
+ **/
+void __init xilinx_system_init(void)
+{
+#ifdef CONFIG_CACHE_L2X0
+	/*
+	 * 64KB way size, 8-way associativity, parity disabled
+	 */
+	l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF);
+#endif
+}
+
+/**
+ * irq_init - Interrupt controller initialization for the GIC.
+ *
+ **/
+void __init xilinx_irq_init(void)
+{
+	gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE);
+}
+
+/* The minimum devices needed to be mapped before the VM system is up and
+ * running include the GIC, UART and Timer Counter.
+ */
+
+static struct map_desc io_desc[] __initdata = {
+	{
+		.virtual	= TTC0_VIRT,
+		.pfn		= __phys_to_pfn(TTC0_PHYS),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= SCU_PERIPH_VIRT,
+		.pfn		= __phys_to_pfn(SCU_PERIPH_PHYS),
+		.length		= SZ_8K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= PL310_L2CC_VIRT,
+		.pfn		= __phys_to_pfn(PL310_L2CC_PHYS),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+
+#ifdef CONFIG_DEBUG_LL
+	{
+		.virtual	= UART0_VIRT,
+		.pfn		= __phys_to_pfn(UART0_PHYS),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+#endif
+
+};
+
+/**
+ * map_io - Create memory mappings needed for early I/O.
+ *
+ **/
+void __init xilinx_map_io(void)
+{
+	iotable_init(io_desc, ARRAY_SIZE(io_desc));
+}
diff --git a/arch/arm/mach-xilinx/common.h b/arch/arm/mach-xilinx/common.h
new file mode 100644
index 0000000..9a7cf65
--- /dev/null
+++ b/arch/arm/mach-xilinx/common.h
@@ -0,0 +1,30 @@
+/* arch/arm/mach-xilinx/common.h
+ *
+ * This file contains common function prototypes to avoid externs
+ * in the c files.
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_XILINX_COMMON_H__
+#define __MACH_XILINX_COMMON_H__
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+void __init xilinx_system_init(void);
+void __init xilinx_irq_init(void);
+void __init xilinx_map_io(void);
+
+extern struct sys_timer xttcpss_sys_timer;
+
+#endif
-- 
1.6.2.1



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[PATCH V3 1/4] ARM: Xilinx: Adding Xilinx board support

[Jamie Iles]

Hi John,

One nitpick, otherwise looks nice.

Jamie

On Wed, Feb 16, 2011 at 09:11:53AM -0700, John Linn wrote:
> diff --git a/arch/arm/mach-xilinx/common.h b/arch/arm/mach-xilinx/common.h
> new file mode 100644
> index 0000000..9a7cf65
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/common.h
> @@ -0,0 +1,30 @@
> +/* arch/arm/mach-xilinx/common.h
> + *
> + * This file contains common function prototypes to avoid externs
> + * in the c files.
> + *
> + *  Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_XILINX_COMMON_H__
> +#define __MACH_XILINX_COMMON_H__
> +
> +#include <linux/init.h>
> +#include <linux/platform_device.h>

You don't appear to use the contents of platform_device.h in here so you 
could probably drop this include.

[PATCH V3 1/4] ARM: Xilinx: Adding Xilinx board support

[John Linn]

> -----Original Message-----
> From: Jamie Iles [mailto:jamie at jamieiles.com]
> Sent: Thursday, February 17, 2011 2:35 AM
> To: John Linn
> Cc: linux-arm-kernel at lists.infradead.org;
linux-kernel at vger.kernel.org; linux at arm.linux.org.uk;
> catalin.marinas at arm.com; glikely at secretlab.ca; arnd at arndb.de
> Subject: Re: [PATCH V3 1/4] ARM: Xilinx: Adding Xilinx board support
> 
> Hi John,
> 
> One nitpick, otherwise looks nice.
> 
> Jamie
> 
> On Wed, Feb 16, 2011 at 09:11:53AM -0700, John Linn wrote:
> > diff --git a/arch/arm/mach-xilinx/common.h
b/arch/arm/mach-xilinx/common.h
> > new file mode 100644
> > index 0000000..9a7cf65
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/common.h
> > @@ -0,0 +1,30 @@
> > +/* arch/arm/mach-xilinx/common.h
> > + *
> > + * This file contains common function prototypes to avoid externs
> > + * in the c files.
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_XILINX_COMMON_H__
> > +#define __MACH_XILINX_COMMON_H__
> > +
> > +#include <linux/init.h>
> > +#include <linux/platform_device.h>
> 
> You don't appear to use the contents of platform_device.h in here so
you
> could probably drop this include.

Good point.  Easy enough.

Thanks,
John

This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

[PATCH V3 2/4] ARM: Xilinx: Adding timer support to the platform

[John Linn]

The timer driver supports the Xilinx PS Timer Counter IP.

Signed-off-by: Kiran Sutariya <kiran.sutariya@einfochips.com>
Signed-off-by: John Linn <john.linn@xilinx.com>
---

V3 Changes

Updates based on Russell Kings' comments
	Changed headers to update the license info and remove
	the address

V2 Changes

The timer code was changed quite a bit based on review inputs. It
got much smaller and cleaner I think.

Updates based on Russell King's comments	
	minor cleanups for documentation comments
	removed the name from the timer structure
	removed interrupt for clock source 
	moved to using clock functions provided in the kernel
		for calculating shift/mult values
	removed PM code as generic handles it

Updated based on Jamie Iles's comment
	cleaned up ENABLE_MASK which was confusing
	now using platform_add_devices() from platform code
	moved base_addr to void __iomem pointer
	removed stop of the event timer in one shot mode

 arch/arm/mach-xilinx/Makefile |    2 +-
 arch/arm/mach-xilinx/timer.c  |  301 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 302 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-xilinx/timer.c

diff --git a/arch/arm/mach-xilinx/Makefile b/arch/arm/mach-xilinx/Makefile
index 76e9e55..660fb19 100644
--- a/arch/arm/mach-xilinx/Makefile
+++ b/arch/arm/mach-xilinx/Makefile
@@ -3,5 +3,5 @@
 #
 
 # Common support
-obj-y 				:= common.o
+obj-y 				:= common.o timer.o
 obj-$(CONFIG_MACH_XILINX)	+= board_ep107.o
diff --git a/arch/arm/mach-xilinx/timer.c b/arch/arm/mach-xilinx/timer.c
new file mode 100644
index 0000000..f08a2f1
--- /dev/null
+++ b/arch/arm/mach-xilinx/timer.c
@@ -0,0 +1,301 @@
+/* arch/arm/mach-xilinx/timer.c
+ *
+ * This file contains driver for the Xilinx PS Timer Counter IP.
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * based on arch/mips/kernel/time.c timer driver
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/types.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/io.h>
+
+#include <asm/mach/time.h>
+#include <mach/xilinx_soc.h>
+
+/*
+ * This driver configures the 2 16-bit count-up timers as follows:
+ *
+ * T1: Timer 1, clocksource for generic timekeeping
+ * T2: Timer 2, clockevent source for hrtimers
+ * T3: Timer 3, <unused>
+ *
+ * The input frequency to the timer module for emulation is 2.5MHz which is
+ * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
+ * the timers are clocked at 78.125KHz (12.8 us resolution).
+ *
+ * The input frequency to the timer module in silicon will be 200MHz. With the
+ * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution).
+ */
+#define XTTCPSS_CLOCKSOURCE	0	/* Timer 1 as a generic timekeeping */
+#define XTTCPSS_CLOCKEVENT	1	/* Timer 2 as a clock event */
+
+#define XTTCPSS_TIMER_BASE		TTC0_BASE
+#define XTTCPCC_EVENT_TIMER_IRQ		(IRQ_TIMERCOUNTER0 + 1)
+/*
+ * Timer Register Offset Definitions of Timer 1, Increment base address by 4
+ * and use same offsets for Timer 2
+ */
+#define XTTCPSS_CLK_CNTRL_OFFSET	0x00 /* Clock Control Reg, RW */
+#define XTTCPSS_CNT_CNTRL_OFFSET	0x0C /* Counter Control Reg, RW */
+#define XTTCPSS_COUNT_VAL_OFFSET	0x18 /* Counter Value Reg, RO */
+#define XTTCPSS_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
+#define XTTCPSS_MATCH_1_OFFSET		0x30 /* Match 1 Value Reg, RW */
+#define XTTCPSS_MATCH_2_OFFSET		0x3C /* Match 2 Value Reg, RW */
+#define XTTCPSS_MATCH_3_OFFSET		0x48 /* Match 3 Value Reg, RW */
+#define XTTCPSS_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
+#define XTTCPSS_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */
+
+#define XTTCPSS_CNT_CNTRL_DISABLE_MASK	0x1
+
+/**
+ * struct xttcpss_timer - This definition defines local timer structure
+ *
+ * @base_addr:	Base address of timer
+ * @timer_irq:	irqaction structure for the timer device
+ * @mode:       only valid for an clock event, periodic or one-shot
+ **/
+struct xttcpss_timer {
+	void __iomem *base_addr;
+	enum clock_event_mode mode;
+};
+
+static struct xttcpss_timer timers[2];
+static struct clock_event_device xttcpss_clockevent;
+
+/**
+ * xttcpss_set_interval - Set the timer interval value
+ *
+ * @timer:	Pointer to the timer instance
+ * @cycles:	Timer interval ticks
+ **/
+static void xttcpss_set_interval(struct xttcpss_timer *timer,
+					unsigned long cycles)
+{
+	u32 ctrl_reg;
+
+	/* Disable the counter, set the counter value  and re-enable counter */
+	ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+	ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+	__raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+
+	__raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET);
+
+	/* Reset the counter (0x10) so that it starts from 0, one-shot
+	   mode makes this needed for timing to be right. */
+	ctrl_reg |= 0x10;
+	ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+	__raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+}
+
+/**
+ * xttcpss_clock_event_interrupt - Clock event timer interrupt handler
+ *
+ * @irq:	IRQ number of the Timer
+ * @dev_id:	void pointer to the xttcpss_timer instance
+ *
+ * returns: Always IRQ_HANDLED - success
+ **/
+static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = &xttcpss_clockevent;
+	struct xttcpss_timer *timer = dev_id;
+
+	/* Acknowledge the interrupt and call event handler */
+	__raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
+			timer->base_addr + XTTCPSS_ISR_OFFSET);
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction event_timer_irq = {
+	.name	= "xttcpss clockevent",
+	.flags	= IRQF_DISABLED | IRQF_TIMER,
+	.handler = xttcpss_clock_event_interrupt,
+};
+
+/**
+ * xttcpss_timer_hardware_init - Initialize the timer hardware
+ *
+ * Initialize the hardware to start the clock source, get the clock
+ * event timer ready to use, and hook up the interrupt.
+ **/
+static void __init xttcpss_timer_hardware_init(void)
+{
+	/* Setup the clock source counter to be an incrementing counter
+	 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
+	   it by 32 also. Let it start running now.
+	 */
+	timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
+
+	__raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
+				XTTCPSS_IER_OFFSET);
+	__raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
+				XTTCPSS_CLK_CNTRL_OFFSET);
+	__raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
+				XTTCPSS_CNT_CNTRL_OFFSET);
+
+	/* Setup the clock event timer to be an interval timer which
+	 * is prescaled by 32 using the interval interrupt. Leave it
+	 * disabled for now.
+	 */
+
+	timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
+
+	__raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
+			XTTCPSS_CNT_CNTRL_OFFSET);
+	__raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
+			XTTCPSS_CLK_CNTRL_OFFSET);
+	__raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
+			XTTCPSS_IER_OFFSET);
+
+	/* Setup IRQ the clock event timer */
+	event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
+
+	if (event_timer_irq.handler != NULL)
+		setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);
+}
+
+/**
+ * __raw_readl_cycles - Reads the timer counter register
+ *
+ * returns: Current timer counter register value
+ **/
+static cycle_t __raw_readl_cycles(struct clocksource *cs)
+{
+	struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE];
+
+	return (cycle_t)__raw_readl(timer->base_addr +
+				XTTCPSS_COUNT_VAL_OFFSET);
+}
+
+
+/*
+ * Instantiate and initialize the clock source structure
+ */
+static struct clocksource clocksource_xttcpss = {
+	.name		= "xttcpss_timer1",
+	.rating		= 200,			/* Reasonable clock source */
+	.read		= __raw_readl_cycles,
+	.mask		= CLOCKSOURCE_MASK(16),
+	.shift		= 0,			/* Initialized to zero */
+	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+
+/**
+ * xttcpss_set_next_event - Sets the time interval for next event
+ *
+ * @cycles:	Timer interval ticks
+ * @evt:	Address of clock event instance
+ *
+ * returns: Always 0 - success
+ **/
+static int xttcpss_set_next_event(unsigned long cycles,
+					struct clock_event_device *evt)
+{
+	struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
+
+	xttcpss_set_interval(timer, cycles);
+	return 0;
+}
+
+/**
+ * xttcpss_set_mode - Sets the mode of timer
+ *
+ * @mode:	Mode to be set
+ * @evt:	Address of clock event instance
+ **/
+static void xttcpss_set_mode(enum clock_event_mode mode,
+					struct clock_event_device *evt)
+{
+	struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
+	u32 ctrl_reg;
+
+	timer->mode = mode;
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		xttcpss_set_interval(timer, CLOCK_TICK_RATE / HZ);
+		break;
+	case CLOCK_EVT_MODE_ONESHOT:
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+		ctrl_reg = __raw_readl(timer->base_addr +
+					XTTCPSS_CNT_CNTRL_OFFSET);
+		ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+		__raw_writel(ctrl_reg,
+				timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+		break;
+	case CLOCK_EVT_MODE_RESUME:
+		ctrl_reg = __raw_readl(timer->base_addr +
+					XTTCPSS_CNT_CNTRL_OFFSET);
+		ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+		__raw_writel(ctrl_reg,
+				timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+		break;
+	}
+}
+
+/*
+ * Instantiate and initialize the clock event structure
+ */
+static struct clock_event_device xttcpss_clockevent = {
+	.name		= "xttcpss_timer2",
+	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+	.shift		= 0,		/* Initialized to zero */
+	.set_next_event	= xttcpss_set_next_event,
+	.set_mode	= xttcpss_set_mode,
+	.rating		= 200,
+};
+
+/**
+ * xttcpss_timer_init - Initialize the timer
+ *
+ * Initializes the timer hardware and register the clock source and clock event
+ * timers with Linux kernal timer framework
+ **/
+static void __init xttcpss_timer_init(void)
+{
+	xttcpss_timer_hardware_init();
+	clocksource_register_hz(&clocksource_xttcpss, CLOCK_TICK_RATE);
+
+	/* Calculate the parameters to allow the clockevent to operate using
+	   integer math
+	*/
+	clockevents_calc_mult_shift(&xttcpss_clockevent, CLOCK_TICK_RATE, 4);
+
+	xttcpss_clockevent.max_delta_ns =
+		clockevent_delta2ns(0xfffe, &xttcpss_clockevent);
+	xttcpss_clockevent.min_delta_ns =
+		clockevent_delta2ns(1, &xttcpss_clockevent);
+
+	/* Indicate that clock event can be used on any of the CPUs */
+
+	xttcpss_clockevent.cpumask = cpu_all_mask;
+	clockevents_register_device(&xttcpss_clockevent);
+}
+
+/*
+ * Instantiate and initialize the system timer structure
+ */
+struct sys_timer xttcpss_sys_timer = {
+	.init		= xttcpss_timer_init,
+};
-- 
1.6.2.1



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[PATCH V3 2/4] ARM: Xilinx: Adding timer support to the platform

[Jamie Iles]

Hi John,

A couple more nitpicks.

Jamie

On Wed, Feb 16, 2011 at 09:11:54AM -0700, John Linn wrote:
> The timer driver supports the Xilinx PS Timer Counter IP.
> 
> Signed-off-by: Kiran Sutariya <kiran.sutariya@einfochips.com>
> Signed-off-by: John Linn <john.linn@xilinx.com>
> ---
> 
> V3 Changes
> 
> Updates based on Russell Kings' comments
> 	Changed headers to update the license info and remove
> 	the address
> 
> V2 Changes
> 
> The timer code was changed quite a bit based on review inputs. It
> got much smaller and cleaner I think.
> 
> Updates based on Russell King's comments	
> 	minor cleanups for documentation comments
> 	removed the name from the timer structure
> 	removed interrupt for clock source 
> 	moved to using clock functions provided in the kernel
> 		for calculating shift/mult values
> 	removed PM code as generic handles it
> 
> Updated based on Jamie Iles's comment
> 	cleaned up ENABLE_MASK which was confusing
> 	now using platform_add_devices() from platform code
> 	moved base_addr to void __iomem pointer
> 	removed stop of the event timer in one shot mode
> 
>  arch/arm/mach-xilinx/Makefile |    2 +-
>  arch/arm/mach-xilinx/timer.c  |  301 +++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 302 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/mach-xilinx/timer.c
> 
> diff --git a/arch/arm/mach-xilinx/Makefile b/arch/arm/mach-xilinx/Makefile
> index 76e9e55..660fb19 100644
> --- a/arch/arm/mach-xilinx/Makefile
> +++ b/arch/arm/mach-xilinx/Makefile
> @@ -3,5 +3,5 @@
>  #
>  
>  # Common support
> -obj-y 				:= common.o
> +obj-y 				:= common.o timer.o
>  obj-$(CONFIG_MACH_XILINX)	+= board_ep107.o
> diff --git a/arch/arm/mach-xilinx/timer.c b/arch/arm/mach-xilinx/timer.c
> new file mode 100644
> index 0000000..f08a2f1
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/timer.c
> @@ -0,0 +1,301 @@
> +/* arch/arm/mach-xilinx/timer.c
> + *
> + * This file contains driver for the Xilinx PS Timer Counter IP.
> + *
> + *  Copyright (C) 2011 Xilinx
> + *
> + * based on arch/mips/kernel/time.c timer driver
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/types.h>
> +#include <linux/clocksource.h>
> +#include <linux/clockchips.h>
> +#include <linux/io.h>
> +
> +#include <asm/mach/time.h>
> +#include <mach/xilinx_soc.h>
> +
> +/*
> + * This driver configures the 2 16-bit count-up timers as follows:
> + *
> + * T1: Timer 1, clocksource for generic timekeeping
> + * T2: Timer 2, clockevent source for hrtimers
> + * T3: Timer 3, <unused>
> + *
> + * The input frequency to the timer module for emulation is 2.5MHz which is
> + * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
> + * the timers are clocked at 78.125KHz (12.8 us resolution).
> + *
> + * The input frequency to the timer module in silicon will be 200MHz. With the
> + * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution).
> + */
> +#define XTTCPSS_CLOCKSOURCE	0	/* Timer 1 as a generic timekeeping */
> +#define XTTCPSS_CLOCKEVENT	1	/* Timer 2 as a clock event */
> +
> +#define XTTCPSS_TIMER_BASE		TTC0_BASE
> +#define XTTCPCC_EVENT_TIMER_IRQ		(IRQ_TIMERCOUNTER0 + 1)
> +/*
> + * Timer Register Offset Definitions of Timer 1, Increment base address by 4
> + * and use same offsets for Timer 2
> + */
> +#define XTTCPSS_CLK_CNTRL_OFFSET	0x00 /* Clock Control Reg, RW */
> +#define XTTCPSS_CNT_CNTRL_OFFSET	0x0C /* Counter Control Reg, RW */
> +#define XTTCPSS_COUNT_VAL_OFFSET	0x18 /* Counter Value Reg, RO */
> +#define XTTCPSS_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
> +#define XTTCPSS_MATCH_1_OFFSET		0x30 /* Match 1 Value Reg, RW */
> +#define XTTCPSS_MATCH_2_OFFSET		0x3C /* Match 2 Value Reg, RW */
> +#define XTTCPSS_MATCH_3_OFFSET		0x48 /* Match 3 Value Reg, RW */
> +#define XTTCPSS_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
> +#define XTTCPSS_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */
> +
> +#define XTTCPSS_CNT_CNTRL_DISABLE_MASK	0x1
> +
> +/**
> + * struct xttcpss_timer - This definition defines local timer structure
> + *
> + * @base_addr:	Base address of timer
> + * @timer_irq:	irqaction structure for the timer device
> + * @mode:       only valid for an clock event, periodic or one-shot
> + **/
> +struct xttcpss_timer {
> +	void __iomem *base_addr;
> +	enum clock_event_mode mode;

I can't see .mode being used anywhere in this file so this could 
probably be simplified a bit to just two base address pointers.

> +};
> +
> +static struct xttcpss_timer timers[2];
> +static struct clock_event_device xttcpss_clockevent;
> +
> +/**
> + * xttcpss_set_interval - Set the timer interval value
> + *
> + * @timer:	Pointer to the timer instance
> + * @cycles:	Timer interval ticks
> + **/
> +static void xttcpss_set_interval(struct xttcpss_timer *timer,
> +					unsigned long cycles)
> +{
> +	u32 ctrl_reg;
> +
> +	/* Disable the counter, set the counter value  and re-enable counter */
> +	ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
> +	ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> +	__raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
> +
> +	__raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET);
> +
> +	/* Reset the counter (0x10) so that it starts from 0, one-shot
> +	   mode makes this needed for timing to be right. */
> +	ctrl_reg |= 0x10;
> +	ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> +	__raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
> +}
> +
> +/**
> + * xttcpss_clock_event_interrupt - Clock event timer interrupt handler
> + *
> + * @irq:	IRQ number of the Timer
> + * @dev_id:	void pointer to the xttcpss_timer instance
> + *
> + * returns: Always IRQ_HANDLED - success
> + **/
> +static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = &xttcpss_clockevent;
> +	struct xttcpss_timer *timer = dev_id;
> +
> +	/* Acknowledge the interrupt and call event handler */
> +	__raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
> +			timer->base_addr + XTTCPSS_ISR_OFFSET);
> +
> +	evt->event_handler(evt);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static struct irqaction event_timer_irq = {
> +	.name	= "xttcpss clockevent",
> +	.flags	= IRQF_DISABLED | IRQF_TIMER,
> +	.handler = xttcpss_clock_event_interrupt,
> +};
> +
> +/**
> + * xttcpss_timer_hardware_init - Initialize the timer hardware
> + *
> + * Initialize the hardware to start the clock source, get the clock
> + * event timer ready to use, and hook up the interrupt.
> + **/
> +static void __init xttcpss_timer_hardware_init(void)
> +{
> +	/* Setup the clock source counter to be an incrementing counter
> +	 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
> +	   it by 32 also. Let it start running now.
> +	 */
> +	timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
> +
> +	__raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
> +				XTTCPSS_IER_OFFSET);
> +	__raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
> +				XTTCPSS_CLK_CNTRL_OFFSET);
> +	__raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
> +				XTTCPSS_CNT_CNTRL_OFFSET);
> +
> +	/* Setup the clock event timer to be an interval timer which
> +	 * is prescaled by 32 using the interval interrupt. Leave it
> +	 * disabled for now.
> +	 */
> +
> +	timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
> +
> +	__raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
> +			XTTCPSS_CNT_CNTRL_OFFSET);
> +	__raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
> +			XTTCPSS_CLK_CNTRL_OFFSET);
> +	__raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
> +			XTTCPSS_IER_OFFSET);
> +
> +	/* Setup IRQ the clock event timer */
> +	event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
> +
> +	if (event_timer_irq.handler != NULL)
> +		setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);

You've explicitly initialized event_timer_irq.handler above so I don't 
think you need to check against NULL, and just always call setup_irq().

> +}
> +
> +/**
> + * __raw_readl_cycles - Reads the timer counter register
> + *
> + * returns: Current timer counter register value
> + **/
> +static cycle_t __raw_readl_cycles(struct clocksource *cs)
> +{
> +	struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE];
> +
> +	return (cycle_t)__raw_readl(timer->base_addr +
> +				XTTCPSS_COUNT_VAL_OFFSET);
> +}
> +
> +
> +/*
> + * Instantiate and initialize the clock source structure
> + */
> +static struct clocksource clocksource_xttcpss = {
> +	.name		= "xttcpss_timer1",
> +	.rating		= 200,			/* Reasonable clock source */
> +	.read		= __raw_readl_cycles,
> +	.mask		= CLOCKSOURCE_MASK(16),
> +	.shift		= 0,			/* Initialized to zero */

This is static data so you don't need to explicitly initialize shift to 
0.  It doesn't hurt anything though.

> +	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
> +};
> +
> +
> +/**
> + * xttcpss_set_next_event - Sets the time interval for next event
> + *
> + * @cycles:	Timer interval ticks
> + * @evt:	Address of clock event instance
> + *
> + * returns: Always 0 - success
> + **/
> +static int xttcpss_set_next_event(unsigned long cycles,
> +					struct clock_event_device *evt)
> +{
> +	struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
> +
> +	xttcpss_set_interval(timer, cycles);
> +	return 0;
> +}
> +
> +/**
> + * xttcpss_set_mode - Sets the mode of timer
> + *
> + * @mode:	Mode to be set
> + * @evt:	Address of clock event instance
> + **/
> +static void xttcpss_set_mode(enum clock_event_mode mode,
> +					struct clock_event_device *evt)
> +{
> +	struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
> +	u32 ctrl_reg;
> +
> +	timer->mode = mode;
> +
> +	switch (mode) {
> +	case CLOCK_EVT_MODE_PERIODIC:
> +		xttcpss_set_interval(timer, CLOCK_TICK_RATE / HZ);
> +		break;
> +	case CLOCK_EVT_MODE_ONESHOT:
> +	case CLOCK_EVT_MODE_UNUSED:
> +	case CLOCK_EVT_MODE_SHUTDOWN:
> +		ctrl_reg = __raw_readl(timer->base_addr +
> +					XTTCPSS_CNT_CNTRL_OFFSET);
> +		ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> +		__raw_writel(ctrl_reg,
> +				timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
> +		break;
> +	case CLOCK_EVT_MODE_RESUME:
> +		ctrl_reg = __raw_readl(timer->base_addr +
> +					XTTCPSS_CNT_CNTRL_OFFSET);
> +		ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> +		__raw_writel(ctrl_reg,
> +				timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
> +		break;
> +	}
> +}
> +
> +/*
> + * Instantiate and initialize the clock event structure
> + */
> +static struct clock_event_device xttcpss_clockevent = {
> +	.name		= "xttcpss_timer2",
> +	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
> +	.shift		= 0,		/* Initialized to zero */

Same here, that .shift = 0 isn't really needed (but doesn't hurt).

> +	.set_next_event	= xttcpss_set_next_event,
> +	.set_mode	= xttcpss_set_mode,
> +	.rating		= 200,
> +};
> +
> +/**
> + * xttcpss_timer_init - Initialize the timer
> + *
> + * Initializes the timer hardware and register the clock source and clock event
> + * timers with Linux kernal timer framework
> + **/
> +static void __init xttcpss_timer_init(void)
> +{
> +	xttcpss_timer_hardware_init();
> +	clocksource_register_hz(&clocksource_xttcpss, CLOCK_TICK_RATE);
> +
> +	/* Calculate the parameters to allow the clockevent to operate using
> +	   integer math
> +	*/
> +	clockevents_calc_mult_shift(&xttcpss_clockevent, CLOCK_TICK_RATE, 4);
> +
> +	xttcpss_clockevent.max_delta_ns =
> +		clockevent_delta2ns(0xfffe, &xttcpss_clockevent);
> +	xttcpss_clockevent.min_delta_ns =
> +		clockevent_delta2ns(1, &xttcpss_clockevent);
> +
> +	/* Indicate that clock event can be used on any of the CPUs */
> +
> +	xttcpss_clockevent.cpumask = cpu_all_mask;
> +	clockevents_register_device(&xttcpss_clockevent);
> +}
> +
> +/*
> + * Instantiate and initialize the system timer structure
> + */
> +struct sys_timer xttcpss_sys_timer = {
> +	.init		= xttcpss_timer_init,
> +};
> -- 
> 1.6.2.1
> 
> 
> 
> This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
> 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH V3 2/4] ARM: Xilinx: Adding timer support to the platform

[John Linn]

> -----Original Message-----
> From: Jamie Iles [mailto:jamie at jamieiles.com]
> Sent: Thursday, February 17, 2011 2:48 AM
> To: John Linn
> Cc: linux-arm-kernel at lists.infradead.org;
linux-kernel at vger.kernel.org; linux at arm.linux.org.uk;
> catalin.marinas at arm.com; glikely at secretlab.ca; arnd at arndb.de; Kiran
Sutariya
> Subject: Re: [PATCH V3 2/4] ARM: Xilinx: Adding timer support to the
platform
> 
> Hi John,
> 
> A couple more nitpicks.
> 
> Jamie
> 
> On Wed, Feb 16, 2011 at 09:11:54AM -0700, John Linn wrote:
> > The timer driver supports the Xilinx PS Timer Counter IP.
> >
> > Signed-off-by: Kiran Sutariya <kiran.sutariya@einfochips.com>
> > Signed-off-by: John Linn <john.linn@xilinx.com>
> > ---
> >
> > V3 Changes
> >
> > Updates based on Russell Kings' comments
> > 	Changed headers to update the license info and remove
> > 	the address
> >
> > V2 Changes
> >
> > The timer code was changed quite a bit based on review inputs. It
> > got much smaller and cleaner I think.
> >
> > Updates based on Russell King's comments
> > 	minor cleanups for documentation comments
> > 	removed the name from the timer structure
> > 	removed interrupt for clock source
> > 	moved to using clock functions provided in the kernel
> > 		for calculating shift/mult values
> > 	removed PM code as generic handles it
> >
> > Updated based on Jamie Iles's comment
> > 	cleaned up ENABLE_MASK which was confusing
> > 	now using platform_add_devices() from platform code
> > 	moved base_addr to void __iomem pointer
> > 	removed stop of the event timer in one shot mode
> >
> >  arch/arm/mach-xilinx/Makefile |    2 +-
> >  arch/arm/mach-xilinx/timer.c  |  301
+++++++++++++++++++++++++++++++++++++++++
> >  2 files changed, 302 insertions(+), 1 deletions(-)
> >  create mode 100644 arch/arm/mach-xilinx/timer.c
> >
> > diff --git a/arch/arm/mach-xilinx/Makefile
b/arch/arm/mach-xilinx/Makefile
> > index 76e9e55..660fb19 100644
> > --- a/arch/arm/mach-xilinx/Makefile
> > +++ b/arch/arm/mach-xilinx/Makefile
> > @@ -3,5 +3,5 @@
> >  #
> >
> >  # Common support
> > -obj-y 				:= common.o
> > +obj-y 				:= common.o timer.o
> >  obj-$(CONFIG_MACH_XILINX)	+= board_ep107.o
> > diff --git a/arch/arm/mach-xilinx/timer.c
b/arch/arm/mach-xilinx/timer.c
> > new file mode 100644
> > index 0000000..f08a2f1
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/timer.c
> > @@ -0,0 +1,301 @@
> > +/* arch/arm/mach-xilinx/timer.c
> > + *
> > + * This file contains driver for the Xilinx PS Timer Counter IP.
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * based on arch/mips/kernel/time.c timer driver
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/init.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/irq.h>
> > +#include <linux/types.h>
> > +#include <linux/clocksource.h>
> > +#include <linux/clockchips.h>
> > +#include <linux/io.h>
> > +
> > +#include <asm/mach/time.h>
> > +#include <mach/xilinx_soc.h>
> > +
> > +/*
> > + * This driver configures the 2 16-bit count-up timers as follows:
> > + *
> > + * T1: Timer 1, clocksource for generic timekeeping
> > + * T2: Timer 2, clockevent source for hrtimers
> > + * T3: Timer 3, <unused>
> > + *
> > + * The input frequency to the timer module for emulation is 2.5MHz
which is
> > + * common to all the timer channels (T1, T2, and T3). With a
pre-scaler of 32,
> > + * the timers are clocked at 78.125KHz (12.8 us resolution).
> > + *
> > + * The input frequency to the timer module in silicon will be
200MHz. With the
> > + * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns
resolution).
> > + */
> > +#define XTTCPSS_CLOCKSOURCE	0	/* Timer 1 as a generic
timekeeping */
> > +#define XTTCPSS_CLOCKEVENT	1	/* Timer 2 as a clock event */
> > +
> > +#define XTTCPSS_TIMER_BASE		TTC0_BASE
> > +#define XTTCPCC_EVENT_TIMER_IRQ		(IRQ_TIMERCOUNTER0 + 1)
> > +/*
> > + * Timer Register Offset Definitions of Timer 1, Increment base
address by 4
> > + * and use same offsets for Timer 2
> > + */
> > +#define XTTCPSS_CLK_CNTRL_OFFSET	0x00 /* Clock Control Reg, RW */
> > +#define XTTCPSS_CNT_CNTRL_OFFSET	0x0C /* Counter Control Reg, RW
*/
> > +#define XTTCPSS_COUNT_VAL_OFFSET	0x18 /* Counter Value Reg, RO */
> > +#define XTTCPSS_INTR_VAL_OFFSET		0x24 /* Interval Count
Reg, RW */
> > +#define XTTCPSS_MATCH_1_OFFSET		0x30 /* Match 1 Value
Reg, RW */
> > +#define XTTCPSS_MATCH_2_OFFSET		0x3C /* Match 2 Value
Reg, RW */
> > +#define XTTCPSS_MATCH_3_OFFSET		0x48 /* Match 3 Value
Reg, RW */
> > +#define XTTCPSS_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO
*/
> > +#define XTTCPSS_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW
*/
> > +
> > +#define XTTCPSS_CNT_CNTRL_DISABLE_MASK	0x1
> > +
> > +/**
> > + * struct xttcpss_timer - This definition defines local timer
structure
> > + *
> > + * @base_addr:	Base address of timer
> > + * @timer_irq:	irqaction structure for the timer device
> > + * @mode:       only valid for an clock event, periodic or one-shot
> > + **/
> > +struct xttcpss_timer {
> > +	void __iomem *base_addr;
> > +	enum clock_event_mode mode;
> 
> I can't see .mode being used anywhere in this file so this could
> probably be simplified a bit to just two base address pointers.

Yep, got removed in the cleanup.  Obviously the cleanup didn't get quite
everything.

Will do.

> 
> > +};
> > +
> > +static struct xttcpss_timer timers[2];
> > +static struct clock_event_device xttcpss_clockevent;
> > +
> > +/**
> > + * xttcpss_set_interval - Set the timer interval value
> > + *
> > + * @timer:	Pointer to the timer instance
> > + * @cycles:	Timer interval ticks
> > + **/
> > +static void xttcpss_set_interval(struct xttcpss_timer *timer,
> > +					unsigned long cycles)
> > +{
> > +	u32 ctrl_reg;
> > +
> > +	/* Disable the counter, set the counter value  and re-enable
counter */
> > +	ctrl_reg = __raw_readl(timer->base_addr +
XTTCPSS_CNT_CNTRL_OFFSET);
> > +	ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> > +	__raw_writel(ctrl_reg, timer->base_addr +
XTTCPSS_CNT_CNTRL_OFFSET);
> > +
> > +	__raw_writel(cycles, timer->base_addr +
XTTCPSS_INTR_VAL_OFFSET);
> > +
> > +	/* Reset the counter (0x10) so that it starts from 0, one-shot
> > +	   mode makes this needed for timing to be right. */
> > +	ctrl_reg |= 0x10;
> > +	ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> > +	__raw_writel(ctrl_reg, timer->base_addr +
XTTCPSS_CNT_CNTRL_OFFSET);
> > +}
> > +
> > +/**
> > + * xttcpss_clock_event_interrupt - Clock event timer interrupt
handler
> > + *
> > + * @irq:	IRQ number of the Timer
> > + * @dev_id:	void pointer to the xttcpss_timer instance
> > + *
> > + * returns: Always IRQ_HANDLED - success
> > + **/
> > +static irqreturn_t xttcpss_clock_event_interrupt(int irq, void
*dev_id)
> > +{
> > +	struct clock_event_device *evt = &xttcpss_clockevent;
> > +	struct xttcpss_timer *timer = dev_id;
> > +
> > +	/* Acknowledge the interrupt and call event handler */
> > +	__raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
> > +			timer->base_addr + XTTCPSS_ISR_OFFSET);
> > +
> > +	evt->event_handler(evt);
> > +
> > +	return IRQ_HANDLED;
> > +}
> > +
> > +static struct irqaction event_timer_irq = {
> > +	.name	= "xttcpss clockevent",
> > +	.flags	= IRQF_DISABLED | IRQF_TIMER,
> > +	.handler = xttcpss_clock_event_interrupt,
> > +};
> > +
> > +/**
> > + * xttcpss_timer_hardware_init - Initialize the timer hardware
> > + *
> > + * Initialize the hardware to start the clock source, get the clock
> > + * event timer ready to use, and hook up the interrupt.
> > + **/
> > +static void __init xttcpss_timer_hardware_init(void)
> > +{
> > +	/* Setup the clock source counter to be an incrementing counter
> > +	 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
> > +	   it by 32 also. Let it start running now.
> > +	 */
> > +	timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
> > +
> > +	__raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
> > +				XTTCPSS_IER_OFFSET);
> > +	__raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
> > +				XTTCPSS_CLK_CNTRL_OFFSET);
> > +	__raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
> > +				XTTCPSS_CNT_CNTRL_OFFSET);
> > +
> > +	/* Setup the clock event timer to be an interval timer which
> > +	 * is prescaled by 32 using the interval interrupt. Leave it
> > +	 * disabled for now.
> > +	 */
> > +
> > +	timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
> > +
> > +	__raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
> > +			XTTCPSS_CNT_CNTRL_OFFSET);
> > +	__raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
> > +			XTTCPSS_CLK_CNTRL_OFFSET);
> > +	__raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
> > +			XTTCPSS_IER_OFFSET);
> > +
> > +	/* Setup IRQ the clock event timer */
> > +	event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
> > +
> > +	if (event_timer_irq.handler != NULL)
> > +		setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);
> 
> You've explicitly initialized event_timer_irq.handler above so I don't
> think you need to check against NULL, and just always call
setup_irq().

Makes sense.

> 
> > +}
> > +
> > +/**
> > + * __raw_readl_cycles - Reads the timer counter register
> > + *
> > + * returns: Current timer counter register value
> > + **/
> > +static cycle_t __raw_readl_cycles(struct clocksource *cs)
> > +{
> > +	struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE];
> > +
> > +	return (cycle_t)__raw_readl(timer->base_addr +
> > +				XTTCPSS_COUNT_VAL_OFFSET);
> > +}
> > +
> > +
> > +/*
> > + * Instantiate and initialize the clock source structure
> > + */
> > +static struct clocksource clocksource_xttcpss = {
> > +	.name		= "xttcpss_timer1",
> > +	.rating		= 200,			/* Reasonable clock
source */
> > +	.read		= __raw_readl_cycles,
> > +	.mask		= CLOCKSOURCE_MASK(16),
> > +	.shift		= 0,			/* Initialized to zero
*/
> 
> This is static data so you don't need to explicitly initialize shift
to
> 0.  It doesn't hurt anything though.
> 

Yes, agreed.

> > +	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
> > +};
> > +
> > +
> > +/**
> > + * xttcpss_set_next_event - Sets the time interval for next event
> > + *
> > + * @cycles:	Timer interval ticks
> > + * @evt:	Address of clock event instance
> > + *
> > + * returns: Always 0 - success
> > + **/
> > +static int xttcpss_set_next_event(unsigned long cycles,
> > +					struct clock_event_device *evt)
> > +{
> > +	struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
> > +
> > +	xttcpss_set_interval(timer, cycles);
> > +	return 0;
> > +}
> > +
> > +/**
> > + * xttcpss_set_mode - Sets the mode of timer
> > + *
> > + * @mode:	Mode to be set
> > + * @evt:	Address of clock event instance
> > + **/
> > +static void xttcpss_set_mode(enum clock_event_mode mode,
> > +					struct clock_event_device *evt)
> > +{
> > +	struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
> > +	u32 ctrl_reg;
> > +
> > +	timer->mode = mode;
> > +
> > +	switch (mode) {
> > +	case CLOCK_EVT_MODE_PERIODIC:
> > +		xttcpss_set_interval(timer, CLOCK_TICK_RATE / HZ);
> > +		break;
> > +	case CLOCK_EVT_MODE_ONESHOT:
> > +	case CLOCK_EVT_MODE_UNUSED:
> > +	case CLOCK_EVT_MODE_SHUTDOWN:
> > +		ctrl_reg = __raw_readl(timer->base_addr +
> > +					XTTCPSS_CNT_CNTRL_OFFSET);
> > +		ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> > +		__raw_writel(ctrl_reg,
> > +				timer->base_addr +
XTTCPSS_CNT_CNTRL_OFFSET);
> > +		break;
> > +	case CLOCK_EVT_MODE_RESUME:
> > +		ctrl_reg = __raw_readl(timer->base_addr +
> > +					XTTCPSS_CNT_CNTRL_OFFSET);
> > +		ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> > +		__raw_writel(ctrl_reg,
> > +				timer->base_addr +
XTTCPSS_CNT_CNTRL_OFFSET);
> > +		break;
> > +	}
> > +}
> > +
> > +/*
> > + * Instantiate and initialize the clock event structure
> > + */
> > +static struct clock_event_device xttcpss_clockevent = {
> > +	.name		= "xttcpss_timer2",
> > +	.features	= CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
> > +	.shift		= 0,		/* Initialized to zero */
> 
> Same here, that .shift = 0 isn't really needed (but doesn't hurt).

OK.

Thanks,
John

> 
> > +	.set_next_event	= xttcpss_set_next_event,
> > +	.set_mode	= xttcpss_set_mode,
> > +	.rating		= 200,
> > +};
> > +
> > +/**
> > + * xttcpss_timer_init - Initialize the timer
> > + *
> > + * Initializes the timer hardware and register the clock source and
clock event
> > + * timers with Linux kernal timer framework
> > + **/
> > +static void __init xttcpss_timer_init(void)
> > +{
> > +	xttcpss_timer_hardware_init();
> > +	clocksource_register_hz(&clocksource_xttcpss, CLOCK_TICK_RATE);
> > +
> > +	/* Calculate the parameters to allow the clockevent to operate
using
> > +	   integer math
> > +	*/
> > +	clockevents_calc_mult_shift(&xttcpss_clockevent,
CLOCK_TICK_RATE, 4);
> > +
> > +	xttcpss_clockevent.max_delta_ns =
> > +		clockevent_delta2ns(0xfffe, &xttcpss_clockevent);
> > +	xttcpss_clockevent.min_delta_ns =
> > +		clockevent_delta2ns(1, &xttcpss_clockevent);
> > +
> > +	/* Indicate that clock event can be used on any of the CPUs */
> > +
> > +	xttcpss_clockevent.cpumask = cpu_all_mask;
> > +	clockevents_register_device(&xttcpss_clockevent);
> > +}
> > +
> > +/*
> > + * Instantiate and initialize the system timer structure
> > + */
> > +struct sys_timer xttcpss_sys_timer = {
> > +	.init		= xttcpss_timer_init,
> > +};
> > --
> > 1.6.2.1
> >
> >
> >
> > This email and any attachments are intended for the sole use of the
named recipient(s) and
> contain(s) confidential information that may be proprietary,
privileged or copyrighted under
> applicable law. If you are not the intended recipient, do not read,
copy, or forward this email
> message or any attachments. Delete this email message and any
attachments immediately.
> >
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

[PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros

[John Linn]

These are the minimum needed to build the kernel for the new platform.

Signed-off-by: John Linn <john.linn@xilinx.com>
---

V3 Changes

Updates based on Russell Kings' comments
	Changed headers to update the license info and remove
	the address

	Updated the constant to use UL in vmalloc.h

V2 Changes

Updates based on Russell King's comments	
	moved to using entry-macro-gic.S
	moved stuff from hardware.h to xilinx_soc.h 
	added IOMEM() in io.h to help with typing
	Minor updates to IO_SPACE_LIMIT and __io()
	Updated addresses to be clear with seperate virtual
		and physical addresses

 arch/arm/mach-xilinx/include/mach/clkdev.h      |   33 ++++++++++++++++
 arch/arm/mach-xilinx/include/mach/debug-macro.S |   36 +++++++++++++++++
 arch/arm/mach-xilinx/include/mach/entry-macro.S |   30 ++++++++++++++
 arch/arm/mach-xilinx/include/mach/hardware.h    |   18 +++++++++
 arch/arm/mach-xilinx/include/mach/io.h          |   33 ++++++++++++++++
 arch/arm/mach-xilinx/include/mach/irqs.h        |   29 ++++++++++++++
 arch/arm/mach-xilinx/include/mach/memory.h      |   23 +++++++++++
 arch/arm/mach-xilinx/include/mach/system.h      |   28 +++++++++++++
 arch/arm/mach-xilinx/include/mach/timex.h       |   24 ++++++++++++
 arch/arm/mach-xilinx/include/mach/uart.h        |   31 +++++++++++++++
 arch/arm/mach-xilinx/include/mach/uncompress.h  |   47 +++++++++++++++++++++++
 arch/arm/mach-xilinx/include/mach/vmalloc.h     |   20 ++++++++++
 arch/arm/mach-xilinx/include/mach/xilinx_soc.h  |   46 ++++++++++++++++++++++
 13 files changed, 398 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-xilinx/include/mach/clkdev.h
 create mode 100644 arch/arm/mach-xilinx/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-xilinx/include/mach/entry-macro.S
 create mode 100644 arch/arm/mach-xilinx/include/mach/hardware.h
 create mode 100644 arch/arm/mach-xilinx/include/mach/io.h
 create mode 100644 arch/arm/mach-xilinx/include/mach/irqs.h
 create mode 100644 arch/arm/mach-xilinx/include/mach/memory.h
 create mode 100644 arch/arm/mach-xilinx/include/mach/system.h
 create mode 100644 arch/arm/mach-xilinx/include/mach/timex.h
 create mode 100644 arch/arm/mach-xilinx/include/mach/uart.h
 create mode 100644 arch/arm/mach-xilinx/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-xilinx/include/mach/vmalloc.h
 create mode 100644 arch/arm/mach-xilinx/include/mach/xilinx_soc.h

diff --git a/arch/arm/mach-xilinx/include/mach/clkdev.h b/arch/arm/mach-xilinx/include/mach/clkdev.h
new file mode 100644
index 0000000..5dd1453
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/clkdev.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-xilinx/include/mach/clkdev.h
+ *
+ *  Copyright (C) 2011 Xilinx, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_CLKDEV_H__
+#define __MACH_CLKDEV_H__
+
+struct clk {
+	unsigned long rate;
+};
+
+static inline int __clk_get(struct clk *clk)
+{
+	return 1;
+}
+
+static inline void __clk_put(struct clk *clk)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/debug-macro.S b/arch/arm/mach-xilinx/include/mach/debug-macro.S
new file mode 100644
index 0000000..30d3d3d
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/debug-macro.S
@@ -0,0 +1,36 @@
+/* arch/arm/mach-xilinx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <mach/xilinx_soc.h>
+#include <mach/uart.h>
+
+		.macro	addruart, rp, rv
+		ldr	\rp, =LL_UART_PADDR	@ physical
+		ldr	\rv, =LL_UART_VADDR	@ virtual
+		.endm
+
+		.macro	senduart,rd,rx
+		str	\rd, [\rx, #UART_FIFO_OFFSET]	@ TXDATA
+		.endm
+
+		.macro	waituart,rd,rx
+		.endm
+
+		.macro	busyuart,rd,rx
+1002:		ldr	\rd, [\rx, #UART_SR_OFFSET]	@ get status register
+		tst	\rd, #UART_SR_TXFULL		@
+		bne	1002b			@ wait if FIFO is full
+		.endm
diff --git a/arch/arm/mach-xilinx/include/mach/entry-macro.S b/arch/arm/mach-xilinx/include/mach/entry-macro.S
new file mode 100644
index 0000000..11a2866
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/entry-macro.S
@@ -0,0 +1,30 @@
+/*
+ * arch/arm/mach-xilinx/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * based on arch/plat-mxc/include/mach/entry-macro.S
+ *
+ *  Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <mach/hardware.h>
+#include <asm/hardware/entry-macro-gic.S>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
diff --git a/arch/arm/mach-xilinx/include/mach/hardware.h b/arch/arm/mach-xilinx/include/mach/hardware.h
new file mode 100644
index 0000000..f9685c4
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/hardware.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-xilinx/include/mach/hardware.h
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_HARDWARE_H__
+#define __MACH_HARDWARE_H__
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/io.h b/arch/arm/mach-xilinx/include/mach/io.h
new file mode 100644
index 0000000..ef69e65
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/io.h
@@ -0,0 +1,33 @@
+/* arch/arm/mach-xilinx/include/mach/io.h
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_IO_H__
+#define __MACH_IO_H__
+
+/* Allow IO space to be anywhere in the memory */
+
+#define IO_SPACE_LIMIT 0xffff
+
+/* IO address mapping macros, nothing special at this time but required */
+
+#ifdef __ASSEMBLER__
+#define IOMEM(x)		(x)
+#else
+#define IOMEM(x)		((void __force __iomem *)(x))
+#endif
+
+#define __io(a)			__typesafe_io(a)
+#define __mem_pci(a)		(a)
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/irqs.h b/arch/arm/mach-xilinx/include/mach/irqs.h
new file mode 100644
index 0000000..47a8162
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/irqs.h
@@ -0,0 +1,29 @@
+/* arch/arm/mach-xilinx/include/mach/irqs.h
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define ARCH_NR_GPIOS	118
+#define NR_IRQS		(128 + ARCH_NR_GPIOS)
+
+/*
+ * GIC Interrupts
+ */
+
+#define IRQ_GIC_SPI_START	32
+#define IRQ_TIMERCOUNTER0	42
+#define IRQ_UART0		59
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/memory.h b/arch/arm/mach-xilinx/include/mach/memory.h
new file mode 100644
index 0000000..c200486
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/memory.h
@@ -0,0 +1,23 @@
+/* arch/arm/mach-xilinx/include/mach/memory.h
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_MEMORY_H__
+#define __MACH_MEMORY_H__
+
+#include <mach/hardware.h>
+
+#define PHYS_OFFSET             0x0
+#define MEM_SIZE		SZ_256M
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/system.h b/arch/arm/mach-xilinx/include/mach/system.h
new file mode 100644
index 0000000..e8514a0
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/system.h
@@ -0,0 +1,28 @@
+/* arch/arm/mach-xilinx/include/mach/system.h
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_SYSTEM_H__
+#define __MACH_SYSTEM_H__
+
+static inline void arch_idle(void)
+{
+	cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+	/* Add architecture specific reset processing here */
+}
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/timex.h b/arch/arm/mach-xilinx/include/mach/timex.h
new file mode 100644
index 0000000..6765e15
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/timex.h
@@ -0,0 +1,24 @@
+/* arch/arm/mach-xilinx/include/mach/timex.h
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_TIMEX_H__
+#define __MACH_TIMEX_H__
+
+#include <mach/hardware.h>
+
+#define PERIPHERAL_CLOCK_RATE	2500000
+
+#define CLOCK_TICK_RATE	(PERIPHERAL_CLOCK_RATE / 32)
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/uart.h b/arch/arm/mach-xilinx/include/mach/uart.h
new file mode 100644
index 0000000..20a10d7
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/uart.h
@@ -0,0 +1,31 @@
+/* arch/arm/mach-xilinx/include/mach/uart.h
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_UART_H__
+#define __MACH_UART_H__
+
+#define UART_CR_OFFSET          0x00  /* Control Register [8:0] */
+#define UART_SR_OFFSET          0x2C  /* Channel Status [11:0] */
+#define UART_FIFO_OFFSET        0x30  /* FIFO [15:0] or [7:0] */
+
+#define UART_SR_TXFULL		0x00000010	/* TX FIFO full */
+#define UART_SR_TXEMPTY		0x00000008	/* TX FIFO empty */
+
+#define UART_FIFO_WRITE(base, value) \
+	(*(volatile unsigned int *)((base) + UART_FIFO_OFFSET) = (value))
+
+#define UART_STATUS(base) \
+	(*(volatile unsigned int *)((base) + UART_SR_OFFSET))
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/uncompress.h b/arch/arm/mach-xilinx/include/mach/uncompress.h
new file mode 100644
index 0000000..b7a5110
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/uncompress.h
@@ -0,0 +1,47 @@
+/* arch/arm/mach-xilinx/include/mach/uncompress.h
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_UNCOMPRESS_H__
+#define __MACH_UNCOMPRESS_H__
+
+#include <mach/xilinx_soc.h>
+#include <mach/uart.h>
+
+void arch_decomp_setup(void)
+{
+}
+
+static inline void flush(void)
+{
+	/*
+	 * Wait while the FIFO is not empty
+	 */
+	while (!(UART_STATUS(LL_UART_PADDR) & UART_SR_TXEMPTY))
+		;
+}
+
+#define arch_decomp_wdog()
+
+static void putc(char ch)
+{
+	/*
+	 * Wait for room in the FIFO, then write the char into the FIFO
+	 */
+	while (UART_STATUS(LL_UART_PADDR) & UART_SR_TXFULL)
+		;
+
+	UART_FIFO_WRITE(LL_UART_PADDR, ch);
+}
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/vmalloc.h b/arch/arm/mach-xilinx/include/mach/vmalloc.h
new file mode 100644
index 0000000..aba20a3
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
+/* arch/arm/mach-xilinx/include/mach/vmalloc.h
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_VMALLOC_H__
+#define __MACH_VMALLOC_H__
+
+#define VMALLOC_END       0xE0000000UL
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/xilinx_soc.h b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
new file mode 100644
index 0000000..d01cde1
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
@@ -0,0 +1,46 @@
+/* arch/arm/mach-xilinx/include/mach/xilinx_soc.h
+ *
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_XILINX_SOC_H__
+#define __MACH_XILINX_SOC_H__
+
+/* For now, all mappings are flat (physical = virtual)
+ */
+#define UART0_PHYS			0xE0000000
+#define UART0_VIRT			UART0_PHYS
+
+#define TTC0_PHYS			0xF8001000
+#define TTC0_VIRT			TTC0_PHYS
+
+#define PL310_L2CC_PHYS			0xF8F02000
+#define PL310_L2CC_VIRT			PL310_L2CC_PHYS
+
+#define SCU_PERIPH_PHYS			0xF8F00000
+#define SCU_PERIPH_VIRT			SCU_PERIPH_PHYS
+
+/* The following are intended for the devices that are mapped early */
+
+#define TTC0_BASE			IOMEM(TTC0_VIRT)
+#define SCU_PERIPH_BASE			IOMEM(SCU_PERIPH_VIRT)
+#define SCU_GIC_CPU_BASE		(SCU_PERIPH_BASE + 0x100)
+#define SCU_GIC_DIST_BASE		(SCU_PERIPH_BASE + 0x1000)
+#define PL310_L2CC_BASE			IOMEM(PL310_L2CC_VIRT)
+
+/*
+ * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical
+ */
+#define LL_UART_PADDR	UART0_PHYS
+#define LL_UART_VADDR	UART0_VIRT
+
+#endif
-- 
1.6.2.1



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[PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros

[Jamie Iles]

Hi John,

A few more nitpicks, but looking good now!

Jamie

On Wed, Feb 16, 2011 at 09:11:55AM -0700, John Linn wrote:
> These are the minimum needed to build the kernel for the new platform.
> 
> Signed-off-by: John Linn <john.linn@xilinx.com>
> ---
> 
> V3 Changes
> 
> Updates based on Russell Kings' comments
> 	Changed headers to update the license info and remove
> 	the address
> 
> 	Updated the constant to use UL in vmalloc.h
> 
> V2 Changes
> 
> Updates based on Russell King's comments	
> 	moved to using entry-macro-gic.S
> 	moved stuff from hardware.h to xilinx_soc.h 
> 	added IOMEM() in io.h to help with typing
> 	Minor updates to IO_SPACE_LIMIT and __io()
> 	Updated addresses to be clear with seperate virtual
> 		and physical addresses
> 
>  arch/arm/mach-xilinx/include/mach/clkdev.h      |   33 ++++++++++++++++
>  arch/arm/mach-xilinx/include/mach/debug-macro.S |   36 +++++++++++++++++
>  arch/arm/mach-xilinx/include/mach/entry-macro.S |   30 ++++++++++++++
>  arch/arm/mach-xilinx/include/mach/hardware.h    |   18 +++++++++
>  arch/arm/mach-xilinx/include/mach/io.h          |   33 ++++++++++++++++
>  arch/arm/mach-xilinx/include/mach/irqs.h        |   29 ++++++++++++++
>  arch/arm/mach-xilinx/include/mach/memory.h      |   23 +++++++++++
>  arch/arm/mach-xilinx/include/mach/system.h      |   28 +++++++++++++
>  arch/arm/mach-xilinx/include/mach/timex.h       |   24 ++++++++++++
>  arch/arm/mach-xilinx/include/mach/uart.h        |   31 +++++++++++++++
>  arch/arm/mach-xilinx/include/mach/uncompress.h  |   47 +++++++++++++++++++++++
>  arch/arm/mach-xilinx/include/mach/vmalloc.h     |   20 ++++++++++
>  arch/arm/mach-xilinx/include/mach/xilinx_soc.h  |   46 ++++++++++++++++++++++
>  13 files changed, 398 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-xilinx/include/mach/clkdev.h
>  create mode 100644 arch/arm/mach-xilinx/include/mach/debug-macro.S
>  create mode 100644 arch/arm/mach-xilinx/include/mach/entry-macro.S
>  create mode 100644 arch/arm/mach-xilinx/include/mach/hardware.h
>  create mode 100644 arch/arm/mach-xilinx/include/mach/io.h
>  create mode 100644 arch/arm/mach-xilinx/include/mach/irqs.h
>  create mode 100644 arch/arm/mach-xilinx/include/mach/memory.h
>  create mode 100644 arch/arm/mach-xilinx/include/mach/system.h
>  create mode 100644 arch/arm/mach-xilinx/include/mach/timex.h
>  create mode 100644 arch/arm/mach-xilinx/include/mach/uart.h
>  create mode 100644 arch/arm/mach-xilinx/include/mach/uncompress.h
>  create mode 100644 arch/arm/mach-xilinx/include/mach/vmalloc.h
>  create mode 100644 arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> 
> diff --git a/arch/arm/mach-xilinx/include/mach/clkdev.h b/arch/arm/mach-xilinx/include/mach/clkdev.h
> new file mode 100644
> index 0000000..5dd1453
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/clkdev.h
> @@ -0,0 +1,33 @@
> +/*
> + * arch/arm/mach-xilinx/include/mach/clkdev.h
> + *
> + *  Copyright (C) 2011 Xilinx, Inc.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef __MACH_CLKDEV_H__
> +#define __MACH_CLKDEV_H__
> +
> +struct clk {
> +	unsigned long rate;
> +};
> +
> +static inline int __clk_get(struct clk *clk)
> +{
> +	return 1;
> +}
> +
> +static inline void __clk_put(struct clk *clk)
> +{
> +}
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/debug-macro.S b/arch/arm/mach-xilinx/include/mach/debug-macro.S
> new file mode 100644
> index 0000000..30d3d3d
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/debug-macro.S
> @@ -0,0 +1,36 @@
> +/* arch/arm/mach-xilinx/include/mach/debug-macro.S
> + *
> + * Debugging macro include header
> + *
> + *  Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <mach/xilinx_soc.h>
> +#include <mach/uart.h>
> +
> +		.macro	addruart, rp, rv
> +		ldr	\rp, =LL_UART_PADDR	@ physical
> +		ldr	\rv, =LL_UART_VADDR	@ virtual
> +		.endm
> +
> +		.macro	senduart,rd,rx
> +		str	\rd, [\rx, #UART_FIFO_OFFSET]	@ TXDATA
> +		.endm
> +
> +		.macro	waituart,rd,rx
> +		.endm
> +
> +		.macro	busyuart,rd,rx
> +1002:		ldr	\rd, [\rx, #UART_SR_OFFSET]	@ get status register
> +		tst	\rd, #UART_SR_TXFULL		@
> +		bne	1002b			@ wait if FIFO is full
> +		.endm
> diff --git a/arch/arm/mach-xilinx/include/mach/entry-macro.S b/arch/arm/mach-xilinx/include/mach/entry-macro.S
> new file mode 100644
> index 0000000..11a2866
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/entry-macro.S
> @@ -0,0 +1,30 @@
> +/*
> + * arch/arm/mach-xilinx/include/mach/entry-macro.S
> + *
> + * Low-level IRQ helper macros
> + *
> + *  Copyright (C) 2011 Xilinx
> + *
> + * based on arch/plat-mxc/include/mach/entry-macro.S
> + *
> + *  Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
> + *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <mach/hardware.h>
> +#include <asm/hardware/entry-macro-gic.S>
> +
> +                .macro  disable_fiq
> +                .endm
> +
> +                .macro  arch_ret_to_user, tmp1, tmp2
> +                .endm
> diff --git a/arch/arm/mach-xilinx/include/mach/hardware.h b/arch/arm/mach-xilinx/include/mach/hardware.h
> new file mode 100644
> index 0000000..f9685c4
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/hardware.h
> @@ -0,0 +1,18 @@
> +/* arch/arm/mach-xilinx/include/mach/hardware.h
> + *
> + *  Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_HARDWARE_H__
> +#define __MACH_HARDWARE_H__
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/io.h b/arch/arm/mach-xilinx/include/mach/io.h
> new file mode 100644
> index 0000000..ef69e65
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/io.h
> @@ -0,0 +1,33 @@
> +/* arch/arm/mach-xilinx/include/mach/io.h
> + *
> + *  Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_IO_H__
> +#define __MACH_IO_H__
> +
> +/* Allow IO space to be anywhere in the memory */
> +
> +#define IO_SPACE_LIMIT 0xffff
> +
> +/* IO address mapping macros, nothing special at this time but required */
> +
> +#ifdef __ASSEMBLER__
> +#define IOMEM(x)		(x)
> +#else
> +#define IOMEM(x)		((void __force __iomem *)(x))
> +#endif
> +
> +#define __io(a)			__typesafe_io(a)
> +#define __mem_pci(a)		(a)
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/irqs.h b/arch/arm/mach-xilinx/include/mach/irqs.h
> new file mode 100644
> index 0000000..47a8162
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/irqs.h
> @@ -0,0 +1,29 @@
> +/* arch/arm/mach-xilinx/include/mach/irqs.h
> + *
> + *  Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_IRQS_H
> +#define __MACH_IRQS_H
> +
> +#define ARCH_NR_GPIOS	118
> +#define NR_IRQS		(128 + ARCH_NR_GPIOS)
> +
> +/*
> + * GIC Interrupts
> + */
> +
> +#define IRQ_GIC_SPI_START	32
> +#define IRQ_TIMERCOUNTER0	42
> +#define IRQ_UART0		59
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/memory.h b/arch/arm/mach-xilinx/include/mach/memory.h
> new file mode 100644
> index 0000000..c200486
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/memory.h
> @@ -0,0 +1,23 @@
> +/* arch/arm/mach-xilinx/include/mach/memory.h
> + *
> + *  Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_MEMORY_H__
> +#define __MACH_MEMORY_H__
> +
> +#include <mach/hardware.h>
> +
> +#define PHYS_OFFSET             0x0

This should be PLAT_PHYS_OFFSET and could do with being surrounded with 
UL() e.g.

#define PLAT_PHYS_OFFSET	UL(0x00000000)

> +#define MEM_SIZE		SZ_256M
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/system.h b/arch/arm/mach-xilinx/include/mach/system.h
> new file mode 100644
> index 0000000..e8514a0
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/system.h
> @@ -0,0 +1,28 @@
> +/* arch/arm/mach-xilinx/include/mach/system.h
> + *
> + *  Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_SYSTEM_H__
> +#define __MACH_SYSTEM_H__
> +
> +static inline void arch_idle(void)
> +{
> +	cpu_do_idle();
> +}
> +
> +static inline void arch_reset(char mode, const char *cmd)
> +{
> +	/* Add architecture specific reset processing here */

I think you can add cpu_reset(0) in here to try a soft reset by jumping 
to the reset vector.  This should give you some reset functionality.

> +}
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/timex.h b/arch/arm/mach-xilinx/include/mach/timex.h
> new file mode 100644
> index 0000000..6765e15
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/timex.h
> @@ -0,0 +1,24 @@
> +/* arch/arm/mach-xilinx/include/mach/timex.h
> + *
> + *  Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_TIMEX_H__
> +#define __MACH_TIMEX_H__
> +
> +#include <mach/hardware.h>

I don't think you need mach/hardware.h included in here.

> +
> +#define PERIPHERAL_CLOCK_RATE	2500000
> +
> +#define CLOCK_TICK_RATE	(PERIPHERAL_CLOCK_RATE / 32)
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/uart.h b/arch/arm/mach-xilinx/include/mach/uart.h
> new file mode 100644
> index 0000000..20a10d7
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/uart.h
> @@ -0,0 +1,31 @@
> +/* arch/arm/mach-xilinx/include/mach/uart.h
> + *
> + *  Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_UART_H__
> +#define __MACH_UART_H__
> +
> +#define UART_CR_OFFSET          0x00  /* Control Register [8:0] */
> +#define UART_SR_OFFSET          0x2C  /* Channel Status [11:0] */
> +#define UART_FIFO_OFFSET        0x30  /* FIFO [15:0] or [7:0] */
> +
> +#define UART_SR_TXFULL		0x00000010	/* TX FIFO full */
> +#define UART_SR_TXEMPTY		0x00000008	/* TX FIFO empty */
> +
> +#define UART_FIFO_WRITE(base, value) \
> +	(*(volatile unsigned int *)((base) + UART_FIFO_OFFSET) = (value))
> +
> +#define UART_STATUS(base) \
> +	(*(volatile unsigned int *)((base) + UART_SR_OFFSET))

You could probably make these static inline functions in the header and 
use __raw_{readl,writel}() to make this a little cleaner.

> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/uncompress.h b/arch/arm/mach-xilinx/include/mach/uncompress.h
> new file mode 100644
> index 0000000..b7a5110
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/uncompress.h
> @@ -0,0 +1,47 @@
> +/* arch/arm/mach-xilinx/include/mach/uncompress.h
> + *
> + *  Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_UNCOMPRESS_H__
> +#define __MACH_UNCOMPRESS_H__
> +
> +#include <mach/xilinx_soc.h>
> +#include <mach/uart.h>
> +
> +void arch_decomp_setup(void)
> +{
> +}
> +
> +static inline void flush(void)
> +{
> +	/*
> +	 * Wait while the FIFO is not empty
> +	 */
> +	while (!(UART_STATUS(LL_UART_PADDR) & UART_SR_TXEMPTY))
> +		;
> +}
> +
> +#define arch_decomp_wdog()
> +
> +static void putc(char ch)
> +{
> +	/*
> +	 * Wait for room in the FIFO, then write the char into the FIFO
> +	 */
> +	while (UART_STATUS(LL_UART_PADDR) & UART_SR_TXFULL)
> +		;

It might be worth adding a barrier() call to these loops to be explicit 
about the volatility.

> +
> +	UART_FIFO_WRITE(LL_UART_PADDR, ch);
> +}
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/vmalloc.h b/arch/arm/mach-xilinx/include/mach/vmalloc.h
> new file mode 100644
> index 0000000..aba20a3
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/vmalloc.h
> @@ -0,0 +1,20 @@
> +/* arch/arm/mach-xilinx/include/mach/vmalloc.h
> + *
> + *  Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_VMALLOC_H__
> +#define __MACH_VMALLOC_H__
> +
> +#define VMALLOC_END       0xE0000000UL
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/xilinx_soc.h b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> new file mode 100644
> index 0000000..d01cde1
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> @@ -0,0 +1,46 @@
> +/* arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> + *
> + *  Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_XILINX_SOC_H__
> +#define __MACH_XILINX_SOC_H__
> +
> +/* For now, all mappings are flat (physical = virtual)
> + */
> +#define UART0_PHYS			0xE0000000
> +#define UART0_VIRT			UART0_PHYS
> +
> +#define TTC0_PHYS			0xF8001000
> +#define TTC0_VIRT			TTC0_PHYS
> +
> +#define PL310_L2CC_PHYS			0xF8F02000
> +#define PL310_L2CC_VIRT			PL310_L2CC_PHYS
> +
> +#define SCU_PERIPH_PHYS			0xF8F00000
> +#define SCU_PERIPH_VIRT			SCU_PERIPH_PHYS
> +
> +/* The following are intended for the devices that are mapped early */
> +
> +#define TTC0_BASE			IOMEM(TTC0_VIRT)
> +#define SCU_PERIPH_BASE			IOMEM(SCU_PERIPH_VIRT)
> +#define SCU_GIC_CPU_BASE		(SCU_PERIPH_BASE + 0x100)
> +#define SCU_GIC_DIST_BASE		(SCU_PERIPH_BASE + 0x1000)
> +#define PL310_L2CC_BASE			IOMEM(PL310_L2CC_VIRT)
> +
> +/*
> + * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical
> + */
> +#define LL_UART_PADDR	UART0_PHYS
> +#define LL_UART_VADDR	UART0_VIRT
> +
> +#endif
> -- 
> 1.6.2.1
> 
> 
> 
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> 
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[PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros

[John Linn]

> -----Original Message-----
> From: Jamie Iles [mailto:jamie at jamieiles.com]
> Sent: Thursday, February 17, 2011 3:01 AM
> To: John Linn
> Cc: linux-arm-kernel at lists.infradead.org;
linux-kernel at vger.kernel.org; linux at arm.linux.org.uk;
> catalin.marinas at arm.com; glikely at secretlab.ca; arnd at arndb.de
> Subject: Re: [PATCH V3 3/4] ARM: Xilinx: base header files and
assembly macros
> 
> Hi John,
> 
> A few more nitpicks, but looking good now!
> 
> Jamie
> 
> On Wed, Feb 16, 2011 at 09:11:55AM -0700, John Linn wrote:
> > These are the minimum needed to build the kernel for the new
platform.
> >
> > Signed-off-by: John Linn <john.linn@xilinx.com>
> > ---
> >
> > V3 Changes
> >
> > Updates based on Russell Kings' comments
> > 	Changed headers to update the license info and remove
> > 	the address
> >
> > 	Updated the constant to use UL in vmalloc.h
> >
> > V2 Changes
> >
> > Updates based on Russell King's comments
> > 	moved to using entry-macro-gic.S
> > 	moved stuff from hardware.h to xilinx_soc.h
> > 	added IOMEM() in io.h to help with typing
> > 	Minor updates to IO_SPACE_LIMIT and __io()
> > 	Updated addresses to be clear with seperate virtual
> > 		and physical addresses
> >
> >  arch/arm/mach-xilinx/include/mach/clkdev.h      |   33
++++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/debug-macro.S |   36
+++++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/entry-macro.S |   30
++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/hardware.h    |   18 +++++++++
> >  arch/arm/mach-xilinx/include/mach/io.h          |   33
++++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/irqs.h        |   29
++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/memory.h      |   23 +++++++++++
> >  arch/arm/mach-xilinx/include/mach/system.h      |   28
+++++++++++++
> >  arch/arm/mach-xilinx/include/mach/timex.h       |   24 ++++++++++++
> >  arch/arm/mach-xilinx/include/mach/uart.h        |   31
+++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/uncompress.h  |   47
+++++++++++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/vmalloc.h     |   20 ++++++++++
> >  arch/arm/mach-xilinx/include/mach/xilinx_soc.h  |   46
++++++++++++++++++++++
> >  13 files changed, 398 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/clkdev.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/debug-macro.S
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/entry-macro.S
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/hardware.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/io.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/irqs.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/memory.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/system.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/timex.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/uart.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/uncompress.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/vmalloc.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> >
> > diff --git a/arch/arm/mach-xilinx/include/mach/clkdev.h
b/arch/arm/mach-xilinx/include/mach/clkdev.h
> > new file mode 100644
> > index 0000000..5dd1453
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/clkdev.h
> > @@ -0,0 +1,33 @@
> > +/*
> > + * arch/arm/mach-xilinx/include/mach/clkdev.h
> > + *
> > + *  Copyright (C) 2011 Xilinx, Inc.
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + */
> > +
> > +#ifndef __MACH_CLKDEV_H__
> > +#define __MACH_CLKDEV_H__
> > +
> > +struct clk {
> > +	unsigned long rate;
> > +};
> > +
> > +static inline int __clk_get(struct clk *clk)
> > +{
> > +	return 1;
> > +}
> > +
> > +static inline void __clk_put(struct clk *clk)
> > +{
> > +}
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/debug-macro.S
b/arch/arm/mach-
> xilinx/include/mach/debug-macro.S
> > new file mode 100644
> > index 0000000..30d3d3d
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/debug-macro.S
> > @@ -0,0 +1,36 @@
> > +/* arch/arm/mach-xilinx/include/mach/debug-macro.S
> > + *
> > + * Debugging macro include header
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <mach/xilinx_soc.h>
> > +#include <mach/uart.h>
> > +
> > +		.macro	addruart, rp, rv
> > +		ldr	\rp, =LL_UART_PADDR	@ physical
> > +		ldr	\rv, =LL_UART_VADDR	@ virtual
> > +		.endm
> > +
> > +		.macro	senduart,rd,rx
> > +		str	\rd, [\rx, #UART_FIFO_OFFSET]	@ TXDATA
> > +		.endm
> > +
> > +		.macro	waituart,rd,rx
> > +		.endm
> > +
> > +		.macro	busyuart,rd,rx
> > +1002:		ldr	\rd, [\rx, #UART_SR_OFFSET]	@ get
status register
> > +		tst	\rd, #UART_SR_TXFULL		@
> > +		bne	1002b			@ wait if FIFO is full
> > +		.endm
> > diff --git a/arch/arm/mach-xilinx/include/mach/entry-macro.S
b/arch/arm/mach-
> xilinx/include/mach/entry-macro.S
> > new file mode 100644
> > index 0000000..11a2866
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/entry-macro.S
> > @@ -0,0 +1,30 @@
> > +/*
> > + * arch/arm/mach-xilinx/include/mach/entry-macro.S
> > + *
> > + * Low-level IRQ helper macros
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * based on arch/plat-mxc/include/mach/entry-macro.S
> > + *
> > + *  Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
> > + *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights
Reserved.
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <mach/hardware.h>
> > +#include <asm/hardware/entry-macro-gic.S>
> > +
> > +                .macro  disable_fiq
> > +                .endm
> > +
> > +                .macro  arch_ret_to_user, tmp1, tmp2
> > +                .endm
> > diff --git a/arch/arm/mach-xilinx/include/mach/hardware.h
b/arch/arm/mach-
> xilinx/include/mach/hardware.h
> > new file mode 100644
> > index 0000000..f9685c4
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/hardware.h
> > @@ -0,0 +1,18 @@
> > +/* arch/arm/mach-xilinx/include/mach/hardware.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_HARDWARE_H__
> > +#define __MACH_HARDWARE_H__
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/io.h
b/arch/arm/mach-xilinx/include/mach/io.h
> > new file mode 100644
> > index 0000000..ef69e65
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/io.h
> > @@ -0,0 +1,33 @@
> > +/* arch/arm/mach-xilinx/include/mach/io.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_IO_H__
> > +#define __MACH_IO_H__
> > +
> > +/* Allow IO space to be anywhere in the memory */
> > +
> > +#define IO_SPACE_LIMIT 0xffff
> > +
> > +/* IO address mapping macros, nothing special at this time but
required */
> > +
> > +#ifdef __ASSEMBLER__
> > +#define IOMEM(x)		(x)
> > +#else
> > +#define IOMEM(x)		((void __force __iomem *)(x))
> > +#endif
> > +
> > +#define __io(a)			__typesafe_io(a)
> > +#define __mem_pci(a)		(a)
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/irqs.h
b/arch/arm/mach-xilinx/include/mach/irqs.h
> > new file mode 100644
> > index 0000000..47a8162
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/irqs.h
> > @@ -0,0 +1,29 @@
> > +/* arch/arm/mach-xilinx/include/mach/irqs.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_IRQS_H
> > +#define __MACH_IRQS_H
> > +
> > +#define ARCH_NR_GPIOS	118
> > +#define NR_IRQS		(128 + ARCH_NR_GPIOS)
> > +
> > +/*
> > + * GIC Interrupts
> > + */
> > +
> > +#define IRQ_GIC_SPI_START	32
> > +#define IRQ_TIMERCOUNTER0	42
> > +#define IRQ_UART0		59
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/memory.h
b/arch/arm/mach-xilinx/include/mach/memory.h
> > new file mode 100644
> > index 0000000..c200486
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/memory.h
> > @@ -0,0 +1,23 @@
> > +/* arch/arm/mach-xilinx/include/mach/memory.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_MEMORY_H__
> > +#define __MACH_MEMORY_H__
> > +
> > +#include <mach/hardware.h>
> > +
> > +#define PHYS_OFFSET             0x0
> 
> This should be PLAT_PHYS_OFFSET and could do with being surrounded
with
> UL() e.g.
> 
> #define PLAT_PHYS_OFFSET	UL(0x00000000)

I think Russell mentioned it was changing in the future but I didn't
know when to do it.

Easy enough.

> 
> > +#define MEM_SIZE		SZ_256M
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/system.h
b/arch/arm/mach-xilinx/include/mach/system.h
> > new file mode 100644
> > index 0000000..e8514a0
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/system.h
> > @@ -0,0 +1,28 @@
> > +/* arch/arm/mach-xilinx/include/mach/system.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_SYSTEM_H__
> > +#define __MACH_SYSTEM_H__
> > +
> > +static inline void arch_idle(void)
> > +{
> > +	cpu_do_idle();
> > +}
> > +
> > +static inline void arch_reset(char mode, const char *cmd)
> > +{
> > +	/* Add architecture specific reset processing here */
> 
> I think you can add cpu_reset(0) in here to try a soft reset by
jumping
> to the reset vector.  This should give you some reset functionality.
> 

Will look at that.  I think it requires a lot more than that for our
platform to clean up.

> > +}
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/timex.h
b/arch/arm/mach-xilinx/include/mach/timex.h
> > new file mode 100644
> > index 0000000..6765e15
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/timex.h
> > @@ -0,0 +1,24 @@
> > +/* arch/arm/mach-xilinx/include/mach/timex.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_TIMEX_H__
> > +#define __MACH_TIMEX_H__
> > +
> > +#include <mach/hardware.h>
> 
> I don't think you need mach/hardware.h included in here.
> 

Looks like that's true.  I should have caught that.

> > +
> > +#define PERIPHERAL_CLOCK_RATE	2500000
> > +
> > +#define CLOCK_TICK_RATE	(PERIPHERAL_CLOCK_RATE / 32)
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/uart.h
b/arch/arm/mach-xilinx/include/mach/uart.h
> > new file mode 100644
> > index 0000000..20a10d7
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/uart.h
> > @@ -0,0 +1,31 @@
> > +/* arch/arm/mach-xilinx/include/mach/uart.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_UART_H__
> > +#define __MACH_UART_H__
> > +
> > +#define UART_CR_OFFSET          0x00  /* Control Register [8:0] */
> > +#define UART_SR_OFFSET          0x2C  /* Channel Status [11:0] */
> > +#define UART_FIFO_OFFSET        0x30  /* FIFO [15:0] or [7:0] */
> > +
> > +#define UART_SR_TXFULL		0x00000010	/* TX FIFO full
*/
> > +#define UART_SR_TXEMPTY		0x00000008	/* TX FIFO empty
*/
> > +
> > +#define UART_FIFO_WRITE(base, value) \
> > +	(*(volatile unsigned int *)((base) + UART_FIFO_OFFSET) =
(value))
> > +
> > +#define UART_STATUS(base) \
> > +	(*(volatile unsigned int *)((base) + UART_SR_OFFSET))
> 
> You could probably make these static inline functions in the header
and
> use __raw_{readl,writel}() to make this a little cleaner.
> 

I had considered that, but it wasn't clear to me at the time what the
compressor could use or not.

I'll give it a try as I agree that's cleaner.

> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/uncompress.h
b/arch/arm/mach-
> xilinx/include/mach/uncompress.h
> > new file mode 100644
> > index 0000000..b7a5110
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/uncompress.h
> > @@ -0,0 +1,47 @@
> > +/* arch/arm/mach-xilinx/include/mach/uncompress.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_UNCOMPRESS_H__
> > +#define __MACH_UNCOMPRESS_H__
> > +
> > +#include <mach/xilinx_soc.h>
> > +#include <mach/uart.h>
> > +
> > +void arch_decomp_setup(void)
> > +{
> > +}
> > +
> > +static inline void flush(void)
> > +{
> > +	/*
> > +	 * Wait while the FIFO is not empty
> > +	 */
> > +	while (!(UART_STATUS(LL_UART_PADDR) & UART_SR_TXEMPTY))
> > +		;
> > +}
> > +
> > +#define arch_decomp_wdog()
> > +
> > +static void putc(char ch)
> > +{
> > +	/*
> > +	 * Wait for room in the FIFO, then write the char into the FIFO
> > +	 */
> > +	while (UART_STATUS(LL_UART_PADDR) & UART_SR_TXFULL)
> > +		;
> 
> It might be worth adding a barrier() call to these loops to be
explicit
> about the volatility.

OK

I appreciate all your help and time to review, both you and Russell. I'm
learning a lot and it's much
cleaner too.

I hope there's an ack in the near future :)

Thanks
John

> 
> > +
> > +	UART_FIFO_WRITE(LL_UART_PADDR, ch);
> > +}
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/vmalloc.h
b/arch/arm/mach-
> xilinx/include/mach/vmalloc.h
> > new file mode 100644
> > index 0000000..aba20a3
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/vmalloc.h
> > @@ -0,0 +1,20 @@
> > +/* arch/arm/mach-xilinx/include/mach/vmalloc.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_VMALLOC_H__
> > +#define __MACH_VMALLOC_H__
> > +
> > +#define VMALLOC_END       0xE0000000UL
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
b/arch/arm/mach-
> xilinx/include/mach/xilinx_soc.h
> > new file mode 100644
> > index 0000000..d01cde1
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> > @@ -0,0 +1,46 @@
> > +/* arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_XILINX_SOC_H__
> > +#define __MACH_XILINX_SOC_H__
> > +
> > +/* For now, all mappings are flat (physical = virtual)
> > + */
> > +#define UART0_PHYS			0xE0000000
> > +#define UART0_VIRT			UART0_PHYS
> > +
> > +#define TTC0_PHYS			0xF8001000
> > +#define TTC0_VIRT			TTC0_PHYS
> > +
> > +#define PL310_L2CC_PHYS			0xF8F02000
> > +#define PL310_L2CC_VIRT			PL310_L2CC_PHYS
> > +
> > +#define SCU_PERIPH_PHYS			0xF8F00000
> > +#define SCU_PERIPH_VIRT			SCU_PERIPH_PHYS
> > +
> > +/* The following are intended for the devices that are mapped early
*/
> > +
> > +#define TTC0_BASE			IOMEM(TTC0_VIRT)
> > +#define SCU_PERIPH_BASE			IOMEM(SCU_PERIPH_VIRT)
> > +#define SCU_GIC_CPU_BASE		(SCU_PERIPH_BASE + 0x100)
> > +#define SCU_GIC_DIST_BASE		(SCU_PERIPH_BASE + 0x1000)
> > +#define PL310_L2CC_BASE			IOMEM(PL310_L2CC_VIRT)
> > +
> > +/*
> > + * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical
> > + */
> > +#define LL_UART_PADDR	UART0_PHYS
> > +#define LL_UART_VADDR	UART0_VIRT
> > +
> > +#endif
> > --
> > 1.6.2.1
> >
> >
> >
> > This email and any attachments are intended for the sole use of the
named recipient(s) and
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> >
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe
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This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

[PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros

[Arnd Bergmann]

On Thursday 17 February 2011, John Linn wrote:
> > > +
> > > +#define UART_FIFO_WRITE(base, value) \
> > > +   (*(volatile unsigned int *)((base) + UART_FIFO_OFFSET) =
> (value))
> > > +
> > > +#define UART_STATUS(base) \
> > > +   (*(volatile unsigned int *)((base) + UART_SR_OFFSET))
> > 
> > You could probably make these static inline functions in the header
> and
> > use __raw_{readl,writel}() to make this a little cleaner.
> > 
> 
> I had considered that, but it wasn't clear to me at the time what the
> compressor could use or not.
> 
> I'll give it a try as I agree that's cleaner.

Actually, for correctness you should use the regular readl/writel, not
the __raw_ versions, which can result in reordered or partial accesses
on the bus.

	Arnd

[PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros

[Russell King - ARM Linux]

On Thu, Feb 17, 2011 at 03:41:11PM +0100, Arnd Bergmann wrote:
> On Thursday 17 February 2011, John Linn wrote:
> > > > +
> > > > +#define UART_FIFO_WRITE(base, value) \
> > > > +   (*(volatile unsigned int *)((base) + UART_FIFO_OFFSET) =
> > (value))
> > > > +
> > > > +#define UART_STATUS(base) \
> > > > +   (*(volatile unsigned int *)((base) + UART_SR_OFFSET))
> > > 
> > > You could probably make these static inline functions in the header
> > and
> > > use __raw_{readl,writel}() to make this a little cleaner.
> > > 
> > 
> > I had considered that, but it wasn't clear to me at the time what the
> > compressor could use or not.
> > 
> > I'll give it a try as I agree that's cleaner.
> 
> Actually, for correctness you should use the regular readl/writel, not
> the __raw_ versions, which can result in reordered or partial accesses
> on the bus.

Not in the decompressor.  readl/writel are unsupported there - the
decompressor doesn't have the L2 cache support code and so the barriers
necessary for readl/writel cause link errors.

[PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros

[Arnd Bergmann]

On Thursday 17 February 2011, Russell King - ARM Linux wrote:
> > Actually, for correctness you should use the regular readl/writel, not
> > the __raw_ versions, which can result in reordered or partial accesses
> > on the bus.
> 
> Not in the decompressor.  readl/writel are unsupported there - the
> decompressor doesn't have the L2 cache support code and so the barriers
> necessary for readl/writel cause link errors.

Ah right, of course. Sorry for the confusion.

	Arnd

[PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros

[Stephen Boyd]

On 02/17/2011 02:01 AM, Jamie Iles wrote:
>> +
>> +static void putc(char ch)
>> +{
>> +	/*
>> +	 * Wait for room in the FIFO, then write the char into the FIFO
>> +	 */
>> +	while (UART_STATUS(LL_UART_PADDR) & UART_SR_TXFULL)
>> +		;
>
> It might be worth adding a barrier() call to these loops to be explicit 
> about the volatility.

I think you want cpu_relax() then.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros

[John Linn]

> -----Original Message-----
> From: Stephen Boyd [mailto:sboyd at codeaurora.org]
> Sent: Thursday, February 17, 2011 2:58 PM
> To: Jamie Iles
> Cc: John Linn; linux at arm.linux.org.uk; arnd at arndb.de;
catalin.marinas at arm.com; linux-
> kernel at vger.kernel.org; glikely at secretlab.ca;
linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH V3 3/4] ARM: Xilinx: base header files and
assembly macros
> 
> On 02/17/2011 02:01 AM, Jamie Iles wrote:
> >> +
> >> +static void putc(char ch)
> >> +{
> >> +	/*
> >> +	 * Wait for room in the FIFO, then write the char into the FIFO
> >> +	 */
> >> +	while (UART_STATUS(LL_UART_PADDR) & UART_SR_TXFULL)
> >> +		;
> >
> > It might be worth adding a barrier() call to these loops to be
explicit
> > about the volatility.
> 
> I think you want cpu_relax() then.

Thanks Stephen.

> 
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum.
> 


This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

[PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros

[John Linn]

> -----Original Message-----
> From: Jamie Iles [mailto:jamie at jamieiles.com]
> Sent: Thursday, February 17, 2011 3:01 AM
> To: John Linn
> Cc: linux-arm-kernel at lists.infradead.org;
linux-kernel at vger.kernel.org; linux at arm.linux.org.uk;
> catalin.marinas at arm.com; glikely at secretlab.ca; arnd at arndb.de
> Subject: Re: [PATCH V3 3/4] ARM: Xilinx: base header files and
assembly macros
> 
> Hi John,
> 
> A few more nitpicks, but looking good now!
> 
> Jamie
> 
> On Wed, Feb 16, 2011 at 09:11:55AM -0700, John Linn wrote:
> > These are the minimum needed to build the kernel for the new
platform.
> >
> > Signed-off-by: John Linn <john.linn@xilinx.com>
> > ---
> >
> > V3 Changes
> >
> > Updates based on Russell Kings' comments
> > 	Changed headers to update the license info and remove
> > 	the address
> >
> > 	Updated the constant to use UL in vmalloc.h
> >
> > V2 Changes
> >
> > Updates based on Russell King's comments
> > 	moved to using entry-macro-gic.S
> > 	moved stuff from hardware.h to xilinx_soc.h
> > 	added IOMEM() in io.h to help with typing
> > 	Minor updates to IO_SPACE_LIMIT and __io()
> > 	Updated addresses to be clear with seperate virtual
> > 		and physical addresses
> >
> >  arch/arm/mach-xilinx/include/mach/clkdev.h      |   33
++++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/debug-macro.S |   36
+++++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/entry-macro.S |   30
++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/hardware.h    |   18 +++++++++
> >  arch/arm/mach-xilinx/include/mach/io.h          |   33
++++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/irqs.h        |   29
++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/memory.h      |   23 +++++++++++
> >  arch/arm/mach-xilinx/include/mach/system.h      |   28
+++++++++++++
> >  arch/arm/mach-xilinx/include/mach/timex.h       |   24 ++++++++++++
> >  arch/arm/mach-xilinx/include/mach/uart.h        |   31
+++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/uncompress.h  |   47
+++++++++++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/vmalloc.h     |   20 ++++++++++
> >  arch/arm/mach-xilinx/include/mach/xilinx_soc.h  |   46
++++++++++++++++++++++
> >  13 files changed, 398 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/clkdev.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/debug-macro.S
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/entry-macro.S
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/hardware.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/io.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/irqs.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/memory.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/system.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/timex.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/uart.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/uncompress.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/vmalloc.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> >
> > diff --git a/arch/arm/mach-xilinx/include/mach/clkdev.h
b/arch/arm/mach-xilinx/include/mach/clkdev.h
> > new file mode 100644
> > index 0000000..5dd1453
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/clkdev.h
> > @@ -0,0 +1,33 @@
> > +/*
> > + * arch/arm/mach-xilinx/include/mach/clkdev.h
> > + *
> > + *  Copyright (C) 2011 Xilinx, Inc.
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + */
> > +
> > +#ifndef __MACH_CLKDEV_H__
> > +#define __MACH_CLKDEV_H__
> > +
> > +struct clk {
> > +	unsigned long rate;
> > +};
> > +
> > +static inline int __clk_get(struct clk *clk)
> > +{
> > +	return 1;
> > +}
> > +
> > +static inline void __clk_put(struct clk *clk)
> > +{
> > +}
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/debug-macro.S
b/arch/arm/mach-
> xilinx/include/mach/debug-macro.S
> > new file mode 100644
> > index 0000000..30d3d3d
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/debug-macro.S
> > @@ -0,0 +1,36 @@
> > +/* arch/arm/mach-xilinx/include/mach/debug-macro.S
> > + *
> > + * Debugging macro include header
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <mach/xilinx_soc.h>
> > +#include <mach/uart.h>
> > +
> > +		.macro	addruart, rp, rv
> > +		ldr	\rp, =LL_UART_PADDR	@ physical
> > +		ldr	\rv, =LL_UART_VADDR	@ virtual
> > +		.endm
> > +
> > +		.macro	senduart,rd,rx
> > +		str	\rd, [\rx, #UART_FIFO_OFFSET]	@ TXDATA
> > +		.endm
> > +
> > +		.macro	waituart,rd,rx
> > +		.endm
> > +
> > +		.macro	busyuart,rd,rx
> > +1002:		ldr	\rd, [\rx, #UART_SR_OFFSET]	@ get
status register
> > +		tst	\rd, #UART_SR_TXFULL		@
> > +		bne	1002b			@ wait if FIFO is full
> > +		.endm
> > diff --git a/arch/arm/mach-xilinx/include/mach/entry-macro.S
b/arch/arm/mach-
> xilinx/include/mach/entry-macro.S
> > new file mode 100644
> > index 0000000..11a2866
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/entry-macro.S
> > @@ -0,0 +1,30 @@
> > +/*
> > + * arch/arm/mach-xilinx/include/mach/entry-macro.S
> > + *
> > + * Low-level IRQ helper macros
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * based on arch/plat-mxc/include/mach/entry-macro.S
> > + *
> > + *  Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
> > + *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights
Reserved.
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <mach/hardware.h>
> > +#include <asm/hardware/entry-macro-gic.S>
> > +
> > +                .macro  disable_fiq
> > +                .endm
> > +
> > +                .macro  arch_ret_to_user, tmp1, tmp2
> > +                .endm
> > diff --git a/arch/arm/mach-xilinx/include/mach/hardware.h
b/arch/arm/mach-
> xilinx/include/mach/hardware.h
> > new file mode 100644
> > index 0000000..f9685c4
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/hardware.h
> > @@ -0,0 +1,18 @@
> > +/* arch/arm/mach-xilinx/include/mach/hardware.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_HARDWARE_H__
> > +#define __MACH_HARDWARE_H__
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/io.h
b/arch/arm/mach-xilinx/include/mach/io.h
> > new file mode 100644
> > index 0000000..ef69e65
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/io.h
> > @@ -0,0 +1,33 @@
> > +/* arch/arm/mach-xilinx/include/mach/io.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_IO_H__
> > +#define __MACH_IO_H__
> > +
> > +/* Allow IO space to be anywhere in the memory */
> > +
> > +#define IO_SPACE_LIMIT 0xffff
> > +
> > +/* IO address mapping macros, nothing special at this time but
required */
> > +
> > +#ifdef __ASSEMBLER__
> > +#define IOMEM(x)		(x)
> > +#else
> > +#define IOMEM(x)		((void __force __iomem *)(x))
> > +#endif
> > +
> > +#define __io(a)			__typesafe_io(a)
> > +#define __mem_pci(a)		(a)
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/irqs.h
b/arch/arm/mach-xilinx/include/mach/irqs.h
> > new file mode 100644
> > index 0000000..47a8162
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/irqs.h
> > @@ -0,0 +1,29 @@
> > +/* arch/arm/mach-xilinx/include/mach/irqs.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_IRQS_H
> > +#define __MACH_IRQS_H
> > +
> > +#define ARCH_NR_GPIOS	118
> > +#define NR_IRQS		(128 + ARCH_NR_GPIOS)
> > +
> > +/*
> > + * GIC Interrupts
> > + */
> > +
> > +#define IRQ_GIC_SPI_START	32
> > +#define IRQ_TIMERCOUNTER0	42
> > +#define IRQ_UART0		59
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/memory.h
b/arch/arm/mach-xilinx/include/mach/memory.h
> > new file mode 100644
> > index 0000000..c200486
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/memory.h
> > @@ -0,0 +1,23 @@
> > +/* arch/arm/mach-xilinx/include/mach/memory.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_MEMORY_H__
> > +#define __MACH_MEMORY_H__
> > +
> > +#include <mach/hardware.h>
> > +
> > +#define PHYS_OFFSET             0x0
> 
> This should be PLAT_PHYS_OFFSET and could do with being surrounded
with
> UL() e.g.
> 
> #define PLAT_PHYS_OFFSET	UL(0x00000000)
> 
> > +#define MEM_SIZE		SZ_256M
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/system.h
b/arch/arm/mach-xilinx/include/mach/system.h
> > new file mode 100644
> > index 0000000..e8514a0
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/system.h
> > @@ -0,0 +1,28 @@
> > +/* arch/arm/mach-xilinx/include/mach/system.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_SYSTEM_H__
> > +#define __MACH_SYSTEM_H__
> > +
> > +static inline void arch_idle(void)
> > +{
> > +	cpu_do_idle();
> > +}
> > +
> > +static inline void arch_reset(char mode, const char *cmd)
> > +{
> > +	/* Add architecture specific reset processing here */
> 
> I think you can add cpu_reset(0) in here to try a soft reset by
jumping
> to the reset vector.  This should give you some reset functionality.

Hi Jamie,

How strongly do you feel that this has to be in on this initial patch
set?

There will be many more coming later and I'd like to postpone that one
as it's really additional
functionality vs a bug (to me anyway).

Thanks,
John

> 
> > +}
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/timex.h
b/arch/arm/mach-xilinx/include/mach/timex.h
> > new file mode 100644
> > index 0000000..6765e15
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/timex.h
> > @@ -0,0 +1,24 @@
> > +/* arch/arm/mach-xilinx/include/mach/timex.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_TIMEX_H__
> > +#define __MACH_TIMEX_H__
> > +
> > +#include <mach/hardware.h>
> 
> I don't think you need mach/hardware.h included in here.
> 
> > +
> > +#define PERIPHERAL_CLOCK_RATE	2500000
> > +
> > +#define CLOCK_TICK_RATE	(PERIPHERAL_CLOCK_RATE / 32)
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/uart.h
b/arch/arm/mach-xilinx/include/mach/uart.h
> > new file mode 100644
> > index 0000000..20a10d7
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/uart.h
> > @@ -0,0 +1,31 @@
> > +/* arch/arm/mach-xilinx/include/mach/uart.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_UART_H__
> > +#define __MACH_UART_H__
> > +
> > +#define UART_CR_OFFSET          0x00  /* Control Register [8:0] */
> > +#define UART_SR_OFFSET          0x2C  /* Channel Status [11:0] */
> > +#define UART_FIFO_OFFSET        0x30  /* FIFO [15:0] or [7:0] */
> > +
> > +#define UART_SR_TXFULL		0x00000010	/* TX FIFO full
*/
> > +#define UART_SR_TXEMPTY		0x00000008	/* TX FIFO empty
*/
> > +
> > +#define UART_FIFO_WRITE(base, value) \
> > +	(*(volatile unsigned int *)((base) + UART_FIFO_OFFSET) =
(value))
> > +
> > +#define UART_STATUS(base) \
> > +	(*(volatile unsigned int *)((base) + UART_SR_OFFSET))
> 
> You could probably make these static inline functions in the header
and
> use __raw_{readl,writel}() to make this a little cleaner.
> 
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/uncompress.h
b/arch/arm/mach-
> xilinx/include/mach/uncompress.h
> > new file mode 100644
> > index 0000000..b7a5110
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/uncompress.h
> > @@ -0,0 +1,47 @@
> > +/* arch/arm/mach-xilinx/include/mach/uncompress.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_UNCOMPRESS_H__
> > +#define __MACH_UNCOMPRESS_H__
> > +
> > +#include <mach/xilinx_soc.h>
> > +#include <mach/uart.h>
> > +
> > +void arch_decomp_setup(void)
> > +{
> > +}
> > +
> > +static inline void flush(void)
> > +{
> > +	/*
> > +	 * Wait while the FIFO is not empty
> > +	 */
> > +	while (!(UART_STATUS(LL_UART_PADDR) & UART_SR_TXEMPTY))
> > +		;
> > +}
> > +
> > +#define arch_decomp_wdog()
> > +
> > +static void putc(char ch)
> > +{
> > +	/*
> > +	 * Wait for room in the FIFO, then write the char into the FIFO
> > +	 */
> > +	while (UART_STATUS(LL_UART_PADDR) & UART_SR_TXFULL)
> > +		;
> 
> It might be worth adding a barrier() call to these loops to be
explicit
> about the volatility.
> 
> > +
> > +	UART_FIFO_WRITE(LL_UART_PADDR, ch);
> > +}
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/vmalloc.h
b/arch/arm/mach-
> xilinx/include/mach/vmalloc.h
> > new file mode 100644
> > index 0000000..aba20a3
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/vmalloc.h
> > @@ -0,0 +1,20 @@
> > +/* arch/arm/mach-xilinx/include/mach/vmalloc.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_VMALLOC_H__
> > +#define __MACH_VMALLOC_H__
> > +
> > +#define VMALLOC_END       0xE0000000UL
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
b/arch/arm/mach-
> xilinx/include/mach/xilinx_soc.h
> > new file mode 100644
> > index 0000000..d01cde1
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> > @@ -0,0 +1,46 @@
> > +/* arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_XILINX_SOC_H__
> > +#define __MACH_XILINX_SOC_H__
> > +
> > +/* For now, all mappings are flat (physical = virtual)
> > + */
> > +#define UART0_PHYS			0xE0000000
> > +#define UART0_VIRT			UART0_PHYS
> > +
> > +#define TTC0_PHYS			0xF8001000
> > +#define TTC0_VIRT			TTC0_PHYS
> > +
> > +#define PL310_L2CC_PHYS			0xF8F02000
> > +#define PL310_L2CC_VIRT			PL310_L2CC_PHYS
> > +
> > +#define SCU_PERIPH_PHYS			0xF8F00000
> > +#define SCU_PERIPH_VIRT			SCU_PERIPH_PHYS
> > +
> > +/* The following are intended for the devices that are mapped early
*/
> > +
> > +#define TTC0_BASE			IOMEM(TTC0_VIRT)
> > +#define SCU_PERIPH_BASE			IOMEM(SCU_PERIPH_VIRT)
> > +#define SCU_GIC_CPU_BASE		(SCU_PERIPH_BASE + 0x100)
> > +#define SCU_GIC_DIST_BASE		(SCU_PERIPH_BASE + 0x1000)
> > +#define PL310_L2CC_BASE			IOMEM(PL310_L2CC_VIRT)
> > +
> > +/*
> > + * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical
> > + */
> > +#define LL_UART_PADDR	UART0_PHYS
> > +#define LL_UART_VADDR	UART0_VIRT
> > +
> > +#endif
> > --
> > 1.6.2.1
> >
> >
> >
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[PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros

[Jamie Iles]

On Thu, Feb 17, 2011 at 05:37:47PM -0700, John Linn wrote:
> > > +static inline void arch_reset(char mode, const char *cmd)
> > > +{
> > > +	/* Add architecture specific reset processing here */
> > 
> > I think you can add cpu_reset(0) in here to try a soft reset by
> jumping
> > to the reset vector.  This should give you some reset functionality.
> 
> Hi Jamie,
> 
> How strongly do you feel that this has to be in on this initial patch
> set?
> 
> There will be many more coming later and I'd like to postpone that one
> as it's really additional
> functionality vs a bug (to me anyway).

I don't have a strong opinion on it.  If you leave it as it is so that 
arch_reset() will return then the generic ARM code will issue a printk 
to tell the user that it failed then drop into an infinite loop so it 
should be obvious that reset isn't implemented!

If reset is nontrivial then you're probably right to leave it out of 
this patch and put it into another later on.

Jamie

[PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros

[John Linn]

> -----Original Message-----
> From: Jamie Iles [mailto:jamie at jamieiles.com]
> Sent: Thursday, February 17, 2011 3:01 AM
> To: John Linn
> Cc: linux-arm-kernel at lists.infradead.org;
linux-kernel at vger.kernel.org; linux at arm.linux.org.uk;
> catalin.marinas at arm.com; glikely at secretlab.ca; arnd at arndb.de
> Subject: Re: [PATCH V3 3/4] ARM: Xilinx: base header files and
assembly macros
> 
> Hi John,
> 
> A few more nitpicks, but looking good now!
> 
> Jamie
> 
> On Wed, Feb 16, 2011 at 09:11:55AM -0700, John Linn wrote:
> > These are the minimum needed to build the kernel for the new
platform.
> >
> > Signed-off-by: John Linn <john.linn@xilinx.com>
> > ---
> >
> > V3 Changes
> >
> > Updates based on Russell Kings' comments
> > 	Changed headers to update the license info and remove
> > 	the address
> >
> > 	Updated the constant to use UL in vmalloc.h
> >
> > V2 Changes
> >
> > Updates based on Russell King's comments
> > 	moved to using entry-macro-gic.S
> > 	moved stuff from hardware.h to xilinx_soc.h
> > 	added IOMEM() in io.h to help with typing
> > 	Minor updates to IO_SPACE_LIMIT and __io()
> > 	Updated addresses to be clear with seperate virtual
> > 		and physical addresses
> >
> >  arch/arm/mach-xilinx/include/mach/clkdev.h      |   33
++++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/debug-macro.S |   36
+++++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/entry-macro.S |   30
++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/hardware.h    |   18 +++++++++
> >  arch/arm/mach-xilinx/include/mach/io.h          |   33
++++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/irqs.h        |   29
++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/memory.h      |   23 +++++++++++
> >  arch/arm/mach-xilinx/include/mach/system.h      |   28
+++++++++++++
> >  arch/arm/mach-xilinx/include/mach/timex.h       |   24 ++++++++++++
> >  arch/arm/mach-xilinx/include/mach/uart.h        |   31
+++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/uncompress.h  |   47
+++++++++++++++++++++++
> >  arch/arm/mach-xilinx/include/mach/vmalloc.h     |   20 ++++++++++
> >  arch/arm/mach-xilinx/include/mach/xilinx_soc.h  |   46
++++++++++++++++++++++
> >  13 files changed, 398 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/clkdev.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/debug-macro.S
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/entry-macro.S
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/hardware.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/io.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/irqs.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/memory.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/system.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/timex.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/uart.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/uncompress.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/vmalloc.h
> >  create mode 100644 arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> >

<snip>

> > diff --git a/arch/arm/mach-xilinx/include/mach/memory.h
b/arch/arm/mach-xilinx/include/mach/memory.h
> > new file mode 100644
> > index 0000000..c200486
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/memory.h
> > @@ -0,0 +1,23 @@
> > +/* arch/arm/mach-xilinx/include/mach/memory.h
> > + *
> > + *  Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_MEMORY_H__
> > +#define __MACH_MEMORY_H__
> > +
> > +#include <mach/hardware.h>
> > +
> > +#define PHYS_OFFSET             0x0
> 
> This should be PLAT_PHYS_OFFSET and could do with being surrounded
with
> UL() e.g.
> 
> #define PLAT_PHYS_OFFSET	UL(0x00000000)

This doesn't build with 2.6.38-rc5, am I missing something?

PHYS_OFFSET is still needed from what I can tell, but maybe I overlooked
something.

Thanks,
John


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[PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros

[Jamie Iles]

On Thu, Feb 17, 2011 at 06:19:09PM -0700, John Linn wrote:
> > > +#define PHYS_OFFSET             0x0
> > 
> > This should be PLAT_PHYS_OFFSET and could do with being surrounded
> with
> > UL() e.g.
> > 
> > #define PLAT_PHYS_OFFSET	UL(0x00000000)
> 
> This doesn't build with 2.6.38-rc5, am I missing something?
> 
> PHYS_OFFSET is still needed from what I can tell, but maybe I overlooked
> something.

The change is queued up in Russell's devel branch for the dynamic p2v 
and will be in 2.6.39.  For a patch series like this it's probably worth 
developing off of linux-next[1].  This contains all of the trees that 
will be mereged into the next kernel so carries the bigger changes like 
dynamic p2v.

Jamie

1. git://git.kernel.org/pub/scm/linux/kernel/git/sfr/linux-next.git

[PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros

[John Linn]

> -----Original Message-----
> From: Jamie Iles [mailto:jamie at jamieiles.com]
> Sent: Friday, February 18, 2011 2:06 AM
> To: John Linn
> Cc: Jamie Iles; linux-arm-kernel at lists.infradead.org;
linux-kernel at vger.kernel.org;
> linux at arm.linux.org.uk; catalin.marinas at arm.com; glikely at secretlab.ca;
arnd at arndb.de
> Subject: Re: [PATCH V3 3/4] ARM: Xilinx: base header files and
assembly macros
> 
> On Thu, Feb 17, 2011 at 06:19:09PM -0700, John Linn wrote:
> > > > +#define PHYS_OFFSET             0x0
> > >
> > > This should be PLAT_PHYS_OFFSET and could do with being surrounded
> > with
> > > UL() e.g.
> > >
> > > #define PLAT_PHYS_OFFSET	UL(0x00000000)
> >
> > This doesn't build with 2.6.38-rc5, am I missing something?
> >
> > PHYS_OFFSET is still needed from what I can tell, but maybe I
overlooked
> > something.
> 
> The change is queued up in Russell's devel branch for the dynamic p2v
> and will be in 2.6.39.  For a patch series like this it's probably
worth
> developing off of linux-next[1].  This contains all of the trees that
> will be mereged into the next kernel so carries the bigger changes
like
> dynamic p2v.

My hope was to get into 2.6.38 and maybe that was not realistic.  If
it's too late
for 2.6.38 then I'll revise the patch for this branch.

Any thoughts Russell based on where we are?

Thanks for the insight.
John

> 
> Jamie
> 
> 1. git://git.kernel.org/pub/scm/linux/kernel/git/sfr/linux-next.git


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[PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros

[John Linn]

> -----Original Message-----
> From: John Linn
> Sent: Friday, February 18, 2011 7:00 AM
> To: 'Jamie Iles'
> Cc: linux-arm-kernel at lists.infradead.org;
linux-kernel at vger.kernel.org; linux at arm.linux.org.uk;
> catalin.marinas at arm.com; glikely at secretlab.ca; arnd at arndb.de
> Subject: RE: [PATCH V3 3/4] ARM: Xilinx: base header files and
assembly macros
> 
> > -----Original Message-----
> > From: Jamie Iles [mailto:jamie at jamieiles.com]
> > Sent: Friday, February 18, 2011 2:06 AM
> > To: John Linn
> > Cc: Jamie Iles; linux-arm-kernel at lists.infradead.org;
linux-kernel at vger.kernel.org;
> > linux at arm.linux.org.uk; catalin.marinas at arm.com;
glikely at secretlab.ca; arnd at arndb.de
> > Subject: Re: [PATCH V3 3/4] ARM: Xilinx: base header files and
assembly macros
> >
> > On Thu, Feb 17, 2011 at 06:19:09PM -0700, John Linn wrote:
> > > > > +#define PHYS_OFFSET             0x0
> > > >
> > > > This should be PLAT_PHYS_OFFSET and could do with being
surrounded
> > > with
> > > > UL() e.g.
> > > >
> > > > #define PLAT_PHYS_OFFSET	UL(0x00000000)
> > >
> > > This doesn't build with 2.6.38-rc5, am I missing something?
> > >
> > > PHYS_OFFSET is still needed from what I can tell, but maybe I
overlooked
> > > something.
> >
> > The change is queued up in Russell's devel branch for the dynamic
p2v
> > and will be in 2.6.39.  For a patch series like this it's probably
worth
> > developing off of linux-next[1].  This contains all of the trees
that
> > will be mereged into the next kernel so carries the bigger changes
like
> > dynamic p2v.
> 
> My hope was to get into 2.6.38 and maybe that was not realistic.  If
it's too late
> for 2.6.38 then I'll revise the patch for this branch.

I guess it was too early and I wasn't thinking clearly there with
2.6.38.

You were right on 2.6.39.  Sounds like I should switch to this other
branch
to develop against.

Thanks,
John

> 
> Any thoughts Russell based on where we are?
> 
> Thanks for the insight.
> John
> 
> >
> > Jamie
> >
> > 1. git://git.kernel.org/pub/scm/linux/kernel/git/sfr/linux-next.git


This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

[PATCH V3 4/4] ARM: Xilinx: Adding Xilinx platform infrastructure support

[John Linn]

Minimum infrastructure to add the Xilinx machine and allow it to
be selected in the build.

Signed-off-by: John Linn <john.linn@xilinx.com>
---

No updates for V3

V2 Changes

Updates based on Russell King's comments	
	Cleanup of the Kconfig
	Moved this patch to be last in the patch series

 arch/arm/Kconfig    |   13 +++++++++++++
 arch/arm/Makefile   |    1 +
 arch/arm/mm/Kconfig |    2 +-
 3 files changed, 15 insertions(+), 1 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5cff165..3317671 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -875,6 +875,17 @@ config PLAT_SPEAR
 	help
 	  Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 
+config ARCH_XILINX
+	bool "Xilinx ARM Cortex A9 Based FPGA"
+	select CPU_V7
+	select GENERIC_TIME
+	select GENERIC_CLOCKEVENTS
+	select CLKDEV_LOOKUP
+	select ARM_GIC
+	select ARM_AMBA
+	help
+	  Support for Xilinx ARM Cortex A9 Based FPGA
+
 endchoice
 
 #
@@ -1009,6 +1020,8 @@ source "arch/arm/mach-vexpress/Kconfig"
 
 source "arch/arm/mach-w90x900/Kconfig"
 
+source "arch/arm/mach-xilinx/Kconfig"
+
 # Definitions to make life easier
 config ARCH_ACORN
 	bool
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c22c1ad..4bad6ef 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -197,6 +197,7 @@ machine-$(CONFIG_MACH_SPEAR300)		:= spear3xx
 machine-$(CONFIG_MACH_SPEAR310)		:= spear3xx
 machine-$(CONFIG_MACH_SPEAR320)		:= spear3xx
 machine-$(CONFIG_MACH_SPEAR600)		:= spear6xx
+machine-$(CONFIG_ARCH_XILINX)		:= xilinx
 
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 9d30c6f..c8a9f5c 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -813,7 +813,7 @@ config CACHE_L2X0
 	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
 		   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
 		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
-		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
+		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_XILINX
 	default y
 	select OUTER_CACHE
 	select OUTER_CACHE_SYNC
-- 
1.6.2.1



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