[PATCH] ARMv7: Flush the vectors page using the base address

[PATCH] ARMv7: Flush the vectors page using the base address

[Catalin Marinas]

With the domains removal patch, the vectors page is populated using the
kernel linear mapping address. However, the flush_icache_range()
function must be called on the high vectors address because the I-cache
is allowed to have aliases (or can even be ASID-tagged VIVT).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: <stable@kernel.org>
---
 arch/arm/kernel/traps.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index ee57640..3d520c8 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -791,6 +791,6 @@ void __init early_trap_init(void)
 	memcpy((void *)(vectors + KERN_RESTART_CODE - CONFIG_VECTORS_BASE),
 	       syscall_restart_code, sizeof(syscall_restart_code));
 
-	flush_icache_range(vectors, vectors + PAGE_SIZE);
+	flush_icache_range(CONFIG_VECTORS_BASE, CONFIG_VECTORS_BASE+PAGE_SIZE);
 	modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
 }

[PATCH] ARMv7: Flush the vectors page using the base address

[Russell King - ARM Linux]

On Tue, Mar 15, 2011 at 06:13:15PM +0000, Catalin Marinas wrote:
> With the domains removal patch, the vectors page is populated using the
> kernel linear mapping address. However, the flush_icache_range()
> function must be called on the high vectors address because the I-cache
> is allowed to have aliases (or can even be ASID-tagged VIVT).

This is exactly one of the issues I raised when we went down this hacky
path of always doing this crap.

What you're now doing is missing the D-cache flush in the case of an
aliasing D-cache.  It's no better than it was before.

[PATCH] ARMv7: Flush the vectors page using the base address

[Catalin Marinas]

On Tuesday, 15 March 2011, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Tue, Mar 15, 2011 at 06:13:15PM +0000, Catalin Marinas wrote:
>> With the domains removal patch, the vectors page is populated using the
>> kernel linear mapping address. However, the flush_icache_range()
>> function must be called on the high vectors address because the I-cache
>> is allowed to have aliases (or can even be ASID-tagged VIVT).
>
> This is exactly one of the issues I raised when we went down this hacky
> path of always doing this crap.

I don't think we have better options but feel free to rewrite it.

> What you're now doing is missing the D-cache flush in the case of an
> aliasing D-cache. ?It's no better than it was before.

In cases where we have domains disabled (ARMv7), the D-cache is
non-aliasing, so there is no issue.

Even if we enable this code for other cache configurations, we can
always flush both aliases. This only happen during boot and I doubt
you would notice any delay.

Catalin

-- 
Catalin