From mboxrd@z Thu Jan 1 00:00:00 1970 From: s.hauer@pengutronix.de (Sascha Hauer) Date: Thu, 17 Mar 2011 09:00:31 +0100 Subject: [PATCHv3 1/3] ARM: mx51: Add entry for gpc_dvfs_clk In-Reply-To: <1300305787-7970-1-git-send-email-Dinh.Nguyen@freescale.com> References: <1300305787-7970-1-git-send-email-Dinh.Nguyen@freescale.com> Message-ID: <20110317080031.GR29521@pengutronix.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Mar 16, 2011 at 03:03:05PM -0500, Dinh.Nguyen at freescale.com wrote: > From: Dinh Nguyen > > For MX51 SRPG, we need to turn on the GPC clock in order to set the > SRPG registers. > > Signed-off-by: Dinh Nguyen > --- > arch/arm/mach-mx5/clock-mx51-mx53.c | 8 ++++++++ > 1 files changed, 8 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c > index 652ace4..18492fa 100644 > --- a/arch/arm/mach-mx5/clock-mx51-mx53.c > +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c > @@ -865,6 +865,13 @@ static struct clk aips_tz2_clk = { > .disable = _clk_ccgr_disable_inwait, > }; > > +static struct clk gpc_dvfs_clk = { > + .enable_reg = MXC_CCM_CCGR5, > + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, > + .enable = _clk_ccgr_enable, > + .disable = _clk_ccgr_disable, > +}; > + > static struct clk gpt_32k_clk = { > .id = 0, > .parent = &ckil_clk, > @@ -1448,6 +1455,7 @@ static struct clk_lookup mx51_lookups[] = { > _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk) > _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) > _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) > + _REGISTER_CLOCK(NULL, "gpc_dvfs_clk", gpc_dvfs_clk) Please remove the _clk. The context makes it clear already that it's a clock. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |