[PATCH 0/4] add gpio driver gpio-mxs

[PATCH 0/4] add gpio driver gpio-mxs

[Shawn Guo]

The patch set is to move Freescale MXS gpio driver from mach-mxs
into drivers/gpio.  Different from u300 gpio driver that all gpio
ports are registered as one device, gpio-mxs expects every single
port is a gpio device.

The first 3 patches are just to ease review and can be squashed into
the last one.

Shawn Guo (4):
      gpio: gpio-mxs: add file gpio-mxs.c
      gpio: gpio-mxs: drop mach-specific accessors
      gpio: gpio-mxs: remove gpio port definition and registration
      gpio: gpio-mxs: add gpio driver for Freescale MXS architecture

 drivers/gpio/Kconfig    |    3 +
 drivers/gpio/Makefile   |    1 +
 drivers/gpio/gpio-mxs.c |  371 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 375 insertions(+), 0 deletions(-)

Regards,
Shawn

[PATCH 1/4] gpio: gpio-mxs: add file gpio-mxs.c

[Shawn Guo]

This is a direct file copy from arch/arm/mach-mxs/gpio.c to ease
the review.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 drivers/gpio/gpio-mxs.c |  331 +++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 331 insertions(+), 0 deletions(-)
 create mode 100644 drivers/gpio/gpio-mxs.c

diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
new file mode 100644
index 0000000..2c950fe
--- /dev/null
+++ b/drivers/gpio/gpio-mxs.c
@@ -0,0 +1,331 @@
+/*
+ * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
+ * Copyright 2008 Juergen Beisert, kernel at pengutronix.de
+ *
+ * Based on code from Freescale,
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <asm-generic/bug.h>
+
+#include "gpio.h"
+
+static struct mxs_gpio_port *mxs_gpio_ports;
+static int gpio_table_size;
+
+#define PINCTRL_DOUT(n)		((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
+#define PINCTRL_DIN(n)		((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
+#define PINCTRL_DOE(n)		((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
+#define PINCTRL_PIN2IRQ(n)	((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
+#define PINCTRL_IRQEN(n)	((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
+#define PINCTRL_IRQLEV(n)	((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
+#define PINCTRL_IRQPOL(n)	((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
+#define PINCTRL_IRQSTAT(n)	((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
+
+#define GPIO_INT_FALL_EDGE	0x0
+#define GPIO_INT_LOW_LEV	0x1
+#define GPIO_INT_RISE_EDGE	0x2
+#define GPIO_INT_HIGH_LEV	0x3
+#define GPIO_INT_LEV_MASK	(1 << 0)
+#define GPIO_INT_POL_MASK	(1 << 1)
+
+/* Note: This driver assumes 32 GPIOs are handled in one register */
+
+static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
+{
+	__mxs_clrl(1 << index, port->base + PINCTRL_IRQSTAT(port->id));
+}
+
+static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
+				int enable)
+{
+	if (enable) {
+		__mxs_setl(1 << index, port->base + PINCTRL_IRQEN(port->id));
+		__mxs_setl(1 << index, port->base + PINCTRL_PIN2IRQ(port->id));
+	} else {
+		__mxs_clrl(1 << index, port->base + PINCTRL_IRQEN(port->id));
+	}
+}
+
+static void mxs_gpio_ack_irq(struct irq_data *d)
+{
+	u32 gpio = irq_to_gpio(d->irq);
+	clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f);
+}
+
+static void mxs_gpio_mask_irq(struct irq_data *d)
+{
+	u32 gpio = irq_to_gpio(d->irq);
+	set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0);
+}
+
+static void mxs_gpio_unmask_irq(struct irq_data *d)
+{
+	u32 gpio = irq_to_gpio(d->irq);
+	set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1);
+}
+
+static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);
+
+static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
+{
+	u32 gpio = irq_to_gpio(d->irq);
+	u32 pin_mask = 1 << (gpio & 31);
+	struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
+	void __iomem *pin_addr;
+	int edge;
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		edge = GPIO_INT_RISE_EDGE;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		edge = GPIO_INT_FALL_EDGE;
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		edge = GPIO_INT_LOW_LEV;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		edge = GPIO_INT_HIGH_LEV;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* set level or edge */
+	pin_addr = port->base + PINCTRL_IRQLEV(port->id);
+	if (edge & GPIO_INT_LEV_MASK)
+		__mxs_setl(pin_mask, pin_addr);
+	else
+		__mxs_clrl(pin_mask, pin_addr);
+
+	/* set polarity */
+	pin_addr = port->base + PINCTRL_IRQPOL(port->id);
+	if (edge & GPIO_INT_POL_MASK)
+		__mxs_setl(pin_mask, pin_addr);
+	else
+		__mxs_clrl(pin_mask, pin_addr);
+
+	clear_gpio_irqstatus(port, gpio & 0x1f);
+
+	return 0;
+}
+
+/* MXS has one interrupt *per* gpio port */
+static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+	u32 irq_stat;
+	struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq);
+	u32 gpio_irq_no_base = port->virtual_irq_start;
+
+	desc->irq_data.chip->irq_ack(&desc->irq_data);
+
+	irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) &
+			__raw_readl(port->base + PINCTRL_IRQEN(port->id));
+
+	while (irq_stat != 0) {
+		int irqoffset = fls(irq_stat) - 1;
+		generic_handle_irq(gpio_irq_no_base + irqoffset);
+		irq_stat &= ~(1 << irqoffset);
+	}
+}
+
+/*
+ * Set interrupt number "irq" in the GPIO as a wake-up source.
+ * While system is running, all registered GPIO interrupts need to have
+ * wake-up enabled. When system is suspended, only selected GPIO interrupts
+ * need to have wake-up enabled.
+ * @param  irq          interrupt source number
+ * @param  enable       enable as wake-up if equal to non-zero
+ * @return       This function returns 0 on success.
+ */
+static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
+{
+	u32 gpio = irq_to_gpio(d->irq);
+	u32 gpio_idx = gpio & 0x1f;
+	struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
+
+	if (enable) {
+		if (port->irq_high && (gpio_idx >= 16))
+			enable_irq_wake(port->irq_high);
+		else
+			enable_irq_wake(port->irq);
+	} else {
+		if (port->irq_high && (gpio_idx >= 16))
+			disable_irq_wake(port->irq_high);
+		else
+			disable_irq_wake(port->irq);
+	}
+
+	return 0;
+}
+
+static struct irq_chip gpio_irq_chip = {
+	.name = "mxs gpio",
+	.irq_ack = mxs_gpio_ack_irq,
+	.irq_mask = mxs_gpio_mask_irq,
+	.irq_unmask = mxs_gpio_unmask_irq,
+	.irq_set_type = mxs_gpio_set_irq_type,
+	.irq_set_wake = mxs_gpio_set_wake_irq,
+};
+
+static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset,
+				int dir)
+{
+	struct mxs_gpio_port *port =
+		container_of(chip, struct mxs_gpio_port, chip);
+	void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id);
+
+	if (dir)
+		__mxs_setl(1 << offset, pin_addr);
+	else
+		__mxs_clrl(1 << offset, pin_addr);
+}
+
+static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+	struct mxs_gpio_port *port =
+		container_of(chip, struct mxs_gpio_port, chip);
+
+	return (__raw_readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
+}
+
+static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+	struct mxs_gpio_port *port =
+		container_of(chip, struct mxs_gpio_port, chip);
+	void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id);
+
+	if (value)
+		__mxs_setl(1 << offset, pin_addr);
+	else
+		__mxs_clrl(1 << offset, pin_addr);
+}
+
+static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+	struct mxs_gpio_port *port =
+		container_of(chip, struct mxs_gpio_port, chip);
+
+	return port->virtual_irq_start + offset;
+}
+
+static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+	mxs_set_gpio_direction(chip, offset, 0);
+	return 0;
+}
+
+static int mxs_gpio_direction_output(struct gpio_chip *chip,
+				     unsigned offset, int value)
+{
+	mxs_gpio_set(chip, offset, value);
+	mxs_set_gpio_direction(chip, offset, 1);
+	return 0;
+}
+
+int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
+{
+	int i, j;
+
+	/* save for local usage */
+	mxs_gpio_ports = port;
+	gpio_table_size = cnt;
+
+	pr_info("MXS GPIO hardware\n");
+
+	for (i = 0; i < cnt; i++) {
+		/* disable the interrupt and clear the status */
+		__raw_writel(0, port[i].base + PINCTRL_PIN2IRQ(i));
+		__raw_writel(0, port[i].base + PINCTRL_IRQEN(i));
+
+		/* clear address has to be used to clear IRQSTAT bits */
+		__mxs_clrl(~0U, port[i].base + PINCTRL_IRQSTAT(i));
+
+		for (j = port[i].virtual_irq_start;
+			j < port[i].virtual_irq_start + 32; j++) {
+			irq_set_chip_and_handler(j, &gpio_irq_chip,
+						 handle_level_irq);
+			set_irq_flags(j, IRQF_VALID);
+		}
+
+		/* setup one handler for each entry */
+		irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler);
+		irq_set_handler_data(port[i].irq, &port[i]);
+
+		/* register gpio chip */
+		port[i].chip.direction_input = mxs_gpio_direction_input;
+		port[i].chip.direction_output = mxs_gpio_direction_output;
+		port[i].chip.get = mxs_gpio_get;
+		port[i].chip.set = mxs_gpio_set;
+		port[i].chip.to_irq = mxs_gpio_to_irq;
+		port[i].chip.base = i * 32;
+		port[i].chip.ngpio = 32;
+
+		/* its a serious configuration bug when it fails */
+		BUG_ON(gpiochip_add(&port[i].chip) < 0);
+	}
+
+	return 0;
+}
+
+#define MX23_GPIO_BASE	MX23_IO_ADDRESS(MX23_PINCTRL_BASE_ADDR)
+#define MX28_GPIO_BASE	MX28_IO_ADDRESS(MX28_PINCTRL_BASE_ADDR)
+
+#define DEFINE_MXS_GPIO_PORT(_base, _irq, _id)				\
+	{								\
+		.chip.label = "gpio-" #_id,				\
+		.id = _id,						\
+		.irq = _irq,						\
+		.base = _base,						\
+		.virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32,	\
+	}
+
+#ifdef CONFIG_SOC_IMX23
+static struct mxs_gpio_port mx23_gpio_ports[] = {
+	DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO0, 0),
+	DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO1, 1),
+	DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO2, 2),
+};
+
+int __init mx23_register_gpios(void)
+{
+	return mxs_gpio_init(mx23_gpio_ports, ARRAY_SIZE(mx23_gpio_ports));
+}
+#endif
+
+#ifdef CONFIG_SOC_IMX28
+static struct mxs_gpio_port mx28_gpio_ports[] = {
+	DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO0, 0),
+	DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO1, 1),
+	DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO2, 2),
+	DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO3, 3),
+	DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO4, 4),
+};
+
+int __init mx28_register_gpios(void)
+{
+	return mxs_gpio_init(mx28_gpio_ports, ARRAY_SIZE(mx28_gpio_ports));
+}
+#endif
-- 
1.7.4.1

[PATCH 2/4] gpio: gpio-mxs: drop mach-specific accessors

[Shawn Guo]

Use readl/writel to replace __raw_readl/__raw_writel.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 drivers/gpio/gpio-mxs.c |   42 ++++++++++++++++++++++++------------------
 1 files changed, 24 insertions(+), 18 deletions(-)

diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
index 2c950fe..260d7ed 100644
--- a/drivers/gpio/gpio-mxs.c
+++ b/drivers/gpio/gpio-mxs.c
@@ -34,6 +34,9 @@
 static struct mxs_gpio_port *mxs_gpio_ports;
 static int gpio_table_size;
 
+#define MXS_SET		0x4
+#define MXS_CLR		0x8
+
 #define PINCTRL_DOUT(n)		((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
 #define PINCTRL_DIN(n)		((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
 #define PINCTRL_DOE(n)		((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
@@ -54,17 +57,20 @@ static int gpio_table_size;
 
 static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
 {
-	__mxs_clrl(1 << index, port->base + PINCTRL_IRQSTAT(port->id));
+	writel(1 << index, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
 }
 
 static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
 				int enable)
 {
 	if (enable) {
-		__mxs_setl(1 << index, port->base + PINCTRL_IRQEN(port->id));
-		__mxs_setl(1 << index, port->base + PINCTRL_PIN2IRQ(port->id));
+		writel(1 << index,
+			port->base + PINCTRL_IRQEN(port->id) + MXS_SET);
+		writel(1 << index,
+			port->base + PINCTRL_PIN2IRQ(port->id) + MXS_SET);
 	} else {
-		__mxs_clrl(1 << index, port->base + PINCTRL_IRQEN(port->id));
+		writel(1 << index,
+			port->base + PINCTRL_IRQEN(port->id) + MXS_CLR);
 	}
 }
 
@@ -116,16 +122,16 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
 	/* set level or edge */
 	pin_addr = port->base + PINCTRL_IRQLEV(port->id);
 	if (edge & GPIO_INT_LEV_MASK)
-		__mxs_setl(pin_mask, pin_addr);
+		writel(pin_mask, pin_addr + MXS_SET);
 	else
-		__mxs_clrl(pin_mask, pin_addr);
+		writel(pin_mask, pin_addr + MXS_CLR);
 
 	/* set polarity */
 	pin_addr = port->base + PINCTRL_IRQPOL(port->id);
 	if (edge & GPIO_INT_POL_MASK)
-		__mxs_setl(pin_mask, pin_addr);
+		writel(pin_mask, pin_addr + MXS_SET);
 	else
-		__mxs_clrl(pin_mask, pin_addr);
+		writel(pin_mask, pin_addr + MXS_CLR);
 
 	clear_gpio_irqstatus(port, gpio & 0x1f);
 
@@ -141,8 +147,8 @@ static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 
 	desc->irq_data.chip->irq_ack(&desc->irq_data);
 
-	irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) &
-			__raw_readl(port->base + PINCTRL_IRQEN(port->id));
+	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) &
+			readl(port->base + PINCTRL_IRQEN(port->id));
 
 	while (irq_stat != 0) {
 		int irqoffset = fls(irq_stat) - 1;
@@ -198,9 +204,9 @@ static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset,
 	void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id);
 
 	if (dir)
-		__mxs_setl(1 << offset, pin_addr);
+		writel(1 << offset, pin_addr + MXS_SET);
 	else
-		__mxs_clrl(1 << offset, pin_addr);
+		writel(1 << offset, pin_addr + MXS_CLR);
 }
 
 static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
@@ -208,7 +214,7 @@ static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
 	struct mxs_gpio_port *port =
 		container_of(chip, struct mxs_gpio_port, chip);
 
-	return (__raw_readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
+	return (readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
 }
 
 static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
@@ -218,9 +224,9 @@ static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 	void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id);
 
 	if (value)
-		__mxs_setl(1 << offset, pin_addr);
+		writel(1 << offset, pin_addr + MXS_SET);
 	else
-		__mxs_clrl(1 << offset, pin_addr);
+		writel(1 << offset, pin_addr + MXS_CLR);
 }
 
 static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
@@ -257,11 +263,11 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
 
 	for (i = 0; i < cnt; i++) {
 		/* disable the interrupt and clear the status */
-		__raw_writel(0, port[i].base + PINCTRL_PIN2IRQ(i));
-		__raw_writel(0, port[i].base + PINCTRL_IRQEN(i));
+		writel(0, port[i].base + PINCTRL_PIN2IRQ(i));
+		writel(0, port[i].base + PINCTRL_IRQEN(i));
 
 		/* clear address has to be used to clear IRQSTAT bits */
-		__mxs_clrl(~0U, port[i].base + PINCTRL_IRQSTAT(i));
+		writel(~0U, port[i].base + PINCTRL_IRQSTAT(i) + MXS_CLR);
 
 		for (j = port[i].virtual_irq_start;
 			j < port[i].virtual_irq_start + 32; j++) {
-- 
1.7.4.1

[PATCH 3/4] gpio: gpio-mxs: remove gpio port definition and registration

[Shawn Guo]

This is to ease the review.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 drivers/gpio/gpio-mxs.c |   40 ----------------------------------------
 1 files changed, 0 insertions(+), 40 deletions(-)

diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
index 260d7ed..6a59bf2 100644
--- a/drivers/gpio/gpio-mxs.c
+++ b/drivers/gpio/gpio-mxs.c
@@ -295,43 +295,3 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
 
 	return 0;
 }
-
-#define MX23_GPIO_BASE	MX23_IO_ADDRESS(MX23_PINCTRL_BASE_ADDR)
-#define MX28_GPIO_BASE	MX28_IO_ADDRESS(MX28_PINCTRL_BASE_ADDR)
-
-#define DEFINE_MXS_GPIO_PORT(_base, _irq, _id)				\
-	{								\
-		.chip.label = "gpio-" #_id,				\
-		.id = _id,						\
-		.irq = _irq,						\
-		.base = _base,						\
-		.virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32,	\
-	}
-
-#ifdef CONFIG_SOC_IMX23
-static struct mxs_gpio_port mx23_gpio_ports[] = {
-	DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO0, 0),
-	DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO1, 1),
-	DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO2, 2),
-};
-
-int __init mx23_register_gpios(void)
-{
-	return mxs_gpio_init(mx23_gpio_ports, ARRAY_SIZE(mx23_gpio_ports));
-}
-#endif
-
-#ifdef CONFIG_SOC_IMX28
-static struct mxs_gpio_port mx28_gpio_ports[] = {
-	DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO0, 0),
-	DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO1, 1),
-	DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO2, 2),
-	DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO3, 3),
-	DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO4, 4),
-};
-
-int __init mx28_register_gpios(void)
-{
-	return mxs_gpio_init(mx28_gpio_ports, ARRAY_SIZE(mx28_gpio_ports));
-}
-#endif
-- 
1.7.4.1

[PATCH 4/4] gpio: gpio-mxs: add gpio driver for Freescale MXS architecture

[Shawn Guo]

Add gpio-mxs driver by moving arch/arm/mach-mxs/gpio.c into
drivers/gpio.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 drivers/gpio/Kconfig    |    3 +
 drivers/gpio/Makefile   |    1 +
 drivers/gpio/gpio-mxs.c |  168 ++++++++++++++++++++++++++++++++++-------------
 3 files changed, 125 insertions(+), 47 deletions(-)

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d3b2953..ccca658 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -81,6 +81,9 @@ config GPIO_IT8761E
 	help
 	  Say yes here to support GPIO functionality of IT8761E super I/O chip.
 
+config GPIO_MXS
+	bool
+
 config GPIO_PL061
 	bool "PrimeCell PL061 GPIO support"
 	depends on ARM_AMBA
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index becef59..b06a335 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_GPIO_MAX7301)	+= max7301.o
 obj-$(CONFIG_GPIO_MAX732X)	+= max732x.o
 obj-$(CONFIG_GPIO_MC33880)	+= mc33880.o
 obj-$(CONFIG_GPIO_MCP23S08)	+= mcp23s08.o
+obj-$(CONFIG_GPIO_MXS)		+= gpio-mxs.o
 obj-$(CONFIG_GPIO_74X164)	+= 74x164.o
 obj-$(CONFIG_GPIO_PCA953X)	+= pca953x.o
 obj-$(CONFIG_GPIO_PCF857X)	+= pcf857x.o
diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
index 6a59bf2..b33b2bc 100644
--- a/drivers/gpio/gpio-mxs.c
+++ b/drivers/gpio/gpio-mxs.c
@@ -25,14 +25,18 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <asm-generic/bug.h>
-
-#include "gpio.h"
-
-static struct mxs_gpio_port *mxs_gpio_ports;
-static int gpio_table_size;
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <mach/mxs.h>
+
+struct mxs_gpio_port {
+	void __iomem *base;
+	int id;
+	int irq;
+	int irq_high;
+	int virtual_irq_start;
+	struct gpio_chip chip;
+};
 
 #define MXS_SET		0x4
 #define MXS_CLR		0x8
@@ -76,20 +80,23 @@ static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
 
 static void mxs_gpio_ack_irq(struct irq_data *d)
 {
+	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
 	u32 gpio = irq_to_gpio(d->irq);
-	clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f);
+	clear_gpio_irqstatus(port, gpio & 0x1f);
 }
 
 static void mxs_gpio_mask_irq(struct irq_data *d)
 {
+	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
 	u32 gpio = irq_to_gpio(d->irq);
-	set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0);
+	set_gpio_irqenable(port, gpio & 0x1f, 0);
 }
 
 static void mxs_gpio_unmask_irq(struct irq_data *d)
 {
+	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
 	u32 gpio = irq_to_gpio(d->irq);
-	set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1);
+	set_gpio_irqenable(port, gpio & 0x1f, 1);
 }
 
 static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);
@@ -98,7 +105,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
 {
 	u32 gpio = irq_to_gpio(d->irq);
 	u32 pin_mask = 1 << (gpio & 31);
-	struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
+	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
 	void __iomem *pin_addr;
 	int edge;
 
@@ -142,7 +149,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
 static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
 	u32 irq_stat;
-	struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq);
+	struct mxs_gpio_port *port = irq_get_handler_data(irq);
 	u32 gpio_irq_no_base = port->virtual_irq_start;
 
 	desc->irq_data.chip->irq_ack(&desc->irq_data);
@@ -170,7 +177,7 @@ static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
 {
 	u32 gpio = irq_to_gpio(d->irq);
 	u32 gpio_idx = gpio & 0x1f;
-	struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
+	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
 
 	if (enable) {
 		if (port->irq_high && (gpio_idx >= 16))
@@ -251,47 +258,114 @@ static int mxs_gpio_direction_output(struct gpio_chip *chip,
 	return 0;
 }
 
-int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
+static int __devinit mxs_gpio_probe(struct platform_device *pdev)
 {
-	int i, j;
+	static void __iomem *base;
+	struct mxs_gpio_port *port;
+	struct resource *iores = NULL;
+	int err, i;
+
+	port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
+	if (!port)
+		return -ENOMEM;
+
+	port->id = pdev->id;
+	port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
+
+	/*
+	 * map memory region only once, as all the gpio ports
+	 * share the same one
+	 */
+	if (!base) {
+		iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		if (!iores) {
+			err = -ENODEV;
+			goto out_kfree;
+		}
 
-	/* save for local usage */
-	mxs_gpio_ports = port;
-	gpio_table_size = cnt;
+		if (!request_mem_region(iores->start, resource_size(iores),
+					pdev->name)) {
+			err = -EBUSY;
+			goto out_kfree;
+		}
 
-	pr_info("MXS GPIO hardware\n");
+		base = ioremap(iores->start, resource_size(iores));
+		if (!base) {
+			err = -ENOMEM;
+			goto out_release_mem;
+		}
+	}
+	port->base = base;
 
-	for (i = 0; i < cnt; i++) {
-		/* disable the interrupt and clear the status */
-		writel(0, port[i].base + PINCTRL_PIN2IRQ(i));
-		writel(0, port[i].base + PINCTRL_IRQEN(i));
+	port->irq = platform_get_irq(pdev, 0);
+	if (port->irq < 0) {
+		err = -EINVAL;
+		goto out_iounmap;
+	}
 
-		/* clear address has to be used to clear IRQSTAT bits */
-		writel(~0U, port[i].base + PINCTRL_IRQSTAT(i) + MXS_CLR);
+	/* disable the interrupt and clear the status */
+	writel(0, port->base + PINCTRL_PIN2IRQ(port->id));
+	writel(0, port->base + PINCTRL_IRQEN(port->id));
 
-		for (j = port[i].virtual_irq_start;
-			j < port[i].virtual_irq_start + 32; j++) {
-			irq_set_chip_and_handler(j, &gpio_irq_chip,
-						 handle_level_irq);
-			set_irq_flags(j, IRQF_VALID);
-		}
+	/* clear address has to be used to clear IRQSTAT bits */
+	writel(~0U, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
 
-		/* setup one handler for each entry */
-		irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler);
-		irq_set_handler_data(port[i].irq, &port[i]);
-
-		/* register gpio chip */
-		port[i].chip.direction_input = mxs_gpio_direction_input;
-		port[i].chip.direction_output = mxs_gpio_direction_output;
-		port[i].chip.get = mxs_gpio_get;
-		port[i].chip.set = mxs_gpio_set;
-		port[i].chip.to_irq = mxs_gpio_to_irq;
-		port[i].chip.base = i * 32;
-		port[i].chip.ngpio = 32;
-
-		/* its a serious configuration bug when it fails */
-		BUG_ON(gpiochip_add(&port[i].chip) < 0);
+	for (i = port->virtual_irq_start;
+		i < port->virtual_irq_start + 32; i++) {
+		irq_set_chip_and_handler(i, &gpio_irq_chip,
+					 handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+		irq_set_chip_data(i, port);
 	}
 
+	/* setup one handler for each entry */
+	irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
+	irq_set_handler_data(port->irq, port);
+
+	/* register gpio chip */
+	port->chip.direction_input = mxs_gpio_direction_input;
+	port->chip.direction_output = mxs_gpio_direction_output;
+	port->chip.get = mxs_gpio_get;
+	port->chip.set = mxs_gpio_set;
+	port->chip.to_irq = mxs_gpio_to_irq;
+	port->chip.base = port->id * 32;
+	port->chip.ngpio = 32;
+
+	err = gpiochip_add(&port->chip);
+	if (err)
+		goto out_iounmap;
+
+	platform_set_drvdata(pdev, port);
+
 	return 0;
+
+out_iounmap:
+	if (iores)
+		iounmap(port->base);
+out_release_mem:
+	if (iores)
+		release_mem_region(iores->start, resource_size(iores));
+out_kfree:
+	kfree(port);
+	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
+	return err;
+}
+
+static struct platform_driver mxs_gpio_driver = {
+	.driver		= {
+		.name	= "mxs-gpio",
+	},
+	.probe		= mxs_gpio_probe,
+};
+
+static int __init mxs_gpio_init(void)
+{
+	return platform_driver_register(&mxs_gpio_driver);
 }
+postcore_initcall(mxs_gpio_init);
+
+MODULE_AUTHOR("Freescale Semiconductor, "
+	      "Daniel Mack <danielncaiaq.de>, "
+	      "Juergen Beisert <kernel@pengutronix.de>");
+MODULE_DESCRIPTION("Freescale MXS GPIO");
+MODULE_LICENSE("GPL");
-- 
1.7.4.1

[PATCH 4/4] gpio: gpio-mxs: add gpio driver for Freescale MXS architecture

[Sascha Hauer]

On Fri, May 20, 2011 at 05:51:29PM +0800, Shawn Guo wrote:
> Add gpio-mxs driver by moving arch/arm/mach-mxs/gpio.c into
> drivers/gpio.
> 
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
>  drivers/gpio/Kconfig    |    3 +
>  drivers/gpio/Makefile   |    1 +
>  drivers/gpio/gpio-mxs.c |  168 ++++++++++++++++++++++++++++++++++-------------
>  3 files changed, 125 insertions(+), 47 deletions(-)
> 
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index d3b2953..ccca658 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -81,6 +81,9 @@ config GPIO_IT8761E
>  	help
>  	  Say yes here to support GPIO functionality of IT8761E super I/O chip.
>  
> +config GPIO_MXS
> +	bool
> +
>  config GPIO_PL061
>  	bool "PrimeCell PL061 GPIO support"
>  	depends on ARM_AMBA
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index becef59..b06a335 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_GPIO_MAX7301)	+= max7301.o
>  obj-$(CONFIG_GPIO_MAX732X)	+= max732x.o
>  obj-$(CONFIG_GPIO_MC33880)	+= mc33880.o
>  obj-$(CONFIG_GPIO_MCP23S08)	+= mcp23s08.o
> +obj-$(CONFIG_GPIO_MXS)		+= gpio-mxs.o
>  obj-$(CONFIG_GPIO_74X164)	+= 74x164.o
>  obj-$(CONFIG_GPIO_PCA953X)	+= pca953x.o
>  obj-$(CONFIG_GPIO_PCF857X)	+= pcf857x.o
> diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
> index 6a59bf2..b33b2bc 100644
> --- a/drivers/gpio/gpio-mxs.c
> +++ b/drivers/gpio/gpio-mxs.c
> @@ -25,14 +25,18 @@
>  #include <linux/io.h>
>  #include <linux/irq.h>
>  #include <linux/gpio.h>
> -#include <mach/mx23.h>
> -#include <mach/mx28.h>
> -#include <asm-generic/bug.h>
> -
> -#include "gpio.h"
> -
> -static struct mxs_gpio_port *mxs_gpio_ports;
> -static int gpio_table_size;
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <mach/mxs.h>
> +
> +struct mxs_gpio_port {
> +	void __iomem *base;
> +	int id;
> +	int irq;
> +	int irq_high;
> +	int virtual_irq_start;
> +	struct gpio_chip chip;
> +};
>  
>  #define MXS_SET		0x4
>  #define MXS_CLR		0x8
> @@ -76,20 +80,23 @@ static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
>  
>  static void mxs_gpio_ack_irq(struct irq_data *d)
>  {
> +	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
>  	u32 gpio = irq_to_gpio(d->irq);
> -	clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f);
> +	clear_gpio_irqstatus(port, gpio & 0x1f);
>  }
>  
>  static void mxs_gpio_mask_irq(struct irq_data *d)
>  {
> +	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
>  	u32 gpio = irq_to_gpio(d->irq);
> -	set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0);
> +	set_gpio_irqenable(port, gpio & 0x1f, 0);
>  }
>  
>  static void mxs_gpio_unmask_irq(struct irq_data *d)
>  {
> +	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
>  	u32 gpio = irq_to_gpio(d->irq);
> -	set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1);
> +	set_gpio_irqenable(port, gpio & 0x1f, 1);
>  }
>  
>  static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);
> @@ -98,7 +105,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
>  {
>  	u32 gpio = irq_to_gpio(d->irq);
>  	u32 pin_mask = 1 << (gpio & 31);
> -	struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
> +	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
>  	void __iomem *pin_addr;
>  	int edge;
>  
> @@ -142,7 +149,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
>  static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
>  {
>  	u32 irq_stat;
> -	struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq);
> +	struct mxs_gpio_port *port = irq_get_handler_data(irq);
>  	u32 gpio_irq_no_base = port->virtual_irq_start;
>  
>  	desc->irq_data.chip->irq_ack(&desc->irq_data);
> @@ -170,7 +177,7 @@ static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
>  {
>  	u32 gpio = irq_to_gpio(d->irq);
>  	u32 gpio_idx = gpio & 0x1f;
> -	struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
> +	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
>  
>  	if (enable) {
>  		if (port->irq_high && (gpio_idx >= 16))
> @@ -251,47 +258,114 @@ static int mxs_gpio_direction_output(struct gpio_chip *chip,
>  	return 0;
>  }
>  
> -int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
> +static int __devinit mxs_gpio_probe(struct platform_device *pdev)
>  {
> -	int i, j;
> +	static void __iomem *base;
> +	struct mxs_gpio_port *port;
> +	struct resource *iores = NULL;
> +	int err, i;
> +
> +	port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
> +	if (!port)
> +		return -ENOMEM;
> +
> +	port->id = pdev->id;
> +	port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
> +
> +	/*
> +	 * map memory region only once, as all the gpio ports
> +	 * share the same one
> +	 */
> +	if (!base) {

If the different ports share the same address and can't be seperated I
wonder whether it's better to register only one platform device for all
ports.
(classic) i.MX has a similar problem where one single interrupt is
shared by all gpio ports. Ok, this could be worked around with another
chained handler which dispatches the single interrupt to each port.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH 4/4] gpio: gpio-mxs: add gpio driver for Freescale MXS architecture

[Shawn Guo]

On Fri, May 20, 2011 at 01:24:55PM +0200, Sascha Hauer wrote:
> On Fri, May 20, 2011 at 05:51:29PM +0800, Shawn Guo wrote:
> > Add gpio-mxs driver by moving arch/arm/mach-mxs/gpio.c into
> > drivers/gpio.
> > 
> > Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> > ---
> >  drivers/gpio/Kconfig    |    3 +
> >  drivers/gpio/Makefile   |    1 +
> >  drivers/gpio/gpio-mxs.c |  168 ++++++++++++++++++++++++++++++++++-------------
> >  3 files changed, 125 insertions(+), 47 deletions(-)
> > 
> > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> > index d3b2953..ccca658 100644
> > --- a/drivers/gpio/Kconfig
> > +++ b/drivers/gpio/Kconfig
> > @@ -81,6 +81,9 @@ config GPIO_IT8761E
> >  	help
> >  	  Say yes here to support GPIO functionality of IT8761E super I/O chip.
> >  
> > +config GPIO_MXS
> > +	bool
> > +
> >  config GPIO_PL061
> >  	bool "PrimeCell PL061 GPIO support"
> >  	depends on ARM_AMBA
> > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> > index becef59..b06a335 100644
> > --- a/drivers/gpio/Makefile
> > +++ b/drivers/gpio/Makefile
> > @@ -18,6 +18,7 @@ obj-$(CONFIG_GPIO_MAX7301)	+= max7301.o
> >  obj-$(CONFIG_GPIO_MAX732X)	+= max732x.o
> >  obj-$(CONFIG_GPIO_MC33880)	+= mc33880.o
> >  obj-$(CONFIG_GPIO_MCP23S08)	+= mcp23s08.o
> > +obj-$(CONFIG_GPIO_MXS)		+= gpio-mxs.o
> >  obj-$(CONFIG_GPIO_74X164)	+= 74x164.o
> >  obj-$(CONFIG_GPIO_PCA953X)	+= pca953x.o
> >  obj-$(CONFIG_GPIO_PCF857X)	+= pcf857x.o
> > diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
> > index 6a59bf2..b33b2bc 100644
> > --- a/drivers/gpio/gpio-mxs.c
> > +++ b/drivers/gpio/gpio-mxs.c
> > @@ -25,14 +25,18 @@
> >  #include <linux/io.h>
> >  #include <linux/irq.h>
> >  #include <linux/gpio.h>
> > -#include <mach/mx23.h>
> > -#include <mach/mx28.h>
> > -#include <asm-generic/bug.h>
> > -
> > -#include "gpio.h"
> > -
> > -static struct mxs_gpio_port *mxs_gpio_ports;
> > -static int gpio_table_size;
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +#include <mach/mxs.h>
> > +
> > +struct mxs_gpio_port {
> > +	void __iomem *base;
> > +	int id;
> > +	int irq;
> > +	int irq_high;
> > +	int virtual_irq_start;
> > +	struct gpio_chip chip;
> > +};
> >  
> >  #define MXS_SET		0x4
> >  #define MXS_CLR		0x8
> > @@ -76,20 +80,23 @@ static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
> >  
> >  static void mxs_gpio_ack_irq(struct irq_data *d)
> >  {
> > +	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
> >  	u32 gpio = irq_to_gpio(d->irq);
> > -	clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f);
> > +	clear_gpio_irqstatus(port, gpio & 0x1f);
> >  }
> >  
> >  static void mxs_gpio_mask_irq(struct irq_data *d)
> >  {
> > +	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
> >  	u32 gpio = irq_to_gpio(d->irq);
> > -	set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0);
> > +	set_gpio_irqenable(port, gpio & 0x1f, 0);
> >  }
> >  
> >  static void mxs_gpio_unmask_irq(struct irq_data *d)
> >  {
> > +	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
> >  	u32 gpio = irq_to_gpio(d->irq);
> > -	set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1);
> > +	set_gpio_irqenable(port, gpio & 0x1f, 1);
> >  }
> >  
> >  static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);
> > @@ -98,7 +105,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
> >  {
> >  	u32 gpio = irq_to_gpio(d->irq);
> >  	u32 pin_mask = 1 << (gpio & 31);
> > -	struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
> > +	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
> >  	void __iomem *pin_addr;
> >  	int edge;
> >  
> > @@ -142,7 +149,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
> >  static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
> >  {
> >  	u32 irq_stat;
> > -	struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq);
> > +	struct mxs_gpio_port *port = irq_get_handler_data(irq);
> >  	u32 gpio_irq_no_base = port->virtual_irq_start;
> >  
> >  	desc->irq_data.chip->irq_ack(&desc->irq_data);
> > @@ -170,7 +177,7 @@ static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
> >  {
> >  	u32 gpio = irq_to_gpio(d->irq);
> >  	u32 gpio_idx = gpio & 0x1f;
> > -	struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
> > +	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
> >  
> >  	if (enable) {
> >  		if (port->irq_high && (gpio_idx >= 16))
> > @@ -251,47 +258,114 @@ static int mxs_gpio_direction_output(struct gpio_chip *chip,
> >  	return 0;
> >  }
> >  
> > -int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
> > +static int __devinit mxs_gpio_probe(struct platform_device *pdev)
> >  {
> > -	int i, j;
> > +	static void __iomem *base;
> > +	struct mxs_gpio_port *port;
> > +	struct resource *iores = NULL;
> > +	int err, i;
> > +
> > +	port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
> > +	if (!port)
> > +		return -ENOMEM;
> > +
> > +	port->id = pdev->id;
> > +	port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
> > +
> > +	/*
> > +	 * map memory region only once, as all the gpio ports
> > +	 * share the same one
> > +	 */
> > +	if (!base) {
> 
> If the different ports share the same address and can't be seperated I
> wonder whether it's better to register only one platform device for all
> ports.

gpio-u300 is one example that register one platform device for all
ports.  Comparing to it, the gpio-mxs driver looks simpler and
cleaner, and there is no platform data.

We may agree that every single port should register its own platform
device, if the ports are all independent to each other with their own
base address.  Then same base address could be special case of
different base address, so that we can make driver implementation
a little common for both cases.

If people think these two cases (sharing ports vs. independent ports)
will be sorted into two different patterns, yes, gpio-mxs should go
the way that gpio-u300 is going.

So please comment, people (Grant? :)

> (classic) i.MX has a similar problem where one single interrupt is
> shared by all gpio ports. Ok, this could be worked around with another
> chained handler which dispatches the single interrupt to each port.
> 

-- 
Regards,
Shawn

[PATCH 0/4] add gpio driver gpio-mxs

[Sascha Hauer]

Hi Shawn,

On Fri, May 20, 2011 at 05:51:25PM +0800, Shawn Guo wrote:
> The patch set is to move Freescale MXS gpio driver from mach-mxs
> into drivers/gpio.  Different from u300 gpio driver that all gpio
> ports are registered as one device, gpio-mxs expects every single
> port is a gpio device.
> 
> The first 3 patches are just to ease review and can be squashed into
> the last one.
> 
> Shawn Guo (4):
>       gpio: gpio-mxs: add file gpio-mxs.c
>       gpio: gpio-mxs: drop mach-specific accessors
>       gpio: gpio-mxs: remove gpio port definition and registration
>       gpio: gpio-mxs: add gpio driver for Freescale MXS architecture

Your series should be bisectible. So please either:

- Add the driver the way you want it (no need to modify a new file in
  four steps)
- atomically switch to the new driver
- remove old driver

or:

- work on old file until it's suitable for drivers/gpio
- move old file to drivers/gpio and adjust the makefiles in one step.


There may be different variations on this depending on the actual code,
but whatever you do, each step should be able to compile and working.


Sascha

-- 
Pengutronix e.K.                           |                             |
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[PATCH 0/4] add gpio driver gpio-mxs

[Sascha Hauer]

On Fri, May 20, 2011 at 06:24:11PM +0800, Shawn Guo wrote:
> On Fri, May 20, 2011 at 12:02:42PM +0200, Sascha Hauer wrote:
> > Hi Shawn,
> > 
> Hi Sascha,
> 
> > On Fri, May 20, 2011 at 05:51:25PM +0800, Shawn Guo wrote:
> > > The patch set is to move Freescale MXS gpio driver from mach-mxs
> > > into drivers/gpio.  Different from u300 gpio driver that all gpio
> > > ports are registered as one device, gpio-mxs expects every single
> > > port is a gpio device.
> > > 
> > > The first 3 patches are just to ease review and can be squashed into
> > > the last one.
> > > 
> > > Shawn Guo (4):
> > >       gpio: gpio-mxs: add file gpio-mxs.c
> > >       gpio: gpio-mxs: drop mach-specific accessors
> > >       gpio: gpio-mxs: remove gpio port definition and registration
> > >       gpio: gpio-mxs: add gpio driver for Freescale MXS architecture
> > 
> > Your series should be bisectible. So please either:
> > 
> > - Add the driver the way you want it (no need to modify a new file in
> >   four steps)
> 
> As I said above, I split it into 4 patches just to ease the review,
> and they can be squashed into one when applying.
> 
> > - atomically switch to the new driver
> > - remove old driver
> > 
> These two steps happened in the patch set '[PATCH 0/3] remove mach-mxs
> gpio driver'.  The patch order should be reworked though.
> 
> BTW, are you looking at moving plat-mxc/gpio.c, or I can give a hand
> there?

I'm not working on this, go ahead.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH 0/4] add gpio driver gpio-mxs

[Grant Likely]

On Fri, May 20, 2011 at 06:24:11PM +0800, Shawn Guo wrote:
> On Fri, May 20, 2011 at 12:02:42PM +0200, Sascha Hauer wrote:
> > Hi Shawn,
> > 
> Hi Sascha,
> 
> > On Fri, May 20, 2011 at 05:51:25PM +0800, Shawn Guo wrote:
> > > The patch set is to move Freescale MXS gpio driver from mach-mxs
> > > into drivers/gpio.  Different from u300 gpio driver that all gpio
> > > ports are registered as one device, gpio-mxs expects every single
> > > port is a gpio device.
> > > 
> > > The first 3 patches are just to ease review and can be squashed into
> > > the last one.
> > > 
> > > Shawn Guo (4):
> > >       gpio: gpio-mxs: add file gpio-mxs.c
> > >       gpio: gpio-mxs: drop mach-specific accessors
> > >       gpio: gpio-mxs: remove gpio port definition and registration
> > >       gpio: gpio-mxs: add gpio driver for Freescale MXS architecture
> > 
> > Your series should be bisectible. So please either:
> > 
> > - Add the driver the way you want it (no need to modify a new file in
> >   four steps)
> 
> As I said above, I split it into 4 patches just to ease the review,
> and they can be squashed into one when applying.

If you use the -M flag when posting the patch, then the diff will show
both that the file has moved, and also only show the changes made to
the file when it was moved.  That way you can squash the series into
one.

g.