[PATCH 00/11] Core support for Cortex-A5 and Cortex-A15

[PATCH 00/11] Core support for Cortex-A5 and Cortex-A15

[Will Deacon]

Hello,

Here is a patch series for adding support for the Cortex-A5 and
Cortex-A15 cores to Linux. The first two patches (from Pawel) are
already in Russell's patch system, but I included them here for
completeness.

Anyway, the main thing is the HWCAP stuff as the perf stuff is all
rather boring.

Enjoy!

Will


Pawel Moll (2):
  arm: Convert v7 proc infos into a common macro
  arm: Add Cortex A5 proc info

Will Deacon (9):
  ARM: hwcaps: use shifts instead of hardcoded constants
  ARM: hwcaps: add new HWCAP defines for ARMv7-A
  ARM: proc: reorder macro parameters for __v7_proc macro
  ARM: cortex-a5: add HWCAP_VFPv4D16 to proc info structure
  ARM: proc: add proc info for Cortex-A15MP using classic page tables
  ARM: perf: remove confusing comment from v7 perf events backend
  ARM: perf: add PMUv2 common event definitions
  ARM: perf: add support for the Cortex-A5 PMU
  ARM: perf: add support for the Cortex-A15 PMU

 arch/arm/include/asm/hwcap.h      |   37 +++--
 arch/arm/include/asm/perf_event.h |    2 +
 arch/arm/kernel/perf_event.c      |    6 +
 arch/arm/kernel/perf_event_v7.c   |  344 ++++++++++++++++++++++++++++++++++--
 arch/arm/mm/proc-v7.S             |   98 ++++++-----
 5 files changed, 406 insertions(+), 81 deletions(-)

[PATCH 01/11] arm: Convert v7 proc infos into a common macro

[Will Deacon]

From: Pawel Moll <pawel.moll@arm.com>

As most of the proc info content is common across all v7
processors, this patch converts existing A9 and generic v7
descriptions into a macro (allowing extra flags in future).

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
 arch/arm/mm/proc-v7.S |   67 +++++++++++++++++-------------------------------
 1 files changed, 24 insertions(+), 43 deletions(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b3b566e..d5245d4 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -436,33 +436,36 @@ cpu_elf_name:
 
 	.section ".proc.info.init", #alloc, #execinstr
 
-	.type   __v7_ca9mp_proc_info, #object
-__v7_ca9mp_proc_info:
-	.long	0x410fc090		@ Required ID value
-	.long	0xff0ffff0		@ Mask for ID
-	ALT_SMP(.long \
-		PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ | \
-		PMD_FLAGS_SMP)
-	ALT_UP(.long \
-		PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ | \
-		PMD_FLAGS_UP)
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_XN | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	W(b)	__v7_ca9mp_setup
+	/*
+	 * Standard v7 proc info content
+	 */
+.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
+	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
+			PMD_FLAGS_SMP | \mm_mmuflags)
+	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
+			PMD_FLAGS_UP | \mm_mmuflags)
+	.long	PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \io_mmuflags
+	W(b)	\initfunc
 	.long	cpu_arch_name
 	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
+	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
+		HWCAP_EDSP | HWCAP_TLS | \hwcaps
 	.long	cpu_v7_name
 	.long	v7_processor_functions
 	.long	v7wbi_tlb_fns
 	.long	v6_user_fns
 	.long	v7_cache_fns
+.endm
+
+	/*
+	 * ARM Ltd. Cortex A9 processor.
+	 */
+	.type   __v7_ca9mp_proc_info, #object
+__v7_ca9mp_proc_info:
+	.long	0x410fc090
+	.long	0xff0ffff0
+	__v7_proc __v7_ca9mp_setup
 	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
 
 	/*
@@ -472,27 +475,5 @@ __v7_ca9mp_proc_info:
 __v7_proc_info:
 	.long	0x000f0000		@ Required ID value
 	.long	0x000f0000		@ Mask for ID
-	ALT_SMP(.long \
-		PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ | \
-		PMD_FLAGS_SMP)
-	ALT_UP(.long \
-		PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ | \
-		PMD_FLAGS_UP)
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_XN | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	W(b)	__v7_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
-	.long	cpu_v7_name
-	.long	v7_processor_functions
-	.long	v7wbi_tlb_fns
-	.long	v6_user_fns
-	.long	v7_cache_fns
+	__v7_proc __v7_setup
 	.size	__v7_proc_info, . - __v7_proc_info
-- 
1.7.0.4

[PATCH 02/11] arm: Add Cortex A5 proc info

[Will Deacon]

From: Pawel Moll <pawel.moll@arm.com>

This patch adds processor info for ARM Ltd. Cortex A5,
which has SCU initialisation procedure identical to A9.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
 arch/arm/mm/proc-v7.S |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index d5245d4..7f482c2 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -273,6 +273,7 @@ cpu_resume_l1_flags:
  *	It is assumed that:
  *	- cache type register is implemented
  */
+__v7_ca5mp_setup:
 __v7_ca9mp_setup:
 #ifdef CONFIG_SMP
 	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
@@ -459,6 +460,16 @@ cpu_elf_name:
 .endm
 
 	/*
+	 * ARM Ltd. Cortex A5 processor.
+	 */
+	.type   __v7_ca5mp_proc_info, #object
+__v7_ca5mp_proc_info:
+	.long	0x410fc050
+	.long	0xff0ffff0
+	__v7_proc __v7_ca5mp_setup
+	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
+
+	/*
 	 * ARM Ltd. Cortex A9 processor.
 	 */
 	.type   __v7_ca9mp_proc_info, #object
-- 
1.7.0.4

[PATCH 03/11] ARM: hwcaps: use shifts instead of hardcoded constants

[Will Deacon]

The HWCAP numbers are defined as constants, each one being a power of 2.
This has become slightly unwieldy now that we have reached 32k.

This patch changes the HWCAP defines to use (1 << n) instead of coding
the constant directly. The values remain unchanged.

Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/include/asm/hwcap.h |   32 ++++++++++++++++----------------
 1 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index c1062c3..81512db 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -4,22 +4,22 @@
 /*
  * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
  */
-#define HWCAP_SWP	1
-#define HWCAP_HALF	2
-#define HWCAP_THUMB	4
-#define HWCAP_26BIT	8	/* Play it safe */
-#define HWCAP_FAST_MULT	16
-#define HWCAP_FPA	32
-#define HWCAP_VFP	64
-#define HWCAP_EDSP	128
-#define HWCAP_JAVA	256
-#define HWCAP_IWMMXT	512
-#define HWCAP_CRUNCH	1024
-#define HWCAP_THUMBEE	2048
-#define HWCAP_NEON	4096
-#define HWCAP_VFPv3	8192
-#define HWCAP_VFPv3D16	16384
-#define HWCAP_TLS	32768
+#define HWCAP_SWP	(1 << 0)
+#define HWCAP_HALF	(1 << 1)
+#define HWCAP_THUMB	(1 << 2)
+#define HWCAP_26BIT	(1 << 3)	/* Play it safe */
+#define HWCAP_FAST_MULT	(1 << 4)
+#define HWCAP_FPA	(1 << 5)
+#define HWCAP_VFP	(1 << 6)
+#define HWCAP_EDSP	(1 << 7)
+#define HWCAP_JAVA	(1 << 8)
+#define HWCAP_IWMMXT	(1 << 9)
+#define HWCAP_CRUNCH	(1 << 10)
+#define HWCAP_THUMBEE	(1 << 11)
+#define HWCAP_NEON	(1 << 12)
+#define HWCAP_VFPv3	(1 << 13)
+#define HWCAP_VFPv3D16	(1 << 14)
+#define HWCAP_TLS	(1 << 15)
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 /*
-- 
1.7.0.4

[PATCH 04/11] ARM: hwcaps: add new HWCAP defines for ARMv7-A

[Will Deacon]

Modern ARMv7-A cores can optionally implement these new hardware
features:

- VFPv4:
    The latest version of the ARMv7 vector floating-point extensions,
    including hardware support for fused multiple accumulate. D16 or D32
    variants may be implemented.

- Integer divide:
    The SDIV and UDIV instructions provide signed and unsigned integer
    division in hardware. When implemented, these instructions may be
    available in either both Thumb and ARM, or Thumb only.

This patch adds new HWCAP defines to describe these new features. The
integer divide capabilities are split into two bits for ARM and Thumb
respectively. Whilst HWCAP_IDIVA should never bet set if HWCAP_IDIVT is
clear, separating the bits makes it easier to interpret from userspace.

Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/include/asm/hwcap.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index 81512db..69d69f5 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -20,6 +20,11 @@
 #define HWCAP_VFPv3	(1 << 13)
 #define HWCAP_VFPv3D16	(1 << 14)
 #define HWCAP_TLS	(1 << 15)
+#define HWCAP_VFPv4	(1 << 16)
+#define HWCAP_VFPv4D16	(1 << 17)
+#define HWCAP_IDIVA	(1 << 18)
+#define HWCAP_IDIVT	(1 << 19)
+#define HWCAP_IDIV	(HWCAP_IDIVA | HWCAP_IDIVT)
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 /*
-- 
1.7.0.4

[PATCH 05/11] ARM: proc: reorder macro parameters for __v7_proc macro

[Will Deacon]

The __v7_proc macro takes paramaters for mmu flags, io flags and hwcaps.

Since hwcaps tend to change more often between cores than the other
parameters, change the ordering so we don't have to provide empty values
for the flag arguments in the common case.

Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/mm/proc-v7.S |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7f482c2..b22d98d 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -440,7 +440,7 @@ cpu_elf_name:
 	/*
 	 * Standard v7 proc info content
 	 */
-.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
+.macro __v7_proc initfunc, hwcaps = 0, mm_mmuflags = 0, io_mmuflags = 0
 	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 			PMD_FLAGS_SMP | \mm_mmuflags)
 	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
-- 
1.7.0.4

[PATCH 06/11] ARM: cortex-a5: add HWCAP_VFPv4D16 to proc info structure

[Will Deacon]

The Cortex-A5 implements VFPv4D16, so add this to the hwcaps for this
processor.

Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/mm/proc-v7.S |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b22d98d..8eba506 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -466,7 +466,7 @@ cpu_elf_name:
 __v7_ca5mp_proc_info:
 	.long	0x410fc050
 	.long	0xff0ffff0
-	__v7_proc __v7_ca5mp_setup
+	__v7_proc __v7_ca5mp_setup, HWCAP_VFPv4D16
 	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
 
 	/*
-- 
1.7.0.4

[PATCH 06/11] ARM: cortex-a5: add HWCAP_VFPv4D16 to proc info structure

[Dave Martin]

On Mon, Jun 06, 2011 at 05:55:50PM +0100, Will Deacon wrote:
> The Cortex-A5 implements VFPv4D16, so add this to the hwcaps for this
> processor.
> 
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
>  arch/arm/mm/proc-v7.S |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index b22d98d..8eba506 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -466,7 +466,7 @@ cpu_elf_name:
>  __v7_ca5mp_proc_info:
>  	.long	0x410fc050
>  	.long	0xff0ffff0
> -	__v7_proc __v7_ca5mp_setup
> +	__v7_proc __v7_ca5mp_setup, HWCAP_VFPv4D16

Is VFPv4 a superset of VFPv3?  If so, should we also include
HWCAP_VFPv3D16 (and what about HWCAP_VFP)?

>  	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
>  
>  	/*
> -- 
> 1.7.0.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 06/11] ARM: cortex-a5: add HWCAP_VFPv4D16 to proc info structure

[Will Deacon]

On Tue, Jun 07, 2011 at 05:17:36PM +0100, Dave Martin wrote:
> On Mon, Jun 06, 2011 at 05:55:50PM +0100, Will Deacon wrote:
> > The Cortex-A5 implements VFPv4D16, so add this to the hwcaps for this
> > processor.
> > 
> > Signed-off-by: Will Deacon <will.deacon@arm.com>
> > ---
> >  arch/arm/mm/proc-v7.S |    2 +-
> >  1 files changed, 1 insertions(+), 1 deletions(-)
> > 
> > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> > index b22d98d..8eba506 100644
> > --- a/arch/arm/mm/proc-v7.S
> > +++ b/arch/arm/mm/proc-v7.S
> > @@ -466,7 +466,7 @@ cpu_elf_name:
> >  __v7_ca5mp_proc_info:
> >  	.long	0x410fc050
> >  	.long	0xff0ffff0
> > -	__v7_proc __v7_ca5mp_setup
> > +	__v7_proc __v7_ca5mp_setup, HWCAP_VFPv4D16
> 
> Is VFPv4 a superset of VFPv3?  If so, should we also include
> HWCAP_VFPv3D16 (and what about HWCAP_VFP)?
>

Actually, it looks like this shouldn't be declared statically at all, since the
kernel have not have VFP support compiled in. Rather, the vfp code will detect
the capability and adjust elf_hwcap at runtime.

Will

[PATCH 06/11] ARM: cortex-a5: add HWCAP_VFPv4D16 to proc info structure

[Dave Martin]

On Tue, Jun 07, 2011 at 05:22:04PM +0100, Will Deacon wrote:
> On Tue, Jun 07, 2011 at 05:17:36PM +0100, Dave Martin wrote:
> > On Mon, Jun 06, 2011 at 05:55:50PM +0100, Will Deacon wrote:
> > > The Cortex-A5 implements VFPv4D16, so add this to the hwcaps for this
> > > processor.
> > > 
> > > Signed-off-by: Will Deacon <will.deacon@arm.com>
> > > ---
> > >  arch/arm/mm/proc-v7.S |    2 +-
> > >  1 files changed, 1 insertions(+), 1 deletions(-)
> > > 
> > > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> > > index b22d98d..8eba506 100644
> > > --- a/arch/arm/mm/proc-v7.S
> > > +++ b/arch/arm/mm/proc-v7.S
> > > @@ -466,7 +466,7 @@ cpu_elf_name:
> > >  __v7_ca5mp_proc_info:
> > >  	.long	0x410fc050
> > >  	.long	0xff0ffff0
> > > -	__v7_proc __v7_ca5mp_setup
> > > +	__v7_proc __v7_ca5mp_setup, HWCAP_VFPv4D16
> > 
> > Is VFPv4 a superset of VFPv3?  If so, should we also include
> > HWCAP_VFPv3D16 (and what about HWCAP_VFP)?
> >
> 
> Actually, it looks like this shouldn't be declared statically at all, since the
> kernel have not have VFP support compiled in. Rather, the vfp code will detect
> the capability and adjust elf_hwcap at runtime.

Hah, yes, quite right.  My bad.

---Dave

[PATCH 06/11] ARM: cortex-a5: add HWCAP_VFPv4D16 to proc info structure

[Will Deacon]

On Wed, Jun 08, 2011 at 10:05:01AM +0100, Dave Martin wrote:
> On Tue, Jun 07, 2011 at 05:22:04PM +0100, Will Deacon wrote:
> > On Tue, Jun 07, 2011 at 05:17:36PM +0100, Dave Martin wrote:
> > > On Mon, Jun 06, 2011 at 05:55:50PM +0100, Will Deacon wrote:
> > > > The Cortex-A5 implements VFPv4D16, so add this to the hwcaps for this
> > > > processor.
> > > > 
> > > > Signed-off-by: Will Deacon <will.deacon@arm.com>
> > > > ---
> > > >  arch/arm/mm/proc-v7.S |    2 +-
> > > >  1 files changed, 1 insertions(+), 1 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> > > > index b22d98d..8eba506 100644
> > > > --- a/arch/arm/mm/proc-v7.S
> > > > +++ b/arch/arm/mm/proc-v7.S
> > > > @@ -466,7 +466,7 @@ cpu_elf_name:
> > > >  __v7_ca5mp_proc_info:
> > > >  	.long	0x410fc050
> > > >  	.long	0xff0ffff0
> > > > -	__v7_proc __v7_ca5mp_setup
> > > > +	__v7_proc __v7_ca5mp_setup, HWCAP_VFPv4D16
> > > 
> > > Is VFPv4 a superset of VFPv3?  If so, should we also include
> > > HWCAP_VFPv3D16 (and what about HWCAP_VFP)?
> > >
> > 
> > Actually, it looks like this shouldn't be declared statically at all, since the
> > kernel have not have VFP support compiled in. Rather, the vfp code will detect
> > the capability and adjust elf_hwcap at runtime.
> 
> Hah, yes, quite right.  My bad.

I'll fix it for v2.

As for the D16 stuff, I've had a better idea [need to check with the tools
guys]. Rather than waste two bits for VFPv4 and VFPv4D16, it should probably
be something like:

VFPv3    : HWCAP_VFPv3
VFPv3D16 : HWCAP_VFPv3 | HWCAP_VFPv3D16
VFPv4    : HWCAP_VFPv3 | HWCAP_VFPv4
VFPv4D16 : HWCAP_VFPv3 | HWCAP_VFPv3D16 | HWCAP_VFPv4

Will

[PATCH 07/11] ARM: proc: add proc info for Cortex-A15MP using classic page tables

[Will Deacon]

Multicore implementations of the Cortex-A15 require bit 6 of the
auxiliary control register to be set in order for cache and TLB
maintenance operations to be broadcast between CPUs.

This patch adds a new proc_info structure for Cortex-A15, which enables
the SMP bit during setup and includes the new HWCAPs for integer
division and VFPv4.

Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/mm/proc-v7.S |   20 ++++++++++++++++++--
 1 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 8eba506..1e74e16 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -275,12 +275,18 @@ cpu_resume_l1_flags:
  */
 __v7_ca5mp_setup:
 __v7_ca9mp_setup:
+	mov	r10, #(1 << 0)			@ TLB ops broadcasting
+	b	1f
+__v7_ca15mp_setup:
+	mov	r10, #0
+1:
 #ifdef CONFIG_SMP
 	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
 	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
 	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
-	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
-	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
+	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
+	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
+	mcreq	p15, 0, r0, c1, c0, 1
 #endif
 __v7_setup:
 	adr	r12, __v7_setup_stack		@ the local stack
@@ -480,6 +486,16 @@ __v7_ca9mp_proc_info:
 	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
 
 	/*
+	 * ARM Ltd. Cortex A15 processor.
+	 */
+	.type	__v7_ca15mp_proc_info, #object
+__v7_ca15mp_proc_info:
+	.long	0x410fc0f0
+	.long	0xff0ffff0
+	__v7_proc __v7_ca15mp_setup, HWCAP_VFPv4 | HWCAP_IDIV
+	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
+
+	/*
 	 * Match any ARMv7 processor core.
 	 */
 	.type	__v7_proc_info, #object
-- 
1.7.0.4

[PATCH 07/11] ARM: proc: add proc info for Cortex-A15MP using classic page tables

[Dave Martin]

On Mon, Jun 06, 2011 at 05:55:51PM +0100, Will Deacon wrote:
> Multicore implementations of the Cortex-A15 require bit 6 of the
> auxiliary control register to be set in order for cache and TLB
> maintenance operations to be broadcast between CPUs.
> 
> This patch adds a new proc_info structure for Cortex-A15, which enables
> the SMP bit during setup and includes the new HWCAPs for integer
> division and VFPv4.
> 
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
>  arch/arm/mm/proc-v7.S |   20 ++++++++++++++++++--
>  1 files changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 8eba506..1e74e16 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -275,12 +275,18 @@ cpu_resume_l1_flags:
>   */
>  __v7_ca5mp_setup:
>  __v7_ca9mp_setup:
> +	mov	r10, #(1 << 0)			@ TLB ops broadcasting
> +	b	1f
> +__v7_ca15mp_setup:
> +	mov	r10, #0
> +1:
>  #ifdef CONFIG_SMP
>  	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
>  	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
>  	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
> -	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
> -	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
> +	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
> +	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
> +	mcreq	p15, 0, r0, c1, c0, 1
>  #endif
>  __v7_setup:
>  	adr	r12, __v7_setup_stack		@ the local stack
> @@ -480,6 +486,16 @@ __v7_ca9mp_proc_info:
>  	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
>  
>  	/*
> +	 * ARM Ltd. Cortex A15 processor.
> +	 */
> +	.type	__v7_ca15mp_proc_info, #object
> +__v7_ca15mp_proc_info:
> +	.long	0x410fc0f0
> +	.long	0xff0ffff0
> +	__v7_proc __v7_ca15mp_setup, HWCAP_VFPv4 | HWCAP_IDIV

As for A5, do we need to include additional VFP hwcap flags?

---Dave

[PATCH 08/11] ARM: perf: remove confusing comment from v7 perf events backend

[Will Deacon]

The comment about measuring TLB misses and refills in the ARMv7 perf
backend makes little sense and refers loosely to raw counters that
should be used instead.

This patch removes the comments to avoid any confusion.

Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/kernel/perf_event_v7.c |   10 ----------
 1 files changed, 0 insertions(+), 10 deletions(-)

diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 4960686..554eba3 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -207,11 +207,6 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 		},
 	},
 	[C(DTLB)] = {
-		/*
-		 * Only ITLB misses and DTLB refills are supported.
-		 * If users want the DTLB refills misses a raw counter
-		 * must be used.
-		 */
 		[C(OP_READ)] = {
 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
 			[C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
@@ -323,11 +318,6 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 		},
 	},
 	[C(DTLB)] = {
-		/*
-		 * Only ITLB misses and DTLB refills are supported.
-		 * If users want the DTLB refills misses a raw counter
-		 * must be used.
-		 */
 		[C(OP_READ)] = {
 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
 			[C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
-- 
1.7.0.4

[PATCH 09/11] ARM: perf: add PMUv2 common event definitions

[Will Deacon]

The PMUv2 specification reserves a number of event encodings
for common events.

This patch adds these events to the common event enumeration
in preparation for PMUv2 cores, such as Cortex-A15.

Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/kernel/perf_event_v7.c |   35 +++++++++++++++++++++++++----------
 1 files changed, 25 insertions(+), 10 deletions(-)

diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 554eba3..01b1145 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -17,17 +17,23 @@
  */
 
 #ifdef CONFIG_CPU_V7
-/* Common ARMv7 event types */
+/*
+ * Common ARMv7 event types
+ *
+ * Note: An implementation may not be able to count all of these events
+ * but the encodings are considered to be `reserved' in the case that
+ * they are not available.
+ */
 enum armv7_perf_types {
 	ARMV7_PERFCTR_PMNC_SW_INCR		= 0x00,
 	ARMV7_PERFCTR_IFETCH_MISS		= 0x01,
 	ARMV7_PERFCTR_ITLB_MISS			= 0x02,
-	ARMV7_PERFCTR_DCACHE_REFILL		= 0x03,
-	ARMV7_PERFCTR_DCACHE_ACCESS		= 0x04,
+	ARMV7_PERFCTR_DCACHE_REFILL		= 0x03,	/* L1 */
+	ARMV7_PERFCTR_DCACHE_ACCESS		= 0x04,	/* L1 */
 	ARMV7_PERFCTR_DTLB_REFILL		= 0x05,
 	ARMV7_PERFCTR_DREAD			= 0x06,
 	ARMV7_PERFCTR_DWRITE			= 0x07,
-
+	ARMV7_PERFCTR_INSTR_EXECUTED		= 0x08,
 	ARMV7_PERFCTR_EXC_TAKEN			= 0x09,
 	ARMV7_PERFCTR_EXC_EXECUTED		= 0x0A,
 	ARMV7_PERFCTR_CID_WRITE			= 0x0B,
@@ -39,21 +45,30 @@ enum armv7_perf_types {
 	 */
 	ARMV7_PERFCTR_PC_WRITE			= 0x0C,
 	ARMV7_PERFCTR_PC_IMM_BRANCH		= 0x0D,
+	ARMV7_PERFCTR_PC_PROC_RETURN		= 0x0E,
 	ARMV7_PERFCTR_UNALIGNED_ACCESS		= 0x0F,
+
+	/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
 	ARMV7_PERFCTR_PC_BRANCH_MIS_PRED	= 0x10,
 	ARMV7_PERFCTR_CLOCK_CYCLES		= 0x11,
-
-	ARMV7_PERFCTR_PC_BRANCH_MIS_USED	= 0x12,
+	ARMV7_PERFCTR_PC_BRANCH_PRED		= 0x12,
+	ARMV7_PERFCTR_MEM_ACCESS		= 0x13,
+	ARMV7_PERFCTR_L1_ICACHE_ACCESS		= 0x14,
+	ARMV7_PERFCTR_L1_DCACHE_WB		= 0x15,
+	ARMV7_PERFCTR_L2_DCACHE_ACCESS		= 0x16,
+	ARMV7_PERFCTR_L2_DCACHE_REFILL		= 0x17,
+	ARMV7_PERFCTR_L2_DCACHE_WB		= 0x18,
+	ARMV7_PERFCTR_BUS_ACCESS		= 0x19,
+	ARMV7_PERFCTR_MEMORY_ERROR		= 0x1A,
+	ARMV7_PERFCTR_INSTR_SPEC		= 0x1B,
+	ARMV7_PERFCTR_TTBR_WRITE		= 0x1C,
+	ARMV7_PERFCTR_BUS_CYCLES		= 0x1D,
 
 	ARMV7_PERFCTR_CPU_CYCLES		= 0xFF
 };
 
 /* ARMv7 Cortex-A8 specific event types */
 enum armv7_a8_perf_types {
-	ARMV7_PERFCTR_INSTR_EXECUTED		= 0x08,
-
-	ARMV7_PERFCTR_PC_PROC_RETURN		= 0x0E,
-
 	ARMV7_PERFCTR_WRITE_BUFFER_FULL		= 0x40,
 	ARMV7_PERFCTR_L2_STORE_MERGED		= 0x41,
 	ARMV7_PERFCTR_L2_STORE_BUFF		= 0x42,
-- 
1.7.0.4

[PATCH 09/11] ARM: perf: add PMUv2 common event definitions

[Jean Pihet]

Hi Will,

On Mon, Jun 6, 2011 at 6:55 PM, Will Deacon <will.deacon@arm.com> wrote:
> The PMUv2 specification reserves a number of event encodings
> for common events.
>
> This patch adds these events to the common event enumeration
> in preparation for PMUv2 cores, such as Cortex-A15.
>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
> ?arch/arm/kernel/perf_event_v7.c | ? 35 +++++++++++++++++++++++++----------
> ?1 files changed, 25 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
> index 554eba3..01b1145 100644
> --- a/arch/arm/kernel/perf_event_v7.c
> +++ b/arch/arm/kernel/perf_event_v7.c
> @@ -17,17 +17,23 @@
> ?*/
>
> ?#ifdef CONFIG_CPU_V7
> -/* Common ARMv7 event types */
> +/*
> + * Common ARMv7 event types
> + *
> + * Note: An implementation may not be able to count all of these events
> + * but the encodings are considered to be `reserved' in the case that
> + * they are not available.
> + */
> ?enum armv7_perf_types {
> ? ? ? ?ARMV7_PERFCTR_PMNC_SW_INCR ? ? ? ? ? ? ?= 0x00,
> ? ? ? ?ARMV7_PERFCTR_IFETCH_MISS ? ? ? ? ? ? ? = 0x01,
> ? ? ? ?ARMV7_PERFCTR_ITLB_MISS ? ? ? ? ? ? ? ? = 0x02,
> - ? ? ? ARMV7_PERFCTR_DCACHE_REFILL ? ? ? ? ? ? = 0x03,
> - ? ? ? ARMV7_PERFCTR_DCACHE_ACCESS ? ? ? ? ? ? = 0x04,
> + ? ? ? ARMV7_PERFCTR_DCACHE_REFILL ? ? ? ? ? ? = 0x03, /* L1 */
> + ? ? ? ARMV7_PERFCTR_DCACHE_ACCESS ? ? ? ? ? ? = 0x04, /* L1 */
> ? ? ? ?ARMV7_PERFCTR_DTLB_REFILL ? ? ? ? ? ? ? = 0x05,
> ? ? ? ?ARMV7_PERFCTR_DREAD ? ? ? ? ? ? ? ? ? ? = 0x06,
> ? ? ? ?ARMV7_PERFCTR_DWRITE ? ? ? ? ? ? ? ? ? ?= 0x07,
> -
> + ? ? ? ARMV7_PERFCTR_INSTR_EXECUTED ? ? ? ? ? ?= 0x08,
> ? ? ? ?ARMV7_PERFCTR_EXC_TAKEN ? ? ? ? ? ? ? ? = 0x09,
> ? ? ? ?ARMV7_PERFCTR_EXC_EXECUTED ? ? ? ? ? ? ?= 0x0A,
> ? ? ? ?ARMV7_PERFCTR_CID_WRITE ? ? ? ? ? ? ? ? = 0x0B,
> @@ -39,21 +45,30 @@ enum armv7_perf_types {
> ? ? ? ? */
> ? ? ? ?ARMV7_PERFCTR_PC_WRITE ? ? ? ? ? ? ? ? ?= 0x0C,
> ? ? ? ?ARMV7_PERFCTR_PC_IMM_BRANCH ? ? ? ? ? ? = 0x0D,
> + ? ? ? ARMV7_PERFCTR_PC_PROC_RETURN ? ? ? ? ? ?= 0x0E,
Will ARMV7_PERFCTR_INSTR_EXECUTED and ARMV7_PERFCTR_PC_PROC_RETURN
work for all v7 implementations? For example they are not defined for
A9.

> ? ? ? ?ARMV7_PERFCTR_UNALIGNED_ACCESS ? ? ? ? ?= 0x0F,
> +
> + ? ? ? /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
> ? ? ? ?ARMV7_PERFCTR_PC_BRANCH_MIS_PRED ? ? ? ?= 0x10,
> ? ? ? ?ARMV7_PERFCTR_CLOCK_CYCLES ? ? ? ? ? ? ?= 0x11,
> -
> - ? ? ? ARMV7_PERFCTR_PC_BRANCH_MIS_USED ? ? ? ?= 0x12,
> + ? ? ? ARMV7_PERFCTR_PC_BRANCH_PRED ? ? ? ? ? ?= 0x12,
> + ? ? ? ARMV7_PERFCTR_MEM_ACCESS ? ? ? ? ? ? ? ?= 0x13,
> + ? ? ? ARMV7_PERFCTR_L1_ICACHE_ACCESS ? ? ? ? ?= 0x14,
> + ? ? ? ARMV7_PERFCTR_L1_DCACHE_WB ? ? ? ? ? ? ?= 0x15,
> + ? ? ? ARMV7_PERFCTR_L2_DCACHE_ACCESS ? ? ? ? ?= 0x16,
> + ? ? ? ARMV7_PERFCTR_L2_DCACHE_REFILL ? ? ? ? ?= 0x17,
> + ? ? ? ARMV7_PERFCTR_L2_DCACHE_WB ? ? ? ? ? ? ?= 0x18,
> + ? ? ? ARMV7_PERFCTR_BUS_ACCESS ? ? ? ? ? ? ? ?= 0x19,
> + ? ? ? ARMV7_PERFCTR_MEMORY_ERROR ? ? ? ? ? ? ?= 0x1A,
> + ? ? ? ARMV7_PERFCTR_INSTR_SPEC ? ? ? ? ? ? ? ?= 0x1B,
> + ? ? ? ARMV7_PERFCTR_TTBR_WRITE ? ? ? ? ? ? ? ?= 0x1C,
> + ? ? ? ARMV7_PERFCTR_BUS_CYCLES ? ? ? ? ? ? ? ?= 0x1D,
Same question for those new events that are not defined for A8 and A9.

Thanks,
Jean

>
> ? ? ? ?ARMV7_PERFCTR_CPU_CYCLES ? ? ? ? ? ? ? ?= 0xFF
> ?};
>
> ?/* ARMv7 Cortex-A8 specific event types */
> ?enum armv7_a8_perf_types {
> - ? ? ? ARMV7_PERFCTR_INSTR_EXECUTED ? ? ? ? ? ?= 0x08,
> -
> - ? ? ? ARMV7_PERFCTR_PC_PROC_RETURN ? ? ? ? ? ?= 0x0E,
> -
> ? ? ? ?ARMV7_PERFCTR_WRITE_BUFFER_FULL ? ? ? ? = 0x40,
> ? ? ? ?ARMV7_PERFCTR_L2_STORE_MERGED ? ? ? ? ? = 0x41,
> ? ? ? ?ARMV7_PERFCTR_L2_STORE_BUFF ? ? ? ? ? ? = 0x42,
> --
> 1.7.0.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

[PATCH 09/11] ARM: perf: add PMUv2 common event definitions

[Will Deacon]

Hi Jean,

Thanks for looking at this bag of hex values!

> On Mon, Jun 6, 2011 at 6:55 PM, Will Deacon <will.deacon@arm.com> wrote:
> > The PMUv2 specification reserves a number of event encodings
> > for common events.
> >
> > This patch adds these events to the common event enumeration
> > in preparation for PMUv2 cores, such as Cortex-A15.
> >
> > Signed-off-by: Will Deacon <will.deacon@arm.com>
> > ---
> > ?arch/arm/kernel/perf_event_v7.c | ? 35 +++++++++++++++++++++++++----------
> > ?1 files changed, 25 insertions(+), 10 deletions(-)

[...]

> > ?enum armv7_perf_types {
> > ? ? ? ?ARMV7_PERFCTR_PMNC_SW_INCR ? ? ? ? ? ? ?= 0x00,
> > ? ? ? ?ARMV7_PERFCTR_IFETCH_MISS ? ? ? ? ? ? ? = 0x01,
> > ? ? ? ?ARMV7_PERFCTR_ITLB_MISS ? ? ? ? ? ? ? ? = 0x02,
> > - ? ? ? ARMV7_PERFCTR_DCACHE_REFILL ? ? ? ? ? ? = 0x03,
> > - ? ? ? ARMV7_PERFCTR_DCACHE_ACCESS ? ? ? ? ? ? = 0x04,
> > + ? ? ? ARMV7_PERFCTR_DCACHE_REFILL ? ? ? ? ? ? = 0x03, /* L1 */
> > + ? ? ? ARMV7_PERFCTR_DCACHE_ACCESS ? ? ? ? ? ? = 0x04, /* L1 */
> > ? ? ? ?ARMV7_PERFCTR_DTLB_REFILL ? ? ? ? ? ? ? = 0x05,
> > ? ? ? ?ARMV7_PERFCTR_DREAD ? ? ? ? ? ? ? ? ? ? = 0x06,
> > ? ? ? ?ARMV7_PERFCTR_DWRITE ? ? ? ? ? ? ? ? ? ?= 0x07,
> > -
> > + ? ? ? ARMV7_PERFCTR_INSTR_EXECUTED ? ? ? ? ? ?= 0x08,
> > ? ? ? ?ARMV7_PERFCTR_EXC_TAKEN ? ? ? ? ? ? ? ? = 0x09,
> > ? ? ? ?ARMV7_PERFCTR_EXC_EXECUTED ? ? ? ? ? ? ?= 0x0A,
> > ? ? ? ?ARMV7_PERFCTR_CID_WRITE ? ? ? ? ? ? ? ? = 0x0B,
> > @@ -39,21 +45,30 @@ enum armv7_perf_types {
> > ? ? ? ? */
> > ? ? ? ?ARMV7_PERFCTR_PC_WRITE ? ? ? ? ? ? ? ? ?= 0x0C,
> > ? ? ? ?ARMV7_PERFCTR_PC_IMM_BRANCH ? ? ? ? ? ? = 0x0D,
> > + ? ? ? ARMV7_PERFCTR_PC_PROC_RETURN ? ? ? ? ? ?= 0x0E,
> Will ARMV7_PERFCTR_INSTR_EXECUTED and ARMV7_PERFCTR_PC_PROC_RETURN
> work for all v7 implementations? For example they are not defined for
> A9.

Correct, A9 doesn't support these and in general they are not mandatory.
The useful part is that this event space cannot be reused for different
events, so if an event of encoding 0x08 *is* supported, it absolutely
must be ARMV7_PERFCTR_INSTR_EXECUTED.

PMUv2 does define some feature registers (bitmaps) in the co-processor
space, which tell you the supported events out of the common encodings.
I don't think this is much use for the kernel, but it might be for
userspace. If somebody decides they want it then I'll happily expose it
through debugfs.
 
> > ? ? ? ?ARMV7_PERFCTR_UNALIGNED_ACCESS ? ? ? ? ?= 0x0F,
> > +
> > + ? ? ? /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
> > ? ? ? ?ARMV7_PERFCTR_PC_BRANCH_MIS_PRED ? ? ? ?= 0x10,
> > ? ? ? ?ARMV7_PERFCTR_CLOCK_CYCLES ? ? ? ? ? ? ?= 0x11,
> > -
> > - ? ? ? ARMV7_PERFCTR_PC_BRANCH_MIS_USED ? ? ? ?= 0x12,
> > + ? ? ? ARMV7_PERFCTR_PC_BRANCH_PRED ? ? ? ? ? ?= 0x12,
> > + ? ? ? ARMV7_PERFCTR_MEM_ACCESS ? ? ? ? ? ? ? ?= 0x13,
> > + ? ? ? ARMV7_PERFCTR_L1_ICACHE_ACCESS ? ? ? ? ?= 0x14,
> > + ? ? ? ARMV7_PERFCTR_L1_DCACHE_WB ? ? ? ? ? ? ?= 0x15,
> > + ? ? ? ARMV7_PERFCTR_L2_DCACHE_ACCESS ? ? ? ? ?= 0x16,
> > + ? ? ? ARMV7_PERFCTR_L2_DCACHE_REFILL ? ? ? ? ?= 0x17,
> > + ? ? ? ARMV7_PERFCTR_L2_DCACHE_WB ? ? ? ? ? ? ?= 0x18,
> > + ? ? ? ARMV7_PERFCTR_BUS_ACCESS ? ? ? ? ? ? ? ?= 0x19,
> > + ? ? ? ARMV7_PERFCTR_MEMORY_ERROR ? ? ? ? ? ? ?= 0x1A,
> > + ? ? ? ARMV7_PERFCTR_INSTR_SPEC ? ? ? ? ? ? ? ?= 0x1B,
> > + ? ? ? ARMV7_PERFCTR_TTBR_WRITE ? ? ? ? ? ? ? ?= 0x1C,
> > + ? ? ? ARMV7_PERFCTR_BUS_CYCLES ? ? ? ? ? ? ? ?= 0x1D,
> Same question for those new events that are not defined for A8 and A9.

Same response actually. The core may implement a subset of these, but the
encodings remain reserved otherwise.

Thanks for taking a look,

Will

[PATCH 10/11] ARM: perf: add support for the Cortex-A5 PMU

[Will Deacon]

This patch adds support for the Cortex-A5 PMU to the ARMv7 perf-event
backend.

Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/include/asm/perf_event.h |    1 +
 arch/arm/kernel/perf_event.c      |    3 +
 arch/arm/kernel/perf_event_v7.c   |  146 +++++++++++++++++++++++++++++++++++++
 3 files changed, 150 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index c4aa4e8..207bd3c 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -24,6 +24,7 @@ enum arm_perf_pmu_ids {
 	ARM_PERF_PMU_ID_V6MP,
 	ARM_PERF_PMU_ID_CA8,
 	ARM_PERF_PMU_ID_CA9,
+	ARM_PERF_PMU_ID_CA5,
 	ARM_NUM_PMU_IDS,
 };
 
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index d53c0ab..df4e517 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -660,6 +660,9 @@ init_hw_perf_events(void)
 		case 0xC090:	/* Cortex-A9 */
 			armpmu = armv7_a9_pmu_init();
 			break;
+		case 0xC050:	/* Cortex-A5 */
+			armpmu = armv7_a5_pmu_init();
+			break;
 		}
 	/* Intel CPUs [xscale]. */
 	} else if (0x69 == implementor) {
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 01b1145..db1d6c4 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -153,6 +153,21 @@ enum armv7_a9_perf_types {
 	ARMV7_PERFCTR_PLE_RQST_PROG		= 0xA5
 };
 
+/* ARMv7 Cortex-A5 specific event types */
+enum armv7_a5_perf_types {
+	ARMV7_PERFCTR_IRQ_TAKEN			= 0x86,
+	ARMV7_PERFCTR_FIQ_TAKEN			= 0x87,
+
+	ARMV7_PERFCTR_EXT_MEM_RQST		= 0xc0,
+	ARMV7_PERFCTR_NC_EXT_MEM_RQST		= 0xc1,
+	ARMV7_PERFCTR_PREFETCH_LINEFILL		= 0xc2,
+	ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP	= 0xc3,
+	ARMV7_PERFCTR_ENTER_READ_ALLOC		= 0xc4,
+	ARMV7_PERFCTR_READ_ALLOC		= 0xc5,
+
+	ARMV7_PERFCTR_STALL_SB_FULL		= 0xc9,
+};
+
 /*
  * Cortex-A8 HW events mapping
  *
@@ -379,6 +394,122 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 };
 
 /*
+ * Cortex-A5 HW events mapping
+ */
+static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {
+	[PERF_COUNT_HW_CPU_CYCLES]	    = ARMV7_PERFCTR_CPU_CYCLES,
+	[PERF_COUNT_HW_INSTRUCTIONS]	    = ARMV7_PERFCTR_INSTR_EXECUTED,
+	[PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+	[PERF_COUNT_HW_CACHE_MISSES]	    = HW_OP_UNSUPPORTED,
+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+	[PERF_COUNT_HW_BRANCH_MISSES]	    = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+	[PERF_COUNT_HW_BUS_CYCLES]	    = HW_OP_UNSUPPORTED,
+};
+
+static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+					[PERF_COUNT_HW_CACHE_OP_MAX]
+					[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+	[C(L1D)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]
+					= ARMV7_PERFCTR_DCACHE_ACCESS,
+			[C(RESULT_MISS)]
+					= ARMV7_PERFCTR_DCACHE_REFILL,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]
+					= ARMV7_PERFCTR_DCACHE_ACCESS,
+			[C(RESULT_MISS)]
+					= ARMV7_PERFCTR_DCACHE_REFILL,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]
+					= ARMV7_PERFCTR_PREFETCH_LINEFILL,
+			[C(RESULT_MISS)]
+					= ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
+		},
+	},
+	[C(L1I)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,
+		},
+		/*
+		 * The prefetch counters don't differentiate between the I
+		 * side and the D side.
+		 */
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]
+					= ARMV7_PERFCTR_PREFETCH_LINEFILL,
+			[C(RESULT_MISS)]
+					= ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
+		},
+	},
+	[C(LL)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+	[C(DTLB)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+	[C(ITLB)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+	[C(BPU)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
+			[C(RESULT_MISS)]
+					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
+			[C(RESULT_MISS)]
+					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+};
+
+/*
  * Perf Events counters
  */
 enum armv7_counters {
@@ -910,6 +1041,16 @@ static const struct arm_pmu *__init armv7_a9_pmu_init(void)
 	armv7pmu.num_events	= armv7_read_num_pmnc_events();
 	return &armv7pmu;
 }
+
+static const struct arm_pmu *__init armv7_a5_pmu_init(void)
+{
+	armv7pmu.id		= ARM_PERF_PMU_ID_CA5;
+	armv7pmu.name		= "ARMv7 Cortex-A5";
+	armv7pmu.cache_map	= &armv7_a5_perf_cache_map;
+	armv7pmu.event_map	= &armv7_a5_perf_map;
+	armv7pmu.num_events	= armv7_read_num_pmnc_events();
+	return &armv7pmu;
+}
 #else
 static const struct arm_pmu *__init armv7_a8_pmu_init(void)
 {
@@ -920,4 +1061,9 @@ static const struct arm_pmu *__init armv7_a9_pmu_init(void)
 {
 	return NULL;
 }
+
+static const struct arm_pmu *__init armv7_a5_pmu_init(void)
+{
+	return NULL;
+}
 #endif	/* CONFIG_CPU_V7 */
-- 
1.7.0.4

[PATCH 11/11] ARM: perf: add support for the Cortex-A15 PMU

[Will Deacon]

This patch adds support for the Cortex-A15 PMU to the ARMv7
perf-event backend.

Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/include/asm/perf_event.h |    1 +
 arch/arm/kernel/perf_event.c      |    3 +
 arch/arm/kernel/perf_event_v7.c   |  153 +++++++++++++++++++++++++++++++++++++
 3 files changed, 157 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index 207bd3c..0f8e382 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -25,6 +25,7 @@ enum arm_perf_pmu_ids {
 	ARM_PERF_PMU_ID_CA8,
 	ARM_PERF_PMU_ID_CA9,
 	ARM_PERF_PMU_ID_CA5,
+	ARM_PERF_PMU_ID_CA15,
 	ARM_NUM_PMU_IDS,
 };
 
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index df4e517..262ea67 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -663,6 +663,9 @@ init_hw_perf_events(void)
 		case 0xC050:	/* Cortex-A5 */
 			armpmu = armv7_a5_pmu_init();
 			break;
+		case 0xC0F0:	/* Cortex-A15 */
+			armpmu = armv7_a15_pmu_init();
+			break;
 		}
 	/* Intel CPUs [xscale]. */
 	} else if (0x69 == implementor) {
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index db1d6c4..9633178 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -168,6 +168,24 @@ enum armv7_a5_perf_types {
 	ARMV7_PERFCTR_STALL_SB_FULL		= 0xc9,
 };
 
+/* ARMv7 Cortex-A15 specific event types */
+enum armv7_a15_perf_types {
+	ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS	= 0x40,
+	ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS	= 0x41,
+	ARMV7_PERFCTR_L1_DCACHE_READ_REFILL	= 0x42,
+	ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL	= 0x43,
+
+	ARMV7_PERFCTR_L1_DTLB_READ_REFILL	= 0x4C,
+	ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL	= 0x4D,
+
+	ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS	= 0x50,
+	ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS	= 0x51,
+	ARMV7_PERFCTR_L2_DCACHE_READ_REFILL	= 0x52,
+	ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL	= 0x53,
+
+	ARMV7_PERFCTR_SPEC_PC_WRITE		= 0x76,
+};
+
 /*
  * Cortex-A8 HW events mapping
  *
@@ -510,6 +528,126 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 };
 
 /*
+ * Cortex-A15 HW events mapping
+ */
+static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {
+	[PERF_COUNT_HW_CPU_CYCLES]	    = ARMV7_PERFCTR_CPU_CYCLES,
+	[PERF_COUNT_HW_INSTRUCTIONS]	    = ARMV7_PERFCTR_INSTR_EXECUTED,
+	[PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+	[PERF_COUNT_HW_CACHE_MISSES]	    = HW_OP_UNSUPPORTED,
+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_SPEC_PC_WRITE,
+	[PERF_COUNT_HW_BRANCH_MISSES]	    = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+	[PERF_COUNT_HW_BUS_CYCLES]	    = ARMV7_PERFCTR_BUS_CYCLES,
+};
+
+static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+					[PERF_COUNT_HW_CACHE_OP_MAX]
+					[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+	[C(L1D)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]
+					= ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS,
+			[C(RESULT_MISS)]
+					= ARMV7_PERFCTR_L1_DCACHE_READ_REFILL,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]
+					= ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS,
+			[C(RESULT_MISS)]
+					= ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+	[C(L1I)] = {
+		/*
+		 * Not all performance counters differentiate between read
+		 * and write accesses/misses so we're not always strictly
+		 * correct, but it's the best we can do. Writes and reads get
+		 * combined in these cases.
+		 */
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+	[C(LL)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]
+					= ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS,
+			[C(RESULT_MISS)]
+					= ARMV7_PERFCTR_L2_DCACHE_READ_REFILL,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]
+					= ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS,
+			[C(RESULT_MISS)]
+					= ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+	[C(DTLB)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]
+					= ARMV7_PERFCTR_L1_DTLB_READ_REFILL,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]
+					= ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+	[C(ITLB)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+	[C(BPU)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
+			[C(RESULT_MISS)]
+					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
+			[C(RESULT_MISS)]
+					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+};
+
+/*
  * Perf Events counters
  */
 enum armv7_counters {
@@ -1051,6 +1189,16 @@ static const struct arm_pmu *__init armv7_a5_pmu_init(void)
 	armv7pmu.num_events	= armv7_read_num_pmnc_events();
 	return &armv7pmu;
 }
+
+static const struct arm_pmu *__init armv7_a15_pmu_init(void)
+{
+	armv7pmu.id		= ARM_PERF_PMU_ID_CA15;
+	armv7pmu.name		= "ARMv7 Cortex-A15";
+	armv7pmu.cache_map	= &armv7_a15_perf_cache_map;
+	armv7pmu.event_map	= &armv7_a15_perf_map;
+	armv7pmu.num_events	= armv7_read_num_pmnc_events();
+	return &armv7pmu;
+}
 #else
 static const struct arm_pmu *__init armv7_a8_pmu_init(void)
 {
@@ -1066,4 +1214,9 @@ static const struct arm_pmu *__init armv7_a5_pmu_init(void)
 {
 	return NULL;
 }
+
+static const struct arm_pmu *__init armv7_a15_pmu_init(void)
+{
+	return NULL;
+}
 #endif	/* CONFIG_CPU_V7 */
-- 
1.7.0.4