From: cbouatmailru@gmail.com (Anton Vorontsov)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: cns3xxx: Add support for L2 Cache Controller
Date: Thu, 7 Jul 2011 20:51:11 +0400 [thread overview]
Message-ID: <20110707165111.GA1242@oksana.dev.rtsoft.ru> (raw)
In-Reply-To: <4E14A51F.4030108@gmail.com>
On Wed, Jul 06, 2011 at 01:10:39PM -0500, Rob Herring wrote:
[...]
> > + * 1 cycle of setup latency, 2 cycles of read and write accesses latency
> > + */
> > + val = readl(base + L2X0_DATA_LATENCY_CTRL);
> > + val &= 0xfffff888;
>
> You're missing a "val |= 0x110" or your comment is wrong.
Thanks for spotting this.
These values were taken from the BSP* code, which was tested
the most (and apparently works), I tend to leave the value as is
and fixup the comment.
Thanks!
* The BSP does not use L2X0 driver, instead, it contains 'L2CC'
driver with these values hard-coded. But nowadays the L2CC driver
is unneeded as L2X0 supports PL310 controllers.
--
Anton Vorontsov
Email: cbouatmailru at gmail.com
next prev parent reply other threads:[~2011-07-07 16:51 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-07-06 14:08 [PATCH] ARM: cns3xxx: Add support for L2 Cache Controller Anton Vorontsov
2011-07-06 14:23 ` Arnd Bergmann
2011-07-07 16:55 ` [PATCH v2] " Anton Vorontsov
2011-07-06 18:10 ` [PATCH] " Rob Herring
2011-07-07 16:51 ` Anton Vorontsov [this message]
2011-07-06 23:57 ` Lin Mac
2011-07-07 7:16 ` Arnd Bergmann
2011-07-07 7:52 ` Russell King - ARM Linux
2011-07-07 7:36 ` Imre Kaloz
2011-07-08 6:27 ` Tommy Lin
2011-07-07 16:51 ` Anton Vorontsov
2011-07-19 18:11 ` Lin Mac
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