* [PATCH 1/5] ARM: mx5: Allow CCM definitions to work on MX51 and MX53 @ 2011-08-26 19:21 Fabio Estevam 2011-08-26 19:21 ` [PATCH 2/5] ARM: mx53: Register gpc_dvfs clock Fabio Estevam 2011-08-27 11:19 ` [PATCH 1/5] ARM: mx5: Allow CCM definitions to work on MX51 and MX53 Sascha Hauer 0 siblings, 2 replies; 8+ messages in thread From: Fabio Estevam @ 2011-08-26 19:21 UTC (permalink / raw) To: linux-arm-kernel Allow CCM (Clock Control Module) definitions to work on MX51 and MX53 by checking the cpu type in run-time and using the appropriate register bases. Also, MX50 shares the same base addresses for these registers as MX53. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> --- arch/arm/mach-mx5/crm_regs.h | 136 ++++++++++++++++++++++------------------- 1 files changed, 73 insertions(+), 63 deletions(-) diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index 5e11ba7..4385307 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -24,6 +24,16 @@ #define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR) #define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) #define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) +#define MX53_CORTEXA8_BASE MX53_IO_ADDRESS(MX53_ARM_BASE_ADDR) +#define MX53_GPC_BASE MX53_IO_ADDRESS(MX53_GPC_BASE_ADDR) + +#define MX5_CORTEXA8_BASE (cpu_is_mx51() ? MX51_CORTEXA8_BASE : \ + MX53_CORTEXA8_BASE) +#define MX5_GPC_BASE (cpu_is_mx51() ? MX51_GPC_BASE : \ + MX53_GPC_BASE) + +#define MX5_CCM_BASE (cpu_is_mx51() ? MX51_CCM_BASE : \ + MX53_CCM_BASE) /* PLL Register Offsets */ #define MXC_PLL_DP_CTL 0x00 @@ -81,42 +91,42 @@ #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF /* Register addresses of CCM*/ -#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00) -#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04) -#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08) -#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C) -#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10) -#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14) -#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18) -#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C) -#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20) -#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24) -#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28) -#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C) -#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30) -#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34) -#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38) -#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C) -#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40) -#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44) -#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48) -#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C) -#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50) -#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54) -#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58) -#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C) -#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60) -#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64) -#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68) -#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C) -#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70) -#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74) -#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) -#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) -#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) -#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84) - -#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) +#define MXC_CCM_CCR (MX5_CCM_BASE + 0x00) +#define MXC_CCM_CCDR (MX5_CCM_BASE + 0x04) +#define MXC_CCM_CSR (MX5_CCM_BASE + 0x08) +#define MXC_CCM_CCSR (MX5_CCM_BASE + 0x0C) +#define MXC_CCM_CACRR (MX5_CCM_BASE + 0x10) +#define MXC_CCM_CBCDR (MX5_CCM_BASE + 0x14) +#define MXC_CCM_CBCMR (MX5_CCM_BASE + 0x18) +#define MXC_CCM_CSCMR1 (MX5_CCM_BASE + 0x1C) +#define MXC_CCM_CSCMR2 (MX5_CCM_BASE + 0x20) +#define MXC_CCM_CSCDR1 (MX5_CCM_BASE + 0x24) +#define MXC_CCM_CS1CDR (MX5_CCM_BASE + 0x28) +#define MXC_CCM_CS2CDR (MX5_CCM_BASE + 0x2C) +#define MXC_CCM_CDCDR (MX5_CCM_BASE + 0x30) +#define MXC_CCM_CHSCDR (MX5_CCM_BASE + 0x34) +#define MXC_CCM_CSCDR2 (MX5_CCM_BASE + 0x38) +#define MXC_CCM_CSCDR3 (MX5_CCM_BASE + 0x3C) +#define MXC_CCM_CSCDR4 (MX5_CCM_BASE + 0x40) +#define MXC_CCM_CWDR (MX5_CCM_BASE + 0x44) +#define MXC_CCM_CDHIPR (MX5_CCM_BASE + 0x48) +#define MXC_CCM_CDCR (MX5_CCM_BASE + 0x4C) +#define MXC_CCM_CTOR (MX5_CCM_BASE + 0x50) +#define MXC_CCM_CLPCR (MX5_CCM_BASE + 0x54) +#define MXC_CCM_CISR (MX5_CCM_BASE + 0x58) +#define MXC_CCM_CIMR (MX5_CCM_BASE + 0x5C) +#define MXC_CCM_CCOSR (MX5_CCM_BASE + 0x60) +#define MXC_CCM_CGPR (MX5_CCM_BASE + 0x64) +#define MXC_CCM_CCGR0 (MX5_CCM_BASE + 0x68) +#define MXC_CCM_CCGR1 (MX5_CCM_BASE + 0x6C) +#define MXC_CCM_CCGR2 (MX5_CCM_BASE + 0x70) +#define MXC_CCM_CCGR3 (MX5_CCM_BASE + 0x74) +#define MXC_CCM_CCGR4 (MX5_CCM_BASE + 0x78) +#define MXC_CCM_CCGR5 (MX5_CCM_BASE + 0x7C) +#define MXC_CCM_CCGR6 (MX5_CCM_BASE + 0x80) +#define MXC_CCM_CCGR7 (MX5_CCM_BASE + 0x84) + +#define MXC_CCM_CMEOR (MX5_CCM_BASE + 0x84) /* Define the bits in register CCR */ #define MXC_CCM_CCR_COSC_EN (1 << 12) @@ -502,30 +512,30 @@ #define MXC_CCM_CCGRx_CG1_OFFSET 2 #define MXC_CCM_CCGRx_CG0_OFFSET 0 -#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80) -#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100) -#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180) -#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0) -#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220) -#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240) -#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260) -#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280) -#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0) -#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0) -#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0) -#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0) -#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300) +#define MXC_DPTC_LP_BASE (MX5_GPC_BASE + 0x80) +#define MXC_DPTC_GP_BASE (MX5_GPC_BASE + 0x100) +#define MXC_DVFS_CORE_BASE (MX5_GPC_BASE + 0x180) +#define MXC_DPTC_PER_BASE (MX5_GPC_BASE + 0x1C0) +#define MXC_PGC_IPU_BASE (MX5_GPC_BASE + 0x220) +#define MXC_PGC_VPU_BASE (MX5_GPC_BASE + 0x240) +#define MXC_PGC_GPU_BASE (MX5_GPC_BASE + 0x260) +#define MXC_SRPG_NEON_BASE (MX5_GPC_BASE + 0x280) +#define MXC_SRPG_ARM_BASE (MX5_GPC_BASE + 0x2A0) +#define MXC_SRPG_EMPGC0_BASE (MX5_GPC_BASE + 0x2C0) +#define MXC_SRPG_EMPGC1_BASE (MX5_GPC_BASE + 0x2D0) +#define MXC_SRPG_MEGAMIX_BASE (MX5_GPC_BASE + 0x2E0) +#define MXC_SRPG_EMI_BASE (MX5_GPC_BASE + 0x300) /* CORTEXA8 platform */ -#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0) -#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4) -#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8) -#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC) -#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10) -#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14) -#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18) -#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20) -#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24) +#define MXC_CORTEXA8_PLAT_PVID (MX5_CORTEXA8_BASE + 0x0) +#define MXC_CORTEXA8_PLAT_GPC (MX5_CORTEXA8_BASE + 0x4) +#define MXC_CORTEXA8_PLAT_PIC (MX5_CORTEXA8_BASE + 0x8) +#define MXC_CORTEXA8_PLAT_LPC (MX5_CORTEXA8_BASE + 0xC) +#define MXC_CORTEXA8_PLAT_NEON_LPC (MX5_CORTEXA8_BASE + 0x10) +#define MXC_CORTEXA8_PLAT_ICGC (MX5_CORTEXA8_BASE + 0x14) +#define MXC_CORTEXA8_PLAT_AMC (MX5_CORTEXA8_BASE + 0x18) +#define MXC_CORTEXA8_PLAT_NMC (MX5_CORTEXA8_BASE + 0x20) +#define MXC_CORTEXA8_PLAT_NMS (MX5_CORTEXA8_BASE + 0x24) /* DVFS CORE */ #define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) @@ -547,11 +557,11 @@ #define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) /* GPC */ -#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0) -#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4) -#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8) -#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC) -#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10) +#define MXC_GPC_CNTR (MX5_GPC_BASE + 0x0) +#define MXC_GPC_PGR (MX5_GPC_BASE + 0x4) +#define MXC_GPC_VCR (MX5_GPC_BASE + 0x8) +#define MXC_GPC_ALL_PU (MX5_GPC_BASE + 0xC) +#define MXC_GPC_NEON (MX5_GPC_BASE + 0x10) #define MXC_GPC_PGR_ARMPG_OFFSET 8 #define MXC_GPC_PGR_ARMPG_MASK (3 << 8) -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/5] ARM: mx53: Register gpc_dvfs clock 2011-08-26 19:21 [PATCH 1/5] ARM: mx5: Allow CCM definitions to work on MX51 and MX53 Fabio Estevam @ 2011-08-26 19:21 ` Fabio Estevam 2011-08-26 19:21 ` [PATCH 3/5] ARM: mx53: Fix the logic for BYPASS_MAX_LPM_HS Fabio Estevam 2011-08-27 11:19 ` [PATCH 1/5] ARM: mx5: Allow CCM definitions to work on MX51 and MX53 Sascha Hauer 1 sibling, 1 reply; 8+ messages in thread From: Fabio Estevam @ 2011-08-26 19:21 UTC (permalink / raw) To: linux-arm-kernel gpc_dvfs_clk is needed for entering low power mode. Add support for it on MX53. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> --- arch/arm/mach-mx5/clock-mx51-mx53.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 2b9bd1f..058fb42 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -1513,6 +1513,7 @@ static struct clk_lookup mx53_lookups[] = { _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk) _REGISTER_CLOCK("pata_imx", NULL, pata_clk) + _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk) }; static void clk_tree_init(void) -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/5] ARM: mx53: Fix the logic for BYPASS_MAX_LPM_HS 2011-08-26 19:21 ` [PATCH 2/5] ARM: mx53: Register gpc_dvfs clock Fabio Estevam @ 2011-08-26 19:21 ` Fabio Estevam 2011-08-26 19:22 ` [PATCH 5/5] ARM: mx53: Allow suspend/resume on mx53 Fabio Estevam 0 siblings, 1 reply; 8+ messages in thread From: Fabio Estevam @ 2011-08-26 19:21 UTC (permalink / raw) To: linux-arm-kernel In order to bypass the handshake with MAX the BYPASS_MAX_LPM_HS bit of CCM_CLPCR needs to be set to one. Fix the logic. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> --- arch/arm/mach-mx5/clock-mx51-mx53.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 058fb42..588e689 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -569,7 +569,7 @@ static void _clk_max_disable(struct clk *clk) if (cpu_is_mx51()) reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; else if (cpu_is_mx53()) - reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; + reg |= MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; __raw_writel(reg, MXC_CCM_CLPCR); } -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 5/5] ARM: mx53: Allow suspend/resume on mx53 2011-08-26 19:21 ` [PATCH 3/5] ARM: mx53: Fix the logic for BYPASS_MAX_LPM_HS Fabio Estevam @ 2011-08-26 19:22 ` Fabio Estevam 2011-08-26 19:22 ` [PATCH 4/5] ARM: mx53: Allow gpio_keys to wake the system Fabio Estevam 0 siblings, 1 reply; 8+ messages in thread From: Fabio Estevam @ 2011-08-26 19:22 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> --- This is still work in progress, as I can still not fully get access to the console after a suspend/resume cycle on my mx53loco. Freezing user space processes ... (elapsed 0.01 seconds) done. Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done. PM: suspend of devices complete after 0.635 msecs PM: suspend devices took 0.000 seconds (Press the button here:) PM: late suspend of devices complete after 0.418 msecs and console does not come back after this message. arch/arm/mach-mx5/pm-imx5.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c index e4529af..a9bac88 100644 --- a/arch/arm/mach-mx5/pm-imx5.c +++ b/arch/arm/mach-mx5/pm-imx5.c @@ -63,7 +63,7 @@ static int __init mx5_pm_init(void) gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); if (!IS_ERR(gpc_dvfs_clk)) { - if (cpu_is_mx51()) + if (cpu_is_mx51() || cpu_is_mx53()) suspend_set_ops(&mx5_suspend_ops); } else return -EPERM; -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/5] ARM: mx53: Allow gpio_keys to wake the system 2011-08-26 19:22 ` [PATCH 5/5] ARM: mx53: Allow suspend/resume on mx53 Fabio Estevam @ 2011-08-26 19:22 ` Fabio Estevam 0 siblings, 0 replies; 8+ messages in thread From: Fabio Estevam @ 2011-08-26 19:22 UTC (permalink / raw) To: linux-arm-kernel Allow KEY_HOME on mx53ard and KEY_POWER on mx53loco to generate a wakeup event. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> --- arch/arm/mach-mx5/board-mx53_ard.c | 2 +- arch/arm/mach-mx5/board-mx53_loco.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c index ddc3015..40ea3b7 100644 --- a/arch/arm/mach-mx5/board-mx53_ard.c +++ b/arch/arm/mach-mx5/board-mx53_ard.c @@ -115,7 +115,7 @@ static iomux_v3_cfg_t mx53_ard_pads[] = { } static struct gpio_keys_button ard_buttons[] = { - GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0), + GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 1), GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0), GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0), GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0), diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index 1bb0b3c..6529bde 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -204,7 +204,7 @@ static iomux_v3_cfg_t mx53_loco_pads[] = { } static struct gpio_keys_button loco_buttons[] = { - GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0), + GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 1), GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0), GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0), }; -- 1.6.0.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 1/5] ARM: mx5: Allow CCM definitions to work on MX51 and MX53 2011-08-26 19:21 [PATCH 1/5] ARM: mx5: Allow CCM definitions to work on MX51 and MX53 Fabio Estevam 2011-08-26 19:21 ` [PATCH 2/5] ARM: mx53: Register gpc_dvfs clock Fabio Estevam @ 2011-08-27 11:19 ` Sascha Hauer 2011-08-27 15:17 ` Fabio Estevam 1 sibling, 1 reply; 8+ messages in thread From: Sascha Hauer @ 2011-08-27 11:19 UTC (permalink / raw) To: linux-arm-kernel On Fri, Aug 26, 2011 at 04:21:57PM -0300, Fabio Estevam wrote: > Allow CCM (Clock Control Module) definitions to work on MX51 and MX53 > by checking the cpu type in run-time and using the appropriate register bases. They already work on i.MX51 and i.MX53. They have different physical addresses, but have (more or less accidently...) the same virtual address. Sascha > > Also, MX50 shares the same base addresses for these registers as MX53. > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> > --- > arch/arm/mach-mx5/crm_regs.h | 136 ++++++++++++++++++++++------------------- > 1 files changed, 73 insertions(+), 63 deletions(-) > > diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h > index 5e11ba7..4385307 100644 > --- a/arch/arm/mach-mx5/crm_regs.h > +++ b/arch/arm/mach-mx5/crm_regs.h > @@ -24,6 +24,16 @@ > #define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR) > #define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) > #define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) > +#define MX53_CORTEXA8_BASE MX53_IO_ADDRESS(MX53_ARM_BASE_ADDR) > +#define MX53_GPC_BASE MX53_IO_ADDRESS(MX53_GPC_BASE_ADDR) > + > +#define MX5_CORTEXA8_BASE (cpu_is_mx51() ? MX51_CORTEXA8_BASE : \ > + MX53_CORTEXA8_BASE) > +#define MX5_GPC_BASE (cpu_is_mx51() ? MX51_GPC_BASE : \ > + MX53_GPC_BASE) > + > +#define MX5_CCM_BASE (cpu_is_mx51() ? MX51_CCM_BASE : \ > + MX53_CCM_BASE) > > /* PLL Register Offsets */ > #define MXC_PLL_DP_CTL 0x00 > @@ -81,42 +91,42 @@ > #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF > > /* Register addresses of CCM*/ > -#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00) > -#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04) > -#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08) > -#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C) > -#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10) > -#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14) > -#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18) > -#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C) > -#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20) > -#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24) > -#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28) > -#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C) > -#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30) > -#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34) > -#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38) > -#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C) > -#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40) > -#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44) > -#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48) > -#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C) > -#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50) > -#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54) > -#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58) > -#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C) > -#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60) > -#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64) > -#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68) > -#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C) > -#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70) > -#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74) > -#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) > -#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) > -#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) > -#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84) > - > -#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) > +#define MXC_CCM_CCR (MX5_CCM_BASE + 0x00) > +#define MXC_CCM_CCDR (MX5_CCM_BASE + 0x04) > +#define MXC_CCM_CSR (MX5_CCM_BASE + 0x08) > +#define MXC_CCM_CCSR (MX5_CCM_BASE + 0x0C) > +#define MXC_CCM_CACRR (MX5_CCM_BASE + 0x10) > +#define MXC_CCM_CBCDR (MX5_CCM_BASE + 0x14) > +#define MXC_CCM_CBCMR (MX5_CCM_BASE + 0x18) > +#define MXC_CCM_CSCMR1 (MX5_CCM_BASE + 0x1C) > +#define MXC_CCM_CSCMR2 (MX5_CCM_BASE + 0x20) > +#define MXC_CCM_CSCDR1 (MX5_CCM_BASE + 0x24) > +#define MXC_CCM_CS1CDR (MX5_CCM_BASE + 0x28) > +#define MXC_CCM_CS2CDR (MX5_CCM_BASE + 0x2C) > +#define MXC_CCM_CDCDR (MX5_CCM_BASE + 0x30) > +#define MXC_CCM_CHSCDR (MX5_CCM_BASE + 0x34) > +#define MXC_CCM_CSCDR2 (MX5_CCM_BASE + 0x38) > +#define MXC_CCM_CSCDR3 (MX5_CCM_BASE + 0x3C) > +#define MXC_CCM_CSCDR4 (MX5_CCM_BASE + 0x40) > +#define MXC_CCM_CWDR (MX5_CCM_BASE + 0x44) > +#define MXC_CCM_CDHIPR (MX5_CCM_BASE + 0x48) > +#define MXC_CCM_CDCR (MX5_CCM_BASE + 0x4C) > +#define MXC_CCM_CTOR (MX5_CCM_BASE + 0x50) > +#define MXC_CCM_CLPCR (MX5_CCM_BASE + 0x54) > +#define MXC_CCM_CISR (MX5_CCM_BASE + 0x58) > +#define MXC_CCM_CIMR (MX5_CCM_BASE + 0x5C) > +#define MXC_CCM_CCOSR (MX5_CCM_BASE + 0x60) > +#define MXC_CCM_CGPR (MX5_CCM_BASE + 0x64) > +#define MXC_CCM_CCGR0 (MX5_CCM_BASE + 0x68) > +#define MXC_CCM_CCGR1 (MX5_CCM_BASE + 0x6C) > +#define MXC_CCM_CCGR2 (MX5_CCM_BASE + 0x70) > +#define MXC_CCM_CCGR3 (MX5_CCM_BASE + 0x74) > +#define MXC_CCM_CCGR4 (MX5_CCM_BASE + 0x78) > +#define MXC_CCM_CCGR5 (MX5_CCM_BASE + 0x7C) > +#define MXC_CCM_CCGR6 (MX5_CCM_BASE + 0x80) > +#define MXC_CCM_CCGR7 (MX5_CCM_BASE + 0x84) > + > +#define MXC_CCM_CMEOR (MX5_CCM_BASE + 0x84) > > /* Define the bits in register CCR */ > #define MXC_CCM_CCR_COSC_EN (1 << 12) > @@ -502,30 +512,30 @@ > #define MXC_CCM_CCGRx_CG1_OFFSET 2 > #define MXC_CCM_CCGRx_CG0_OFFSET 0 > > -#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80) > -#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100) > -#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180) > -#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0) > -#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220) > -#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240) > -#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260) > -#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280) > -#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0) > -#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0) > -#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0) > -#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0) > -#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300) > +#define MXC_DPTC_LP_BASE (MX5_GPC_BASE + 0x80) > +#define MXC_DPTC_GP_BASE (MX5_GPC_BASE + 0x100) > +#define MXC_DVFS_CORE_BASE (MX5_GPC_BASE + 0x180) > +#define MXC_DPTC_PER_BASE (MX5_GPC_BASE + 0x1C0) > +#define MXC_PGC_IPU_BASE (MX5_GPC_BASE + 0x220) > +#define MXC_PGC_VPU_BASE (MX5_GPC_BASE + 0x240) > +#define MXC_PGC_GPU_BASE (MX5_GPC_BASE + 0x260) > +#define MXC_SRPG_NEON_BASE (MX5_GPC_BASE + 0x280) > +#define MXC_SRPG_ARM_BASE (MX5_GPC_BASE + 0x2A0) > +#define MXC_SRPG_EMPGC0_BASE (MX5_GPC_BASE + 0x2C0) > +#define MXC_SRPG_EMPGC1_BASE (MX5_GPC_BASE + 0x2D0) > +#define MXC_SRPG_MEGAMIX_BASE (MX5_GPC_BASE + 0x2E0) > +#define MXC_SRPG_EMI_BASE (MX5_GPC_BASE + 0x300) > > /* CORTEXA8 platform */ > -#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0) > -#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4) > -#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8) > -#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC) > -#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10) > -#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14) > -#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18) > -#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20) > -#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24) > +#define MXC_CORTEXA8_PLAT_PVID (MX5_CORTEXA8_BASE + 0x0) > +#define MXC_CORTEXA8_PLAT_GPC (MX5_CORTEXA8_BASE + 0x4) > +#define MXC_CORTEXA8_PLAT_PIC (MX5_CORTEXA8_BASE + 0x8) > +#define MXC_CORTEXA8_PLAT_LPC (MX5_CORTEXA8_BASE + 0xC) > +#define MXC_CORTEXA8_PLAT_NEON_LPC (MX5_CORTEXA8_BASE + 0x10) > +#define MXC_CORTEXA8_PLAT_ICGC (MX5_CORTEXA8_BASE + 0x14) > +#define MXC_CORTEXA8_PLAT_AMC (MX5_CORTEXA8_BASE + 0x18) > +#define MXC_CORTEXA8_PLAT_NMC (MX5_CORTEXA8_BASE + 0x20) > +#define MXC_CORTEXA8_PLAT_NMS (MX5_CORTEXA8_BASE + 0x24) > > /* DVFS CORE */ > #define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) > @@ -547,11 +557,11 @@ > #define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) > > /* GPC */ > -#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0) > -#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4) > -#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8) > -#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC) > -#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10) > +#define MXC_GPC_CNTR (MX5_GPC_BASE + 0x0) > +#define MXC_GPC_PGR (MX5_GPC_BASE + 0x4) > +#define MXC_GPC_VCR (MX5_GPC_BASE + 0x8) > +#define MXC_GPC_ALL_PU (MX5_GPC_BASE + 0xC) > +#define MXC_GPC_NEON (MX5_GPC_BASE + 0x10) > #define MXC_GPC_PGR_ARMPG_OFFSET 8 > #define MXC_GPC_PGR_ARMPG_MASK (3 << 8) > > -- > 1.6.0.4 > > > -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/5] ARM: mx5: Allow CCM definitions to work on MX51 and MX53 2011-08-27 11:19 ` [PATCH 1/5] ARM: mx5: Allow CCM definitions to work on MX51 and MX53 Sascha Hauer @ 2011-08-27 15:17 ` Fabio Estevam 2011-08-27 18:39 ` Sascha Hauer 0 siblings, 1 reply; 8+ messages in thread From: Fabio Estevam @ 2011-08-27 15:17 UTC (permalink / raw) To: linux-arm-kernel On Sat, Aug 27, 2011 at 8:19 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > On Fri, Aug 26, 2011 at 04:21:57PM -0300, Fabio Estevam wrote: >> Allow CCM (Clock Control Module) definitions to work on MX51 and MX53 >> by checking the cpu type in run-time and using the appropriate register bases. > > They already work on i.MX51 and i.MX53. They have different physical > addresses, but have (more or less accidently...) the same virtual > address. Without this patch I get a kernel crash on MX53 at arch/arm/mach-mx5/system.c , when trying to read the following registers CCM registers: void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) { u32 plat_lpc, arm_srpgcr, ccm_clpcr; u32 empgc0, empgc1; int stop_mode = 0; /* always allow platform to issue a deep sleep mode request */ plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & ~(MXC_CORTEXA8_PLAT_LPC_DSM); ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); Regards, Fabio Estevam ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/5] ARM: mx5: Allow CCM definitions to work on MX51 and MX53 2011-08-27 15:17 ` Fabio Estevam @ 2011-08-27 18:39 ` Sascha Hauer 0 siblings, 0 replies; 8+ messages in thread From: Sascha Hauer @ 2011-08-27 18:39 UTC (permalink / raw) To: linux-arm-kernel On Sat, Aug 27, 2011 at 12:17:47PM -0300, Fabio Estevam wrote: > On Sat, Aug 27, 2011 at 8:19 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > > On Fri, Aug 26, 2011 at 04:21:57PM -0300, Fabio Estevam wrote: > >> Allow CCM (Clock Control Module) definitions to work on MX51 and MX53 > >> by checking the cpu type in run-time and using the appropriate register bases. > > > > They already work on i.MX51 and i.MX53. They have different physical > > addresses, but have (more or less accidently...) the same virtual > > address. > > Without this patch I get a kernel crash on MX53 at > arch/arm/mach-mx5/system.c , when trying to read > the following registers CCM registers: The CCM base address is AIPS1 + x whereas the ARM base address is AIPS2 + x. Maybe only the AIPS1 base addresses are the same. Anyway, I would prefer having the registers defines as offsets to a base and not as absolute addresses. Looking back it was a mistake merging this. Having the registers as offsets is much more flexible. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2011-08-27 18:39 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2011-08-26 19:21 [PATCH 1/5] ARM: mx5: Allow CCM definitions to work on MX51 and MX53 Fabio Estevam 2011-08-26 19:21 ` [PATCH 2/5] ARM: mx53: Register gpc_dvfs clock Fabio Estevam 2011-08-26 19:21 ` [PATCH 3/5] ARM: mx53: Fix the logic for BYPASS_MAX_LPM_HS Fabio Estevam 2011-08-26 19:22 ` [PATCH 5/5] ARM: mx53: Allow suspend/resume on mx53 Fabio Estevam 2011-08-26 19:22 ` [PATCH 4/5] ARM: mx53: Allow gpio_keys to wake the system Fabio Estevam 2011-08-27 11:19 ` [PATCH 1/5] ARM: mx5: Allow CCM definitions to work on MX51 and MX53 Sascha Hauer 2011-08-27 15:17 ` Fabio Estevam 2011-08-27 18:39 ` Sascha Hauer
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