[GIT PULL] ARM: Cavium CNS3xxx updates for 3.1

[GIT PULL] ARM: Cavium CNS3xxx updates for 3.1

[Anton Vorontsov]

Hi Arnd,

Please pull linux-cns3xxx.git tree to receive updates for CNS3xxx.
There are just two patches: the first patch corrects CPU type, and
the second adds L2 cache controller support, which doubles the
performance.

For the second patch, I fixed all the comments, plus added some
notes regarding why we don't want to select CACHE_PL310 for CNS3xxx.

For convenience' sake I inline the patches here, they're pretty
small.

Thanks!

The following changes since commit fe0d42203cb5616eeff68b14576a0f7e2dd56625:

  Linux 3.0-rc6 (2011-07-04 15:56:24 -0700)

are available in the git repository at:
  git://git.infradead.org/users/cbou/linux-cns3xxx.git master

Anton Vorontsov (1):
      ARM: cns3xxx: Add support for L2 Cache Controller

Imre Kaloz (1):
      ARM: cns3xxx: Should select CPU_V6K

 arch/arm/Kconfig                  |    2 +-
 arch/arm/mach-cns3xxx/cns3420vb.c |    2 +
 arch/arm/mach-cns3xxx/core.c      |   43 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-cns3xxx/core.h      |    6 +++++
 arch/arm/mm/Kconfig               |    2 +-
 5 files changed, 53 insertions(+), 2 deletions(-)



commit 93e85d8e902e1a4468c6ade5c6ec3dd3055a489f
Author: Anton Vorontsov <avorontsov@mvista.com>
Date:   Wed Jul 6 16:45:09 2011 +0400

    ARM: cns3xxx: Add support for L2 Cache Controller
    
    CNS3xxx SOCs have L310-compatible cache controller, so let's use it.
    
    With this patch benchmarking with 'gzip' shows that performance is
    doubled, and I'm still able to boot full-fledged userland over NFS
    (using PCIe NIC), so the support should be pretty robust.
    
    p.s. While CNS3xxx reports that it has PL310, it still needs to wait
    on cache line operations, so we should not select 'CACHE_PL310',
    which is a micro-optimization that removes these waits for v7 CPUs.
    Someday we'd better rename CACHE_PL310 Kconfig option into
    NO_CACHE_WAIT or something less ambiguous.
    
    Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>

diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 08e5c87..4b804ba 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -170,6 +170,8 @@ static struct platform_device *cns3420_pdevs[] __initdata = {
 
 static void __init cns3420_init(void)
 {
+	cns3xxx_l2x0_init();
+
 	platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
 
 	cns3xxx_ahci_init();
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index da30078..941a308 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -16,6 +16,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
 #include <mach/cns3xxx.h>
 #include "core.h"
 
@@ -244,3 +245,45 @@ static void __init cns3xxx_timer_init(void)
 struct sys_timer cns3xxx_timer = {
 	.init = cns3xxx_timer_init,
 };
+
+#ifdef CONFIG_CACHE_L2X0
+
+void __init cns3xxx_l2x0_init(void)
+{
+	void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
+	u32 val;
+
+	if (WARN_ON(!base))
+		return;
+
+	/*
+	 * Tag RAM Control register
+	 *
+	 * bit[10:8]	- 1 cycle of write accesses latency
+	 * bit[6:4]	- 1 cycle of read accesses latency
+	 * bit[3:0]	- 1 cycle of setup latency
+	 *
+	 * 1 cycle of latency for setup, read and write accesses
+	 */
+	val = readl(base + L2X0_TAG_LATENCY_CTRL);
+	val &= 0xfffff888;
+	writel(val, base + L2X0_TAG_LATENCY_CTRL);
+
+	/*
+	 * Data RAM Control register
+	 *
+	 * bit[10:8]	- 1 cycles of write accesses latency
+	 * bit[6:4]	- 1 cycles of read accesses latency
+	 * bit[3:0]	- 1 cycle of setup latency
+	 *
+	 * 1 cycle of latency for setup, read and write accesses
+	 */
+	val = readl(base + L2X0_DATA_LATENCY_CTRL);
+	val &= 0xfffff888;
+	writel(val, base + L2X0_DATA_LATENCY_CTRL);
+
+	/* 32 KiB, 8-way, parity disable */
+	l2x0_init(base, 0x00540000, 0xfe000fff);
+}
+
+#endif /* CONFIG_CACHE_L2X0 */
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index ffeb3a8..fcd2253 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -13,6 +13,12 @@
 
 extern struct sys_timer cns3xxx_timer;
 
+#ifdef CONFIG_CACHE_L2X0
+void __init cns3xxx_l2x0_init(void);
+#else
+static inline void cns3xxx_l2x0_init(void) {}
+#endif /* CONFIG_CACHE_L2X0 */
+
 void __init cns3xxx_map_io(void);
 void __init cns3xxx_init_irq(void);
 void cns3xxx_power_off(void);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 0074b8d..cb26d49 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -821,7 +821,7 @@ config CACHE_L2X0
 	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
 		   REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
 		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
-		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
+		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_CNS3XXX
 	default y
 	select OUTER_CACHE
 	select OUTER_CACHE_SYNC

commit 00d2711d700ae77b5bb66ea7c73eaa2cf155fa97
Author: Imre Kaloz <kaloz@openwrt.org>
Date:   Thu Jul 7 12:19:09 2011 +0200

    ARM: cns3xxx: Should select CPU_V6K
    
    CNS3XXX is based on MPCore, so select the right CPU option for it.
    
    Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
    Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9adc278..c2e5f3d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -321,7 +321,7 @@ config ARCH_CLPS711X
 
 config ARCH_CNS3XXX
 	bool "Cavium Networks CNS3XXX family"
-	select CPU_V6
+	select CPU_V6K
 	select GENERIC_CLOCKEVENTS
 	select ARM_GIC
 	select MIGHT_HAVE_PCI

[GIT PULL] ARM: Cavium CNS3xxx updates for 3.1

[Arnd Bergmann]

On Thursday 14 July 2011, Anton Vorontsov wrote:
> Please pull linux-cns3xxx.git tree to receive updates for CNS3xxx.
> There are just two patches: the first patch corrects CPU type, and
> the second adds L2 cache controller support, which doubles the
> performance.
> 
> For the second patch, I fixed all the comments, plus added some
> notes regarding why we don't want to select CACHE_PL310 for CNS3xxx.
> 
> For convenience' sake I inline the patches here, they're pretty
> small.

Pulled, thanks!

	Arnd

[GIT PULL] ARM: Cavium CNS3xxx updates for 3.1

[Anton Vorontsov]

Hi Arnd,

Please pull linux-cns3xxx.git tree to receive some fixes for CNS3xxx
platforms. Note that this is for 3.1.

Several post -rc1 commits broke CNS3xxx, and the pull request contains
patches to fix things. The patches are small, so for convenience' sake
I inline the them here.

Thanks!

The following changes since commit ddf28352b80c86754a6424e3a61e8bdf9213b3c7:

  Linux 3.1-rc5 (2011-09-04 15:45:10 -0700)

are available in the git repository at:
  git://git.infradead.org/users/cbou/linux-cns3xxx.git master

Anton Vorontsov (1):
      ARM: cns3xxx: Fix newly introduced warnings in the PCIe code

Tommy Lin (1):
      ARM: cns3xxx: Fix compile error caused by hardware.h removed

 arch/arm/mach-cns3xxx/include/mach/entry-macro.S |    1 -
 arch/arm/mach-cns3xxx/include/mach/system.h      |    1 -
 arch/arm/mach-cns3xxx/include/mach/uncompress.h  |    1 -
 arch/arm/mach-cns3xxx/pcie.c                     |    2 +-
 4 files changed, 1 insertions(+), 4 deletions(-)

- - -

commit 7caaf7efb98a4f713e4c8b16289e03874aace493
Author: Anton Vorontsov <cbouatmailru@gmail.com>
Date:   Fri Sep 9 23:18:00 2011 +0400

    ARM: cns3xxx: Fix newly introduced warnings in the PCIe code
    
    commit d5341942d784134f2997b3ff82cd63cf71d1f932 ("PCI: Make the struct
    pci_dev * argument of pci_fixup_irqs const") did not change argument
    of pdev_to_cnspci(), and thus introduced the following warnings:
    
      CHECK   arch/arm/mach-cns3xxx/pcie.c
    pcie.c:177:60: warning: incorrect type in argument 1 (different modifiers)
    pcie.c:177:60:    expected struct pci_dev *dev
    pcie.c:177:60:    got struct pci_dev const *dev
      CC      arch/arm/mach-cns3xxx/pcie.o
    pcie.c: In function 'cns3xxx_pcie_map_irq':
    pcie.c:177: warning: passing argument 1 of 'pdev_to_cnspci' discards qualifiers from pointer target type
    pcie.c:52: note: expected 'struct pci_dev *' but argument is of type 'const struct pci_dev *'
    
    This patch fixes the issue.
    
    Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>

diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 06fd25d..0f8fca4 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -49,7 +49,7 @@ static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
 	return &cns3xxx_pcie[root->domain];
 }
 
-static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev)
+static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
 {
 	return sysdata_to_cnspci(dev->sysdata);
 }

commit 83a497cab1baec75e3e493a96e3456db14729ce0
Author: Tommy Lin <tommy.lin.1101@gmail.com>
Date:   Fri Jul 29 01:14:46 2011 +0800

    ARM: cns3xxx: Fix compile error caused by hardware.h removed
    
    Commit c9d95fbe59e426eed7f16e7cac812e46ac4772d0 "ARM: convert PCI defines
    to variables" deleted cns3xxx' hardware.h, but didn't remove references
    for it, so do it now.
    
    This patch removes lines that refer to hardware.h.
    
    Signed-off-by: Tommy Lin <tommy.lin.1101@gmail.com>
    Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
    Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>

diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
index 6bd83ed..d87bfc3 100644
--- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
+++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
@@ -8,7 +8,6 @@
  * published by the Free Software Foundation.
  */
 
-#include <mach/hardware.h>
 #include <asm/hardware/entry-macro-gic.S>
 
 		.macro	disable_fiq
diff --git a/arch/arm/mach-cns3xxx/include/mach/system.h b/arch/arm/mach-cns3xxx/include/mach/system.h
index 58bb03a..4f16c9b 100644
--- a/arch/arm/mach-cns3xxx/include/mach/system.h
+++ b/arch/arm/mach-cns3xxx/include/mach/system.h
@@ -13,7 +13,6 @@
 
 #include <linux/io.h>
 #include <asm/proc-fns.h>
-#include <mach/hardware.h>
 
 static inline void arch_idle(void)
 {
diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
index de8ead9..a91b605 100644
--- a/arch/arm/mach-cns3xxx/include/mach/uncompress.h
+++ b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
@@ -8,7 +8,6 @@
  */
 
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
 #include <mach/cns3xxx.h>
 
 #define AMBA_UART_DR(base)	(*(volatile unsigned char *)((base) + 0x00))

[GIT PULL] ARM: Cavium CNS3xxx updates for 3.1

[Arnd Bergmann]

On Friday 09 September 2011, Anton Vorontsov wrote:
> Hi Arnd,
> 
> Please pull linux-cns3xxx.git tree to receive some fixes for CNS3xxx
> platforms. Note that this is for 3.1.
> 
> Several post -rc1 commits broke CNS3xxx, and the pull request contains
> patches to fix things. The patches are small, so for convenience' sake
> I inline the them here.

Ok, pulled. I've now started publishing the tree on
http://git.linaro.org/git/people/arnd/arm-soc.git while kernel.org
is done. It will move back once the server is up again.

Thanks!

	Arnd