* [RFC PATCH 1/5] ARM: OMAP: TI81XX: prcm: Add module and register offsets
2011-10-04 9:31 [RFC PATCH 0/5] Rework of the TI81xx PRCM support Paul Walmsley
@ 2011-10-04 9:31 ` Paul Walmsley
2011-10-04 9:31 ` [RFC PATCH 2/5] ARM: OMAP: TI81xx: add powerdomain code Paul Walmsley
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Paul Walmsley @ 2011-10-04 9:31 UTC (permalink / raw)
To: linux-arm-kernel
From: Hemant Pedanekar <hemantp@ti.com>
This patch adds some of the PRCM register offsets for the TI814X and
TI816X devices as required for the clockdomain, powerdomain, clock, and
hwmod data.
This patch is a collaboration between Hemant Pedanekar <hemantp@ti.com>
and Paul Walmsley <paul@pwsan.com>.
---
arch/arm/mach-omap2/Makefile | 1
arch/arm/mach-omap2/prcm814x.h | 62 +++++++++++++
arch/arm/mach-omap2/prcm816x.h | 186 +++++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/prcm81xx.c | 32 +++++++
arch/arm/mach-omap2/prcm81xx.h | 193 ++++++++++++++++++++++++++++++++++++++++
5 files changed, 474 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/prcm814x.h
create mode 100644 arch/arm/mach-omap2/prcm816x.h
create mode 100644 arch/arm/mach-omap2/prcm81xx.c
create mode 100644 arch/arm/mach-omap2/prcm81xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d4918ca..9c6b185 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
cm44xx.o prcm_mpu44xx.o \
prminst44xx.o vc44xx_data.o \
vp44xx_data.o
+obj-$(CONFIG_SOC_OMAPTI81XX) += prcm81xx.o
# OMAP voltage domains
ifeq ($(CONFIG_PM),y)
diff --git a/arch/arm/mach-omap2/prcm814x.h b/arch/arm/mach-omap2/prcm814x.h
new file mode 100644
index 0000000..82ea300
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm814x.h
@@ -0,0 +1,62 @@
+/*
+ * TI814X-specific PRCM register access macros
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM814X_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM814X_H
+
+#include "prcm81xx.h"
+
+/* TI814X-specific PRCM instances */
+#define TI814X_CM_HDVICP_INST 0x0600 /* 256B */
+#define TI814X_CM_ISP_INST 0x0700 /* 256B */
+#define TI814X_CM_DSS_INST 0x0800 /* 256B */
+#define TI814X_PRM_HDVICP_INST 0x0c00 /* 256B */
+#define TI814X_PRM_ISP_INST 0x0d00 /* 256B */
+#define TI814X_PRM_DSS_INST 0x0e00 /* 256B */
+#define TI814X_PRM_ALWON_INST 0x1800 /* 1KiB */
+
+
+/*
+ * TI814x-specific PRCM registers offsets. The offsets below are
+ * relative to the PRCM instance base.
+ */
+
+/* CM_ALWON */
+#define TI814X_CM_ALWON_L3_SLOW_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_ALWON_L3_SLOW_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0000)
+#define TI814X_CM_ALWON_L3_MED_CLKSTCTRL_OFFSET 0x0008
+#define TI814X_CM_ALWON_L3_MED_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0008)
+
+/* CM_HDVICP */
+#define TI814X_CM_HDVICP_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_HDVICP_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_HDVICP_INST, 0x0000)
+
+/* CM_ISP */
+#define TI814X_CM_ISP_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_ISP_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ISP_INST, 0x0000)
+
+/* CM_DSS */
+#define TI814X_CM_DSS_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_DSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ISP_INST, 0x0000)
+
+/* CM_DEFAULT */
+#define TI814X_CM_DEFAULT_TPPSS_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_DEFAULT_TPPSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0000)
+#define TI814X_CM_DEFAULT_PCI_CLKSTCTRL_OFFSET 0x0004
+#define TI814X_CM_DEFAULT_PCI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0004)
+#define TI814X_CM_DEFAULT_DUCATI_CLKSTCTRL_OFFSET 0x000c
+#define TI814X_CM_DEFAULT_DUCATI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x000c)
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm816x.h b/arch/arm/mach-omap2/prcm816x.h
new file mode 100644
index 0000000..74491d9
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm816x.h
@@ -0,0 +1,186 @@
+/*
+ * TI816X-specific PRCM register access macros
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM816X_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM816X_H
+
+#include "prcm81xx.h"
+
+/*
+ * TI816x-specific PRCM registers offsets. The offsets below are
+ * relative to the PRCM instance base.
+ */
+
+/* CM_DPLL */
+#define TI816X_CM_DPLL_SYSCLK1_CLKSEL_OFFSET 0x0000
+#define TI816X_CM_DPLL_SYSCLK1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0000)
+#define TI816X_CM_DPLL_SYSCLK2_CLKSEL_OFFSET 0x0004
+#define TI816X_CM_DPLL_SYSCLK2_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0004)
+#define TI816X_CM_DPLL_SYSCLK3_CLKSEL_OFFSET 0x0008
+#define TI816X_CM_DPLL_SYSCLK3_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0008)
+#define TI816X_CM_DPLL_SYSCLK4_CLKSEL_OFFSET 0x000C
+#define TI816X_CM_DPLL_SYSCLK4_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x000C)
+#define TI816X_CM_DPLL_SYSCLK5_CLKSEL_OFFSET 0x0010
+#define TI816X_CM_DPLL_SYSCLK5_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0010)
+#define TI816X_CM_DPLL_SYSCLK6_CLKSEL_OFFSET 0x0014
+#define TI816X_CM_DPLL_SYSCLK6_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0014)
+#define TI816X_CM_DPLL_SYSCLK7_CLKSEL_OFFSET 0x0018
+#define TI816X_CM_DPLL_SYSCLK7_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0018)
+#define TI816X_CM_DPLL_SYSCLK10_CLKSEL_OFFSET 0x0024
+#define TI816X_CM_DPLL_SYSCLK10_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0024)
+#define TI816X_CM_DPLL_SYSCLK11_CLKSEL_OFFSET 0x002C
+#define TI816X_CM_DPLL_SYSCLK11_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x002C)
+#define TI816X_CM_DPLL_SYSCLK12_CLKSEL_OFFSET 0x0030
+#define TI816X_CM_DPLL_SYSCLK12_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0030)
+#define TI816X_CM_DPLL_SYSCLK13_CLKSEL_OFFSET 0x0034
+#define TI816X_CM_DPLL_SYSCLK13_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0034)
+#define TI816X_CM_DPLL_SYSCLK15_CLKSEL_OFFSET 0x0038
+#define TI816X_CM_DPLL_SYSCLK15_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0038)
+#define TI816X_CM_DPLL_VPB3_CLKSEL_OFFSET 0x0040
+#define TI816X_CM_DPLL_VPB3_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0040)
+#define TI816X_CM_DPLL_VPC1_CLKSEL_OFFSET 0x0044
+#define TI816X_CM_DPLL_VPC1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0044)
+#define TI816X_CM_DPLL_VPD1_CLKSEL_OFFSET 0x0048
+#define TI816X_CM_DPLL_VPD1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0048)
+#define TI816X_CM_DPLL_SYSCLK19_CLKSEL_OFFSET 0x004C
+#define TI816X_CM_DPLL_SYSCLK19_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x004C)
+#define TI816X_CM_DPLL_SYSCLK20_CLKSEL_OFFSET 0x0050
+#define TI816X_CM_DPLL_SYSCLK20_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0050)
+#define TI816X_CM_DPLL_SYSCLK21_CLKSEL_OFFSET 0x0054
+#define TI816X_CM_DPLL_SYSCLK21_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0054)
+#define TI816X_CM_DPLL_SYSCLK22_CLKSEL_OFFSET 0x0058
+#define TI816X_CM_DPLL_SYSCLK22_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0058)
+#define TI816X_CM_DPLL_APA_CLKSEL_OFFSET 0x005C
+#define TI816X_CM_DPLL_APA_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x005C)
+#define TI816X_CM_DPLL_SYSCLK14_CLKSEL_OFFSET 0x0070
+#define TI816X_CM_DPLL_SYSCLK14_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0070)
+#define TI816X_CM_DPLL_SYSCLK16_CLKSEL_OFFSET 0x0074
+#define TI816X_CM_DPLL_SYSCLK16_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0074)
+#define TI816X_CM_DPLL_SYSCLK18_CLKSEL_OFFSET 0x0078
+#define TI816X_CM_DPLL_SYSCLK18_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0078)
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP0_CLKSEL_OFFSET 0x007C
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP0_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x007C)
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP1_CLKSEL_OFFSET 0x0080
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0080)
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP2_CLKSEL_OFFSET 0x0084
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP2_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0084)
+#define TI816X_CM_DPLL_AUDIOCLK_MCBSP_CLKSEL_OFFSET 0x0088
+#define TI816X_CM_DPLL_AUDIOCLK_MCBSP_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0088)
+#define TI816X_CM_DPLL_TIMER1_CLKSEL_OFFSET 0x0090
+#define TI816X_CM_DPLL_TIMER1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0090)
+#define TI816X_CM_DPLL_TIMER2_CLKSEL_OFFSET 0x0094
+#define TI816X_CM_DPLL_TIMER2_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0094)
+#define TI816X_CM_DPLL_TIMER3_CLKSEL_OFFSET 0x0098
+#define TI816X_CM_DPLL_TIMER3_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0098)
+#define TI816X_CM_DPLL_TIMER4_CLKSEL_OFFSET 0x009C
+#define TI816X_CM_DPLL_TIMER4_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x009C)
+#define TI816X_CM_DPLL_TIMER5_CLKSEL_OFFSET 0x00A0
+#define TI816X_CM_DPLL_TIMER5_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00A0)
+#define TI816X_CM_DPLL_TIMER6_CLKSEL_OFFSET 0x00A4
+#define TI816X_CM_DPLL_TIMER6_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00A4)
+#define TI816X_CM_DPLL_TIMER7_CLKSEL_OFFSET 0x00A8
+#define TI816X_CM_DPLL_TIMER7_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00A8)
+#define TI816X_CM_DPLL_HDMI_CLKSEL_OFFSET 0x00AC
+#define TI816X_CM_DPLL_HDMI_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00AC)
+#define TI816X_CM_DPLL_SYSCLK23_CLKSEL_OFFSET 0x00B0
+#define TI816X_CM_DPLL_SYSCLK23_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00B0)
+#define TI816X_CM_DPLL_SYSCLK24_CLKSEL_OFFSET 0x00B4
+#define TI816X_CM_DPLL_SYSCLK24_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00B4)
+
+/* CM_DEFAULT */
+#define TI816X_CM_DEFAULT_L3_MED_CLKSTCTRL_OFFSET 0x0004
+#define TI816X_CM_DEFAULT_L3_MED_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0004)
+#define TI816X_CM_DEFAULT_L3_FAST_CLKSTCTRL_OFFSET 0x0008
+#define TI816X_CM_DEFAULT_L3_FAST_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0008)
+#define TI816X_CM_DEFAULT_TPPSS_CLKSTCTRL_OFFSET 0x000C
+#define TI816X_CM_DEFAULT_TPPSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x000C)
+#define TI816X_CM_DEFAULT_PCI_CLKSTCTRL_OFFSET 0x0010
+#define TI816X_CM_DEFAULT_PCI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0010)
+#define TI816X_CM_DEFAULT_L3_SLOW_CLKSTCTRL_OFFSET 0x0014
+#define TI816X_CM_DEFAULT_L3_SLOW_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0014)
+#define TI816X_CM_DEFAULT_DUCATI_CLKSTCTRL_OFFSET 0x0018
+#define TI816X_CM_DEFAULT_DUCATI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0018)
+#define TI816X_CM_DEFAULT_EMIF_0_CLKCTRL_OFFSET 0x0020
+#define TI816X_CM_DEFAULT_EMIF_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0020)
+#define TI816X_CM_DEFAULT_EMIF_1_CLKCTRL_OFFSET 0x0024
+#define TI816X_CM_DEFAULT_EMIF_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0024)
+#define TI816X_CM_DEFAULT_DMM_CLKCTRL_OFFSET 0x0028
+#define TI816X_CM_DEFAULT_DMM_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0028)
+#define TI816X_CM_DEFAULT_FW_CLKCTRL_OFFSET 0x002C
+#define TI816X_CM_DEFAULT_FW_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x002C)
+#define TI816X_CM_DEFAULT_TPPSS_CLKCTRL_OFFSET 0x0054
+#define TI816X_CM_DEFAULT_TPPSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0054)
+#define TI816X_CM_DEFAULT_USB_CLKCTRL_OFFSET 0x0058
+#define TI816X_CM_DEFAULT_USB_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0058)
+#define TI816X_CM_DEFAULT_SATA_CLKCTRL_OFFSET 0x0060
+#define TI816X_CM_DEFAULT_SATA_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0060)
+#define TI816X_CM_DEFAULT_DUCATI_CLKCTRL_OFFSET 0x0074
+#define TI816X_CM_DEFAULT_DUCATI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0074)
+#define TI816X_CM_DEFAULT_PCI_CLKCTRL_OFFSET 0x0078
+#define TI816X_CM_DEFAULT_PCI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0078)
+
+/* CM_ALWON */
+#define TI816X_CM_ALWON_OCMC_1_CLKSTCTRL_OFFSET 0x0018
+#define TI816X_CM_ALWON_OCMC_1_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0018)
+#define TI816X_CM_ALWON_MPU_CLKSTCTRL_OFFSET 0x001C
+#define TI816X_CM_ALWON_MPU_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x001C)
+#define TI816X_CM_ALWON_TIMER_0_CLKCTRL_OFFSET 0x016C
+#define TI816X_CM_ALWON_TIMER_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x016C)
+#define TI816X_CM_ALWON_TIMER_1_CLKCTRL_OFFSET 0x0170
+#define TI816X_CM_ALWON_TIMER_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0170)
+#define TI816X_CM_ALWON_TIMER_2_CLKCTRL_OFFSET 0x0174
+#define TI816X_CM_ALWON_TIMER_2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0174)
+#define TI816X_CM_ALWON_TIMER_3_CLKCTRL_OFFSET 0x0178
+#define TI816X_CM_ALWON_TIMER_3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0178)
+#define TI816X_CM_ALWON_TIMER_5_CLKCTRL_OFFSET 0x0180
+#define TI816X_CM_ALWON_TIMER_5_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0180)
+#define TI816X_CM_ALWON_TIMER_6_CLKCTRL_OFFSET 0x0184
+#define TI816X_CM_ALWON_TIMER_6_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0184)
+#define TI816X_CM_ALWON_TIMER_7_CLKCTRL_OFFSET 0x0188
+#define TI816X_CM_ALWON_TIMER_7_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0188)
+#define TI816X_CM_ALWON_OCMC_1_CLKCTRL_OFFSET 0x01B8
+#define TI816X_CM_ALWON_OCMC_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01B8)
+#define TI816X_CM_ALWON_SMARTCARD_0_CLKCTR_OFFSET 0x01BC
+#define TI816X_CM_ALWON_SMARTCARD_0_CLKCTR TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01BC)
+#define TI816X_CM_ALWON_SMARTCARD_1_CLKCTR_OFFSET 0x01C0
+#define TI816X_CM_ALWON_SMARTCARD_1_CLKCTR TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01C0)
+#define TI816X_CM_ALWON_SECSS_CLKCTRL_OFFSET 0x01C8
+#define TI816X_CM_ALWON_SECSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01C8)
+#define TI816X_CM_ALWON_SR_2_CLKCTRL_OFFSET 0x0210
+#define TI816X_CM_ALWON_SR_2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0210)
+#define TI816X_CM_ALWON_SR_3_CLKCTRL_OFFSET 0x0214
+#define TI816X_CM_ALWON_SR_3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0214)
+#define TI816X_CM_ALWON_SR_4_CLKCTRL_OFFSET 0x0218
+#define TI816X_CM_ALWON_SR_4_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0218)
+#define TI816X_CM_ALWON_SR_5_CLKCTRL_OFFSET 0x021C
+#define TI816X_CM_ALWON_SR_5_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x021C)
+#define TI816X_CM_ALWON_SR_6_CLKCTRL_OFFSET 0x0220
+#define TI816X_CM_ALWON_SR_6_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0220)
+#define TI816X_CM_ALWON_SR_7_CLKCTRL_OFFSET 0x0224
+#define TI816X_CM_ALWON_SR_7_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0224)
+#define TI816X_CM_ALWON_CUST_EFUSE_CLKCTRL_OFFSET 0x0228
+#define TI816X_CM_ALWON_CUST_EFUSE_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0228)
+
+/* CM_ACTIVE */
+#define TI816X_CM_ACTIVE_HDDSS_CLKSTCTRL_OFFSET 0x0004
+#define TI816X_CM_ACTIVE_HDDSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0004)
+#define TI816X_CM_ACTIVE_HDMI_CLKSTCTRL_OFFSET 0x0008
+#define TI816X_CM_ACTIVE_HDMI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0008)
+#define TI816X_CM_ACTIVE_HDDSS_CLKCTRL_OFFSET 0x0024
+#define TI816X_CM_ACTIVE_HDDSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0024)
+#define TI816X_CM_ACTIVE_HDMI_CLKCTRL_OFFSET 0x0028
+#define TI816X_CM_ACTIVE_HDMI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0028)
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm81xx.c b/arch/arm/mach-omap2/prcm81xx.c
new file mode 100644
index 0000000..d48e5fc
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm81xx.c
@@ -0,0 +1,32 @@
+/*
+ * TI81XX PRCM register access functions
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+#include "prcm81xx.h"
+
+static u32 ti81xx_prcm_inst_read(u16 inst, u16 offs)
+{
+ return __raw_readl(prm_base + inst + offs);
+}
+
+static void ti81xx_prcm_inst_write(u32 v, u16 inst, u16 offs)
+{
+ __raw_writel(v, prm_base + inst + offs);
+}
+
+
diff --git a/arch/arm/mach-omap2/prcm81xx.h b/arch/arm/mach-omap2/prcm81xx.h
new file mode 100644
index 0000000..fd0a174
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm81xx.h
@@ -0,0 +1,193 @@
+/*
+ * TI81XX PRCM register access macros and module offsets
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM81XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM81XX_H
+
+#include "prcm-common.h"
+
+#define TI81XX_PRCM_REGADDR(instance, reg) \
+ OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE + (instance) + (reg))
+
+/*
+ * TI81XX-common PRM/CM instance offsets
+ */
+#define TI81XX_PRM_DEVICE_INST 0x0000 /* 256B */
+#define TI81XX_CM_DEVICE_INST 0x0100 /* 256B */
+#define TI81XX_PRM_OCP_SOCKET_INST 0x0200 /* 256B */
+#define TI81XX_CM_DPLL_INST 0x0300 /* 256B */
+#define TI81XX_CM_ACTIVE_INST 0x0400 /* 256B */
+#define TI81XX_CM_DEFAULT_INST 0x0500 /* 256B */
+#define TI81XX_CM_SGX_INST 0x0900 /* 256B */
+#define TI81XX_PRM_ACTIVE_INST 0x0a00 /* 256B */
+#define TI81XX_PRM_DEFAULT_INST 0x0b00 /* 256B */
+#define TI81XX_PRM_SGX_INST 0x0f00 /* 256B */
+#define TI81XX_CM_ALWON_INST 0x1400 /* 1KB */
+
+/*
+ * TI81xx-common register offsets
+ */
+
+/* PRM_DEVICE */
+#define TI81XX_PRM_DEVICE_RSTCTRL_OFFSET 0x0000
+#define TI81XX_PRM_DEVICE_RSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_DEVICE_INST, 0x0000)
+#define TI81XX_PRM_DEVICE_RSTTIME_OFFSET 0x0004
+#define TI81XX_PRM_DEVICE_RSTTIME TI81XX_PRCM_REGADDR(TI81XX_PRM_DEVICE_INST, 0x0004)
+#define TI81XX_PRM_DEVICE_RSTST_OFFSET 0x0008
+#define TI81XX_PRM_DEVICE_RSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_DEVICE_INST, 0x0008)
+
+/* CM_DEVICE */
+#define TI81XX_CM_DEVICE_CLKOUT_CTRL_OFFSET 0x0000
+#define TI81XX_CM_DEVICE_CLKOUT_CTRL TI81XX_PRCM_REGADDR(TI81XX_CM_DEVICE_INST, 0x0000)
+
+/* OCP_SOCKET_PRM */
+#define TI81XX_PRM_OCP_SOCKET_REVISION_OFFSET 0x0000
+#define TI81XX_PRM_OCP_SOCKET_REVISION TI81XX_PRCM_REGADDR(TI81XX_PRM_OCP_SOCKET_INST, 0x0000)
+
+/* CM_ACTIVE */
+#define TI81XX_CM_ACTIVE_GEM_CLKSTCTRL_OFFSET 0x0000
+#define TI81XX_CM_ACTIVE_GEM_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0000)
+#define TI81XX_CM_ACTIVE_GEM_CLKCTRL_OFFSET 0x0020
+#define TI81XX_CM_ACTIVE_GEM_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0020)
+
+/* CM_SGX */
+#define TI81XX_CM_SGX_SGX_CLKSTCTRL_OFFSET 0x0000
+#define TI81XX_CM_SGX_SGX_CLKSTCTRL TI81XX_PRCM_REGADDR(TI81XX_CM_SGX_INST, 0x0000)
+#define TI81XX_CM_SGX_SGX_SGX_CLKCTRL_OFFSET 0x0020
+#define TI81XX_CM_SGX_SGX_SGX_CLKCTRL TI81XX_PRCM_REGADDR(TI81XX_CM_SGX_INST, 0x0020)
+
+/* PRM_ACTIVE */
+#define TI81XX_PRM_ACTIVE_PM_PWRSTCTRL_OFFSET 0x0000
+#define TI81XX_PRM_ACTIVE_PM_PWRSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0000)
+#define TI81XX_PRM_ACTIVE_PM_PWRSTST_OFFSET 0x0004
+#define TI81XX_PRM_ACTIVE_PM_PWRSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0004)
+#define TI81XX_PRM_ACTIVE_RM_RSTCTRL_OFFSET 0x0010
+#define TI81XX_PRM_ACTIVE_RM_RSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0010)
+#define TI81XX_PRM_ACTIVE_RM_RSTST_OFFSET 0x0014
+#define TI81XX_PRM_ACTIVE_RM_RSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0014)
+
+/* PRM_SGX */
+#define TI81XX_PRM_SGX_PM_PWRSTCTRL_OFFSET 0x0000
+#define TI81XX_PRM_SGX_PM_PWRSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0000)
+#define TI81XX_PRM_SGX_PM_PWRSTST_OFFSET 0x0004
+#define TI81XX_PRM_SGX_PM_PWRSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0004)
+#define TI81XX_PRM_SGX_RM_RSTCTRL_OFFSET 0x0010
+#define TI81XX_PRM_SGX_RM_RSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0010)
+#define TI81XX_PRM_SGX_RM_RSTST_OFFSET 0x0014
+#define TI81XX_PRM_SGX_RM_RSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0014)
+
+/* CM_ALWON */
+#define TI81XX_CM_ALWON_L3_SLOW_CLKSTCTRL_OFFSET 0x0000
+#define TI81XX_CM_ALWON_L3_SLOW_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0000)
+#define TI81XX_CM_ETHERNET_CLKSTCTRL_OFFSET 0x0004
+#define TI81XX_CM_ETHERNET_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0004)
+#define TI81XX_CM_ALWON_L3_MED_CLKSTCTRL_OFFSET 0x0008
+#define TI81XX_CM_ALWON_L3_MED_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0008)
+#define TI81XX_CM_MMU_CLKSTCTRL_OFFSET 0x000C
+#define TI81XX_CM_MMU_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x000C)
+#define TI81XX_CM_MMUCFG_CLKSTCTRL_OFFSET 0x0010
+#define TI81XX_CM_MMUCFG_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0010)
+#define TI81XX_CM_ALWON_OCMC_0_CLKSTCTRL_OFFSET 0x0014
+#define TI81XX_CM_ALWON_OCMC_0_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0014)
+#define TI81XX_CM_ALWON_SYSCLK4_CLKSTCTRL_OFFSET 0x0020
+#define TI81XX_CM_ALWON_SYSCLK4_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0020)
+#define TI81XX_CM_ALWON_SYSCLK5_CLKSTCTRL_OFFSET 0x0024
+#define TI81XX_CM_ALWON_SYSCLK5_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0024)
+#define TI81XX_CM_ALWON_SYSCLK6_CLKSTCTRL_OFFSET 0x0028
+#define TI81XX_CM_ALWON_SYSCLK6_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0028)
+#define TI81XX_CM_ALWON_RTC_CLKSTCTRL_OFFSET 0x002C
+#define TI81XX_CM_ALWON_RTC_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x002C)
+#define TI81XX_CM_ALWON_L3_FAST_CLKSTCTRL_OFFSET 0x0030
+#define TI81XX_CM_ALWON_L3_FAST_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0030)
+#define TI81XX_CM_ALWON_MCASP0_CLKCTRL_OFFSET 0x0140
+#define TI81XX_CM_ALWON_MCASP0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0140)
+#define TI81XX_CM_ALWON_MCASP1_CLKCTRL_OFFSET 0x0144
+#define TI81XX_CM_ALWON_MCASP1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0144)
+#define TI81XX_CM_ALWON_MCASP2_CLKCTRL_OFFSET 0x0148
+#define TI81XX_CM_ALWON_MCASP2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0148)
+#define TI81XX_CM_ALWON_MCBSP_CLKCTRL_OFFSET 0x014C
+#define TI81XX_CM_ALWON_MCBSP_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x014C)
+#define TI81XX_CM_ALWON_UART_0_CLKCTRL_OFFSET 0x0150
+#define TI81XX_CM_ALWON_UART_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0150)
+#define TI81XX_CM_ALWON_UART_1_CLKCTRL_OFFSET 0x0154
+#define TI81XX_CM_ALWON_UART_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0154)
+#define TI81XX_CM_ALWON_UART_2_CLKCTRL_OFFSET 0x0158
+#define TI81XX_CM_ALWON_UART_2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0158)
+#define TI81XX_CM_ALWON_GPIO_0_CLKCTRL_OFFSET 0x015C
+#define TI81XX_CM_ALWON_GPIO_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x015C)
+#define TI81XX_CM_ALWON_GPIO_1_CLKCTRL_OFFSET 0x0160
+#define TI81XX_CM_ALWON_GPIO_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0160)
+#define TI81XX_CM_ALWON_I2C_0_CLKCTRL_OFFSET 0x0164
+#define TI81XX_CM_ALWON_I2C_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0164)
+#define TI81XX_CM_ALWON_I2C_1_CLKCTRL_OFFSET 0x0168
+#define TI81XX_CM_ALWON_I2C_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0168)
+#define TI81XX_CM_ALWON_TIMER_4_CLKCTRL_OFFSET 0x017C
+#define TI81XX_CM_ALWON_TIMER_4_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x017C)
+#define TI81XX_CM_ALWON_WDTIMER_CLKCTRL_OFFSET 0x018C
+#define TI81XX_CM_ALWON_WDTIMER_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x018C)
+#define TI81XX_CM_ALWON_SPI_CLKCTRL_OFFSET 0x0190
+#define TI81XX_CM_ALWON_SPI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0190)
+#define TI81XX_CM_ALWON_MAILBOX_CLKCTRL_OFFSET 0x0194
+#define TI81XX_CM_ALWON_MAILBOX_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0194)
+#define TI81XX_CM_ALWON_SPINBOX_CLKCTRL_OFFSET 0x0198
+#define TI81XX_CM_ALWON_SPINBOX_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0198)
+#define TI81XX_CM_ALWON_MMUDATA_CLKCTRL_OFFSET 0x019C
+#define TI81XX_CM_ALWON_MMUDATA_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x019C)
+#define TI81XX_CM_ALWON_VLYNQ_CLKCTRL_OFFSET 0x01A0
+#define TI81XX_CM_ALWON_VLYNQ_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01A0)
+#define TI81XX_CM_ALWON_MMUCFG_CLKCTRL_OFFSET 0x01A8
+#define TI81XX_CM_ALWON_MMUCFG_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01A8)
+#define TI81XX_CM_ALWON_SDIO_CLKCTRL_OFFSET 0x01B0
+#define TI81XX_CM_ALWON_SDIO_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01B0)
+#define TI81XX_CM_ALWON_OCMC_0_CLKCTRL_OFFSET 0x01B4
+#define TI81XX_CM_ALWON_OCMC_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01B4)
+#define TI81XX_CM_ALWON_CONTROL_CLKCTRL_OFFSET 0x01C4
+#define TI81XX_CM_ALWON_CONTROL_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01C4)
+#define TI81XX_CM_ALWON_GPMC_CLKCTRL_OFFSET 0x01D0
+#define TI81XX_CM_ALWON_GPMC_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01D0)
+#define TI81XX_CM_ALWON_ETHERNET_0_CLKCTRL_OFFSET 0x01D4
+#define TI81XX_CM_ALWON_ETHERNET_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01D4)
+#define TI81XX_CM_ALWON_ETHERNET_1_CLKCTRL_OFFSET 0x01D8
+#define TI81XX_CM_ALWON_ETHERNET_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01D8)
+#define TI81XX_CM_ALWON_MPU_CLKCTRL_OFFSET 0x01DC
+#define TI81XX_CM_ALWON_MPU_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01DC)
+#define TI81XX_CM_ALWON_DEBUGSS_CLKCTRL_OFFSET 0x01E0
+#define TI81XX_CM_ALWON_DEBUGSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01E0)
+#define TI81XX_CM_ALWON_L3_CLKCTRL_OFFSET 0x01E4
+#define TI81XX_CM_ALWON_L3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01E4)
+#define TI81XX_CM_ALWON_L4HS_CLKCTRL_OFFSET 0x01E8
+#define TI81XX_CM_ALWON_L4HS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01E8)
+#define TI81XX_CM_ALWON_L4LS_CLKCTRL_OFFSET 0x01EC
+#define TI81XX_CM_ALWON_L4LS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01EC)
+#define TI81XX_CM_ALWON_RTC_CLKCTRL_OFFSET 0x01F0
+#define TI81XX_CM_ALWON_RTC_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01F0)
+#define TI81XX_CM_ALWON_TPCC_CLKCTRL_OFFSET 0x01F4
+#define TI81XX_CM_ALWON_TPCC_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01F4)
+#define TI81XX_CM_ALWON_TPTC0_CLKCTRL_OFFSET 0x01F8
+#define TI81XX_CM_ALWON_TPTC0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01F8)
+#define TI81XX_CM_ALWON_TPTC1_CLKCTRL_OFFSET 0x01FC
+#define TI81XX_CM_ALWON_TPTC1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01FC)
+#define TI81XX_CM_ALWON_TPTC2_CLKCTRL_OFFSET 0x0200
+#define TI81XX_CM_ALWON_TPTC2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0200)
+#define TI81XX_CM_ALWON_TPTC3_CLKCTRL_OFFSET 0x0204
+#define TI81XX_CM_ALWON_TPTC3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0204)
+#define TI81XX_CM_ALWON_SR_0_CLKCTRL_OFFSET 0x0208
+#define TI81XX_CM_ALWON_SR_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0208)
+#define TI81XX_CM_ALWON_SR_1_CLKCTRL_OFFSET 0x020C
+#define TI81XX_CM_ALWON_SR_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x020C)
+
+/* Function prototypes */
+
+#endif
^ permalink raw reply related [flat|nested] 6+ messages in thread* [RFC PATCH 2/5] ARM: OMAP: TI81xx: add powerdomain code
2011-10-04 9:31 [RFC PATCH 0/5] Rework of the TI81xx PRCM support Paul Walmsley
2011-10-04 9:31 ` [RFC PATCH 1/5] ARM: OMAP: TI81XX: prcm: Add module and register offsets Paul Walmsley
@ 2011-10-04 9:31 ` Paul Walmsley
2011-10-04 9:31 ` [RFC PATCH 3/5] ARM: OMAP: TI81xx: add powerdomain data Paul Walmsley
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Paul Walmsley @ 2011-10-04 9:31 UTC (permalink / raw)
To: linux-arm-kernel
TI81xx uses a novel PRCM register layout. It most closely resembles
the OMAP4 PRCM, but with a few changes. These devices also have
limited power management functionality.
Add powerdomain & PRCM implementation code for the TI81xx chips.
This patch is a collaboration between Hemant Pedanekar <hemantp@ti.com>
and Paul Walmsley <paul@pwsan.com>.
---
arch/arm/mach-omap2/Makefile | 2 +
arch/arm/mach-omap2/powerdomain.h | 1
arch/arm/mach-omap2/powerdomain81xx.c | 81 +++++++++++++++++++++++++++
arch/arm/mach-omap2/prcm-regbits-81xx.h | 23 ++++++++
arch/arm/mach-omap2/prcm81xx.c | 93 +++++++++++++++++++++++++++++++
arch/arm/mach-omap2/prcm81xx.h | 14 +++++
6 files changed, 214 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/powerdomain81xx.c
create mode 100644 arch/arm/mach-omap2/prcm-regbits-81xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 9c6b185..292941d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -112,6 +112,8 @@ obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common) \
obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \
powerdomain44xx.o \
powerdomains44xx_data.o
+obj-$(CONFIG_SOC_OMAPTI81XX) += $(powerdomain-common) \
+ powerdomain81xx.o
# PRCM clockdomain control
obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 8febd84..b3d51f2 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -218,6 +218,7 @@ extern void omap44xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
extern struct pwrdm_ops omap4_pwrdm_operations;
+extern struct pwrdm_ops ti81xx_pwrdm_operations;
/* Common Internal functions used across OMAP rev's */
extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
diff --git a/arch/arm/mach-omap2/powerdomain81xx.c b/arch/arm/mach-omap2/powerdomain81xx.c
new file mode 100644
index 0000000..c78db22
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain81xx.c
@@ -0,0 +1,81 @@
+/*
+ * TI81xx powerdomain control
+ *
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
+ *
+ * Rajendra Nayak <rnayak@ti.com>
+ * Paul Walmsley
+ * Hemant Pedanekar
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+#include <plat/prcm.h>
+
+#include "powerdomain.h"
+#include "prcm81xx.h"
+
+static int ti81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+ ti81xx_prcm_pwrdm_set_powerstate(pwrdm->prcm_offs, pwrst);
+ return 0;
+}
+
+static int ti81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+ return ti81xx_prcm_pwrdm_read_powerstate(pwrdm->prcm_offs);
+}
+
+static int ti81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+ return ti81xx_prcm_pwrdm_read_powerstatest(pwrdm->prcm_offs);
+}
+
+static int ti81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+ return ti81xx_prcm_pwrdm_read_logicstatest(pwrdm->prcm_offs);
+}
+
+static int ti81xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+ return ti81xx_prcm_pwrdm_read_mem_statest(pwrdm->prcm_offs);
+}
+
+static int ti81xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+ ti81xx_prcm_pwrdm_set_lowpowerstatechange(pwrdm->prcm_offs);
+ return 0;
+}
+
+static int ti81xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+ int r;
+
+ r = ti81xx_prcm_pwrdm_wait_transition(pwrdm->prcm_offs);
+ if (r == -ETIMEDOUT) {
+ pr_err("powerdomain: waited too long for powerdomain %s to complete transition\n",
+ pwrdm->name);
+ return -EAGAIN;
+ }
+
+ pr_debug("powerdomain: completed transition in %d loops\n", r);
+
+ return 0;
+}
+
+struct pwrdm_ops ti81xx_pwrdm_operations = {
+ .pwrdm_set_next_pwrst = ti81xx_pwrdm_set_next_pwrst,
+ .pwrdm_read_next_pwrst = ti81xx_pwrdm_read_next_pwrst,
+ .pwrdm_read_pwrst = ti81xx_pwrdm_read_pwrst,
+ .pwrdm_set_lowpwrstchange = ti81xx_pwrdm_set_lowpwrstchange,
+ .pwrdm_read_logic_pwrst = ti81xx_pwrdm_read_logic_pwrst,
+ .pwrdm_read_mem_pwrst = ti81xx_pwrdm_read_mem_pwrst,
+ .pwrdm_wait_transition = ti81xx_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/prcm-regbits-81xx.h b/arch/arm/mach-omap2/prcm-regbits-81xx.h
new file mode 100644
index 0000000..8eda6b0
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm-regbits-81xx.h
@@ -0,0 +1,23 @@
+/*
+ * OMAP81xx PRCM register bits
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *
+ * Paul Walmsley (paul at pwsan.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_REGBITS_81XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_REGBITS_81XX_H
+
+/*
+ * Used by PM_ACTIVE_PWRSTST, PM_HDVICP_PWRSTST, PM_ISP_PWRSTST,
+ * PM_DSS_PWRSTST, PM_SGX_PWRSTST
+ */
+#define TI81XX_MEM_STATEST_SHIFT 4
+#define TI81XX_MEM_STATEST_MASK (0x3 << 4)
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm81xx.c b/arch/arm/mach-omap2/prcm81xx.c
index d48e5fc..5846969 100644
--- a/arch/arm/mach-omap2/prcm81xx.c
+++ b/arch/arm/mach-omap2/prcm81xx.c
@@ -17,7 +17,17 @@
#include <linux/errno.h>
#include <linux/io.h>
+#include <plat/common.h>
+
+#include "powerdomain.h"
+
#include "prcm81xx.h"
+#include "prcm-regbits-81xx.h"
+#include "prm.h"
+
+#include "prm-regbits-44xx.h"
+
+/* prm_base = cm_base on TI81xx, so either is fine */
static u32 ti81xx_prcm_inst_read(u16 inst, u16 offs)
{
@@ -29,4 +39,87 @@ static void ti81xx_prcm_inst_write(u32 v, u16 inst, u16 offs)
__raw_writel(v, prm_base + inst + offs);
}
+void ti81xx_prcm_pwrdm_set_powerstate(u16 offs, u8 pwrst)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(offs, TI81XX_PM_PWRSTCTRL_OFFSET);
+ v &= ~OMAP_POWERSTATE_MASK;
+ v |= pwrst << OMAP_POWERSTATE_SHIFT;
+ ti81xx_prcm_inst_write(v, offs, TI81XX_PM_PWRSTCTRL_OFFSET);
+}
+
+u8 ti81xx_prcm_pwrdm_read_powerstate(u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(offs, TI81XX_PM_PWRSTCTRL_OFFSET);
+ v &= OMAP_POWERSTATE_MASK;
+ v >>= OMAP_POWERSTATE_SHIFT;
+
+ return v;
+}
+
+u8 ti81xx_prcm_pwrdm_read_powerstatest(u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(offs, TI81XX_PM_PWRSTST_OFFSET);
+ v &= OMAP_POWERSTATEST_MASK;
+ v >>= OMAP_POWERSTATEST_SHIFT;
+
+ return v;
+}
+
+u8 ti81xx_prcm_pwrdm_read_logicstatest(u16 offs)
+{
+ u32 v;
+ v = ti81xx_prcm_inst_read(offs, TI81XX_PM_PWRSTCTRL_OFFSET);
+ v &= OMAP4430_LOGICSTATEST_MASK;
+ v >>= OMAP4430_LOGICSTATEST_SHIFT;
+
+ return v;
+}
+
+u8 ti81xx_prcm_pwrdm_read_mem_statest(u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(offs, TI81XX_PM_PWRSTST_OFFSET);
+ v &= TI81XX_MEM_STATEST_MASK;
+ v >>= TI81XX_MEM_STATEST_SHIFT;
+
+ return v;
+}
+
+void ti81xx_prcm_pwrdm_set_lowpowerstatechange(u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(offs, TI81XX_PM_PWRSTCTRL_OFFSET);
+ v &= ~OMAP4430_LOWPOWERSTATECHANGE_MASK;
+ v |= 1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT;
+ ti81xx_prcm_inst_write(v, offs, TI81XX_PM_PWRSTCTRL_OFFSET);
+}
+
+int ti81xx_prcm_pwrdm_wait_transition(u16 offs)
+{
+ u32 c = 0;
+
+ /*
+ * REVISIT: pwrdm_wait_transition() may be better implemented
+ * via a callback and a periodic timer check -- how long do we expect
+ * powerdomain transitions to take?
+ */
+
+ omap_test_timeout((ti81xx_prcm_inst_read(offs,
+ TI81XX_PM_PWRSTST_OFFSET) &
+ OMAP_INTRANSITION_MASK),
+ PWRDM_TRANSITION_BAILOUT, c);
+
+ if (c > INT_MAX)
+ c = INT_MAX;
+
+ return (c <= PWRDM_TRANSITION_BAILOUT) ? c : -ETIMEDOUT;
+}
diff --git a/arch/arm/mach-omap2/prcm81xx.h b/arch/arm/mach-omap2/prcm81xx.h
index fd0a174..e0c20b9 100644
--- a/arch/arm/mach-omap2/prcm81xx.h
+++ b/arch/arm/mach-omap2/prcm81xx.h
@@ -188,6 +188,20 @@
#define TI81XX_CM_ALWON_SR_1_CLKCTRL_OFFSET 0x020C
#define TI81XX_CM_ALWON_SR_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x020C)
+/*
+ * Register offset aliases (for clearer code,@least in theory)
+ */
+#define TI81XX_PM_PWRSTCTRL_OFFSET TI81XX_PRM_ACTIVE_PM_PWRSTCTRL_OFFSET
+#define TI81XX_PM_PWRSTST_OFFSET TI81XX_PRM_ACTIVE_PM_PWRSTST_OFFSET
+
/* Function prototypes */
+extern void ti81xx_prcm_pwrdm_set_powerstate(u16 offs, u8 pwrst);
+extern u8 ti81xx_prcm_pwrdm_read_powerstate(u16 offs);
+extern u8 ti81xx_prcm_pwrdm_read_powerstatest(u16 offs);
+extern u8 ti81xx_prcm_pwrdm_read_logicstatest(u16 offs);
+extern u8 ti81xx_prcm_pwrdm_read_mem_statest(u16 offs);
+extern void ti81xx_prcm_pwrdm_set_lowpowerstatechange(u16 offs);
+extern int ti81xx_prcm_pwrdm_wait_transition(u16 offs);
+
#endif
^ permalink raw reply related [flat|nested] 6+ messages in thread* [RFC PATCH 3/5] ARM: OMAP: TI81xx: add powerdomain data
2011-10-04 9:31 [RFC PATCH 0/5] Rework of the TI81xx PRCM support Paul Walmsley
2011-10-04 9:31 ` [RFC PATCH 1/5] ARM: OMAP: TI81XX: prcm: Add module and register offsets Paul Walmsley
2011-10-04 9:31 ` [RFC PATCH 2/5] ARM: OMAP: TI81xx: add powerdomain code Paul Walmsley
@ 2011-10-04 9:31 ` Paul Walmsley
2011-10-04 9:31 ` [RFC PATCH 4/5] ARM: OMAP: TI81xx: add clockdomain control code Paul Walmsley
2011-10-04 9:31 ` [RFC PATCH 5/5] ARM: OMAP: TI81xx: add clockdomain data Paul Walmsley
4 siblings, 0 replies; 6+ messages in thread
From: Paul Walmsley @ 2011-10-04 9:31 UTC (permalink / raw)
To: linux-arm-kernel
From: Hemant Pedanekar <hemantp@ti.com>
Add powerdomain data for the TI81xx family of SoCs.
This patch is a collaboration between Hemant Pedanekar <hemantp@ti.com>
and Paul Walmsley <paul@pwsan.com>.
---
arch/arm/mach-omap2/Makefile | 3 +
arch/arm/mach-omap2/io.c | 1
arch/arm/mach-omap2/powerdomain.h | 1
arch/arm/mach-omap2/powerdomain81xx_data.c | 91 ++++++++++++++++++++++++++++
4 files changed, 95 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/powerdomain81xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 292941d..4f728a1 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -113,7 +113,8 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \
powerdomain44xx.o \
powerdomains44xx_data.o
obj-$(CONFIG_SOC_OMAPTI81XX) += $(powerdomain-common) \
- powerdomain81xx.o
+ powerdomain81xx.o \
+ powerdomain81xx_data.o \
# PRCM clockdomain control
obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index d59feec..bad2edb 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -350,6 +350,7 @@ void __init omap2_init_common_infrastructure(void)
omap2430_hwmod_init();
} else if (cpu_is_omap34xx()) {
omap3xxx_powerdomains_init();
+ ti81xx_powerdomains_init();
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
} else if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index b3d51f2..b9e7ab2 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -214,6 +214,7 @@ extern void omap242x_powerdomains_init(void);
extern void omap243x_powerdomains_init(void);
extern void omap3xxx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
+extern void ti81xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomain81xx_data.c b/arch/arm/mach-omap2/powerdomain81xx_data.c
new file mode 100644
index 0000000..1b363ec
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain81xx_data.c
@@ -0,0 +1,91 @@
+/*
+ * TI81XX Power Domain data.
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ * Hemant Pedanekar
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+
+#include "powerdomain.h"
+#include "prcm81xx.h"
+#include "prcm814x.h"
+#include "prcm816x.h"
+
+static struct powerdomain alwon_814x_pwrdm = {
+ .name = "alwon_pwrdm",
+ .prcm_offs = TI814X_PRM_ALWON_INST,
+};
+
+static struct powerdomain active_81xx_pwrdm = {
+ .name = "active_pwrdm",
+ .prcm_offs = TI81XX_PRM_ACTIVE_INST,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct powerdomain default_81xx_pwrdm = {
+ .name = "default_pwrdm",
+ .prcm_offs = TI81XX_PRM_DEFAULT_INST,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct powerdomain hdvicp_814x_pwrdm = {
+ .name = "hdvicp_pwrdm",
+ .prcm_offs = TI814X_PRM_HDVICP_INST,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct powerdomain isp_814x_pwrdm = {
+ .name = "isp_pwrdm",
+ .prcm_offs = TI814X_PRM_ISP_INST,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct powerdomain dss_814x_pwrdm = {
+ .name = "dss_pwrdm",
+ .prcm_offs = TI814X_PRM_DSS_INST,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct powerdomain sgx_81xx_pwrdm = {
+ .name = "sgx_pwrdm",
+ .prcm_offs = TI81XX_PRM_SGX_INST,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct powerdomain *powerdomains_ti81xx[] __initdata = {
+ &active_81xx_pwrdm,
+ &default_81xx_pwrdm,
+ &sgx_81xx_pwrdm,
+ NULL
+};
+
+static struct powerdomain *powerdomains_ti814x[] __initdata = {
+ &alwon_814x_pwrdm,
+ &hdvicp_814x_pwrdm,
+ &isp_814x_pwrdm,
+ &dss_814x_pwrdm,
+ NULL
+};
+
+void __init ti81xx_powerdomains_init(void)
+{
+ if (!cpu_is_ti81xx())
+ return;
+
+ pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
+ pwrdm_register_pwrdms(powerdomains_ti81xx);
+ if (cpu_is_ti814x())
+ pwrdm_register_pwrdms(powerdomains_ti814x);
+ pwrdm_complete_init();
+}
^ permalink raw reply related [flat|nested] 6+ messages in thread* [RFC PATCH 4/5] ARM: OMAP: TI81xx: add clockdomain control code
2011-10-04 9:31 [RFC PATCH 0/5] Rework of the TI81xx PRCM support Paul Walmsley
` (2 preceding siblings ...)
2011-10-04 9:31 ` [RFC PATCH 3/5] ARM: OMAP: TI81xx: add powerdomain data Paul Walmsley
@ 2011-10-04 9:31 ` Paul Walmsley
2011-10-04 9:31 ` [RFC PATCH 5/5] ARM: OMAP: TI81xx: add clockdomain data Paul Walmsley
4 siblings, 0 replies; 6+ messages in thread
From: Paul Walmsley @ 2011-10-04 9:31 UTC (permalink / raw)
To: linux-arm-kernel
Add clockdomain control code for the TI816x and TI814x SoCs.
This patch is a collaboration between Hemant Pedanekar <hemantp@ti.com>
and Paul Walmsley <paul@pwsan.com>.
---
arch/arm/mach-omap2/Makefile | 2 +
arch/arm/mach-omap2/clockdomain.h | 1
arch/arm/mach-omap2/clockdomain81xx.c | 77 +++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/prcm81xx.c | 59 +++++++++++++++++++++++++
arch/arm/mach-omap2/prcm81xx.h | 5 ++
5 files changed, 144 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/clockdomain81xx.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 4f728a1..6962c5c 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -129,6 +129,8 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
clockdomain44xx.o \
clockdomains44xx_data.o
+obj-$(CONFIG_SOC_OMAPTI81XX) += clockdomain.o \
+ clockdomain81xx.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index f7b5860..9c7c5e9 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -202,6 +202,7 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
extern struct clkdm_ops omap2_clkdm_operations;
extern struct clkdm_ops omap3_clkdm_operations;
extern struct clkdm_ops omap4_clkdm_operations;
+extern struct clkdm_ops ti81xx_clkdm_operations;
extern struct clkdm_dep gfx_24xx_wkdeps[];
extern struct clkdm_dep dsp_24xx_wkdeps[];
diff --git a/arch/arm/mach-omap2/clockdomain81xx.c b/arch/arm/mach-omap2/clockdomain81xx.c
new file mode 100644
index 0000000..eab50f8
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain81xx.c
@@ -0,0 +1,77 @@
+/*
+ * TI81XX clockdomain control
+ *
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ * Hemant Pedanekar
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/types.h>
+
+#include <plat/prcm.h>
+
+#include "prcm81xx.h"
+#include "prm.h"
+#include "clockdomain.h"
+
+static int ti81xx_clkdm_sleep(struct clockdomain *clkdm)
+{
+ ti81xx_prcm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
+ return 0;
+}
+
+static int ti81xx_clkdm_wakeup(struct clockdomain *clkdm)
+{
+ ti81xx_prcm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
+ return 0;
+}
+
+static void ti81xx_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+ ti81xx_prcm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+}
+
+static void ti81xx_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+ ti81xx_prcm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+}
+
+static int ti81xx_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+ bool hwsup;
+
+ hwsup = ti81xx_prcm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+
+ if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+ ti81xx_clkdm_wakeup(clkdm);
+
+ return 0;
+}
+
+static int ti81xx_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+ bool hwsup;
+
+ hwsup = ti81xx_prcm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+
+ if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
+ ti81xx_clkdm_sleep(clkdm);
+
+ return 0;
+}
+
+struct clkdm_ops ti81xx_clkdm_operations = {
+ .clkdm_sleep = ti81xx_clkdm_sleep,
+ .clkdm_wakeup = ti81xx_clkdm_wakeup,
+ .clkdm_allow_idle = ti81xx_clkdm_allow_idle,
+ .clkdm_deny_idle = ti81xx_clkdm_deny_idle,
+ .clkdm_clk_enable = ti81xx_clkdm_clk_enable,
+ .clkdm_clk_disable = ti81xx_clkdm_clk_disable,
+};
diff --git a/arch/arm/mach-omap2/prcm81xx.c b/arch/arm/mach-omap2/prcm81xx.c
index 5846969..523b594 100644
--- a/arch/arm/mach-omap2/prcm81xx.c
+++ b/arch/arm/mach-omap2/prcm81xx.c
@@ -2,6 +2,8 @@
* TI81XX PRCM register access functions
*
* Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ * Hemant Pedanekar
+ * Paul Walmsley
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -27,6 +29,9 @@
#include "prm-regbits-44xx.h"
+#include "cm-regbits-34xx.h"
+#include "cm-regbits-44xx.h"
+
/* prm_base = cm_base on TI81xx, so either is fine */
static u32 ti81xx_prcm_inst_read(u16 inst, u16 offs)
@@ -123,3 +128,57 @@ int ti81xx_prcm_pwrdm_wait_transition(u16 offs)
return (c <= PWRDM_TRANSITION_BAILOUT) ? c : -ETIMEDOUT;
}
+
+void ti81xx_prcm_clkdm_enable_hwsup(s16 inst, u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(inst, offs);
+ v &= ~OMAP4430_CLKTRCTRL_MASK;
+ v |= OMAP34XX_CLKSTCTRL_ENABLE_AUTO << OMAP4430_CLKTRCTRL_SHIFT;
+ ti81xx_prcm_inst_write(v, inst, offs);
+
+}
+
+void ti81xx_prcm_clkdm_disable_hwsup(s16 inst, u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(inst, offs);
+ v &= ~OMAP4430_CLKTRCTRL_MASK;
+ v |= OMAP34XX_CLKSTCTRL_DISABLE_AUTO << OMAP4430_CLKTRCTRL_SHIFT;
+ ti81xx_prcm_inst_write(v, inst, offs);
+}
+
+void ti81xx_prcm_clkdm_force_sleep(s16 inst, u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(inst, offs);
+ v &= ~OMAP4430_CLKTRCTRL_MASK;
+ v |= OMAP34XX_CLKSTCTRL_FORCE_SLEEP << OMAP4430_CLKTRCTRL_SHIFT;
+ ti81xx_prcm_inst_write(v, inst, offs);
+}
+
+void ti81xx_prcm_clkdm_force_wakeup(s16 inst, u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(inst, offs);
+ v &= ~OMAP4430_CLKTRCTRL_MASK;
+ v |= OMAP34XX_CLKSTCTRL_FORCE_WAKEUP << OMAP4430_CLKTRCTRL_SHIFT;
+ ti81xx_prcm_inst_write(v, inst, offs);
+}
+
+bool ti81xx_prcm_is_clkdm_in_hwsup(s16 inst, u16 offs)
+{
+ u32 v;
+ bool ret = 0;
+
+ v = ti81xx_prcm_inst_read(inst, offs);
+ v &= OMAP4430_CLKTRCTRL_MASK;
+ v >>= OMAP4430_CLKTRCTRL_SHIFT;
+ ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
+
+ return ret;
+}
diff --git a/arch/arm/mach-omap2/prcm81xx.h b/arch/arm/mach-omap2/prcm81xx.h
index e0c20b9..19a7b40 100644
--- a/arch/arm/mach-omap2/prcm81xx.h
+++ b/arch/arm/mach-omap2/prcm81xx.h
@@ -203,5 +203,10 @@ extern u8 ti81xx_prcm_pwrdm_read_logicstatest(u16 offs);
extern u8 ti81xx_prcm_pwrdm_read_mem_statest(u16 offs);
extern void ti81xx_prcm_pwrdm_set_lowpowerstatechange(u16 offs);
extern int ti81xx_prcm_pwrdm_wait_transition(u16 offs);
+extern void ti81xx_prcm_clkdm_enable_hwsup(s16 inst, u16 offs);
+extern void ti81xx_prcm_clkdm_disable_hwsup(s16 inst, u16 offs);
+extern void ti81xx_prcm_clkdm_force_sleep(s16 inst, u16 offs);
+extern void ti81xx_prcm_clkdm_force_wakeup(s16 inst, u16 offs);
+extern bool ti81xx_prcm_is_clkdm_in_hwsup(s16 inst, u16 offs);
#endif
^ permalink raw reply related [flat|nested] 6+ messages in thread* [RFC PATCH 5/5] ARM: OMAP: TI81xx: add clockdomain data
2011-10-04 9:31 [RFC PATCH 0/5] Rework of the TI81xx PRCM support Paul Walmsley
` (3 preceding siblings ...)
2011-10-04 9:31 ` [RFC PATCH 4/5] ARM: OMAP: TI81xx: add clockdomain control code Paul Walmsley
@ 2011-10-04 9:31 ` Paul Walmsley
4 siblings, 0 replies; 6+ messages in thread
From: Paul Walmsley @ 2011-10-04 9:31 UTC (permalink / raw)
To: linux-arm-kernel
From: Hemant Pedanekar <hemantp@ti.com>
Add clockdomain data for the TI816x and TI814x SoCs.
This patch is a collaboration between Hemant Pedanekar <hemantp@ti.com>
and Paul Walmsley <paul@pwsan.com>.
---
arch/arm/mach-omap2/Makefile | 3
arch/arm/mach-omap2/clockdomain.h | 2
arch/arm/mach-omap2/clockdomains81xx_data.c | 223 +++++++++++++++++++++++++++
arch/arm/mach-omap2/io.c | 1
4 files changed, 228 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/clockdomains81xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 6962c5c..d0a66a2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -130,7 +130,8 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
clockdomain44xx.o \
clockdomains44xx_data.o
obj-$(CONFIG_SOC_OMAPTI81XX) += clockdomain.o \
- clockdomain81xx.o
+ clockdomain81xx.o \
+ clockdomains81xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 9c7c5e9..3f1b310 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -196,6 +196,8 @@ extern void __init omap242x_clockdomains_init(void);
extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
+extern void __init ti81xx_clockdomains_init(void);
+
extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c
new file mode 100644
index 0000000..53a95eb
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains81xx_data.c
@@ -0,0 +1,223 @@
+/*
+ * TI816X Clock Domain data.
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ * Hemant Pedanekar
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "cm.h"
+#include "prcm81xx.h"
+#include "prcm814x.h"
+#include "prcm816x.h"
+#include "prcm-regbits-81xx.h"
+
+static struct clockdomain alwon_mpu_81xx_clkdm = {
+ .name = "alwon_mpu_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = TI81XX_CM_ALWON_INST,
+ .clkdm_offs = TI816X_CM_ALWON_MPU_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain alwon_l3_slow_814x_clkdm = {
+ .name = "alwon_l3_slow_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = TI81XX_CM_ALWON_INST,
+ .clkdm_offs = TI814X_CM_ALWON_L3_SLOW_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain alwon_l3_med_814x_clkdm = {
+ .name = "alwon_l3_med_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = TI81XX_CM_ALWON_INST,
+ .clkdm_offs = TI814X_CM_ALWON_L3_MED_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain alwon_l3_fast_81xx_clkdm = {
+ .name = "alwon_l3_fast_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = TI81XX_CM_ALWON_INST,
+ .clkdm_offs = TI81XX_CM_ALWON_L3_FAST_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain alwon_ethernet_81xx_clkdm = {
+ .name = "alwon_ethernet_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = TI81XX_CM_ALWON_INST,
+ .clkdm_offs = TI81XX_CM_ETHERNET_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mmu_81xx_clkdm = {
+ .name = "mmu_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = TI81XX_CM_ALWON_INST,
+ .clkdm_offs = TI81XX_CM_MMU_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mmu_cfg_81xx_clkdm = {
+ .name = "mmu_cfg_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = TI81XX_CM_ALWON_INST,
+ .clkdm_offs = TI81XX_CM_MMUCFG_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain active_gem_81xx_clkdm = {
+ .name = "active_gem_clkdm",
+ .pwrdm = { .name = "active_pwrdm" },
+ .cm_inst = TI81XX_CM_ACTIVE_INST,
+ .clkdm_offs = TI81XX_CM_ACTIVE_GEM_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain hdvicp_814x_clkdm = {
+ .name = "hdvicp_clkdm",
+ .pwrdm = { .name = "hdvicp_pwrdm" },
+ .cm_inst = TI814X_CM_HDVICP_INST,
+ .clkdm_offs = TI814X_CM_HDVICP_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain isp_814x_clkdm = {
+ .name = "isp_clkdm",
+ .pwrdm = { .name = "isp_pwrdm" },
+ .cm_inst = TI814X_CM_ISP_INST,
+ .clkdm_offs = TI814X_CM_ISP_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dss_814x_clkdm = {
+ .name = "dss_clkdm",
+ .pwrdm = { .name = "dss_pwrdm" },
+ .cm_inst = TI814X_CM_DSS_INST,
+ .clkdm_offs = TI814X_CM_DSS_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain sgx_81xx_clkdm = {
+ .name = "sgx_clkdm",
+ .pwrdm = { .name = "sgx_pwrdm" },
+ .cm_inst = TI81XX_CM_SGX_INST,
+ .clkdm_offs = TI81XX_CM_SGX_SGX_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_l3_slow_816x_clkdm = {
+ .name = "default_l3_slow_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_INST,
+ .clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_tppss_814x_clkdm = {
+ .name = "default_tppss_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_INST,
+ .clkdm_offs = TI814X_CM_DEFAULT_TPPSS_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_l3_med_816x_clkdm = {
+ .name = "default_l3_med_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_INST,
+ .clkdm_offs = TI816X_CM_DEFAULT_L3_MED_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_ducati_814x_clkdm = {
+ .name = "default_ducati_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_INST,
+ .clkdm_offs = TI814X_CM_DEFAULT_DUCATI_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_ducati_816x_clkdm = {
+ .name = "default_ducati_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_INST,
+ .clkdm_offs = TI816X_CM_DEFAULT_DUCATI_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_pcie_814x_clkdm = {
+ .name = "default_pcie_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_INST,
+ .clkdm_offs = TI814X_CM_DEFAULT_PCI_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_pcie_816x_clkdm = {
+ .name = "default_pcie_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_INST,
+ .clkdm_offs = TI816X_CM_DEFAULT_PCI_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain *clockdomains_ti81xx[] __initdata = {
+ &alwon_mpu_81xx_clkdm,
+ &alwon_l3_fast_81xx_clkdm,
+ &alwon_ethernet_81xx_clkdm,
+ &mmu_81xx_clkdm,
+ &mmu_cfg_81xx_clkdm,
+ &active_gem_81xx_clkdm,
+ &sgx_81xx_clkdm,
+ NULL,
+};
+
+static struct clockdomain *clockdomains_ti814x[] __initdata = {
+ &hdvicp_814x_clkdm,
+ &isp_814x_clkdm,
+ &dss_814x_clkdm,
+ &alwon_l3_med_814x_clkdm,
+ &alwon_l3_slow_814x_clkdm,
+ &default_tppss_814x_clkdm,
+ &default_ducati_814x_clkdm,
+ &default_pcie_814x_clkdm,
+ NULL,
+};
+
+static struct clockdomain *clockdomains_ti816x[] __initdata = {
+ &default_l3_med_816x_clkdm,
+ &default_l3_slow_816x_clkdm,
+ &default_ducati_816x_clkdm,
+ &default_pcie_816x_clkdm,
+ NULL,
+};
+
+void __init ti81xx_clockdomains_init(void)
+{
+ if (!cpu_is_ti81xx())
+ return;
+
+ clkdm_register_platform_funcs(&ti81xx_clkdm_operations);
+ clkdm_register_clkdms(clockdomains_ti81xx);
+ if (cpu_is_ti814x())
+ clkdm_register_clkdms(clockdomains_ti814x);
+ if (cpu_is_ti816x())
+ clkdm_register_clkdms(clockdomains_ti816x);
+ clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index bad2edb..2d26820 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -352,6 +352,7 @@ void __init omap2_init_common_infrastructure(void)
omap3xxx_powerdomains_init();
ti81xx_powerdomains_init();
omap3xxx_clockdomains_init();
+ ti81xx_clockdomains_init();
omap3xxx_hwmod_init();
} else if (cpu_is_omap44xx()) {
omap44xx_powerdomains_init();
^ permalink raw reply related [flat|nested] 6+ messages in thread