mxs: enable phy-clock in the driver?

mxs: enable phy-clock in the driver?

[Wolfram Sang]

Hi Shawn,

I recently noticed that my tx28 board did not have net when booting from NAND
(before that, barebox was setting up the network). Adding lines like these from
mx28evk helped:

228         /* Enable fec phy clock */
229         clk = clk_get_sys("pll2", NULL);
230         if (!IS_ERR(clk))
231                 clk_enable(clk);

So, if every board seems to need this, I'd think this should rather be in the
driver? Am I correct or is there something I have overlooked?

Regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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mxs: enable phy-clock in the driver?

[Shawn Guo]

On Sun, Jan 08, 2012 at 03:45:58PM +0100, Wolfram Sang wrote:
> Hi Shawn,
> 
> I recently noticed that my tx28 board did not have net when booting from NAND
> (before that, barebox was setting up the network). Adding lines like these from
> mx28evk helped:
> 
> 228         /* Enable fec phy clock */
> 229         clk = clk_get_sys("pll2", NULL);
> 230         if (!IS_ERR(clk))
> 231                 clk_enable(clk);
> 
> So, if every board seems to need this, I'd think this should rather be in the
> driver? Am I correct or is there something I have overlooked?
> 
Hmm, as far as I know, at least m28evk from denx does not need this.
Different from that imx28 supplies clock to phy on mx28evk board,
m28evk has phy supply clock to imx28. 

-- 
Regards,
Shawn

mxs: enable phy-clock in the driver?

[Lothar Waßmann]

Hi,

Shawn Guo writes:
> On Sun, Jan 08, 2012 at 03:45:58PM +0100, Wolfram Sang wrote:
> > Hi Shawn,
> > 
> > I recently noticed that my tx28 board did not have net when booting from NAND
> > (before that, barebox was setting up the network). Adding lines like these from
> > mx28evk helped:
> > 
> > 228         /* Enable fec phy clock */
> > 229         clk = clk_get_sys("pll2", NULL);
> > 230         if (!IS_ERR(clk))
> > 231                 clk_enable(clk);
> > 
> > So, if every board seems to need this, I'd think this should rather be in the
> > driver? Am I correct or is there something I have overlooked?
> > 
> Hmm, as far as I know, at least m28evk from denx does not need this.
> Different from that imx28 supplies clock to phy on mx28evk board,
> m28evk has phy supply clock to imx28. 
> 
The TX28 derives its PHY clock from the ENET_CLK pin of the
processor. Thus the CLK_ENET_TIME should be enabled by the driver as
mentioned in <20120108033238.GA19721@S2101-09.ap.freescale.net>


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________

mxs: enable phy-clock in the driver?

[Shawn Guo]

On Mon, Jan 09, 2012 at 07:40:47AM +0100, Lothar Wa?mann wrote:
> The TX28 derives its PHY clock from the ENET_CLK pin of the
> processor. Thus the CLK_ENET_TIME should be enabled by the driver as
> mentioned in <20120108033238.GA19721@S2101-09.ap.freescale.net>
> 
Can you give a web link for that message?

-- 
Regards,
Shawn

mxs: enable phy-clock in the driver?

[Lothar Waßmann]

Hi,

Shawn Guo writes:
> On Mon, Jan 09, 2012 at 07:40:47AM +0100, Lothar Wa?mann wrote:
> > The TX28 derives its PHY clock from the ENET_CLK pin of the
> > processor. Thus the CLK_ENET_TIME should be enabled by the driver as
> > mentioned in <20120108033238.GA19721@S2101-09.ap.freescale.net>
> > 
> Can you give a web link for that message?
> 
It's your own email from "Sun, 8 Jan 2012 11:32:40 +0800" with the
subject "Re: MX28 fec clock frequency":
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-January/079556.html


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________

mxs: enable phy-clock in the driver?

[Shawn Guo]

On Mon, Jan 09, 2012 at 08:05:14AM +0100, Lothar Wa?mann wrote:
> Hi,
> 
> Shawn Guo writes:
> > On Mon, Jan 09, 2012 at 07:40:47AM +0100, Lothar Wa?mann wrote:
> > > The TX28 derives its PHY clock from the ENET_CLK pin of the
> > > processor. Thus the CLK_ENET_TIME should be enabled by the driver as
> > > mentioned in <20120108033238.GA19721@S2101-09.ap.freescale.net>
> > > 
> > Can you give a web link for that message?
> > 
> It's your own email from "Sun, 8 Jan 2012 11:32:40 +0800" with the
> subject "Re: MX28 fec clock frequency":
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-January/079556.html
> 
Ah, yes.  But what I said there is the CLK_ENET_TIME should be enabled
by PTP support, not the need of clocking external phy required by
particular board design.

-- 
Regards,
Shawn

mxs: enable phy-clock in the driver?

[Lothar Waßmann]

Hi,

Shawn Guo writes:
> On Mon, Jan 09, 2012 at 08:05:14AM +0100, Lothar Wa?mann wrote:
> > Hi,
> > 
> > Shawn Guo writes:
> > > On Mon, Jan 09, 2012 at 07:40:47AM +0100, Lothar Wa?mann wrote:
> > > > The TX28 derives its PHY clock from the ENET_CLK pin of the
> > > > processor. Thus the CLK_ENET_TIME should be enabled by the driver as
> > > > mentioned in <20120108033238.GA19721@S2101-09.ap.freescale.net>
> > > > 
> > > Can you give a web link for that message?
> > > 
> > It's your own email from "Sun, 8 Jan 2012 11:32:40 +0800" with the
> > subject "Re: MX28 fec clock frequency":
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2012-January/079556.html
> > 
> Ah, yes.  But what I said there is the CLK_ENET_TIME should be enabled
> by PTP support, not the need of clocking external phy required by
> particular board design.
> 
My point was, that it is the same clock. Thus, not "pll2" but
"enet_ptp" or whatever it's name will be needs to be enabled for the
Ethernet PHY on TX28.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________

mxs: enable phy-clock in the driver?

[Marek Vasut]

> Hi Shawn,
> 
> I recently noticed that my tx28 board did not have net when booting from
> NAND (before that, barebox was setting up the network). Adding lines like
> these from mx28evk helped:
> 
> 228         /* Enable fec phy clock */
> 229         clk = clk_get_sys("pll2", NULL);
> 230         if (!IS_ERR(clk))
> 231                 clk_enable(clk);
> 
> So, if every board seems to need this, I'd think this should rather be in
> the driver? Am I correct or is there something I have overlooked?
> 
> Regards,
> 
>    Wolfram

Did you really disable the clock to FEC or only the PHY didn't have clock?

M