[PATCH v2 00/11] ARM: EXYNOS: add suppport for EXYNOS5250 SoC

[PATCH v2 00/11] ARM: EXYNOS: add suppport for EXYNOS5250 SoC

[Kukjin Kim]

This patch adds support EXYNOS5250 SoC which has two A15 cores
can be used on mobile / tablet devices.

Changes since v1:
- address comments from mailing list
- update the option accordingly common.[ch]
- update clock part
- get rid of static mapping for uart
- add device tree enabled board file(mach-exynos5-dt.c)
- add initial dts file for EXYNOS5250(SoC), SMDK5250(Board)

[PATCH v2 01/11] ARM: EXYNOS: to declare static for mach-exynos/common.c
[PATCH v2 02/11] ARM: EXYNOS: use exynos_init_uarts() instead of exynos4_init_uarts()
[PATCH v2 03/11] ARM: EXYNOS: add clock part for EXYNOS5250 SoC
[PATCH v2 04/11] ARM: EXYNOS: add interrupt definitions for EXYNOS5250
[PATCH v2 05/11] ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5
[PATCH v2 06/11] ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5
[PATCH v2 07/11] ARM: EXYNOS: add support get_core_count() for EXYNOS5250
[PATCH v2 08/11] ARM: EXYNOS: add support for ARCH_EXYNOS5 and EXYNOS5250
[PATCH v2 09/11] ARM: EXYNOS: add support device tree enabled board file for EXYNOS5
[PATCH v2 10/11] ARM: dts: add initial dts file for EXYNOS5250, SMDK5250
[PATCH v2 11/11] ARM: EXYNOS: temporary add board file for SMDK5250

[PATCH v2 01/11] ARM: EXYNOS: to declare static for mach-exynos/common.c

[Kukjin Kim]

According to commit cc511b8d84d8 ("ARM: 7257/1: EXYNOS: introduce
arch/arm/mach-exynos/common.[ch]"), we don't need to declare extern
for exynos4_map_io(), exynos4_init_clocks(), exynos4_init_uarts(),
and exynos_init(). And the exynos4210_register_clocks() and
exynos4212_register_clocks depend on each SoC not ARCH_EXYNOS4.
So this patch fixed above.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/common.c |   13 +++++++++----
 arch/arm/mach-exynos/common.h |   28 +++++++++++-----------------
 2 files changed, 20 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index c59e188..3c3e61b 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -50,6 +50,11 @@ static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
 
+static void exynos4_map_io(void);
+static void exynos4_init_clocks(int xtal);
+static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+static int exynos_init(void);
+
 static struct cpu_table cpu_ids[] __initdata = {
 	{
 		.idcode		= EXYNOS4210_CPU_ID,
@@ -233,7 +238,7 @@ void __init exynos_init_io(struct map_desc *mach_desc, int size)
 	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
 
-void __init exynos4_map_io(void)
+static void __init exynos4_map_io(void)
 {
 	iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 
@@ -264,7 +269,7 @@ void __init exynos4_map_io(void)
 	s5p_hdmi_setname("exynos4-hdmi");
 }
 
-void __init exynos4_init_clocks(int xtal)
+static void __init exynos4_init_clocks(int xtal)
 {
 	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 
@@ -464,7 +469,7 @@ static int __init exynos4_l2x0_cache_init(void)
 early_initcall(exynos4_l2x0_cache_init);
 #endif
 
-int __init exynos_init(void)
+static int __init exynos_init(void)
 {
 	printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 
@@ -476,7 +481,7 @@ int __init exynos_init(void)
 
 /* uart registration process */
 
-void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
 	struct s3c2410_uartcfg *tcfg = cfg;
 	u32 ucnt;
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 8c1efe6..b32c6b5 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,39 +12,33 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
+extern struct sys_timer exynos4_timer;
+
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
+void exynos4_restart(char mode, const char *cmd);
 
 #ifdef CONFIG_ARCH_EXYNOS4
 void exynos4_register_clocks(void);
 void exynos4_setup_clocks(void);
 
-void exynos4210_register_clocks(void);
-void exynos4212_register_clocks(void);
-
 #else
 #define exynos4_register_clocks()
 #define exynos4_setup_clocks()
-
-#define exynos4210_register_clocks()
-#define exynos4212_register_clocks()
 #endif
 
-void exynos4_restart(char mode, const char *cmd);
+#ifdef CONFIG_CPU_EXYNOS4210
+void exynos4210_register_clocks(void);
 
-extern struct sys_timer exynos4_timer;
+#else
+#define exynos4210_register_clocks()
+#endif
 
-#ifdef CONFIG_ARCH_EXYNOS
-extern  int exynos_init(void);
-extern void exynos4_map_io(void);
-extern void exynos4_init_clocks(int xtal);
-extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+#ifdef CONFIG_SOC_EXYNOS4212
+void exynos4212_register_clocks(void);
 
 #else
-#define exynos4_init_clocks NULL
-#define exynos4_init_uarts NULL
-#define exynos4_map_io NULL
-#define exynos_init NULL
+#define exynos4212_register_clocks()
 #endif
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
-- 
1.7.4.4

[PATCH v2 02/11] ARM: EXYNOS: use exynos_init_uarts() instead of exynos4_init_uarts()

[Kukjin Kim]

Since exynos4_init_uarts() can be used for EXYNOS5 SoCs,
this patch changes the name of function to exynos_init_uarts().

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/common.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 3c3e61b..37257b0 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,7 +52,7 @@ static const char name_exynos4412[] = "EXYNOS4412";
 
 static void exynos4_map_io(void);
 static void exynos4_init_clocks(int xtal);
-static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
 
 static struct cpu_table cpu_ids[] __initdata = {
@@ -61,7 +61,7 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.idmask		= EXYNOS4_CPU_MASK,
 		.map_io		= exynos4_map_io,
 		.init_clocks	= exynos4_init_clocks,
-		.init_uarts	= exynos4_init_uarts,
+		.init_uarts	= exynos_init_uarts,
 		.init		= exynos_init,
 		.name		= name_exynos4210,
 	}, {
@@ -69,7 +69,7 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.idmask		= EXYNOS4_CPU_MASK,
 		.map_io		= exynos4_map_io,
 		.init_clocks	= exynos4_init_clocks,
-		.init_uarts	= exynos4_init_uarts,
+		.init_uarts	= exynos_init_uarts,
 		.init		= exynos_init,
 		.name		= name_exynos4212,
 	}, {
@@ -77,7 +77,7 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.idmask		= EXYNOS4_CPU_MASK,
 		.map_io		= exynos4_map_io,
 		.init_clocks	= exynos4_init_clocks,
-		.init_uarts	= exynos4_init_uarts,
+		.init_uarts	= exynos_init_uarts,
 		.init		= exynos_init,
 		.name		= name_exynos4412,
 	},
@@ -481,7 +481,7 @@ static int __init exynos_init(void)
 
 /* uart registration process */
 
-static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
 	struct s3c2410_uartcfg *tcfg = cfg;
 	u32 ucnt;
-- 
1.7.4.4

[PATCH v2 03/11] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

[Kukjin Kim]

This patch adds clock-exynos5.c for EXYNOS5250 now
and that can be used for other EXYNOS5 SoCs later.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/clock-exynos5.c           | 1252 ++++++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/regs-clock.h |   62 ++
 arch/arm/plat-s5p/clock.c                      |   36 +
 arch/arm/plat-samsung/include/plat/s5p-clock.h |    6 +
 4 files changed, 1356 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-exynos/clock-exynos5.c

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
new file mode 100644
index 0000000..9d2e7f0
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -0,0 +1,1252 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Clock support for EXYNOS5 SoCs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/pm.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
+
+#include "common.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos5_clock_save[] = {
+	/* will be implemented */
+};
+#endif
+
+static struct clk exynos5_clk_sclk_dptxphy = {
+	.name		= "sclk_dptx",
+};
+
+static struct clk exynos5_clk_sclk_hdmi24m = {
+	.name		= "sclk_hdmi24m",
+	.rate		= 24000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmi27m = {
+	.name		= "sclk_hdmi27m",
+	.rate		= 27000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmiphy = {
+	.name		= "sclk_hdmiphy",
+};
+
+static struct clk exynos5_clk_sclk_usbphy = {
+	.name		= "sclk_usbphy",
+	.rate		= 48000000,
+};
+
+static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
+}
+
+static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
+}
+
+static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
+}
+
+static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
+}
+
+static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
+}
+
+static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
+}
+
+static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
+}
+
+static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
+}
+
+static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
+}
+
+static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
+}
+
+static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk exynos5_clk_mout_apll = {
+	.clk	= {
+		.name		= "mout_apll",
+	},
+	.sources = &clk_src_apll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_apll = {
+	.clk	= {
+		.name		= "sclk_apll",
+		.parent		= &exynos5_clk_mout_apll.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll = {
+	.clk	= {
+		.name		= "mout_bpll",
+	},
+	.sources = &clk_src_bpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_bpll_user_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll_user = {
+	.sources	= exynos5_clk_src_bpll_user_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll_user = {
+	.clk	= {
+		.name		= "mout_bpll_user",
+	},
+	.sources = &exynos5_clk_src_bpll_user,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpll = {
+	.clk	= {
+		.name		= "mout_cpll",
+	},
+	.sources = &clk_src_cpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_epll = {
+	.clk	= {
+		.name		= "mout_epll",
+	},
+	.sources = &clk_src_epll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
+};
+
+struct clksrc_clk exynos5_clk_mout_mpll = {
+	.clk = {
+		.name		= "mout_mpll",
+	},
+	.sources = &clk_src_mpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
+};
+
+static struct clk *exynos_clkset_vpllsrc_list[] = {
+	[0] = &clk_fin_vpll,
+	[1] = &exynos5_clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources exynos5_clkset_vpllsrc = {
+	.sources	= exynos_clkset_vpllsrc_list,
+	.nr_sources	= ARRAY_SIZE(exynos_clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk exynos5_clk_vpllsrc = {
+	.clk	= {
+		.name		= "vpll_src",
+		.enable		= exynos5_clksrc_mask_top_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos5_clkset_vpllsrc,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_sclk_vpll_list[] = {
+	[0] = &exynos5_clk_vpllsrc.clk,
+	[1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_vpll = {
+	.sources	= exynos5_clkset_sclk_vpll_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_vpll = {
+	.clk	= {
+		.name		= "sclk_vpll",
+	},
+	.sources = &exynos5_clkset_sclk_vpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_pixel = {
+	.clk	= {
+		.name		= "sclk_pixel",
+		.parent		= &exynos5_clk_sclk_vpll.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
+};
+
+static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
+	[0] = &exynos5_clk_sclk_pixel.clk,
+	[1] = &exynos5_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
+	.sources	= exynos5_clkset_sclk_hdmi_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_hdmi = {
+	.clk	= {
+		.name           = "sclk_hdmi",
+		.enable		= exynos5_clksrc_mask_disp1_0_ctrl,
+		.ctrlbit	= (1 << 20),
+	},
+	.sources = &exynos5_clkset_sclk_hdmi,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk *exynos5_sclk_tv[] = {
+	&exynos5_clk_sclk_pixel,
+	&exynos5_clk_sclk_hdmi,
+};
+
+static struct clk *exynos5_clk_src_mpll_user_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_mpll_user = {
+	.sources	= exynos5_clk_src_mpll_user_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll_user = {
+	.clk	= {
+		.name		= "mout_mpll_user",
+	},
+	.sources = &exynos5_clk_src_mpll_user,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_mout_cpu_list[] = {
+	[0] = &exynos5_clk_mout_apll.clk,
+	[1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_cpu = {
+	.sources	= exynos5_clkset_mout_cpu_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpu = {
+	.clk	= {
+		.name		= "mout_cpu",
+	},
+	.sources = &exynos5_clkset_mout_cpu,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_armclk = {
+	.clk	= {
+		.name		= "dout_armclk",
+		.parent		= &exynos5_clk_mout_cpu.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_arm2clk = {
+	.clk	= {
+		.name		= "dout_arm2clk",
+		.parent		= &exynos5_clk_dout_armclk.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
+};
+
+static struct clk exynos5_clk_armclk = {
+	.name		= "armclk",
+	.parent		= &exynos5_clk_dout_arm2clk.clk,
+};
+
+/* Core list of CMU_CDREX side */
+
+static struct clk *exynos5_clkset_cdrex_list[] = {
+	[0] = &exynos5_clk_mout_mpll.clk,
+	[1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_cdrex = {
+	.sources	= exynos5_clkset_cdrex_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_cdrex_list),
+};
+
+static struct clksrc_clk exynos5_clk_cdrex = {
+	.clk	= {
+		.name		= "clk_cdrex",
+	},
+	.sources = &exynos5_clkset_cdrex,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_acp = {
+	.clk	= {
+		.name		= "aclk_acp",
+		.parent		= &exynos5_clk_mout_mpll.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_pclk_acp = {
+	.clk	= {
+		.name		= "pclk_acp",
+		.parent		= &exynos5_clk_aclk_acp.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+struct clk *exynos5_clkset_aclk_top_list[] = {
+	[0] = &exynos5_clk_mout_mpll_user.clk,
+	[1] = &exynos5_clk_mout_bpll_user.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk = {
+	.sources	= exynos5_clkset_aclk_top_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_aclk_top_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400 = {
+	.clk	= {
+		.name		= "aclk_400",
+	},
+	.sources = &exynos5_clkset_aclk,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+};
+
+struct clk *exynos5_clkset_aclk_333_166_list[] = {
+	[0] = &exynos5_clk_mout_cpll.clk,
+	[1] = &exynos5_clk_mout_mpll_user.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk_333_166 = {
+	.sources	= exynos5_clkset_aclk_333_166_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_333 = {
+	.clk	= {
+		.name		= "aclk_333",
+	},
+	.sources = &exynos5_clkset_aclk_333_166,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_166 = {
+	.clk	= {
+		.name		= "aclk_166",
+	},
+	.sources = &exynos5_clkset_aclk_333_166,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266 = {
+	.clk	= {
+		.name		= "aclk_266",
+		.parent		= &exynos5_clk_mout_mpll_user.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_200 = {
+	.clk	= {
+		.name		= "aclk_200",
+	},
+	.sources = &exynos5_clkset_aclk,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66_pre = {
+	.clk	= {
+		.name		= "aclk_66_pre",
+		.parent		= &exynos5_clk_mout_mpll_user.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66 = {
+	.clk	= {
+		.name		= "aclk_66",
+		.parent		= &exynos5_clk_aclk_66_pre.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
+};
+
+static struct clk exynos5_init_clocks_off[] = {
+	{
+		.name		= "timers",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 24),
+	}, {
+		.name		= "rtc",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peris_ctrl,
+		.ctrlbit	= (1 << 20),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.0",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.1",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.2",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 14),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.3",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "dwmci",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "sata",
+		.devname	= "ahci",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "sata_phy",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 24),
+	}, {
+		.name		= "sata_phy_i2c",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 25),
+	}, {
+		.name		= "mfc",
+		.devname	= "s5p-mfc",
+		.enable		= exynos5_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "hdmi",
+		.devname	= "exynos4-hdmi",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "mixer",
+		.devname	= "s5p-mixer",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "jpeg",
+		.enable		= exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "dsim0",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "iis",
+		.devname	= "samsung-i2s.1",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 20),
+	}, {
+		.name		= "iis",
+		.devname	= "samsung-i2s.2",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 21),
+	}, {
+		.name		= "pcm",
+		.devname	= "samsung-pcm.1",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 22),
+	}, {
+		.name		= "pcm",
+		.devname	= "samsung-pcm.2",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 23),
+	}, {
+		.name		= "spdif",
+		.devname	= "samsung-spdif",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 26),
+	}, {
+		.name		= "ac97",
+		.devname	= "samsung-ac97",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 27),
+	}, {
+		.name		= "usbhost",
+		.enable		= exynos5_clk_ip_fsys_ctrl ,
+		.ctrlbit	= (1 << 18),
+	}, {
+		.name		= "usbotg",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "gps",
+		.enable		= exynos5_clk_ip_gps_ctrl,
+		.ctrlbit	= ((1 << 3) | (1 << 2) | (1 << 0)),
+	}, {
+		.name		= "nfcon",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 22),
+	}, {
+		.name		= "iop",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= ((1 << 30) | (1 << 26) | (1 << 23)),
+	}, {
+		.name		= "core_iop",
+		.enable		= exynos5_clk_ip_core_ctrl,
+		.ctrlbit	= ((1 << 21) | (1 << 3)),
+	}, {
+		.name		= "mcu_iop",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.0",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.1",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.2",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.3",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.4",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.5",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.6",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.7",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-hdmiphy-i2c",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 14),
+	}
+};
+
+static struct clk exynos5_init_clocks_on[] = {
+	{
+		.name		= "uart",
+		.devname	= "s5pv210-uart.0",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.1",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.2",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.3",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.4",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.5",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 5),
+	}
+};
+
+static struct clk exynos5_clk_pdma0 = {
+	.name		= "dma",
+	.devname	= "dma-pl330.0",
+	.enable		= exynos5_clk_ip_gen_ctrl,
+	.ctrlbit	= (1 << 4),
+};
+
+static struct clk exynos5_clk_pdma1 = {
+	.name		= "dma",
+	.devname	= "dma-pl330.1",
+	.enable		= exynos5_clk_ip_fsys_ctrl,
+	.ctrlbit	= (1 << 1),
+};
+
+static struct clk exynos5_clk_pdma2 = {
+	.name		= "dma",
+	.devname	= "dma-pl330.2",
+	.enable		= exynos5_clk_ip_fsys_ctrl,
+	.ctrlbit	= (1 << 1),
+};
+
+struct clk *exynos5_clkset_group_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = NULL,
+	[2] = &exynos5_clk_sclk_hdmi24m,
+	[3] = &exynos5_clk_sclk_dptxphy,
+	[4] = &exynos5_clk_sclk_usbphy,
+	[5] = &exynos5_clk_sclk_hdmiphy,
+	[6] = &exynos5_clk_mout_mpll_user.clk,
+	[7] = &exynos5_clk_mout_epll.clk,
+	[8] = &exynos5_clk_sclk_vpll.clk,
+	[9] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_group = {
+	.sources	= exynos5_clkset_group_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_group_list),
+};
+
+/* Possible clock sources for aclk_266_gscl_sub Mux */
+static struct clk *clk_src_gscl_266_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = &exynos5_clk_aclk_266.clk,
+};
+
+static struct clksrc_sources clk_src_gscl_266 = {
+	.sources	= clk_src_gscl_266_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_gscl_266_list),
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc0 = {
+	.clk		= {
+		.name		= "dout_mmc0",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc1 = {
+	.clk		= {
+		.name		= "dout_mmc1",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc2 = {
+	.clk		= {
+		.name		= "dout_mmc2",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc3 = {
+	.clk		= {
+		.name		= "dout_mmc3",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc4 = {
+	.clk		= {
+		.name		= "dout_mmc4",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart0 = {
+	.clk	= {
+		.name		= "uclk1",
+		.devname	= "exynos4210-uart.0",
+		.enable		= exynos5_clksrc_mask_peric0_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart1 = {
+	.clk	= {
+		.name		= "uclk1",
+		.devname	= "exynos4210-uart.1",
+		.enable		= exynos5_clksrc_mask_peric0_ctrl,
+		.ctrlbit	= (1 << 4),
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart2 = {
+	.clk	= {
+		.name		= "uclk1",
+		.devname	= "exynos4210-uart.2",
+		.enable		= exynos5_clksrc_mask_peric0_ctrl,
+		.ctrlbit	= (1 << 8),
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart3 = {
+	.clk	= {
+		.name		= "uclk1",
+		.devname	= "exynos4210-uart.3",
+		.enable		= exynos5_clksrc_mask_peric0_ctrl,
+		.ctrlbit	= (1 << 12),
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
+	.clk	= {
+		.name		= "sclk_mmc",
+		.devname	= "s3c-sdhci.0",
+		.parent		= &exynos5_clk_dout_mmc0.clk,
+		.enable		= exynos5_clksrc_mask_fsys_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
+	.clk	= {
+		.name		= "sclk_mmc",
+		.devname	= "s3c-sdhci.1",
+		.parent         = &exynos5_clk_dout_mmc1.clk,
+		.enable		= exynos5_clksrc_mask_fsys_ctrl,
+		.ctrlbit	= (1 << 4),
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
+	.clk	= {
+		.name		= "sclk_mmc",
+		.devname	= "s3c-sdhci.2",
+		.parent         = &exynos5_clk_dout_mmc2.clk,
+		.enable		= exynos5_clksrc_mask_fsys_ctrl,
+		.ctrlbit	= (1 << 8),
+	},
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+	.clk	= {
+		.name		= "sclk_mmc",
+		.devname	= "s3c-sdhci.3",
+		.parent         = &exynos5_clk_dout_mmc3.clk,
+		.enable		= exynos5_clksrc_mask_fsys_ctrl,
+		.ctrlbit	= (1 << 12),
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clksrcs[] = {
+	{
+		.clk	= {
+			.name		= "sclk_dwmci",
+			.parent         = &exynos5_clk_dout_mmc4.clk,
+			.enable		= exynos5_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 16),
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_fimd",
+			.devname	= "s3cfb.1",
+			.enable		= exynos5_clksrc_mask_disp1_0_ctrl,
+			.ctrlbit	= (1 << 0),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "aclk_266_gscl",
+		},
+		.sources = &clk_src_gscl_266,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
+	}, {
+		.clk	= {
+			.name		= "sclk_g3d",
+			.devname	= "mali-t604.0",
+			.enable		= exynos5_clk_block_ctrl,
+			.ctrlbit	= (1 << 1),
+		},
+		.sources = &exynos5_clkset_aclk,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+	}, {
+		.clk	= {
+			.name		= "sclk_gscl_wrap",
+			.devname	= "s5p-mipi-csis.0",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 24),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_gscl_wrap",
+			.devname	= "s5p-mipi-csis.1",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 28),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_cam0",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 16),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_cam1",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 20),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_jpeg",
+			.parent		= &exynos5_clk_mout_cpll.clk,
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+	},
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *exynos5_sysclks[] = {
+	&exynos5_clk_mout_apll,
+	&exynos5_clk_sclk_apll,
+	&exynos5_clk_mout_bpll,
+	&exynos5_clk_mout_bpll_user,
+	&exynos5_clk_mout_cpll,
+	&exynos5_clk_mout_epll,
+	&exynos5_clk_mout_mpll,
+	&exynos5_clk_mout_mpll_user,
+	&exynos5_clk_vpllsrc,
+	&exynos5_clk_sclk_vpll,
+	&exynos5_clk_mout_cpu,
+	&exynos5_clk_dout_armclk,
+	&exynos5_clk_dout_arm2clk,
+	&exynos5_clk_cdrex,
+	&exynos5_clk_aclk_400,
+	&exynos5_clk_aclk_333,
+	&exynos5_clk_aclk_266,
+	&exynos5_clk_aclk_200,
+	&exynos5_clk_aclk_166,
+	&exynos5_clk_aclk_66_pre,
+	&exynos5_clk_aclk_66,
+	&exynos5_clk_dout_mmc0,
+	&exynos5_clk_dout_mmc1,
+	&exynos5_clk_dout_mmc2,
+	&exynos5_clk_dout_mmc3,
+	&exynos5_clk_dout_mmc4,
+	&exynos5_clk_aclk_acp,
+	&exynos5_clk_pclk_acp,
+};
+
+static struct clk *exynos5_clk_cdev[] = {
+	&exynos5_clk_pdma0,
+	&exynos5_clk_pdma1,
+	&exynos5_clk_pdma2,
+};
+
+static struct clksrc_clk *exynos5_clksrc_cdev[] = {
+	&exynos5_clk_sclk_uart0,
+	&exynos5_clk_sclk_uart1,
+	&exynos5_clk_sclk_uart2,
+	&exynos5_clk_sclk_uart3,
+	&exynos5_clk_sclk_mmc0,
+	&exynos5_clk_sclk_mmc1,
+	&exynos5_clk_sclk_mmc2,
+	&exynos5_clk_sclk_mmc3,
+};
+
+static struct clk_lookup exynos5_clk_lookup[] = {
+	CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
+	CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
+	CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
+	CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
+	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
+	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
+	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
+	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
+	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
+	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_pdma2),
+};
+
+static unsigned long exynos5_epll_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+static struct clk *exynos5_clks[] __initdata = {
+	&exynos5_clk_sclk_hdmi27m,
+	&exynos5_clk_sclk_hdmiphy,
+	&clk_fout_bpll,
+	&clk_fout_cpll,
+	&exynos5_clk_armclk,
+};
+
+static u32 epll_div[][6] = {
+	{ 192000000, 0, 48, 3, 1, 0 },
+	{ 180000000, 0, 45, 3, 1, 0 },
+	{  73728000, 1, 73, 3, 3, 47710 },
+	{  67737600, 1, 90, 4, 3, 20762 },
+	{  49152000, 0, 49, 3, 3, 9961 },
+	{  45158400, 0, 45, 3, 3, 10381 },
+	{ 180633600, 0, 45, 3, 1, 10381 },
+};
+
+static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int epll_con, epll_con_k;
+	unsigned int i;
+	unsigned int tmp;
+	unsigned int epll_rate;
+	unsigned int locktime;
+	unsigned int lockcnt;
+
+	/* Return if nothing changed */
+	if (clk->rate == rate)
+		return 0;
+
+	if (clk->parent)
+		epll_rate = clk_get_rate(clk->parent);
+	else
+		epll_rate = clk_ext_xtal_mux.rate;
+
+	if (epll_rate != 24000000) {
+		pr_err("Invalid Clock : recommended clock is 24MHz.\n");
+		return -EINVAL;
+	}
+
+	epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
+	epll_con &= ~(0x1 << 27 | \
+			PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
+			PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
+			PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+	for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+		if (epll_div[i][0] == rate) {
+			epll_con_k = epll_div[i][5] << 0;
+			epll_con |= epll_div[i][1] << 27;
+			epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
+			epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
+			epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(epll_div)) {
+		printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	epll_rate /= 1000000;
+
+	/* 3000 max_cycls : specification data */
+	locktime = 3000 / epll_rate * epll_div[i][3];
+	lockcnt = locktime * 10000 / (10000 / epll_rate);
+
+	__raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
+
+	__raw_writel(epll_con, EXYNOS5_EPLL_CON0);
+	__raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
+
+	do {
+		tmp = __raw_readl(EXYNOS5_EPLL_CON0);
+	} while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
+
+	clk->rate = rate;
+
+	return 0;
+}
+
+static struct clk_ops exynos5_epll_ops = {
+	.get_rate = exynos5_epll_get_rate,
+	.set_rate = exynos5_epll_set_rate,
+};
+
+static int xtal_rate;
+
+static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
+{
+	return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
+}
+
+static struct clk_ops exynos5_fout_apll_ops = {
+	.get_rate = exynos5_fout_apll_get_rate,
+};
+
+#ifdef CONFIG_PM
+static int exynos5_clock_suspend(void)
+{
+	s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+
+	return 0;
+}
+
+static void exynos5_clock_resume(void)
+{
+	s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+}
+#else
+#define exynos5_clock_suspend NULL
+#define exynos5_clock_resume NULL
+#endif
+
+struct syscore_ops exynos5_clock_syscore_ops = {
+	.suspend        = exynos5_clock_suspend,
+	.resume         = exynos5_clock_resume,
+};
+
+void __init_or_cpufreq exynos5_setup_clocks(void)
+{
+	struct clk *xtal_clk;
+	unsigned long apll;
+	unsigned long bpll;
+	unsigned long cpll;
+	unsigned long mpll;
+	unsigned long epll;
+	unsigned long vpll;
+	unsigned long vpllsrc;
+	unsigned long xtal;
+	unsigned long armclk;
+	unsigned long mout_cdrex;
+	unsigned long aclk_400;
+	unsigned long aclk_333;
+	unsigned long aclk_266;
+	unsigned long aclk_200;
+	unsigned long aclk_166;
+	unsigned long aclk_66;
+	unsigned int ptr;
+
+	printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+	xtal_clk = clk_get(NULL, "xtal");
+	BUG_ON(IS_ERR(xtal_clk));
+
+	xtal = clk_get_rate(xtal_clk);
+
+	xtal_rate = xtal;
+
+	clk_put(xtal_clk);
+
+	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+	apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
+	bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
+	cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
+	mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
+	epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
+			__raw_readl(EXYNOS5_EPLL_CON1));
+
+	vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
+	vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
+			__raw_readl(EXYNOS5_VPLL_CON1));
+
+	clk_fout_apll.ops = &exynos5_fout_apll_ops;
+	clk_fout_bpll.rate = bpll;
+	clk_fout_cpll.rate = cpll;
+	clk_fout_mpll.rate = mpll;
+	clk_fout_epll.rate = epll;
+	clk_fout_vpll.rate = vpll;
+
+	printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
+			"M=%ld, E=%ld V=%ld",
+			apll, bpll, cpll, mpll, epll, vpll);
+
+	armclk = clk_get_rate(&exynos5_clk_armclk);
+	mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
+
+	aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
+	aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
+	aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
+	aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
+	aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
+	aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
+
+	printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
+			"ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
+			"ACLK166=%ld, ACLK66=%ld\n",
+			armclk, mout_cdrex, aclk_400,
+			aclk_333, aclk_266, aclk_200,
+			aclk_166, aclk_66);
+
+
+	clk_fout_epll.ops = &exynos5_epll_ops;
+
+	if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
+
+	clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
+	clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
+
+	clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
+	clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
+		s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
+}
+
+void __init exynos5_register_clocks(void)
+{
+	int ptr;
+
+	s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
+		s3c_register_clksrc(exynos5_sysclks[ptr], 1);
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
+		s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
+		s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
+
+	s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
+	s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
+
+	s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
+		s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
+
+	s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+	s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+	clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
+
+	register_syscore_ops(&exynos5_clock_syscore_ops);
+	s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 790f525..113836b 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -201,6 +201,68 @@
 #define EXYNOS4210_CLKDIV_LCD1			EXYNOS_CLKREG(0x0C538)
 #define EXYNOS4210_CLKGATE_IP_LCD1		EXYNOS_CLKREG(0x0C938)
 
+/* For EXYNOS5250 */
+
+#define EXYNOS5_APLL_CON0			EXYNOS_CLKREG(0x00100)
+#define EXYNOS5_CLKSRC_CPU			EXYNOS_CLKREG(0x00200)
+#define EXYNOS5_CLKDIV_CPU0			EXYNOS_CLKREG(0x00500)
+#define EXYNOS5_MPLL_CON0			EXYNOS_CLKREG(0x04100)
+#define EXYNOS5_CLKSRC_CORE1			EXYNOS_CLKREG(0x04204)
+
+#define EXYNOS5_CLKGATE_IP_CORE			EXYNOS_CLKREG(0x04900)
+
+#define EXYNOS5_CLKDIV_ACP			EXYNOS_CLKREG(0x08500)
+
+#define EXYNOS5_CLKSRC_TOP2			EXYNOS_CLKREG(0x10218)
+#define EXYNOS5_EPLL_CON0			EXYNOS_CLKREG(0x10130)
+#define EXYNOS5_EPLL_CON1			EXYNOS_CLKREG(0x10134)
+#define EXYNOS5_VPLL_CON0			EXYNOS_CLKREG(0x10140)
+#define EXYNOS5_VPLL_CON1			EXYNOS_CLKREG(0x10144)
+#define EXYNOS5_CPLL_CON0			EXYNOS_CLKREG(0x10120)
+
+#define EXYNOS5_CLKSRC_TOP0			EXYNOS_CLKREG(0x10210)
+#define EXYNOS5_CLKSRC_TOP3			EXYNOS_CLKREG(0x1021C)
+#define EXYNOS5_CLKSRC_GSCL			EXYNOS_CLKREG(0x10220)
+#define EXYNOS5_CLKSRC_DISP1_0			EXYNOS_CLKREG(0x1022C)
+#define EXYNOS5_CLKSRC_FSYS			EXYNOS_CLKREG(0x10244)
+#define EXYNOS5_CLKSRC_PERIC0			EXYNOS_CLKREG(0x10250)
+
+#define EXYNOS5_CLKSRC_MASK_TOP			EXYNOS_CLKREG(0x10310)
+#define EXYNOS5_CLKSRC_MASK_GSCL		EXYNOS_CLKREG(0x10320)
+#define EXYNOS5_CLKSRC_MASK_DISP1_0		EXYNOS_CLKREG(0x1032C)
+#define EXYNOS5_CLKSRC_MASK_FSYS		EXYNOS_CLKREG(0x10340)
+#define EXYNOS5_CLKSRC_MASK_PERIC0		EXYNOS_CLKREG(0x10350)
+
+#define EXYNOS5_CLKDIV_TOP0			EXYNOS_CLKREG(0x10510)
+#define EXYNOS5_CLKDIV_TOP1			EXYNOS_CLKREG(0x10514)
+#define EXYNOS5_CLKDIV_GSCL			EXYNOS_CLKREG(0x10520)
+#define EXYNOS5_CLKDIV_DISP1_0			EXYNOS_CLKREG(0x1052C)
+#define EXYNOS5_CLKDIV_GEN			EXYNOS_CLKREG(0x1053C)
+#define EXYNOS5_CLKDIV_FSYS0			EXYNOS_CLKREG(0x10548)
+#define EXYNOS5_CLKDIV_FSYS1			EXYNOS_CLKREG(0x1054C)
+#define EXYNOS5_CLKDIV_FSYS2			EXYNOS_CLKREG(0x10550)
+#define EXYNOS5_CLKDIV_FSYS3			EXYNOS_CLKREG(0x10554)
+#define EXYNOS5_CLKDIV_PERIC0			EXYNOS_CLKREG(0x10558)
+
+#define EXYNOS5_CLKGATE_IP_ACP			EXYNOS_CLKREG(0x08800)
+#define EXYNOS5_CLKGATE_IP_GSCL			EXYNOS_CLKREG(0x10920)
+#define EXYNOS5_CLKGATE_IP_DISP1		EXYNOS_CLKREG(0x10928)
+#define EXYNOS5_CLKGATE_IP_MFC			EXYNOS_CLKREG(0x1092C)
+#define EXYNOS5_CLKGATE_IP_GEN			EXYNOS_CLKREG(0x10934)
+#define EXYNOS5_CLKGATE_IP_FSYS			EXYNOS_CLKREG(0x10944)
+#define EXYNOS5_CLKGATE_IP_GPS			EXYNOS_CLKREG(0x1094C)
+#define EXYNOS5_CLKGATE_IP_PERIC		EXYNOS_CLKREG(0x10950)
+#define EXYNOS5_CLKGATE_IP_PERIS		EXYNOS_CLKREG(0x10960)
+#define EXYNOS5_CLKGATE_BLOCK			EXYNOS_CLKREG(0x10980)
+
+#define EXYNOS5_BPLL_CON0			EXYNOS_CLKREG(0x20110)
+#define EXYNOS5_CLKSRC_CDREX			EXYNOS_CLKREG(0x20200)
+#define EXYNOS5_CLKDIV_CDREX			EXYNOS_CLKREG(0x20500)
+
+#define EXYNOS5_EPLL_LOCK			EXYNOS_CLKREG(0x10030)
+
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT		(29)
+
 /* Compatibility defines and inclusion */
 
 #include <mach/regs-pmu.h>
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index 963edea..f68a9bb 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -61,6 +61,20 @@ struct clk clk_fout_apll = {
 	.id		= -1,
 };
 
+/* BPLL clock output */
+
+struct clk clk_fout_bpll = {
+	.name		= "fout_bpll",
+	.id		= -1,
+};
+
+/* CPLL clock output */
+
+struct clk clk_fout_cpll = {
+	.name		= "fout_cpll",
+	.id		= -1,
+};
+
 /* MPLL clock output
  * No need .ctrlbit, this is always on
 */
@@ -101,6 +115,28 @@ struct clksrc_sources clk_src_apll = {
 	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),
 };
 
+/* Possible clock sources for BPLL Mux */
+static struct clk *clk_src_bpll_list[] = {
+	[0] = &clk_fin_bpll,
+	[1] = &clk_fout_bpll,
+};
+
+struct clksrc_sources clk_src_bpll = {
+	.sources	= clk_src_bpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),
+};
+
+/* Possible clock sources for CPLL Mux */
+static struct clk *clk_src_cpll_list[] = {
+	[0] = &clk_fin_cpll,
+	[1] = &clk_fout_cpll,
+};
+
+struct clksrc_sources clk_src_cpll = {
+	.sources	= clk_src_cpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_cpll_list),
+};
+
 /* Possible clock sources for MPLL Mux */
 static struct clk *clk_src_mpll_list[] = {
 	[0] = &clk_fin_mpll,
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 984bf9e..1de4b32 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -18,6 +18,8 @@
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
 
 #define clk_fin_apll clk_ext_xtal_mux
+#define clk_fin_bpll clk_ext_xtal_mux
+#define clk_fin_cpll clk_ext_xtal_mux
 #define clk_fin_mpll clk_ext_xtal_mux
 #define clk_fin_epll clk_ext_xtal_mux
 #define clk_fin_dpll clk_ext_xtal_mux
@@ -29,6 +31,8 @@ extern struct clk clk_xusbxti;
 extern struct clk clk_48m;
 extern struct clk s5p_clk_27m;
 extern struct clk clk_fout_apll;
+extern struct clk clk_fout_bpll;
+extern struct clk clk_fout_cpll;
 extern struct clk clk_fout_mpll;
 extern struct clk clk_fout_epll;
 extern struct clk clk_fout_dpll;
@@ -37,6 +41,8 @@ extern struct clk clk_arm;
 extern struct clk clk_vpll;
 
 extern struct clksrc_sources clk_src_apll;
+extern struct clksrc_sources clk_src_bpll;
+extern struct clksrc_sources clk_src_cpll;
 extern struct clksrc_sources clk_src_mpll;
 extern struct clksrc_sources clk_src_epll;
 extern struct clksrc_sources clk_src_dpll;
-- 
1.7.4.4

[PATCH v2 04/11] ARM: EXYNOS: add interrupt definitions for EXYNOS5250

[Kukjin Kim]

This patch adds the interrupt definitions for EXYNOS5250 at
<mach/irqs.h> file. Basically, now it is needed for EXYNOS5250
interrupt and will be updated for single zImage next time.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/include/mach/irqs.h |  236 +++++++++++++++++++++++++++++-
 1 files changed, 232 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index f77bce0..0dab1b1 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * EXYNOS4 - IRQ definitions
+ * EXYNOS - IRQ definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -25,6 +24,8 @@
 
 #define IRQ_SPI(x)		(x+32)
 
+#ifdef CONFIG_ARCH_EXYNOS4
+
 #define IRQ_EINT0		IRQ_SPI(16)
 #define IRQ_EINT1		IRQ_SPI(17)
 #define IRQ_EINT2		IRQ_SPI(18)
@@ -170,5 +171,232 @@
 
 /* Set the default NR_IRQS */
 #define NR_IRQS			(IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+#endif
+
+#ifdef CONFIG_ARCH_EXYNOS5
+#define IRQ_EINT16_31		IRQ_SPI(32)
+#define IRQ_MDMA0		IRQ_SPI(33)
+#define IRQ_PDMA0		IRQ_SPI(34)
+#define IRQ_PDMA1		IRQ_SPI(35)
+#define IRQ_TIMER0_VIC		IRQ_SPI(36)
+#define IRQ_TIMER1_VIC		IRQ_SPI(37)
+#define IRQ_TIMER2_VIC		IRQ_SPI(38)
+#define IRQ_TIMER3_VIC		IRQ_SPI(39)
+#define IRQ_TIMER4_VIC		IRQ_SPI(40)
+#define IRQ_RTIC		IRQ_SPI(41)
+#define IRQ_WDT			IRQ_SPI(42)
+#define IRQ_RTC_ALARM		IRQ_SPI(43)
+#define IRQ_RTC_TIC		IRQ_SPI(44)
+#define IRQ_GPIO_XB		IRQ_SPI(45)
+#define IRQ_GPIO_XA		IRQ_SPI(46)
+#define IRQ_GPIO		IRQ_SPI(47)
+#define IRQ_IEM_IEC		IRQ_SPI(48)
+#define IRQ_IEM_APC		IRQ_SPI(49)
+#define IRQ_GPIO_C2C		IRQ_SPI(50)
+#define IRQ_UART0		IRQ_SPI(51)
+#define IRQ_UART1		IRQ_SPI(52)
+#define IRQ_UART2		IRQ_SPI(53)
+#define IRQ_UART3		IRQ_SPI(54)
+#define IRQ_UART4		IRQ_SPI(55)
+#define IRQ_IIC			IRQ_SPI(56)
+#define IRQ_IIC1		IRQ_SPI(57)
+#define IRQ_IIC2		IRQ_SPI(58)
+#define IRQ_IIC3		IRQ_SPI(59)
+#define IRQ_IIC4		IRQ_SPI(60)
+#define IRQ_IIC5		IRQ_SPI(61)
+#define IRQ_IIC6		IRQ_SPI(62)
+#define IRQ_IIC7		IRQ_SPI(63)
+#define IRQ_IIC_HDMIPHY		IRQ_SPI(64)
+#define IRQ_TMU			IRQ_SPI(65)
+#define IRQ_FIQ_0		IRQ_SPI(66)
+#define IRQ_FIQ_1		IRQ_SPI(67)
+#define IRQ_SPI0		IRQ_SPI(68)
+#define IRQ_SPI1		IRQ_SPI(69)
+#define IRQ_SPI2		IRQ_SPI(70)
+#define IRQ_USB_HOST		IRQ_SPI(71)
+#define IRQ_USB3_DRD		IRQ_SPI(72)
+#define IRQ_MIPI_HSI		IRQ_SPI(73)
+#define IRQ_USB_HSOTG		IRQ_SPI(74)
+#define IRQ_HSMMC0		IRQ_SPI(75)
+#define IRQ_HSMMC1		IRQ_SPI(76)
+#define IRQ_HSMMC2		IRQ_SPI(77)
+#define IRQ_HSMMC3		IRQ_SPI(78)
+#define IRQ_MIPICSI0		IRQ_SPI(79)
+#define IRQ_MIPICSI1		IRQ_SPI(80)
+#define IRQ_EFNFCON_DMA_ABORT	IRQ_SPI(81)
+#define IRQ_MIPIDSI0		IRQ_SPI(82)
+#define IRQ_ROTATOR		IRQ_SPI(84)
+#define IRQ_GSC0		IRQ_SPI(85)
+#define IRQ_GSC1		IRQ_SPI(86)
+#define IRQ_GSC2		IRQ_SPI(87)
+#define IRQ_GSC3		IRQ_SPI(88)
+#define IRQ_JPEG		IRQ_SPI(89)
+#define IRQ_EFNFCON_DMA		IRQ_SPI(90)
+#define IRQ_2D			IRQ_SPI(91)
+#define IRQ_SFMC0		IRQ_SPI(92)
+#define IRQ_SFMC1		IRQ_SPI(93)
+#define IRQ_MIXER		IRQ_SPI(94)
+#define IRQ_HDMI		IRQ_SPI(95)
+#define IRQ_MFC			IRQ_SPI(96)
+#define IRQ_AUDIO_SS		IRQ_SPI(97)
+#define IRQ_I2S0		IRQ_SPI(98)
+#define IRQ_I2S1		IRQ_SPI(99)
+#define IRQ_I2S2		IRQ_SPI(100)
+#define IRQ_AC97		IRQ_SPI(101)
+#define IRQ_PCM0		IRQ_SPI(102)
+#define IRQ_PCM1		IRQ_SPI(103)
+#define IRQ_PCM2		IRQ_SPI(104)
+#define IRQ_SPDIF		IRQ_SPI(105)
+#define IRQ_ADC0		IRQ_SPI(106)
+
+#define IRQ_SATA_PHY		IRQ_SPI(108)
+#define IRQ_SATA_PMEMREQ	IRQ_SPI(109)
+#define IRQ_CAM_C		IRQ_SPI(110)
+#define IRQ_EAGLE_PMU		IRQ_SPI(111)
+#define IRQ_INTFEEDCTRL_SSS	IRQ_SPI(112)
+#define IRQ_DP1_INTP1		IRQ_SPI(113)
+#define IRQ_CEC			IRQ_SPI(114)
+#define IRQ_SATA		IRQ_SPI(115)
+#define IRQ_NFCON		IRQ_SPI(116)
+#define GPU_IRQ_NUMBER		IRQ_SPI(117)
+#define JOP_IRQ_NUMBER		IRQ_SPI(118)
+#define MMU_IRQ_NUMBER		IRQ_SPI(119)
+
+#define IRQ_MMC44		IRQ_SPI(123)
+#define IRQ_MDMA1		IRQ_SPI(124)
+#define IRQ_FIMC_LITE0		IRQ_SPI(125)
+#define IRQ_FIMC_LITE1		IRQ_SPI(126)
+#define IRQ_RP_TIMER		IRQ_SPI(127)
+
+#define MAX_IRQ_IN_COMBINER	8
+#define COMBINER_GROUP(x)	((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
+#define COMBINER_IRQ(x, y)	(COMBINER_GROUP(x) + y)
+
+#define IRQ_PMU			COMBINER_IRQ(1, 2)
+#define IRQ_PMU_CPU1		COMBINER_IRQ(1, 6)
+
+#define IRQ_SYSMMU_GSC0_0	COMBINER_IRQ(2, 0)
+#define IRQ_SYSMMU_GSC0_1	COMBINER_IRQ(2, 1)
+#define IRQ_SYSMMU_GSC1_0	COMBINER_IRQ(2, 2)
+#define IRQ_SYSMMU_GSC1_1	COMBINER_IRQ(2, 3)
+#define IRQ_SYSMMU_GSC2_0	COMBINER_IRQ(2, 4)
+#define IRQ_SYSMMU_GSC2_1	COMBINER_IRQ(2, 5)
+#define IRQ_SYSMMU_GSC3_0	COMBINER_IRQ(2, 6)
+#define IRQ_SYSMMU_GSC3_1	COMBINER_IRQ(2, 7)
+
+#define IRQ_SYSMMU_FIMD1_0	COMBINER_IRQ(3, 2)
+#define IRQ_SYSMMU_FIMD1_1	COMBINER_IRQ(3, 3)
+#define IRQ_SYSMMU_LITE0_0	COMBINER_IRQ(3, 4)
+#define IRQ_SYSMMU_LITE0_1	COMBINER_IRQ(3, 5)
+#define IRQ_SYSMMU_SCALERPISP_0	COMBINER_IRQ(3, 6)
+#define IRQ_SYSMMU_SCALERPISP_1	COMBINER_IRQ(3, 7)
+
+#define IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(4, 0)
+#define IRQ_SYSMMU_ROTATOR_1	COMBINER_IRQ(4, 1)
+#define IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 2)
+#define IRQ_SYSMMU_JPEG_1	COMBINER_IRQ(4, 3)
+
+#define IRQ_SYSMMU_FD_0		COMBINER_IRQ(5, 0)
+#define IRQ_SYSMMU_FD_1		COMBINER_IRQ(5, 1)
+#define IRQ_SYSMMU_SCALERCISP_0	COMBINER_IRQ(5, 2)
+#define IRQ_SYSMMU_SCALERCISP_1	COMBINER_IRQ(5, 3)
+#define IRQ_SYSMMU_MCUISP_0	COMBINER_IRQ(5, 4)
+#define IRQ_SYSMMU_MCUISP_1	COMBINER_IRQ(5, 5)
+#define IRQ_SYSMMU_3DNR_0	COMBINER_IRQ(5, 6)
+#define IRQ_SYSMMU_3DNR_1	COMBINER_IRQ(5, 7)
+
+#define IRQ_SYSMMU_ARM_0	COMBINER_IRQ(6, 0)
+#define IRQ_SYSMMU_ARM_1	COMBINER_IRQ(6, 1)
+#define IRQ_SYSMMU_MFC_L_0	COMBINER_IRQ(6, 2)
+#define IRQ_SYSMMU_MFC_L_1	COMBINER_IRQ(6, 3)
+#define IRQ_SYSMMU_RTIC_0	COMBINER_IRQ(6, 4)
+#define IRQ_SYSMMU_RTIC_1	COMBINER_IRQ(6, 5)
+#define IRQ_SYSMMU_SSS_0	COMBINER_IRQ(6, 6)
+#define IRQ_SYSMMU_SSS_1	COMBINER_IRQ(6, 7)
+
+#define IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(7, 0)
+#define IRQ_SYSMMU_MDMA0_1	COMBINER_IRQ(7, 1)
+#define IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(7, 2)
+#define IRQ_SYSMMU_MDMA1_1	COMBINER_IRQ(7, 3)
+#define IRQ_SYSMMU_TV_0		COMBINER_IRQ(7, 4)
+#define IRQ_SYSMMU_TV_1		COMBINER_IRQ(7, 5)
+#define IRQ_SYSMMU_GPSX_0	COMBINER_IRQ(7, 6)
+#define IRQ_SYSMMU_GPSX_1	COMBINER_IRQ(7, 7)
+
+#define IRQ_SYSMMU_MFC_R_0	COMBINER_IRQ(8, 5)
+#define IRQ_SYSMMU_MFC_R_1	COMBINER_IRQ(8, 6)
+
+#define IRQ_SYSMMU_DIS1_0	COMBINER_IRQ(9, 4)
+#define IRQ_SYSMMU_DIS1_1	COMBINER_IRQ(9, 5)
+
+#define IRQ_DP			COMBINER_IRQ(10, 3)
+#define IRQ_SYSMMU_DIS0_0	COMBINER_IRQ(10, 4)
+#define IRQ_SYSMMU_DIS0_1	COMBINER_IRQ(10, 5)
+#define IRQ_SYSMMU_ISP_0	COMBINER_IRQ(10, 6)
+#define IRQ_SYSMMU_ISP_1	COMBINER_IRQ(10, 7)
+
+#define IRQ_SYSMMU_ODC_0	COMBINER_IRQ(11, 0)
+#define IRQ_SYSMMU_ODC_1	COMBINER_IRQ(11, 1)
+#define IRQ_SYSMMU_DRC_0	COMBINER_IRQ(11, 6)
+#define IRQ_SYSMMU_DRC_1	COMBINER_IRQ(11, 7)
+
+#define IRQ_FIMD1_FIFO		COMBINER_IRQ(18, 4)
+#define IRQ_FIMD1_VSYNC		COMBINER_IRQ(18, 5)
+#define IRQ_FIMD1_SYSTEM	COMBINER_IRQ(18, 6)
+
+#define IRQ_EINT0		COMBINER_IRQ(23, 0)
+#define IRQ_MCT_L0		COMBINER_IRQ(23, 1)
+#define IRQ_MCT_L1		COMBINER_IRQ(23, 2)
+#define IRQ_MCT_G0		COMBINER_IRQ(23, 3)
+#define IRQ_MCT_G1		COMBINER_IRQ(23, 4)
+#define IRQ_MCT_G2		COMBINER_IRQ(23, 5)
+#define IRQ_MCT_G3		COMBINER_IRQ(23, 6)
+
+#define IRQ_EINT1		COMBINER_IRQ(24, 0)
+#define IRQ_SYSMMU_LITE1_0	COMBINER_IRQ(24, 1)
+#define IRQ_SYSMMU_LITE1_1	COMBINER_IRQ(24, 2)
+#define IRQ_SYSMMU_2D_0		COMBINER_IRQ(24, 5)
+#define IRQ_SYSMMU_2D_1		COMBINER_IRQ(24, 6)
+
+#define IRQ_EINT2		COMBINER_IRQ(25, 0)
+#define IRQ_EINT3		COMBINER_IRQ(25, 1)
+
+#define IRQ_EINT4		COMBINER_IRQ(26, 0)
+#define IRQ_EINT5		COMBINER_IRQ(26, 1)
+
+#define IRQ_EINT6		COMBINER_IRQ(27, 0)
+#define IRQ_EINT7		COMBINER_IRQ(27, 1)
+
+#define IRQ_EINT8		COMBINER_IRQ(28, 0)
+#define IRQ_EINT9		COMBINER_IRQ(28, 1)
+
+#define IRQ_EINT10		COMBINER_IRQ(29, 0)
+#define IRQ_EINT11		COMBINER_IRQ(29, 1)
+
+#define IRQ_EINT12		COMBINER_IRQ(30, 0)
+#define IRQ_EINT13		COMBINER_IRQ(30, 1)
+
+#define IRQ_EINT14		COMBINER_IRQ(31, 0)
+#define IRQ_EINT15		COMBINER_IRQ(31, 1)
+
+#define MAX_COMBINER_NR		32
+
+#define S5P_IRQ_EINT_BASE	COMBINER_IRQ(MAX_COMBINER_NR, 0)
+
+#define S5P_EINT_BASE1		(S5P_IRQ_EINT_BASE + 0)
+#define S5P_EINT_BASE2		(S5P_IRQ_EINT_BASE + 16)
+
+/* optional GPIO interrupts */
+#define S5P_GPIOINT_BASE	(S5P_IRQ_EINT_BASE + 32)
+#define IRQ_GPIO1_NR_GROUPS	13
+#define IRQ_GPIO2_NR_GROUPS	18
+#define IRQ_GPIO_END		(S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
+
+#define IRQ_TIMER_BASE		(IRQ_GPIO_END + 64)
+
+/* Set the default NR_IRQS */
+#define NR_IRQS			(IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+
+#endif
 
 #endif /* __ASM_ARCH_IRQS_H */
-- 
1.7.4.4

[PATCH v2 05/11] ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5

[Kukjin Kim]

In all of Samsung platform, the setup-i2c0.c file for I2C channel 0
is always compiled. So when supporting new SoC,it should be updated
for it. Since EXYNOS5 GPIO will be supported after this, there is no
setup gpio in there now. It will be implemented with that, of course.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/Makefile     |    2 +-
 arch/arm/mach-exynos/setup-i2c0.c |    9 ++++++---
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 995e7cc..2117f02 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -52,7 +52,7 @@ obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o
 obj-$(CONFIG_EXYNOS4_DEV_DMA)		+= dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)	+= dev-ohci.o
 
-obj-$(CONFIG_ARCH_EXYNOS4)		+= setup-i2c0.o
+obj-$(CONFIG_ARCH_EXYNOS)		+= setup-i2c0.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMC)	+= setup-fimc.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)	+= setup-fimd0.o
 obj-$(CONFIG_EXYNOS4_SETUP_I2C1)	+= setup-i2c1.o
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
index d395bd1..b90d94c 100644
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/setup-i2c0.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com/
  *
  * I2C0 GPIO configuration.
@@ -18,9 +16,14 @@ struct platform_device; /* don't need the contents */
 #include <linux/gpio.h>
 #include <plat/iic.h>
 #include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
+	if (soc_is_exynos5250())
+		/* will be implemented with gpio function */
+		return;
+
 	s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
 			      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
-- 
1.7.4.4

[PATCH v2 06/11] ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5

[Kukjin Kim]

Actually, the base address of uart is different between EXYNOS4
and EXYNOS5 and this patch enables to support uart for EXYNOS4
and EXYNOS5 SoCs at runtime.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/Makefile                   |    1 +
 arch/arm/mach-exynos/common.c                   |    5 +-
 arch/arm/mach-exynos/dev-uart.c                 |   78 +++++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/debug-macro.S |    9 ++-
 arch/arm/mach-exynos/include/mach/irqs.h        |   12 ++++
 arch/arm/mach-exynos/include/mach/map.h         |   20 +++---
 arch/arm/mach-exynos/include/mach/uncompress.h  |   17 ++++--
 arch/arm/plat-s5p/Kconfig                       |    4 +
 arch/arm/plat-s5p/Makefile                      |    3 +-
 arch/arm/plat-samsung/include/plat/devs.h       |    2 +
 arch/arm/plat-samsung/include/plat/uncompress.h |    2 +
 11 files changed, 135 insertions(+), 18 deletions(-)
 create mode 100644 arch/arm/mach-exynos/dev-uart.c

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 2117f02..f8a3770 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_MACH_EXYNOS4_DT)		+= mach-exynos4-dt.o
 
 # device support
 
+obj-y					+= dev-uart.o
 obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
 obj-$(CONFIG_EXYNOS4_DEV_PD)		+= dev-pd.o
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 37257b0..8db2627 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -489,7 +489,10 @@ static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 	for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 		tcfg->has_fracval = 1;
 
-	s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
+	if (soc_is_exynos5250())
+		s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
+	else
+		s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 }
 
 static DEFINE_SPINLOCK(eint_lock);
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
new file mode 100644
index 0000000..61ebfd7
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-uart.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Base EXYNOS UART resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+#define EXYNOS_UART_RESOURCE(_series, _nr)	\
+static struct resource exynos##_series##_uart##_nr##_resource[] = {	\
+	[0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART),	\
+	[1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr),	\
+};
+
+EXYNOS_UART_RESOURCE(4, 0)
+EXYNOS_UART_RESOURCE(4, 1)
+EXYNOS_UART_RESOURCE(4, 2)
+EXYNOS_UART_RESOURCE(4, 3)
+
+struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
+	[0] = {
+		.resources	= exynos4_uart0_resource,
+		.nr_resources	= ARRAY_SIZE(exynos4_uart0_resource),
+	},
+	[1] = {
+		.resources	= exynos4_uart1_resource,
+		.nr_resources	= ARRAY_SIZE(exynos4_uart0_resource),
+	},
+	[2] = {
+		.resources	= exynos4_uart2_resource,
+		.nr_resources	= ARRAY_SIZE(exynos4_uart2_resource),
+	},
+	[3] = {
+		.resources	= exynos4_uart3_resource,
+		.nr_resources	= ARRAY_SIZE(exynos4_uart3_resource),
+	},
+};
+
+EXYNOS_UART_RESOURCE(5, 0)
+EXYNOS_UART_RESOURCE(5, 1)
+EXYNOS_UART_RESOURCE(5, 2)
+EXYNOS_UART_RESOURCE(5, 3)
+
+struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
+	[0] = {
+		.resources	= exynos5_uart0_resource,
+		.nr_resources	= ARRAY_SIZE(exynos5_uart0_resource),
+	},
+	[1] = {
+		.resources	= exynos5_uart1_resource,
+		.nr_resources	= ARRAY_SIZE(exynos5_uart0_resource),
+	},
+	[2] = {
+		.resources	= exynos5_uart2_resource,
+		.nr_resources	= ARRAY_SIZE(exynos5_uart2_resource),
+	},
+	[3] = {
+		.resources	= exynos5_uart3_resource,
+		.nr_resources	= ARRAY_SIZE(exynos5_uart3_resource),
+	},
+};
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
index 6cacf16..6c857ff 100644
--- a/arch/arm/mach-exynos/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
@@ -21,8 +21,13 @@
 	 */
 
 	.macro addruart, rp, rv, tmp
-		ldr	\rp, = S3C_PA_UART
-		ldr	\rv, = S3C_VA_UART
+		mov	\rp, #0x10000000
+		ldr	\rp, [\rp, #0x0]
+		and	\rp, \rp, #0xf00000
+		teq	\rp, #0x500000		@@ EXYNOS5
+		ldreq	\rp, =EXYNOS5_PA_UART
+		movne	\rp, #EXYNOS4_PA_UART	@@ EXYNOS4
+		ldr	\rv, =S3C_VA_UART
 #if CONFIG_DEBUG_S3C_UART != 0
 		add	\rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
 		add	\rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 0dab1b1..76aa0d3 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -399,4 +399,16 @@
 
 #endif
 
+#define EXYNOS4_IRQ_UART0		IRQ_SPI(52)
+#define EXYNOS4_IRQ_UART1		IRQ_SPI(53)
+#define EXYNOS4_IRQ_UART2		IRQ_SPI(54)
+#define EXYNOS4_IRQ_UART3		IRQ_SPI(55)
+#define EXYNOS4_IRQ_UART4		IRQ_SPI(56)
+
+#define EXYNOS5_IRQ_UART0		IRQ_SPI(51)
+#define EXYNOS5_IRQ_UART1		IRQ_SPI(52)
+#define EXYNOS5_IRQ_UART2		IRQ_SPI(53)
+#define EXYNOS5_IRQ_UART3		IRQ_SPI(54)
+#define EXYNOS5_IRQ_UART4		IRQ_SPI(55)
+
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c754a22..e8a7801 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -152,7 +152,6 @@
 #define S3C_PA_IIC7			EXYNOS4_PA_IIC(7)
 #define S3C_PA_RTC			EXYNOS4_PA_RTC
 #define S3C_PA_WDT			EXYNOS4_PA_WATCHDOG
-#define S3C_PA_UART			EXYNOS4_PA_UART
 #define S3C_PA_SPI0			EXYNOS4_PA_SPI0
 #define S3C_PA_SPI1			EXYNOS4_PA_SPI1
 #define S3C_PA_SPI2			EXYNOS4_PA_SPI2
@@ -181,15 +180,18 @@
 
 /* Compatibility UART */
 
-#define S3C_VA_UARTx(x)			(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define EXYNOS4_PA_UART0		0x13800000
+#define EXYNOS4_PA_UART1		0x13810000
+#define EXYNOS4_PA_UART2		0x13820000
+#define EXYNOS4_PA_UART3		0x13830000
+#define EXYNOS4_SZ_UART			SZ_256
 
-#define S5P_PA_UART(x)			(EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART0			S5P_PA_UART(0)
-#define S5P_PA_UART1			S5P_PA_UART(1)
-#define S5P_PA_UART2			S5P_PA_UART(2)
-#define S5P_PA_UART3			S5P_PA_UART(3)
-#define S5P_PA_UART4			S5P_PA_UART(4)
+#define EXYNOS5_PA_UART0		0x12C00000
+#define EXYNOS5_PA_UART1		0x12C10000
+#define EXYNOS5_PA_UART2		0x12C20000
+#define EXYNOS5_PA_UART3		0x12C30000
+#define EXYNOS5_SZ_UART			SZ_256
 
-#define S5P_SZ_UART			SZ_256
+#define S3C_VA_UARTx(x)			(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 21d97bc..f412e35 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * EXYNOS4 - uncompress code
+ * EXYNOS - uncompress code
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -13,12 +12,20 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H __FILE__
 
+#include <asm/mach-types.h>
+
 #include <mach/map.h>
+
+volatile u32 *uart_base;
+
 #include <plat/uncompress.h>
 
 static void arch_detect_cpu(void)
 {
-	/* we do not need to do any cpu detection here at the moment. */
+	if (machine_is_smdk5250())
+		uart_base = (volatile u32 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
+	else
+		uart_base = (volatile u32 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
 
 	/*
 	 * For preventing FIFO overrun or infinite loop of UART console,
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 8167ce6..10e235cc7 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -40,6 +40,10 @@ config S5P_HRT
 	help
 	  Use the High Resolution timer support
 
+config S5P_DEV_UART
+	def_bool y
+	depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
+
 config S5P_PM
 	bool
 	help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 30d8c30..4bd8241 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -12,7 +12,6 @@ obj-				:=
 
 # Core files
 
-obj-y				+= dev-uart.o
 obj-y				+= clock.o
 obj-y				+= irq.o
 obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
@@ -23,5 +22,7 @@ obj-$(CONFIG_S5P_SLEEP)		+= sleep.o
 obj-$(CONFIG_S5P_HRT) 		+= s5p-time.o
 
 # devices
+
+obj-$(CONFIG_S5P_DEV_UART)	+= dev-uart.o
 obj-$(CONFIG_S5P_DEV_MFC)	+= dev-mfc.o
 obj-$(CONFIG_S5P_SETUP_MIPIPHY)	+= setup-mipiphy.o
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 4214ea0..32cc67e 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -26,6 +26,8 @@ struct s3c24xx_uart_resources {
 extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
 extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
 extern struct s3c24xx_uart_resources s5p_uart_resources[];
+extern struct s3c24xx_uart_resources exynos4_uart_resources[];
+extern struct s3c24xx_uart_resources exynos5_uart_resources[];
 
 extern struct platform_device *s3c24xx_uart_devs[];
 extern struct platform_device *s3c24xx_uart_src[];
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index ee48e12..7e068d1 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -37,7 +37,9 @@ static void arch_detect_cpu(void);
 /* how many bytes we allow into the FIFO at a time in FIFO mode */
 #define FIFO_MAX	 (14)
 
+#ifdef S3C_PA_UART
 #define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
+#endif
 
 static __inline__ void
 uart_wr(unsigned int reg, unsigned int val)
-- 
1.7.4.4

[PATCH v2 07/11] ARM: EXYNOS: add support get_core_count() for EXYNOS5250

[Kukjin Kim]

The EXYNOS5250 has two Cortex-A15 cores and there's no
need to call scu_enable() in platform_smp_prepare_cpus().

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/platsmp.c |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 0f2035a..36c3984 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -166,7 +166,10 @@ void __init smp_init_cpus(void)
 	void __iomem *scu_base = scu_base_addr();
 	unsigned int i, ncores;
 
-	ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+	if (soc_is_exynos5250())
+		ncores = 2;
+	else
+		ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
 	/* sanity check */
 	if (ncores > nr_cpu_ids) {
@@ -183,8 +186,8 @@ void __init smp_init_cpus(void)
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
-
-	scu_enable(scu_base_addr());
+	if (!soc_is_exynos5250())
+		scu_enable(scu_base_addr());
 
 	/*
 	 * Write the address of secondary startup into the
-- 
1.7.4.4

[PATCH v2 08/11] ARM: EXYNOS: add support for ARCH_EXYNOS5 and EXYNOS5250

[Kukjin Kim]

This patch add the CONFIG_ARCH_EXYNOS5 and CONFIG_SOC_EXYNOS5250
support for EXYNOS5250 SoC has two Cortex-A15 cores. Since actually,
most codes in mach-exynos/ are used commonly for EXYNOS4 and EXYNOS5
the EXYNOS5/EXYNOS5250 has been implemented in mach-exynos/.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/Makefile                            |    1 +
 arch/arm/mach-exynos/Kconfig                 |   13 ++
 arch/arm/mach-exynos/Makefile                |    1 +
 arch/arm/mach-exynos/common.c                |  165 ++++++++++++++++++++++++--
 arch/arm/mach-exynos/common.h                |   11 ++
 arch/arm/mach-exynos/include/mach/map.h      |   21 +++-
 arch/arm/mach-exynos/include/mach/regs-pmu.h |    1 +
 arch/arm/plat-s5p/Kconfig                    |    4 +-
 arch/arm/plat-samsung/include/plat/cpu.h     |   10 ++
 9 files changed, 211 insertions(+), 16 deletions(-)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1683bfb..a826ffc 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_S5P64X0)		:= s5p64x0
 machine-$(CONFIG_ARCH_S5PC100)		:= s5pc100
 machine-$(CONFIG_ARCH_S5PV210)		:= s5pv210
 machine-$(CONFIG_ARCH_EXYNOS4)		:= exynos
+machine-$(CONFIG_ARCH_EXYNOS5)		:= exynos
 machine-$(CONFIG_ARCH_SA1100)		:= sa1100
 machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_SHMOBILE) 	:= shmobile
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 5d602f6..14b3460 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -22,6 +22,12 @@ config ARCH_EXYNOS4
 	help
 	  Samsung EXYNOS4 SoCs based systems
 
+config ARCH_EXYNOS5
+	bool "SAMSUNG EXYNOS5"
+	select HAVE_SMP
+	help
+	  Samsung EXYNOS5 (Cortex-A15) SoC based systems
+
 endchoice
 
 comment "EXYNOS SoCs"
@@ -53,6 +59,13 @@ config SOC_EXYNOS4412
 	help
 	  Enable EXYNOS4412 SoC support
 
+config SOC_EXYNOS5250
+	bool "SAMSUNG EXYNOS5250"
+	default y
+	depends on ARCH_EXYNOS5
+	help
+	  Enable EXYNOS5250 SoC support
+
 config EXYNOS4_MCT
 	bool
 	default y
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index f8a3770..7214092 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -14,6 +14,7 @@ obj-				:=
 
 obj-$(CONFIG_ARCH_EXYNOS)	+= common.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clock-exynos4.o
+obj-$(CONFIG_ARCH_EXYNOS5)	+= clock-exynos5.o
 obj-$(CONFIG_CPU_EXYNOS4210)	+= clock-exynos4210.o
 obj-$(CONFIG_SOC_EXYNOS4212)	+= clock-exynos4212.o
 
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 8db2627..cff7313 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -49,9 +49,12 @@
 static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
+static const char name_exynos5250[] = "EXYNOS5250";
 
 static void exynos4_map_io(void);
+static void exynos5_map_io(void);
 static void exynos4_init_clocks(int xtal);
+static void exynos5_init_clocks(int xtal);
 static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
 
@@ -80,6 +83,14 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.init_uarts	= exynos_init_uarts,
 		.init		= exynos_init,
 		.name		= name_exynos4412,
+	}, {
+		.idcode		= EXYNOS5250_SOC_ID,
+		.idmask		= EXYNOS5_SOC_MASK,
+		.map_io		= exynos5_map_io,
+		.init_clocks	= exynos5_init_clocks,
+		.init_uarts	= exynos_init_uarts,
+		.init		= exynos_init,
+		.name		= name_exynos5250,
 	},
 };
 
@@ -88,10 +99,14 @@ static struct cpu_table cpu_ids[] __initdata = {
 static struct map_desc exynos_iodesc[] __initdata = {
 	{
 		.virtual	= (unsigned long)S5P_VA_CHIPID,
-		.pfn		= __phys_to_pfn(EXYNOS4_PA_CHIPID),
+		.pfn		= __phys_to_pfn(EXYNOS_PA_CHIPID),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
-	}, {
+	},
+};
+
+static struct map_desc exynos4_iodesc[] __initdata = {
+	{
 		.virtual	= (unsigned long)S3C_VA_SYS,
 		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSCON),
 		.length		= SZ_64K,
@@ -141,11 +156,7 @@ static struct map_desc exynos_iodesc[] __initdata = {
 		.pfn		= __phys_to_pfn(EXYNOS4_PA_UART),
 		.length		= SZ_512K,
 		.type		= MT_DEVICE,
-	},
-};
-
-static struct map_desc exynos4_iodesc[] __initdata = {
-	{
+	}, {
 		.virtual	= (unsigned long)S5P_VA_CMU,
 		.pfn		= __phys_to_pfn(EXYNOS4_PA_CMU),
 		.length		= SZ_128K,
@@ -206,6 +217,70 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
 	},
 };
 
+static struct map_desc exynos5_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S3C_VA_SYS,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSCON),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_TIMER,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_TIMER),
+		.length		= SZ_16K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_SROMC,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SROMC),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_SYSTIMER,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_SYSRAM,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSRAM),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_CMU,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_CMU),
+		.length		= 144 * SZ_1K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_PMU,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_PMU),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_COMBINER),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_UART,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_UART),
+		.length		= SZ_512K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	},
+};
+
 static void exynos_idle(void)
 {
 	if (!need_resched())
@@ -219,6 +294,11 @@ void exynos4_restart(char mode, const char *cmd)
 	__raw_writel(0x1, S5P_SWRESET);
 }
 
+void exynos5_restart(char mode, const char *cmd)
+{
+	__raw_writel(0x1, EXYNOS_SWRESET);
+}
+
 /*
  * exynos_map_io
  *
@@ -269,6 +349,16 @@ static void __init exynos4_map_io(void)
 	s5p_hdmi_setname("exynos4-hdmi");
 }
 
+static void __init exynos5_map_io(void)
+{
+	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
+
+	/* The I2C bus controllers are directly compatible with s3c2440 */
+	s3c_i2c0_setname("s3c2440-i2c");
+	s3c_i2c1_setname("s3c2440-i2c");
+	s3c_i2c2_setname("s3c2440-i2c");
+}
+
 static void __init exynos4_init_clocks(int xtal)
 {
 	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
@@ -285,6 +375,17 @@ static void __init exynos4_init_clocks(int xtal)
 	exynos4_setup_clocks();
 }
 
+static void __init exynos5_init_clocks(int xtal)
+{
+	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+	s3c24xx_register_baseclocks(xtal);
+	s5p_register_clocks(xtal);
+
+	exynos5_register_clocks();
+	exynos5_setup_clocks();
+}
+
 #define COMBINER_ENABLE_SET	0x0
 #define COMBINER_ENABLE_CLEAR	0x4
 #define COMBINER_INT_STATUS	0xC
@@ -428,24 +529,59 @@ void __init exynos4_init_irq(void)
 	s5p_init_irq(NULL, 0);
 }
 
+void __init exynos5_init_irq(void)
+{
+	int irq;
+
+	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+
+	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+				COMBINER_IRQ(irq, 0));
+		combiner_cascade_irq(irq, IRQ_SPI(irq));
+	}
+
+	/*
+	 * The parameters of s5p_init_irq() are for VIC init.
+	 * Theses parameters should be NULL and 0 because EXYNOS4
+	 * uses GIC instead of VIC.
+	 */
+	s5p_init_irq(NULL, 0);
+}
+
 struct bus_type exynos4_subsys = {
 	.name		= "exynos4-core",
 	.dev_name	= "exynos4-core",
 };
 
+struct bus_type exynos5_subsys = {
+	.name		= "exynos5-core",
+	.dev_name	= "exynos5-core",
+};
+
 static struct device exynos4_dev = {
 	.bus	= &exynos4_subsys,
 };
 
-static int __init exynos4_core_init(void)
+static struct device exynos5_dev = {
+	.bus	= &exynos5_subsys,
+};
+
+static int __init exynos_core_init(void)
 {
-	return subsys_system_register(&exynos4_subsys, NULL);
+	if (soc_is_exynos5250())
+		return subsys_system_register(&exynos5_subsys, NULL);
+	else
+		return subsys_system_register(&exynos4_subsys, NULL);
 }
-core_initcall(exynos4_core_init);
+core_initcall(exynos_core_init);
 
 #ifdef CONFIG_CACHE_L2X0
 static int __init exynos4_l2x0_cache_init(void)
 {
+	if (soc_is_exynos5250())
+		return 0;
+
 	/* TAG, Data Latency Control: 2cycle */
 	__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 
@@ -465,7 +601,6 @@ static int __init exynos4_l2x0_cache_init(void)
 
 	return 0;
 }
-
 early_initcall(exynos4_l2x0_cache_init);
 #endif
 
@@ -476,7 +611,10 @@ static int __init exynos_init(void)
 	/* set idle function */
 	pm_idle = exynos_idle;
 
-	return device_register(&exynos4_dev);
+	if (soc_is_exynos5250())
+		return device_register(&exynos5_dev);
+	else
+		return device_register(&exynos4_dev);
 }
 
 /* uart registration process */
@@ -685,6 +823,9 @@ int __init exynos4_init_irq_eint(void)
 {
 	int irq;
 
+	if (soc_is_exynos5250())
+		return 0;
+
 	for (irq = 0 ; irq <= 31 ; irq++) {
 		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
 					 handle_level_irq);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index b32c6b5..677b546 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -16,7 +16,9 @@ extern struct sys_timer exynos4_timer;
 
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
+void exynos5_init_irq(void);
 void exynos4_restart(char mode, const char *cmd);
+void exynos5_restart(char mode, const char *cmd);
 
 #ifdef CONFIG_ARCH_EXYNOS4
 void exynos4_register_clocks(void);
@@ -27,6 +29,15 @@ void exynos4_setup_clocks(void);
 #define exynos4_setup_clocks()
 #endif
 
+#ifdef CONFIG_ARCH_EXYNOS5
+void exynos5_register_clocks(void);
+void exynos5_setup_clocks(void);
+
+#else
+#define exynos5_register_clocks()
+#define exynos5_setup_clocks()
+#endif
+
 #ifdef CONFIG_CPU_EXYNOS4210
 void exynos4210_register_clocks(void);
 
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index e8a7801..ac60533 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -25,6 +25,7 @@
 
 #define EXYNOS4_PA_SYSRAM0		0x02025000
 #define EXYNOS4_PA_SYSRAM1		0x02020000
+#define EXYNOS5_PA_SYSRAM		0x02020000
 
 #define EXYNOS4_PA_FIMC0		0x11800000
 #define EXYNOS4_PA_FIMC1		0x11810000
@@ -44,14 +45,23 @@
 #define EXYNOS4_PA_ONENAND		0x0C000000
 #define EXYNOS4_PA_ONENAND_DMA		0x0C600000
 
-#define EXYNOS4_PA_CHIPID		0x10000000
+#define EXYNOS_PA_CHIPID		0x10000000
 
 #define EXYNOS4_PA_SYSCON		0x10010000
+#define EXYNOS5_PA_SYSCON		0x10050100
+
 #define EXYNOS4_PA_PMU			0x10020000
+#define EXYNOS5_PA_PMU			0x10040000
+
 #define EXYNOS4_PA_CMU			0x10030000
+#define EXYNOS5_PA_CMU			0x10010000
 
 #define EXYNOS4_PA_SYSTIMER		0x10050000
+#define EXYNOS5_PA_SYSTIMER		0x101C0000
+
 #define EXYNOS4_PA_WATCHDOG		0x10060000
+#define EXYNOS5_PA_WATCHDOG		0x101D0000
+
 #define EXYNOS4_PA_RTC			0x10070000
 
 #define EXYNOS4_PA_KEYPAD		0x100A0000
@@ -59,9 +69,12 @@
 #define EXYNOS4_PA_DMC0			0x10400000
 
 #define EXYNOS4_PA_COMBINER		0x10440000
+#define EXYNOS5_PA_COMBINER		0x10440000
 
 #define EXYNOS4_PA_GIC_CPU		0x10480000
 #define EXYNOS4_PA_GIC_DIST		0x10490000
+#define EXYNOS5_PA_GIC_CPU		0x10480000
+#define EXYNOS5_PA_GIC_DIST		0x10490000
 
 #define EXYNOS4_PA_COREPERI		0x10500000
 #define EXYNOS4_PA_TWD			0x10500600
@@ -91,7 +104,6 @@
 #define EXYNOS4_PA_SPI1			0x13930000
 #define EXYNOS4_PA_SPI2			0x13940000
 
-
 #define EXYNOS4_PA_GPIO1		0x11400000
 #define EXYNOS4_PA_GPIO2		0x11000000
 #define EXYNOS4_PA_GPIO3		0x03860000
@@ -109,6 +121,7 @@
 #define EXYNOS4_PA_SATAPHY_CTRL		0x126B0000
 
 #define EXYNOS4_PA_SROMC		0x12570000
+#define EXYNOS5_PA_SROMC		0x12250000
 
 #define EXYNOS4_PA_EHCI			0x12580000
 #define EXYNOS4_PA_OHCI			0x12590000
@@ -116,6 +129,7 @@
 #define EXYNOS4_PA_MFC			0x13400000
 
 #define EXYNOS4_PA_UART			0x13800000
+#define EXYNOS5_PA_UART			0x12C00000
 
 #define EXYNOS4_PA_VP			0x12C00000
 #define EXYNOS4_PA_MIXER		0x12C10000
@@ -124,6 +138,7 @@
 #define EXYNOS4_PA_IIC_HDMIPHY		0x138E0000
 
 #define EXYNOS4_PA_IIC(x)		(0x13860000 + ((x) * 0x10000))
+#define EXYNOS5_PA_IIC(x)		(0x12C60000 + ((x) * 0x10000))
 
 #define EXYNOS4_PA_ADC			0x13910000
 #define EXYNOS4_PA_ADC1			0x13911000
@@ -133,8 +148,10 @@
 #define EXYNOS4_PA_SPDIF		0x139B0000
 
 #define EXYNOS4_PA_TIMER		0x139D0000
+#define EXYNOS5_PA_TIMER		0x12DD0000
 
 #define EXYNOS4_PA_SDRAM		0x40000000
+#define EXYNOS5_PA_SDRAM		0x40000000
 
 /* Compatibiltiy Defines */
 
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4fff8e9..4c53f38 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -31,6 +31,7 @@
 #define S5P_USE_STANDBYWFE_ISP_ARM		(1 << 26)
 
 #define S5P_SWRESET				S5P_PMUREG(0x0400)
+#define EXYNOS_SWRESET				S5P_PMUREG(0x0400)
 
 #define S5P_WAKEUP_STAT				S5P_PMUREG(0x0600)
 #define S5P_EINT_WAKEUP_MASK			S5P_PMUREG(0x0604)
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 10e235cc7..88795ea 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -9,8 +9,8 @@ config PLAT_S5P
 	bool
 	depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
 	default y
-	select ARM_VIC if !ARCH_EXYNOS4
-	select ARM_GIC if ARCH_EXYNOS4
+	select ARM_VIC if !ARCH_EXYNOS
+	select ARM_GIC if ARCH_EXYNOS
 	select GIC_NON_BANKED if ARCH_EXYNOS4
 	select NO_IOPORT
 	select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 73cb3cf..787ceac 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -42,6 +42,9 @@ extern unsigned long samsung_cpu_id;
 #define EXYNOS4412_CPU_ID	0xE4412200
 #define EXYNOS4_CPU_MASK	0xFFFE0000
 
+#define EXYNOS5250_SOC_ID	0x43520000
+#define EXYNOS5_SOC_MASK	0xFFFFF000
+
 #define IS_SAMSUNG_CPU(name, id, mask)		\
 static inline int is_samsung_##name(void)	\
 {						\
@@ -58,6 +61,7 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
 
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
     defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -120,6 +124,12 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
 #define EXYNOS4210_REV_1_0	(0x10)
 #define EXYNOS4210_REV_1_1	(0x11)
 
+#if defined(CONFIG_SOC_EXYNOS5250)
+# define soc_is_exynos5250()	is_samsung_exynos5250()
+#else
+# define soc_is_exynos5250()	0
+#endif
+
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 
 #ifndef MHZ
-- 
1.7.4.4

[PATCH v2 09/11] ARM: EXYNOS: add support device tree enabled board file for EXYNOS5

[Kukjin Kim]

This patch adds a new EXYNOS5 compatible device tree enabled board
When using this, a corresponding device tree blob which describes the
board's properties should be supplied at boot time to the kernel.

Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/Kconfig           |   22 +++++++++-
 arch/arm/mach-exynos/Makefile          |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c |   78 ++++++++++++++++++++++++++++++++
 3 files changed, 100 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-exynos/mach-exynos5-dt.c

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 14b3460..deb8e8a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -364,7 +364,18 @@ config MACH_SMDK4412
 	  Machine support for Samsung SMDK4412
 endif
 
-comment "Flattened Device Tree based board for Exynos4 based SoC"
+if ARCH_EXYNOS5
+
+comment "EXYNOS5250 Boards"
+
+config MACH_SMDK5250
+	bool "SMDK5250"
+	select SOC_EXYNOS5250
+	help
+	  Machine support for Samsung SMDK5250
+endif
+
+comment "Flattened Device Tree based board for EXYNOS SoCs"
 
 config MACH_EXYNOS4_DT
 	bool "Samsung Exynos4 Machine using device tree"
@@ -378,6 +389,15 @@ config MACH_EXYNOS4_DT
 	  Note: This is under development and not all peripherals can be supported
 	  with this machine file.
 
+config MACH_EXYNOS5_DT
+	bool "SAMSUNG EXYNOS5 Machine using device tree"
+	select SOC_EXYNOS5250
+	select USE_OF
+	select ARM_AMBA
+	help
+	  Machine support for Samsung Exynos4 machine with device tree enabled.
+	  Select this if a fdt blob is available for the EXYNOS4 SoC based board.
+
 if ARCH_EXYNOS4
 
 comment "Configuration for HSMMC 8-bit bus width"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 7214092..29967ef 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_MACH_SMDK4212)		+= mach-smdk4x12.o
 obj-$(CONFIG_MACH_SMDK4412)		+= mach-smdk4x12.o
 
 obj-$(CONFIG_MACH_EXYNOS4_DT)		+= mach-exynos4-dt.o
+obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
 
 # device support
 
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
new file mode 100644
index 0000000..0d26f50
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -0,0 +1,78 @@
+/*
+ * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/of_platform.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+#include <mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/regs-serial.h>
+
+#include "common.h"
+
+/*
+ * The following lookup table is used to override device names when devices
+ * are registered from device tree. This is temporarily added to enable
+ * device tree support addition for the EXYNOS5 architecture.
+ *
+ * For drivers that require platform data to be provided from the machine
+ * file, a platform data pointer can also be supplied along with the
+ * devices names. Usually, the platform data elements that cannot be parsed
+ * from the device tree by the drivers (example: function pointers) are
+ * supplied. But it should be noted that this is a temporary mechanism and
+ * at some point, the drivers should be capable of parsing all the platform
+ * data from the device tree.
+ */
+static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
+				"exynos4210-uart.0", NULL),
+	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
+				"exynos4210-uart.1", NULL),
+	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
+				"exynos4210-uart.2", NULL),
+	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
+				"exynos4210-uart.3", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL),
+	{},
+};
+
+static void __init exynos5250_dt_map_io(void)
+{
+	exynos_init_io(NULL, 0);
+	s3c24xx_init_clocks(24000000);
+}
+
+static void __init exynos5250_dt_machine_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table,
+				exynos5250_auxdata_lookup, NULL);
+}
+
+static char const *exynos5250_dt_compat[] __initdata = {
+	"samsung,exynos5250",
+	NULL
+};
+
+DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
+	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+	.init_irq	= exynos5_init_irq,
+	.map_io		= exynos5250_dt_map_io,
+	.handle_irq	= gic_handle_irq,
+	.init_machine	= exynos5250_dt_machine_init,
+	.timer		= &exynos4_timer,
+	.dt_compat	= exynos5250_dt_compat,
+	.restart        = exynos5_restart,
+MACHINE_END
-- 
1.7.4.4

[PATCH v2 10/11] ARM: dts: add initial dts file for EXYNOS5250, SMDK5250

[Kukjin Kim]

This patch adds initial dts file for EXYNOS5250 SoC. This dts
file is including the SoC specific devices and properties. And
adds the dts file for SMDK5250 board which uses the EXYNOS5250
dts file. Its board specific properites will be added later.

Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   26 ++
 arch/arm/boot/dts/exynos5250.dtsi         |  413 +++++++++++++++++++++++++++++
 2 files changed, 439 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos5250-smdk5250.dts
 create mode 100644 arch/arm/boot/dts/exynos5250.dtsi

diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
new file mode 100644
index 0000000..491539a
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -0,0 +1,26 @@
+/*
+ * SAMSUNG SMDK5250 board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+
+/ {
+	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
+	compatible = "samsung,smdk5250", "samsung,exynos5250";
+
+	memory {
+		reg = <0x40000000 0x80000000>;
+	};
+
+	chosen {
+		bootargs = "root=/dev/ram0 rw ramdisk=8192 rootfstype=squashfs initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
+	};
+};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
new file mode 100644
index 0000000..3e70608
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -0,0 +1,413 @@
+/*
+ * SAMSUNG EXYNOS5250 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
+ * EXYNOS5250 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
+ * additional nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "samsung,exynos5250";
+	interrupt-parent = <&gic>;
+
+	gic:interrupt-controller at 10490000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+	};
+
+	watchdog at 101D0000 {
+		compatible = "samsung,s3c2410-wdt";
+		reg = <0x101D0000 0x100>;
+		interrupts = <0 42 0>;
+	};
+
+	rtc at 101E0000 {
+		compatible = "samsung,s3c6410-rtc";
+		reg = <0x101E0000 0x100>;
+		interrupts = <0 43 0>, <0 44 0>;
+	};
+
+	sdhci at 12200000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12200000 0x100>;
+		interrupts = <0 75 0>;
+	};
+
+	sdhci at 12210000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12210000 0x100>;
+		interrupts = <0 76 0>;
+	};
+
+	sdhci at 12220000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12220000 0x100>;
+		interrupts = <0 77 0>;
+	};
+
+	sdhci at 12230000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12230000 0x100>;
+		interrupts = <0 78 0>;
+	};
+
+	serial at 12C00000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C00000 0x100>;
+		interrupts = <0 51 0>;
+	};
+
+	serial at 12C10000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C10000 0x100>;
+		interrupts = <0 52 0>;
+	};
+
+	serial at 12C20000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C20000 0x100>;
+		interrupts = <0 53 0>;
+	};
+
+	serial at 12C30000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C30000 0x100>;
+		interrupts = <0 54 0>;
+	};
+
+	i2c at 12C60000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C60000 0x100>;
+		interrupts = <0 56 0>;
+	};
+
+	i2c at 12C70000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C70000 0x100>;
+		interrupts = <0 57 0>;
+	};
+
+	i2c at 12C80000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C80000 0x100>;
+		interrupts = <0 58 0>;
+	};
+
+	i2c at 12C90000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C90000 0x100>;
+		interrupts = <0 59 0>;
+	};
+
+	i2c at 12CA0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CA0000 0x100>;
+		interrupts = <0 60 0>;
+	};
+
+	i2c at 12CB0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CB0000 0x100>;
+		interrupts = <0 61 0>;
+	};
+
+	i2c at 12CC0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CC0000 0x100>;
+		interrupts = <0 62 0>;
+	};
+
+	i2c at 12CD0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CD0000 0x100>;
+		interrupts = <0 63 0>;
+	};
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		pdma0: pdma at 121A0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x121A0000 0x1000>;
+			interrupts = <0 34 0>;
+		};
+
+		pdma1: pdma at 121B0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x121B0000 0x1000>;
+			interrupts = <0 35 0>;
+		};
+
+		mdma0: pdma at 10800000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x10800000 0x1000>;
+			interrupts = <0 33 0>;
+		};
+
+		mdma1: pdma at 11C10000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x11C10000 0x1000>;
+			interrupts = <0 124 0>;
+		};
+	};
+
+	gpio-controllers {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		gpio-controller;
+		ranges;
+
+		gpa0: gpio-controller at 11400000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400000 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpa1: gpio-controller at 11400020 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400020 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpa2: gpio-controller at 11400040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb0: gpio-controller at 11400060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb1: gpio-controller at 11400080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb2: gpio-controller at 114000A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb3: gpio-controller at 114000C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc0: gpio-controller at 114000E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc1: gpio-controller at 11400100 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400100 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc2: gpio-controller at 11400120 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400120 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc3: gpio-controller at 11400140 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400140 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpd0: gpio-controller at 11400160 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400160 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpd1: gpio-controller at 11400180 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400180 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy0: gpio-controller at 114001A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy1: gpio-controller at 114001C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy2: gpio-controller at 114001E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy3: gpio-controller at 11400200 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400200 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy4: gpio-controller at 11400220 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400220 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy5: gpio-controller at 11400240 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400240 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy6: gpio-controller at 11400260 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400260 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx0: gpio-controller at 11400C00 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400C00 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx1: gpio-controller at 11400C20 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400C20 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx2: gpio-controller at 11400C40 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400C40 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx3: gpio-controller at 11400C60 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400C60 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpe0: gpio-controller at 13400000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400000 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpe1: gpio-controller at 13400020 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400020 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf0: gpio-controller at 13400040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf1: gpio-controller at 13400060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpg0: gpio-controller at 13400080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpg1: gpio-controller at 134000A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x134000A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpg2: gpio-controller at 134000C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x134000C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gph0: gpio-controller at 134000E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x134000E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gph1: gpio-controller at 13400100 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400100 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv0: gpio-controller at 10D10000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10000 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv1: gpio-controller at 10D10020 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10020 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv2: gpio-controller at 10D10040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv3: gpio-controller at 10D10060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv4: gpio-controller at 10D10080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpz: gpio-controller at 03860000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x03860000 0x20>;
+			#gpio-cells = <4>;
+		};
+	};
+};
-- 
1.7.4.4

[PATCH v2 11/11] ARM: EXYNOS: temporary add board file for SMDK5250

[Kukjin Kim]

Basically, EXYNOS5 (ARCH_EXYNOS5) is supported with Device Tree.
So the non-dt board, mach-smdk5250.c file is added temporary for
testing.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/Makefile        |    2 +
 arch/arm/mach-exynos/mach-smdk5250.c |   92 ++++++++++++++++++++++++++++++++++
 2 files changed, 94 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-exynos/mach-smdk5250.c

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 29967ef..32676af 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -44,6 +44,8 @@ obj-$(CONFIG_MACH_SMDK4412)		+= mach-smdk4x12.o
 obj-$(CONFIG_MACH_EXYNOS4_DT)		+= mach-exynos4-dt.o
 obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
 
+obj-$(CONFIG_MACH_SMDK5250)		+= mach-smdk5250.o
+
 # device support
 
 obj-y					+= dev-uart.o
diff --git a/arch/arm/mach-exynos/mach-smdk5250.c b/arch/arm/mach-exynos/mach-smdk5250.c
new file mode 100644
index 0000000..b6e506d
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-smdk5250.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/regs-serial.h>
+
+#include <mach/map.h>
+
+#include "common.h"
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDK5250_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK5250_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define SMDK5250_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdk5250_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport		= 0,
+		.flags		= 0,
+		.ucon		= SMDK5250_UCON_DEFAULT,
+		.ulcon		= SMDK5250_ULCON_DEFAULT,
+		.ufcon		= SMDK5250_UFCON_DEFAULT,
+	},
+	[1] = {
+		.hwport		= 1,
+		.flags		= 0,
+		.ucon		= SMDK5250_UCON_DEFAULT,
+		.ulcon		= SMDK5250_ULCON_DEFAULT,
+		.ufcon		= SMDK5250_UFCON_DEFAULT,
+	},
+	[2] = {
+		.hwport		= 2,
+		.flags		= 0,
+		.ucon		= SMDK5250_UCON_DEFAULT,
+		.ulcon		= SMDK5250_ULCON_DEFAULT,
+		.ufcon		= SMDK5250_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport		= 3,
+		.flags		= 0,
+		.ucon		= SMDK5250_UCON_DEFAULT,
+		.ulcon		= SMDK5250_ULCON_DEFAULT,
+		.ufcon		= SMDK5250_UFCON_DEFAULT,
+	},
+};
+
+static void __init smdk5250_map_io(void)
+{
+	clk_xusbxti.rate = 24000000;
+
+	exynos_init_io(NULL, 0);
+	s3c24xx_init_clocks(clk_xusbxti.rate);
+	s3c24xx_init_uarts(smdk5250_uartcfgs, ARRAY_SIZE(smdk5250_uartcfgs));
+}
+
+static void __init smdk5250_machine_init(void)
+{
+	/* nothing here yet */
+}
+
+MACHINE_START(SMDK5250, "SMDK5250")
+	.atag_offset	= 0x100,
+	.init_irq	= exynos5_init_irq,
+	.map_io		= smdk5250_map_io,
+	.handle_irq	= gic_handle_irq,
+	.init_machine	= smdk5250_machine_init,
+	.timer		= &exynos4_timer,
+	.restart	= exynos5_restart,
+MACHINE_END
-- 
1.7.4.4

[PATCH v2 03/11] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

[Sylwester Nawrocki]

Hello,

On 02/11/2012 06:34 PM, Kukjin Kim wrote:
> This patch adds clock-exynos5.c for EXYNOS5250 now
> and that can be used for other EXYNOS5 SoCs later.
>
> Signed-off-by: Kukjin Kim<kgene.kim@samsung.com>
> ---
>   arch/arm/mach-exynos/clock-exynos5.c           | 1252 ++++++++++++++++++++++++
>   arch/arm/mach-exynos/include/mach/regs-clock.h |   62 ++
>   arch/arm/plat-s5p/clock.c                      |   36 +
>   arch/arm/plat-samsung/include/plat/s5p-clock.h |    6 +
>   4 files changed, 1356 insertions(+), 0 deletions(-)
>   create mode 100644 arch/arm/mach-exynos/clock-exynos5.c
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
> new file mode 100644
> index 0000000..9d2e7f0
> --- /dev/null
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -0,0 +1,1252 @@
> +/*
> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * Clock support for EXYNOS5 SoCs
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
...
> +static struct clk exynos5_init_clocks_off[] = {
> +	{
> +		.name		= "timers",
> +		.parent		=&exynos5_clk_aclk_66.clk,
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  24),
> +	}, {
> +		.name		= "rtc",
> +		.parent		=&exynos5_clk_aclk_66.clk,
> +		.enable		= exynos5_clk_ip_peris_ctrl,
> +		.ctrlbit	= (1<<  20),
> +	}, {
> +		.name		= "hsmmc",
> +		.devname	= "s3c-sdhci.0",
> +		.parent		=&exynos5_clk_aclk_200.clk,
> +		.enable		= exynos5_clk_ip_fsys_ctrl,
> +		.ctrlbit	= (1<<  12),
> +	}, {
> +		.name		= "hsmmc",
> +		.devname	= "s3c-sdhci.1",
> +		.parent		=&exynos5_clk_aclk_200.clk,
> +		.enable		= exynos5_clk_ip_fsys_ctrl,
> +		.ctrlbit	= (1<<  13),
> +	}, {
> +		.name		= "hsmmc",
> +		.devname	= "s3c-sdhci.2",
> +		.parent		=&exynos5_clk_aclk_200.clk,
> +		.enable		= exynos5_clk_ip_fsys_ctrl,
> +		.ctrlbit	= (1<<  14),
> +	}, {
> +		.name		= "hsmmc",
> +		.devname	= "s3c-sdhci.3",
> +		.parent		=&exynos5_clk_aclk_200.clk,
> +		.enable		= exynos5_clk_ip_fsys_ctrl,
> +		.ctrlbit	= (1<<  15),
> +	}, {
> +		.name		= "dwmci",
> +		.parent		=&exynos5_clk_aclk_200.clk,
> +		.enable		= exynos5_clk_ip_fsys_ctrl,
> +		.ctrlbit	= (1<<  16),
> +	}, {
> +		.name		= "sata",
> +		.devname	= "ahci",
> +		.enable		= exynos5_clk_ip_fsys_ctrl,
> +		.ctrlbit	= (1<<  6),
> +	}, {
> +		.name		= "sata_phy",
> +		.enable		= exynos5_clk_ip_fsys_ctrl,
> +		.ctrlbit	= (1<<  24),
> +	}, {
> +		.name		= "sata_phy_i2c",
> +		.enable		= exynos5_clk_ip_fsys_ctrl,
> +		.ctrlbit	= (1<<  25),
> +	}, {
> +		.name		= "mfc",
> +		.devname	= "s5p-mfc",
> +		.enable		= exynos5_clk_ip_mfc_ctrl,
> +		.ctrlbit	= (1<<  0),
> +	}, {
> +		.name		= "hdmi",
> +		.devname	= "exynos4-hdmi",
> +		.enable		= exynos5_clk_ip_disp1_ctrl,
> +		.ctrlbit	= (1<<  6),
> +	}, {
> +		.name		= "mixer",
> +		.devname	= "s5p-mixer",
> +		.enable		= exynos5_clk_ip_disp1_ctrl,
> +		.ctrlbit	= (1<<  5),
> +	}, {
> +		.name		= "jpeg",
> +		.enable		= exynos5_clk_ip_gen_ctrl,
> +		.ctrlbit	= (1<<  2),
> +	}, {
> +		.name		= "dsim0",
> +		.enable		= exynos5_clk_ip_disp1_ctrl,
> +		.ctrlbit	= (1<<  3),
> +	}, {
> +		.name		= "iis",
> +		.devname	= "samsung-i2s.1",
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  20),
> +	}, {
> +		.name		= "iis",
> +		.devname	= "samsung-i2s.2",
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  21),
> +	}, {
> +		.name		= "pcm",
> +		.devname	= "samsung-pcm.1",
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  22),
> +	}, {
> +		.name		= "pcm",
> +		.devname	= "samsung-pcm.2",
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  23),
> +	}, {
> +		.name		= "spdif",
> +		.devname	= "samsung-spdif",
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  26),
> +	}, {
> +		.name		= "ac97",
> +		.devname	= "samsung-ac97",
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  27),
> +	}, {
> +		.name		= "usbhost",
> +		.enable		= exynos5_clk_ip_fsys_ctrl ,
> +		.ctrlbit	= (1<<  18),
> +	}, {
> +		.name		= "usbotg",
> +		.enable		= exynos5_clk_ip_fsys_ctrl,
> +		.ctrlbit	= (1<<  7),
> +	}, {
> +		.name		= "gps",
> +		.enable		= exynos5_clk_ip_gps_ctrl,
> +		.ctrlbit	= ((1<<  3) | (1<<  2) | (1<<  0)),
> +	}, {
> +		.name		= "nfcon",
> +		.enable		= exynos5_clk_ip_fsys_ctrl,
> +		.ctrlbit	= (1<<  22),
> +	}, {
> +		.name		= "iop",
> +		.enable		= exynos5_clk_ip_fsys_ctrl,
> +		.ctrlbit	= ((1<<  30) | (1<<  26) | (1<<  23)),
> +	}, {
> +		.name		= "core_iop",
> +		.enable		= exynos5_clk_ip_core_ctrl,
> +		.ctrlbit	= ((1<<  21) | (1<<  3)),
> +	}, {
> +		.name		= "mcu_iop",
> +		.enable		= exynos5_clk_ip_fsys_ctrl,
> +		.ctrlbit	= (1<<  0),
> +	}, {
> +		.name		= "i2c",
> +		.devname	= "s3c2440-i2c.0",
> +		.parent		=&exynos5_clk_aclk_66.clk,
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  6),
> +	}, {
> +		.name		= "i2c",
> +		.devname	= "s3c2440-i2c.1",
> +		.parent		=&exynos5_clk_aclk_66.clk,
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  7),
> +	}, {
> +		.name		= "i2c",
> +		.devname	= "s3c2440-i2c.2",
> +		.parent		=&exynos5_clk_aclk_66.clk,
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  8),
> +	}, {
> +		.name		= "i2c",
> +		.devname	= "s3c2440-i2c.3",
> +		.parent		=&exynos5_clk_aclk_66.clk,
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  9),
> +	}, {
> +		.name		= "i2c",
> +		.devname	= "s3c2440-i2c.4",
> +		.parent		=&exynos5_clk_aclk_66.clk,
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  10),
> +	}, {
> +		.name		= "i2c",
> +		.devname	= "s3c2440-i2c.5",
> +		.parent		=&exynos5_clk_aclk_66.clk,
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  11),
> +	}, {
> +		.name		= "i2c",
> +		.devname	= "s3c2440-i2c.6",
> +		.parent		=&exynos5_clk_aclk_66.clk,
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  12),
> +	}, {
> +		.name		= "i2c",
> +		.devname	= "s3c2440-i2c.7",
> +		.parent		=&exynos5_clk_aclk_66.clk,
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  13),
> +	}, {
> +		.name		= "i2c",
> +		.devname	= "s3c2440-hdmiphy-i2c",
> +		.parent		=&exynos5_clk_aclk_66.clk,
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  14),
> +	}
> +};
> +
> +static struct clk exynos5_init_clocks_on[] = {
> +	{
> +		.name		= "uart",
> +		.devname	= "s5pv210-uart.0",
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  0),
> +	}, {
> +		.name		= "uart",
> +		.devname	= "s5pv210-uart.1",
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  1),
> +	}, {
> +		.name		= "uart",
> +		.devname	= "s5pv210-uart.2",
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  2),
> +	}, {
> +		.name		= "uart",
> +		.devname	= "s5pv210-uart.3",
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  3),
> +	}, {
> +		.name		= "uart",
> +		.devname	= "s5pv210-uart.4",
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  4),
> +	}, {
> +		.name		= "uart",
> +		.devname	= "s5pv210-uart.5",
> +		.enable		= exynos5_clk_ip_peric_ctrl,
> +		.ctrlbit	= (1<<  5),
> +	}
> +};
> +
> +static struct clk exynos5_clk_pdma0 = {
> +	.name		= "dma",
> +	.devname	= "dma-pl330.0",
> +	.enable		= exynos5_clk_ip_gen_ctrl,
> +	.ctrlbit	= (1<<  4),
> +};
> +
> +static struct clk exynos5_clk_pdma1 = {
> +	.name		= "dma",
> +	.devname	= "dma-pl330.1",
> +	.enable		= exynos5_clk_ip_fsys_ctrl,
> +	.ctrlbit	= (1<<  1),
> +};
> +
> +static struct clk exynos5_clk_pdma2 = {
> +	.name		= "dma",
> +	.devname	= "dma-pl330.2",
> +	.enable		= exynos5_clk_ip_fsys_ctrl,
> +	.ctrlbit	= (1<<  1),
> +};
> +
> +struct clk *exynos5_clkset_group_list[] = {
> +	[0] =&clk_ext_xtal_mux,
> +	[1] = NULL,
> +	[2] =&exynos5_clk_sclk_hdmi24m,
> +	[3] =&exynos5_clk_sclk_dptxphy,
> +	[4] =&exynos5_clk_sclk_usbphy,
> +	[5] =&exynos5_clk_sclk_hdmiphy,
> +	[6] =&exynos5_clk_mout_mpll_user.clk,
> +	[7] =&exynos5_clk_mout_epll.clk,
> +	[8] =&exynos5_clk_sclk_vpll.clk,
> +	[9] =&exynos5_clk_mout_cpll.clk,
> +};
> +
> +struct clksrc_sources exynos5_clkset_group = {
> +	.sources	= exynos5_clkset_group_list,
> +	.nr_sources	= ARRAY_SIZE(exynos5_clkset_group_list),
> +};
> +
> +/* Possible clock sources for aclk_266_gscl_sub Mux */
> +static struct clk *clk_src_gscl_266_list[] = {
> +	[0] =&clk_ext_xtal_mux,
> +	[1] =&exynos5_clk_aclk_266.clk,
> +};
> +
> +static struct clksrc_sources clk_src_gscl_266 = {
> +	.sources	= clk_src_gscl_266_list,
> +	.nr_sources	= ARRAY_SIZE(clk_src_gscl_266_list),
> +};
> +
> +static struct clksrc_clk exynos5_clk_dout_mmc0 = {
> +	.clk		= {
> +		.name		= "dout_mmc0",
> +	},
> +	.sources =&exynos5_clkset_group,
> +	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
> +	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_dout_mmc1 = {
> +	.clk		= {
> +		.name		= "dout_mmc1",
> +	},
> +	.sources =&exynos5_clkset_group,
> +	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
> +	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_dout_mmc2 = {
> +	.clk		= {
> +		.name		= "dout_mmc2",
> +	},
> +	.sources =&exynos5_clkset_group,
> +	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
> +	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_dout_mmc3 = {
> +	.clk		= {
> +		.name		= "dout_mmc3",
> +	},
> +	.sources =&exynos5_clkset_group,
> +	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
> +	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_dout_mmc4 = {
> +	.clk		= {
> +		.name		= "dout_mmc4",
> +	},
> +	.sources =&exynos5_clkset_group,
> +	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
> +	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_sclk_uart0 = {
> +	.clk	= {
> +		.name		= "uclk1",
> +		.devname	= "exynos4210-uart.0",
> +		.enable		= exynos5_clksrc_mask_peric0_ctrl,
> +		.ctrlbit	= (1<<  0),
> +	},
> +	.sources =&exynos5_clkset_group,
> +	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
> +	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_sclk_uart1 = {
> +	.clk	= {
> +		.name		= "uclk1",
> +		.devname	= "exynos4210-uart.1",
> +		.enable		= exynos5_clksrc_mask_peric0_ctrl,
> +		.ctrlbit	= (1<<  4),
> +	},
> +	.sources =&exynos5_clkset_group,
> +	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
> +	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_sclk_uart2 = {
> +	.clk	= {
> +		.name		= "uclk1",
> +		.devname	= "exynos4210-uart.2",
> +		.enable		= exynos5_clksrc_mask_peric0_ctrl,
> +		.ctrlbit	= (1<<  8),
> +	},
> +	.sources =&exynos5_clkset_group,
> +	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
> +	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_sclk_uart3 = {
> +	.clk	= {
> +		.name		= "uclk1",
> +		.devname	= "exynos4210-uart.3",
> +		.enable		= exynos5_clksrc_mask_peric0_ctrl,
> +		.ctrlbit	= (1<<  12),
> +	},
> +	.sources =&exynos5_clkset_group,
> +	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
> +	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
> +	.clk	= {
> +		.name		= "sclk_mmc",
> +		.devname	= "s3c-sdhci.0",
> +		.parent		=&exynos5_clk_dout_mmc0.clk,
> +		.enable		= exynos5_clksrc_mask_fsys_ctrl,
> +		.ctrlbit	= (1<<  0),
> +	},
> +	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
> +	.clk	= {
> +		.name		= "sclk_mmc",
> +		.devname	= "s3c-sdhci.1",
> +		.parent         =&exynos5_clk_dout_mmc1.clk,
> +		.enable		= exynos5_clksrc_mask_fsys_ctrl,
> +		.ctrlbit	= (1<<  4),
> +	},
> +	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
> +	.clk	= {
> +		.name		= "sclk_mmc",
> +		.devname	= "s3c-sdhci.2",
> +		.parent         =&exynos5_clk_dout_mmc2.clk,
> +		.enable		= exynos5_clksrc_mask_fsys_ctrl,
> +		.ctrlbit	= (1<<  8),
> +	},
> +};
> +
> +static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
> +	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
> +	.clk	= {
> +		.name		= "sclk_mmc",
> +		.devname	= "s3c-sdhci.3",
> +		.parent         =&exynos5_clk_dout_mmc3.clk,
> +		.enable		= exynos5_clksrc_mask_fsys_ctrl,
> +		.ctrlbit	= (1<<  12),
> +	},
> +	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
> +};
> +
> +static struct clksrc_clk exynos5_clksrcs[] = {


How about eliminating this array by defining each clock separately and
creating an array of struct clk_lookup out of it ? This would be much
more straightforward and would ease consolidation of the clocks among
various Samsung platforms.

Same goes for exynos5_init_clocks_off[] and exynos5_init_clocks_on[]
arrays.

> +	{
> +		.clk	= {
> +			.name		= "sclk_dwmci",
> +			.parent         =&exynos5_clk_dout_mmc4.clk,
> +			.enable		= exynos5_clksrc_mask_fsys_ctrl,
> +			.ctrlbit	= (1<<  16),
> +		},
> +		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
> +	}, {
> +		.clk	= {
> +			.name		= "sclk_fimd",
> +			.devname	= "s3cfb.1",

I thought adding the devname field was just a temporary solution to
enable DT platforms. Could we please not copy this pattern to the new
platforms ? Device names are normally used with the CLKDEV_INIT() macro.

> +			.enable		= exynos5_clksrc_mask_disp1_0_ctrl,
> +			.ctrlbit	= (1<<  0),
> +		},
> +		.sources =&exynos5_clkset_group,
> +		.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
> +		.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
> +	}, {
> +		.clk	= {
> +			.name		= "aclk_266_gscl",
> +		},
> +		.sources =&clk_src_gscl_266,
> +		.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
> +	}, {
> +		.clk	= {
> +			.name		= "sclk_g3d",
> +			.devname	= "mali-t604.0",
> +			.enable		= exynos5_clk_block_ctrl,
> +			.ctrlbit	= (1<<  1),
> +		},
> +		.sources =&exynos5_clkset_aclk,
> +		.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
> +		.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
> +	}, {
> +		.clk	= {
> +			.name		= "sclk_gscl_wrap",
> +			.devname	= "s5p-mipi-csis.0",
> +			.enable		= exynos5_clksrc_mask_gscl_ctrl,
> +			.ctrlbit	= (1<<  24),
> +		},
> +		.sources =&exynos5_clkset_group,
> +		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
> +		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
> +	}, {
> +		.clk	= {
> +			.name		= "sclk_gscl_wrap",
> +			.devname	= "s5p-mipi-csis.1",
> +			.enable		= exynos5_clksrc_mask_gscl_ctrl,
> +			.ctrlbit	= (1<<  28),
> +		},
> +		.sources =&exynos5_clkset_group,
> +		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
> +		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
> +	}, {
> +		.clk	= {
> +			.name		= "sclk_cam0",
> +			.enable		= exynos5_clksrc_mask_gscl_ctrl,
> +			.ctrlbit	= (1<<  16),
> +		},
> +		.sources =&exynos5_clkset_group,
> +		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
> +		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
> +	}, {
> +		.clk	= {
> +			.name		= "sclk_cam1",
> +			.enable		= exynos5_clksrc_mask_gscl_ctrl,
> +			.ctrlbit	= (1<<  20),
> +		},
> +		.sources =&exynos5_clkset_group,
> +		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
> +		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
> +	}, {
> +		.clk	= {
> +			.name		= "sclk_jpeg",
> +			.parent		=&exynos5_clk_mout_cpll.clk,
> +		},
> +		.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
> +	},
> +};
> +
> +/* Clock initialization code */
> +static struct clksrc_clk *exynos5_sysclks[] = {
> +	&exynos5_clk_mout_apll,
> +	&exynos5_clk_sclk_apll,
> +	&exynos5_clk_mout_bpll,
> +	&exynos5_clk_mout_bpll_user,
> +	&exynos5_clk_mout_cpll,
> +	&exynos5_clk_mout_epll,
> +	&exynos5_clk_mout_mpll,
> +	&exynos5_clk_mout_mpll_user,
> +	&exynos5_clk_vpllsrc,
> +	&exynos5_clk_sclk_vpll,
> +	&exynos5_clk_mout_cpu,
> +	&exynos5_clk_dout_armclk,
> +	&exynos5_clk_dout_arm2clk,
> +	&exynos5_clk_cdrex,
> +	&exynos5_clk_aclk_400,
> +	&exynos5_clk_aclk_333,
> +	&exynos5_clk_aclk_266,
> +	&exynos5_clk_aclk_200,
> +	&exynos5_clk_aclk_166,
> +	&exynos5_clk_aclk_66_pre,
> +	&exynos5_clk_aclk_66,
> +	&exynos5_clk_dout_mmc0,
> +	&exynos5_clk_dout_mmc1,
> +	&exynos5_clk_dout_mmc2,
> +	&exynos5_clk_dout_mmc3,
> +	&exynos5_clk_dout_mmc4,
> +	&exynos5_clk_aclk_acp,
> +	&exynos5_clk_pclk_acp,
> +};
> +
> +static struct clk *exynos5_clk_cdev[] = {
> +	&exynos5_clk_pdma0,
> +	&exynos5_clk_pdma1,
> +	&exynos5_clk_pdma2,
> +};
> +
> +static struct clksrc_clk *exynos5_clksrc_cdev[] = {
> +	&exynos5_clk_sclk_uart0,
> +	&exynos5_clk_sclk_uart1,
> +	&exynos5_clk_sclk_uart2,
> +	&exynos5_clk_sclk_uart3,
> +	&exynos5_clk_sclk_mmc0,
> +	&exynos5_clk_sclk_mmc1,
> +	&exynos5_clk_sclk_mmc2,
> +	&exynos5_clk_sclk_mmc3,
> +};
> +
> +static struct clk_lookup exynos5_clk_lookup[] = {
> +	CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0",&exynos5_clk_sclk_uart0.clk),
> +	CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0",&exynos5_clk_sclk_uart1.clk),
> +	CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0",&exynos5_clk_sclk_uart2.clk),
> +	CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0",&exynos5_clk_sclk_uart3.clk),
> +	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2",&exynos5_clk_sclk_mmc0.clk),
> +	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2",&exynos5_clk_sclk_mmc1.clk),
> +	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2",&exynos5_clk_sclk_mmc2.clk),
> +	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2",&exynos5_clk_sclk_mmc3.clk),
> +	CLKDEV_INIT("dma-pl330.0", "apb_pclk",&exynos5_clk_pdma0),
> +	CLKDEV_INIT("dma-pl330.1", "apb_pclk",&exynos5_clk_pdma1),
> +	CLKDEV_INIT("dma-pl330.2", "apb_pclk",&exynos5_clk_pdma2),

How about defining all data for the clkdev like this, i.e. removing all
'devname' occurences above ?

> +};
> +
> +static unsigned long exynos5_epll_get_rate(struct clk *clk)
> +{
> +	return clk->rate;
> +}
> +
> +static struct clk *exynos5_clks[] __initdata = {
> +	&exynos5_clk_sclk_hdmi27m,
> +	&exynos5_clk_sclk_hdmiphy,
> +	&clk_fout_bpll,
> +	&clk_fout_cpll,
> +	&exynos5_clk_armclk,
> +};
> +
...
> +void __init_or_cpufreq exynos5_setup_clocks(void)
> +{
> +	struct clk *xtal_clk;
> +	unsigned long apll;
> +	unsigned long bpll;
> +	unsigned long cpll;
> +	unsigned long mpll;
> +	unsigned long epll;
> +	unsigned long vpll;
> +	unsigned long vpllsrc;
> +	unsigned long xtal;
> +	unsigned long armclk;
> +	unsigned long mout_cdrex;
> +	unsigned long aclk_400;
> +	unsigned long aclk_333;
> +	unsigned long aclk_266;
> +	unsigned long aclk_200;
> +	unsigned long aclk_166;
> +	unsigned long aclk_66;
> +	unsigned int ptr;
> +
> +	printk(KERN_DEBUG "%s: registering clocks\n", __func__);

pr_debug

> +
> +	xtal_clk = clk_get(NULL, "xtal");
> +	BUG_ON(IS_ERR(xtal_clk));
> +
> +	xtal = clk_get_rate(xtal_clk);
> +
> +	xtal_rate = xtal;
> +
> +	clk_put(xtal_clk);
> +
> +	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);

pr_debug

> +
> +	apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
> +	bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
> +	cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
> +	mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
> +	epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
> +			__raw_readl(EXYNOS5_EPLL_CON1));
> +
> +	vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
> +	vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
> +			__raw_readl(EXYNOS5_VPLL_CON1));
> +
> +	clk_fout_apll.ops =&exynos5_fout_apll_ops;
> +	clk_fout_bpll.rate = bpll;
> +	clk_fout_cpll.rate = cpll;
> +	clk_fout_mpll.rate = mpll;
> +	clk_fout_epll.rate = epll;
> +	clk_fout_vpll.rate = vpll;
> +
> +	printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"

pr_info

> +			"M=%ld, E=%ld V=%ld",
> +			apll, bpll, cpll, mpll, epll, vpll);
> +
> +	armclk = clk_get_rate(&exynos5_clk_armclk);
> +	mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
> +
> +	aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
> +	aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
> +	aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
> +	aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
> +	aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
> +	aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
> +
> +	printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"

pr_info

> +			"ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
> +			"ACLK166=%ld, ACLK66=%ld\n",
> +			armclk, mout_cdrex, aclk_400,
> +			aclk_333, aclk_266, aclk_200,
> +			aclk_166, aclk_66);
> +
> +
> +	clk_fout_epll.ops =&exynos5_epll_ops;
> +
> +	if (clk_set_parent(&exynos5_clk_mout_epll.clk,&clk_fout_epll))
> +		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",

pr_err

> +				clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
> +
> +	clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);

100000000UL ?

> +	clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
> +
> +	clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
> +	clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
> +
> +	for (ptr = 0; ptr<  ARRAY_SIZE(exynos5_clksrcs); ptr++)
> +		s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
> +}
> +
> +void __init exynos5_register_clocks(void)
> +{
> +	int ptr;
> +
> +	s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
> +
> +	for (ptr = 0; ptr<  ARRAY_SIZE(exynos5_sysclks); ptr++)
> +		s3c_register_clksrc(exynos5_sysclks[ptr], 1);
> +
> +	for (ptr = 0; ptr<  ARRAY_SIZE(exynos5_sclk_tv); ptr++)
> +		s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
> +
> +	for (ptr = 0; ptr<  ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
> +		s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
> +
> +	s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
> +	s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
> +
> +	s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
> +	for (ptr = 0; ptr<  ARRAY_SIZE(exynos5_clk_cdev); ptr++)
> +		s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
> +
> +	s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
> +	s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
> +	clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));

This clock registration is pretty messy right now and yet we're
copy/pasting it from one platform to the other. IMHO possibly all
clocks should be registered like the exynos5_clk_lookup array.

It would be easy to create a replacement for s3c24xx_register_clock()
function, not relying on struct clk::devname.

> +
> +	register_syscore_ops(&exynos5_clock_syscore_ops);
> +	s3c_pwmclk_init();
> +}

--

Thanks,
Sylwester

[PATCH v2 03/11] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

[Arnd Bergmann]

On Saturday 11 February 2012, Kukjin Kim wrote:
> This patch adds clock-exynos5.c for EXYNOS5250 now
> and that can be used for other EXYNOS5 SoCs later.
> 
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> ---
>  arch/arm/mach-exynos/clock-exynos5.c           | 1252 ++++++++++++++++++++++++
>  arch/arm/mach-exynos/include/mach/regs-clock.h |   62 ++
>  arch/arm/plat-s5p/clock.c                      |   36 +
>  arch/arm/plat-samsung/include/plat/s5p-clock.h |    6 +
>  4 files changed, 1356 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-exynos/clock-exynos5.c

I discussed this patch with a few people at linaro connect, I wanted to
make sure we have consensus before asking for a drastic change. What
we ended up agreeing on is that it should use the common struct clk
from Mike Turquette. You can choose whether you want to take those
patches and base yours on top or whether you want to use a copy of
that the new header file and then move exynos5 over once both series
are in arm-soc.git.

Further, moving over exynos5 but not changing exynos4 will prevent
you from building both into the same kernel. You will have to decide
what the risk is in changing exynos4 at the same time. It would
be great if we can have all exynos use the common struct clk in 3.4,
but I'm also happy if we just get exynos5 to do it that way from the
beginning and move exynos4 over in 3.5 after you have had a chance
to make sure everything still works.

	Arnd

[PATCH v2 03/11] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

[Mark Brown]

On Sat, Feb 11, 2012 at 08:07:08PM +0000, Arnd Bergmann wrote:

> what the risk is in changing exynos4 at the same time. It would
> be great if we can have all exynos use the common struct clk in 3.4,
> but I'm also happy if we just get exynos5 to do it that way from the
> beginning and move exynos4 over in 3.5 after you have had a chance
> to make sure everything still works.

Are we likely to get the common struct clk in 3.4?  It's all been
extremely quiet on that front except for complaints about the lack of
progress.

[PATCH v2 03/11] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

[Arnd Bergmann]

On Saturday 11 February 2012, Mark Brown wrote:
> 
> On Sat, Feb 11, 2012 at 08:07:08PM +0000, Arnd Bergmann wrote:
> 
> > what the risk is in changing exynos4 at the same time. It would
> > be great if we can have all exynos use the common struct clk in 3.4,
> > but I'm also happy if we just get exynos5 to do it that way from the
> > beginning and move exynos4 over in 3.5 after you have had a chance
> > to make sure everything still works.
> 
> Are we likely to get the common struct clk in 3.4?  It's all been
> extremely quiet on that front except for complaints about the lack of
> progress.

Yes, we discussed it during the subarch maintainers meeting at Linaro
Connect last week and it looks like we're finally going forward on
this now. Maybe Grant or Mike are better at explaining the current
status regarding the clk implementation and bindings.

	Arnd

[PATCH v2 03/11] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

[Russell King - ARM Linux]

On Mon, Feb 13, 2012 at 05:47:48AM +0000, Arnd Bergmann wrote:
> On Saturday 11 February 2012, Mark Brown wrote:
> > On Sat, Feb 11, 2012 at 08:07:08PM +0000, Arnd Bergmann wrote:
> > > what the risk is in changing exynos4 at the same time. It would
> > > be great if we can have all exynos use the common struct clk in 3.4,
> > > but I'm also happy if we just get exynos5 to do it that way from the
> > > beginning and move exynos4 over in 3.5 after you have had a chance
> > > to make sure everything still works.
> > 
> > Are we likely to get the common struct clk in 3.4?  It's all been
> > extremely quiet on that front except for complaints about the lack of
> > progress.
> 
> Yes, we discussed it during the subarch maintainers meeting at Linaro
> Connect last week and it looks like we're finally going forward on
> this now. Maybe Grant or Mike are better at explaining the current
> status regarding the clk implementation and bindings.

That would be good for those who weren't there to be updated with what
was discussed.

[PATCH v2 03/11] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

[Grant Likely]

On Mon, Feb 13, 2012 at 11:04:53AM +0000, Russell King - ARM Linux wrote:
> On Mon, Feb 13, 2012 at 05:47:48AM +0000, Arnd Bergmann wrote:
> > On Saturday 11 February 2012, Mark Brown wrote:
> > > On Sat, Feb 11, 2012 at 08:07:08PM +0000, Arnd Bergmann wrote:
> > > > what the risk is in changing exynos4 at the same time. It would
> > > > be great if we can have all exynos use the common struct clk in 3.4,
> > > > but I'm also happy if we just get exynos5 to do it that way from the
> > > > beginning and move exynos4 over in 3.5 after you have had a chance
> > > > to make sure everything still works.
> > > 
> > > Are we likely to get the common struct clk in 3.4?  It's all been
> > > extremely quiet on that front except for complaints about the lack of
> > > progress.
> > 
> > Yes, we discussed it during the subarch maintainers meeting at Linaro
> > Connect last week and it looks like we're finally going forward on
> > this now. Maybe Grant or Mike are better at explaining the current
> > status regarding the clk implementation and bindings.
> 
> That would be good for those who weren't there to be updated with what
> was discussed.

The decision was essentially Mike would repost his series ASAP with a view
to getting it queued up for v3.4.  I think he is also going to get it into
linux-next so at least it gets testing, even if the ultimate decision is to
wait for v3.5.

I'm going to rebase my clk series on top of his patches rather that trying
to merge my temporary versatile-only code.  If his series isn't ready to go
in, I can still probably merge parts of the DT clock bindings anyway, but I'll
need to do some cherry picking to do so.

The rough notes can be found here:

https://blueprints.launchpad.net/linux-linaro/+spec/linaro-kernel-q112-maintainer-summit-1

g.

[PATCH v2 03/11] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

[Kukjin Kim]

Grant Likely wrote:
> 
> On Mon, Feb 13, 2012 at 11:04:53AM +0000, Russell King - ARM Linux wrote:
> > On Mon, Feb 13, 2012 at 05:47:48AM +0000, Arnd Bergmann wrote:
> > > On Saturday 11 February 2012, Mark Brown wrote:
> > > > On Sat, Feb 11, 2012 at 08:07:08PM +0000, Arnd Bergmann wrote:
> > > > > what the risk is in changing exynos4 at the same time. It would
> > > > > be great if we can have all exynos use the common struct clk in 3.4,
> > > > > but I'm also happy if we just get exynos5 to do it that way from the
> > > > > beginning and move exynos4 over in 3.5 after you have had a chance
> > > > > to make sure everything still works.
> > > >
> > > > Are we likely to get the common struct clk in 3.4?  It's all been
> > > > extremely quiet on that front except for complaints about the lack of
> > > > progress.
> > >
> > > Yes, we discussed it during the subarch maintainers meeting at Linaro
> > > Connect last week and it looks like we're finally going forward on
> > > this now. Maybe Grant or Mike are better at explaining the current
> > > status regarding the clk implementation and bindings.
> >
> > That would be good for those who weren't there to be updated with what
> > was discussed.
> 
> The decision was essentially Mike would repost his series ASAP with a view
> to getting it queued up for v3.4.  I think he is also going to get it into
> linux-next so at least it gets testing, even if the ultimate decision is to
> wait for v3.5.
> 
Hmm...so I'm not sure if some exynos5250 products use v3.4, it can use common struct clk for mass production?

If not, I think, this should be kept on v3.4 then it can be changed to use common struct clk from v3.5.

> I'm going to rebase my clk series on top of his patches rather that trying

OK, sounds good to me.

> to merge my temporary versatile-only code.  If his series isn't ready to go
> in, I can still probably merge parts of the DT clock bindings anyway, but I'll
> need to do some cherry picking to do so.
> 
If any branch is ready for it, please let me know.

> The rough notes can be found here:
> 
> https://blueprints.launchpad.net/linux-linaro/+spec/linaro-kernel-q112-maintainer-summit-1
> 
Thanks for your sharing.

OK, I and my team will follow up 'common struct clk' for exynos5250 and it will be done maybe next week. And since I need to
implement other features for exynos5250 now, firstly let me use this and test this series in linux-next in a day.

Of course, if any updates, let you know.

Ah, one more, would be better to us if arm-soc tree could provide the topic branch for 'common struct clk' working as a base.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v2 08/11] ARM: EXYNOS: add support for ARCH_EXYNOS5 and EXYNOS5250

[Kyungmin Park]

Hi,

On 2/12/12, Kukjin Kim <kgene.kim@samsung.com> wrote:
> This patch add the CONFIG_ARCH_EXYNOS5 and CONFIG_SOC_EXYNOS5250
> support for EXYNOS5250 SoC has two Cortex-A15 cores. Since actually,
> most codes in mach-exynos/ are used commonly for EXYNOS4 and EXYNOS5
> the EXYNOS5/EXYNOS5250 has been implemented in mach-exynos/.
>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> ---
>  arch/arm/Makefile                            |    1 +
>  arch/arm/mach-exynos/Kconfig                 |   13 ++
>  arch/arm/mach-exynos/Makefile                |    1 +
>  arch/arm/mach-exynos/common.c                |  165
> ++++++++++++++++++++++++--
>  arch/arm/mach-exynos/common.h                |   11 ++
>  arch/arm/mach-exynos/include/mach/map.h      |   21 +++-
>  arch/arm/mach-exynos/include/mach/regs-pmu.h |    1 +
>  arch/arm/plat-s5p/Kconfig                    |    4 +-
>  arch/arm/plat-samsung/include/plat/cpu.h     |   10 ++
>  9 files changed, 211 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 1683bfb..a826ffc 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_S5P64X0)		:= s5p64x0
>  machine-$(CONFIG_ARCH_S5PC100)		:= s5pc100
>  machine-$(CONFIG_ARCH_S5PV210)		:= s5pv210
>  machine-$(CONFIG_ARCH_EXYNOS4)		:= exynos
> +machine-$(CONFIG_ARCH_EXYNOS5)		:= exynos
>  machine-$(CONFIG_ARCH_SA1100)		:= sa1100
>  machine-$(CONFIG_ARCH_SHARK)		:= shark
>  machine-$(CONFIG_ARCH_SHMOBILE) 	:= shmobile
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index 5d602f6..14b3460 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -22,6 +22,12 @@ config ARCH_EXYNOS4
>  	help
>  	  Samsung EXYNOS4 SoCs based systems
>
> +config ARCH_EXYNOS5
> +	bool "SAMSUNG EXYNOS5"
> +	select HAVE_SMP
> +	help
> +	  Samsung EXYNOS5 (Cortex-A15) SoC based systems
This config is located at choice. It means it can't build the exynos4
and exynos5 simultaneously. I'm not sure it's acceptable for mainline.
> +
>  endchoice
>
>  comment "EXYNOS SoCs"
> @@ -53,6 +59,13 @@ config SOC_EXYNOS4412
>  	help
>  	  Enable EXYNOS4412 SoC support
>
> +config SOC_EXYNOS5250
> +	bool "SAMSUNG EXYNOS5250"
> +	default y
> +	depends on ARCH_EXYNOS5
> +	help
> +	  Enable EXYNOS5250 SoC support
> +
>  config EXYNOS4_MCT
>  	bool
>  	default y
> diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
> index f8a3770..7214092 100644
> --- a/arch/arm/mach-exynos/Makefile
> +++ b/arch/arm/mach-exynos/Makefile
> @@ -14,6 +14,7 @@ obj-				:=
>
>  obj-$(CONFIG_ARCH_EXYNOS)	+= common.o
>  obj-$(CONFIG_ARCH_EXYNOS4)	+= clock-exynos4.o
> +obj-$(CONFIG_ARCH_EXYNOS5)	+= clock-exynos5.o
Where's clock-exynos5.c file in this patch?. maybe it's another patch.
>  obj-$(CONFIG_CPU_EXYNOS4210)	+= clock-exynos4210.o
>  obj-$(CONFIG_SOC_EXYNOS4212)	+= clock-exynos4212.o
>
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 8db2627..cff7313 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -49,9 +49,12 @@
>  static const char name_exynos4210[] = "EXYNOS4210";
>  static const char name_exynos4212[] = "EXYNOS4212";
>  static const char name_exynos4412[] = "EXYNOS4412";
> +static const char name_exynos5250[] = "EXYNOS5250";
>
>  static void exynos4_map_io(void);
> +static void exynos5_map_io(void);
>  static void exynos4_init_clocks(int xtal);
> +static void exynos5_init_clocks(int xtal);
>  static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
>  static int exynos_init(void);
>
> @@ -80,6 +83,14 @@ static struct cpu_table cpu_ids[] __initdata = {
>  		.init_uarts	= exynos_init_uarts,
>  		.init		= exynos_init,
>  		.name		= name_exynos4412,
> +	}, {
> +		.idcode		= EXYNOS5250_SOC_ID,
> +		.idmask		= EXYNOS5_SOC_MASK,
> +		.map_io		= exynos5_map_io,
> +		.init_clocks	= exynos5_init_clocks,
> +		.init_uarts	= exynos_init_uarts,
> +		.init		= exynos_init,
> +		.name		= name_exynos5250,
>  	},
>  };
>
> @@ -88,10 +99,14 @@ static struct cpu_table cpu_ids[] __initdata = {
>  static struct map_desc exynos_iodesc[] __initdata = {
>  	{
>  		.virtual	= (unsigned long)S5P_VA_CHIPID,
> -		.pfn		= __phys_to_pfn(EXYNOS4_PA_CHIPID),
> +		.pfn		= __phys_to_pfn(EXYNOS_PA_CHIPID),
>  		.length		= SZ_4K,
>  		.type		= MT_DEVICE,
> -	}, {
> +	},
> +};
> +
> +static struct map_desc exynos4_iodesc[] __initdata = {
> +	{
>  		.virtual	= (unsigned long)S3C_VA_SYS,
>  		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSCON),
>  		.length		= SZ_64K,
> @@ -141,11 +156,7 @@ static struct map_desc exynos_iodesc[] __initdata = {
>  		.pfn		= __phys_to_pfn(EXYNOS4_PA_UART),
>  		.length		= SZ_512K,
>  		.type		= MT_DEVICE,
> -	},
> -};
> -
> -static struct map_desc exynos4_iodesc[] __initdata = {
> -	{
> +	}, {
>  		.virtual	= (unsigned long)S5P_VA_CMU,
>  		.pfn		= __phys_to_pfn(EXYNOS4_PA_CMU),
>  		.length		= SZ_128K,
> @@ -206,6 +217,70 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
>  	},
>  };
>
> +static struct map_desc exynos5_iodesc[] __initdata = {
> +	{
> +		.virtual	= (unsigned long)S3C_VA_SYS,
> +		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSCON),
> +		.length		= SZ_64K,
> +		.type		= MT_DEVICE,
> +	}, {
> +		.virtual	= (unsigned long)S3C_VA_TIMER,
> +		.pfn		= __phys_to_pfn(EXYNOS5_PA_TIMER),
> +		.length		= SZ_16K,
> +		.type		= MT_DEVICE,
> +	}, {
> +		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
> +		.pfn		= __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE,
> +	}, {
> +		.virtual	= (unsigned long)S5P_VA_SROMC,
> +		.pfn		= __phys_to_pfn(EXYNOS5_PA_SROMC),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE,
> +	}, {
> +		.virtual	= (unsigned long)S5P_VA_SYSTIMER,
> +		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE,
> +	}, {
> +		.virtual	= (unsigned long)S5P_VA_SYSRAM,
> +		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSRAM),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE,
> +	}, {
> +		.virtual	= (unsigned long)S5P_VA_CMU,
> +		.pfn		= __phys_to_pfn(EXYNOS5_PA_CMU),
> +		.length		= 144 * SZ_1K,
> +		.type		= MT_DEVICE,
> +	}, {
> +		.virtual	= (unsigned long)S5P_VA_PMU,
> +		.pfn		= __phys_to_pfn(EXYNOS5_PA_PMU),
> +		.length		= SZ_64K,
> +		.type		= MT_DEVICE,
> +	}, {
> +		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,
> +		.pfn		= __phys_to_pfn(EXYNOS5_PA_COMBINER),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE,
> +	}, {
> +		.virtual	= (unsigned long)S3C_VA_UART,
> +		.pfn		= __phys_to_pfn(EXYNOS5_PA_UART),
> +		.length		= SZ_512K,
> +		.type		= MT_DEVICE,
> +	}, {
> +		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
> +		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
> +		.length		= SZ_64K,
> +		.type		= MT_DEVICE,
> +	}, {
> +		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
> +		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
> +		.length		= SZ_64K,
> +		.type		= MT_DEVICE,
> +	},
> +};
> +
>  static void exynos_idle(void)
>  {
>  	if (!need_resched())
> @@ -219,6 +294,11 @@ void exynos4_restart(char mode, const char *cmd)
>  	__raw_writel(0x1, S5P_SWRESET);
>  }
>
> +void exynos5_restart(char mode, const char *cmd)
> +{
> +	__raw_writel(0x1, EXYNOS_SWRESET);
> +}
Why new restart is required? it's same S5P_SWRESET and EXYNOS_SWRESET.
see below.
> +
>  /*
>   * exynos_map_io
>   *
> @@ -269,6 +349,16 @@ static void __init exynos4_map_io(void)
>  	s5p_hdmi_setname("exynos4-hdmi");
>  }
>
> +static void __init exynos5_map_io(void)
> +{
> +	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
> +
> +	/* The I2C bus controllers are directly compatible with s3c2440 */
> +	s3c_i2c0_setname("s3c2440-i2c");
> +	s3c_i2c1_setname("s3c2440-i2c");
> +	s3c_i2c2_setname("s3c2440-i2c");
> +}
> +
>  static void __init exynos4_init_clocks(int xtal)
>  {
>  	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
> @@ -285,6 +375,17 @@ static void __init exynos4_init_clocks(int xtal)
>  	exynos4_setup_clocks();
>  }
>
> +static void __init exynos5_init_clocks(int xtal)
> +{
> +	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
> +
> +	s3c24xx_register_baseclocks(xtal);
> +	s5p_register_clocks(xtal);
> +
> +	exynos5_register_clocks();
> +	exynos5_setup_clocks();
> +}
> +
>  #define COMBINER_ENABLE_SET	0x0
>  #define COMBINER_ENABLE_CLEAR	0x4
>  #define COMBINER_INT_STATUS	0xC
> @@ -428,24 +529,59 @@ void __init exynos4_init_irq(void)
>  	s5p_init_irq(NULL, 0);
>  }
>
> +void __init exynos5_init_irq(void)
> +{
> +	int irq;
> +
> +	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
> +
> +	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
> +		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
> +				COMBINER_IRQ(irq, 0));
> +		combiner_cascade_irq(irq, IRQ_SPI(irq));
> +	}
> +
> +	/*
> +	 * The parameters of s5p_init_irq() are for VIC init.
> +	 * Theses parameters should be NULL and 0 because EXYNOS4
> +	 * uses GIC instead of VIC.
> +	 */
> +	s5p_init_irq(NULL, 0);
> +}
> +
>  struct bus_type exynos4_subsys = {
>  	.name		= "exynos4-core",
>  	.dev_name	= "exynos4-core",
>  };
>
> +struct bus_type exynos5_subsys = {
> +	.name		= "exynos5-core",
> +	.dev_name	= "exynos5-core",
> +};
> +
>  static struct device exynos4_dev = {
>  	.bus	= &exynos4_subsys,
>  };
>
> -static int __init exynos4_core_init(void)
> +static struct device exynos5_dev = {
> +	.bus	= &exynos5_subsys,
> +};
> +
> +static int __init exynos_core_init(void)
>  {
> -	return subsys_system_register(&exynos4_subsys, NULL);
> +	if (soc_is_exynos5250())
> +		return subsys_system_register(&exynos5_subsys, NULL);
> +	else
> +		return subsys_system_register(&exynos4_subsys, NULL);
>  }
> -core_initcall(exynos4_core_init);
> +core_initcall(exynos_core_init);
>
>  #ifdef CONFIG_CACHE_L2X0
>  static int __init exynos4_l2x0_cache_init(void)
>  {
> +	if (soc_is_exynos5250())
> +		return 0;
> +
>  	/* TAG, Data Latency Control: 2cycle */
>  	__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
>
> @@ -465,7 +601,6 @@ static int __init exynos4_l2x0_cache_init(void)
>
>  	return 0;
>  }
> -
>  early_initcall(exynos4_l2x0_cache_init);
>  #endif
>
> @@ -476,7 +611,10 @@ static int __init exynos_init(void)
>  	/* set idle function */
>  	pm_idle = exynos_idle;
>
> -	return device_register(&exynos4_dev);
> +	if (soc_is_exynos5250())
> +		return device_register(&exynos5_dev);
> +	else
> +		return device_register(&exynos4_dev);
>  }
>
>  /* uart registration process */
> @@ -685,6 +823,9 @@ int __init exynos4_init_irq_eint(void)
>  {
>  	int irq;
>
> +	if (soc_is_exynos5250())
> +		return 0;
> +
>  	for (irq = 0 ; irq <= 31 ; irq++) {
>  		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
>  					 handle_level_irq);
> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
> index b32c6b5..677b546 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -16,7 +16,9 @@ extern struct sys_timer exynos4_timer;
>
>  void exynos_init_io(struct map_desc *mach_desc, int size);
>  void exynos4_init_irq(void);
> +void exynos5_init_irq(void);
>  void exynos4_restart(char mode, const char *cmd);
> +void exynos5_restart(char mode, const char *cmd);
>
>  #ifdef CONFIG_ARCH_EXYNOS4
>  void exynos4_register_clocks(void);
> @@ -27,6 +29,15 @@ void exynos4_setup_clocks(void);
>  #define exynos4_setup_clocks()
>  #endif
>
> +#ifdef CONFIG_ARCH_EXYNOS5
> +void exynos5_register_clocks(void);
> +void exynos5_setup_clocks(void);
> +
> +#else
> +#define exynos5_register_clocks()
> +#define exynos5_setup_clocks()
> +#endif
> +
>  #ifdef CONFIG_CPU_EXYNOS4210
>  void exynos4210_register_clocks(void);
>
> diff --git a/arch/arm/mach-exynos/include/mach/map.h
> b/arch/arm/mach-exynos/include/mach/map.h
> index e8a7801..ac60533 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -25,6 +25,7 @@
>
>  #define EXYNOS4_PA_SYSRAM0		0x02025000
>  #define EXYNOS4_PA_SYSRAM1		0x02020000
> +#define EXYNOS5_PA_SYSRAM		0x02020000
>
>  #define EXYNOS4_PA_FIMC0		0x11800000
>  #define EXYNOS4_PA_FIMC1		0x11810000
> @@ -44,14 +45,23 @@
>  #define EXYNOS4_PA_ONENAND		0x0C000000
>  #define EXYNOS4_PA_ONENAND_DMA		0x0C600000
>
> -#define EXYNOS4_PA_CHIPID		0x10000000
> +#define EXYNOS_PA_CHIPID		0x10000000
>
>  #define EXYNOS4_PA_SYSCON		0x10010000
> +#define EXYNOS5_PA_SYSCON		0x10050100
> +
>  #define EXYNOS4_PA_PMU			0x10020000
> +#define EXYNOS5_PA_PMU			0x10040000
> +
>  #define EXYNOS4_PA_CMU			0x10030000
> +#define EXYNOS5_PA_CMU			0x10010000
>
>  #define EXYNOS4_PA_SYSTIMER		0x10050000
> +#define EXYNOS5_PA_SYSTIMER		0x101C0000
> +
>  #define EXYNOS4_PA_WATCHDOG		0x10060000
> +#define EXYNOS5_PA_WATCHDOG		0x101D0000
> +
>  #define EXYNOS4_PA_RTC			0x10070000
>
>  #define EXYNOS4_PA_KEYPAD		0x100A0000
> @@ -59,9 +69,12 @@
>  #define EXYNOS4_PA_DMC0			0x10400000
>
>  #define EXYNOS4_PA_COMBINER		0x10440000
> +#define EXYNOS5_PA_COMBINER		0x10440000
>
>  #define EXYNOS4_PA_GIC_CPU		0x10480000
>  #define EXYNOS4_PA_GIC_DIST		0x10490000
> +#define EXYNOS5_PA_GIC_CPU		0x10480000
> +#define EXYNOS5_PA_GIC_DIST		0x10490000
>
>  #define EXYNOS4_PA_COREPERI		0x10500000
>  #define EXYNOS4_PA_TWD			0x10500600
> @@ -91,7 +104,6 @@
>  #define EXYNOS4_PA_SPI1			0x13930000
>  #define EXYNOS4_PA_SPI2			0x13940000
>
> -
>  #define EXYNOS4_PA_GPIO1		0x11400000
>  #define EXYNOS4_PA_GPIO2		0x11000000
>  #define EXYNOS4_PA_GPIO3		0x03860000
> @@ -109,6 +121,7 @@
>  #define EXYNOS4_PA_SATAPHY_CTRL		0x126B0000
>
>  #define EXYNOS4_PA_SROMC		0x12570000
> +#define EXYNOS5_PA_SROMC		0x12250000
>
>  #define EXYNOS4_PA_EHCI			0x12580000
>  #define EXYNOS4_PA_OHCI			0x12590000
> @@ -116,6 +129,7 @@
>  #define EXYNOS4_PA_MFC			0x13400000
>
>  #define EXYNOS4_PA_UART			0x13800000
> +#define EXYNOS5_PA_UART			0x12C00000
>
>  #define EXYNOS4_PA_VP			0x12C00000
>  #define EXYNOS4_PA_MIXER		0x12C10000
> @@ -124,6 +138,7 @@
>  #define EXYNOS4_PA_IIC_HDMIPHY		0x138E0000
>
>  #define EXYNOS4_PA_IIC(x)		(0x13860000 + ((x) * 0x10000))
> +#define EXYNOS5_PA_IIC(x)		(0x12C60000 + ((x) * 0x10000))
>
>  #define EXYNOS4_PA_ADC			0x13910000
>  #define EXYNOS4_PA_ADC1			0x13911000
> @@ -133,8 +148,10 @@
>  #define EXYNOS4_PA_SPDIF		0x139B0000
>
>  #define EXYNOS4_PA_TIMER		0x139D0000
> +#define EXYNOS5_PA_TIMER		0x12DD0000
>
>  #define EXYNOS4_PA_SDRAM		0x40000000
> +#define EXYNOS5_PA_SDRAM		0x40000000
>
>  /* Compatibiltiy Defines */
>
> diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h
> b/arch/arm/mach-exynos/include/mach/regs-pmu.h
> index 4fff8e9..4c53f38 100644
> --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
> +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
> @@ -31,6 +31,7 @@
>  #define S5P_USE_STANDBYWFE_ISP_ARM		(1 << 26)
>
>  #define S5P_SWRESET				S5P_PMUREG(0x0400)
> +#define EXYNOS_SWRESET				S5P_PMUREG(0x0400)
Please use just one.

Thank you,
Kyungmin Park
>
>  #define S5P_WAKEUP_STAT				S5P_PMUREG(0x0600)
>  #define S5P_EINT_WAKEUP_MASK			S5P_PMUREG(0x0604)
> diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
> index 10e235cc7..88795ea 100644
> --- a/arch/arm/plat-s5p/Kconfig
> +++ b/arch/arm/plat-s5p/Kconfig
> @@ -9,8 +9,8 @@ config PLAT_S5P
>  	bool
>  	depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
>  	default y
> -	select ARM_VIC if !ARCH_EXYNOS4
> -	select ARM_GIC if ARCH_EXYNOS4
> +	select ARM_VIC if !ARCH_EXYNOS
> +	select ARM_GIC if ARCH_EXYNOS
>  	select GIC_NON_BANKED if ARCH_EXYNOS4
>  	select NO_IOPORT
>  	select ARCH_REQUIRE_GPIOLIB
> diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
> b/arch/arm/plat-samsung/include/plat/cpu.h
> index 73cb3cf..787ceac 100644
> --- a/arch/arm/plat-samsung/include/plat/cpu.h
> +++ b/arch/arm/plat-samsung/include/plat/cpu.h
> @@ -42,6 +42,9 @@ extern unsigned long samsung_cpu_id;
>  #define EXYNOS4412_CPU_ID	0xE4412200
>  #define EXYNOS4_CPU_MASK	0xFFFE0000
>
> +#define EXYNOS5250_SOC_ID	0x43520000
> +#define EXYNOS5_SOC_MASK	0xFFFFF000
> +
>  #define IS_SAMSUNG_CPU(name, id, mask)		\
>  static inline int is_samsung_##name(void)	\
>  {						\
> @@ -58,6 +61,7 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
>  IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
>  IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
>  IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
> +IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
>
>  #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
>      defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
> @@ -120,6 +124,12 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID,
> EXYNOS4_CPU_MASK)
>  #define EXYNOS4210_REV_1_0	(0x10)
>  #define EXYNOS4210_REV_1_1	(0x11)
>
> +#if defined(CONFIG_SOC_EXYNOS5250)
> +# define soc_is_exynos5250()	is_samsung_exynos5250()
> +#else
> +# define soc_is_exynos5250()	0
> +#endif
> +
>  #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x,
> __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
>
>  #ifndef MHZ
> --
> 1.7.4.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

[PATCH v2 08/11] ARM: EXYNOS: add support for ARCH_EXYNOS5 and EXYNOS5250

[Arnd Bergmann]

On Thursday 16 February 2012, Kyungmin Park wrote:
> >
> > +config ARCH_EXYNOS5
> > +     bool "SAMSUNG EXYNOS5"
> > +     select HAVE_SMP
> > +     help
> > +       Samsung EXYNOS5 (Cortex-A15) SoC based systems
> This config is located at choice. It means it can't build the exynos4
> and exynos5 simultaneously. I'm not sure it's acceptable for mainline.

If we use the new common struct clk on exynos5 but not exynos4, it should
stay a "choice" for the time being and get turned into a nonexclusive
selection as soon as exynos4 moves over.

If exynos4 and exynos5 end up using the same struct clk in 3.4, I would
indeed ask to do this change now.

	Arnd

[PATCH v2 08/11] ARM: EXYNOS: add support for ARCH_EXYNOS5 and EXYNOS5250

[Kukjin Kim]

Arnd Bergmann wrote:
> 
> On Thursday 16 February 2012, Kyungmin Park wrote:
> > >
> > > +config ARCH_EXYNOS5
> > > +     bool "SAMSUNG EXYNOS5"
> > > +     select HAVE_SMP
> > > +     help
> > > +       Samsung EXYNOS5 (Cortex-A15) SoC based systems
> > This config is located at choice. It means it can't build the exynos4
> > and exynos5 simultaneously. I'm not sure it's acceptable for mainline.
> 
> If we use the new common struct clk on exynos5 but not exynos4, it should
> stay a "choice" for the time being and get turned into a nonexclusive
> selection as soon as exynos4 moves over.
> 
Yes, right.

> If exynos4 and exynos5 end up using the same struct clk in 3.4, I would
> indeed ask to do this change now.
> 
If possible, yes. But I'm going to move common struct clk for exynos4 and exynos5 next time.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v2 03/11] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

[Arnd Bergmann]

On Thursday 16 February 2012, Kukjin Kim wrote:
> Thanks for your sharing.
> 
> OK, I and my team will follow up 'common struct clk' for exynos5250
> and it will be done maybe next week. And since I need to
> implement other features for exynos5250 now, firstly let me use this
> and test this series in linux-next in a day.

Ok, sounds good to me.

If you like, you could also send the patches that you expect to stay
stable for inclusion into arm-soc, or send the entire series as a
preliminary branch that I will put into arm-soc now and then
replace when you are done with the remaining changes.

As we discussed last week at Linaro Connect, we will start taking
both stable and unstable branches into arm-soc now, whereas we used
to take only stable branches. Anything that is not considered stable
yet will be marked as a staging branch, e.g. staging/samsung/soc instead
of samsung/soc.

> Ah, one more, would be better to us if arm-soc tree could provide
> the topic branch for 'common struct clk' working as a base.

Good point. Mike, can you send a pull request for whatever you have
now as another staging branch for arm-soc?

	Arnd

[PATCH v2 08/11] ARM: EXYNOS: add support for ARCH_EXYNOS5 and EXYNOS5250

[Kukjin Kim]

Kyungmin Park wrote:
> 
> Hi,
> 

[...]

> >
> > +config ARCH_EXYNOS5
> > +	bool "SAMSUNG EXYNOS5"
> > +	select HAVE_SMP
> > +	help
> > +	  Samsung EXYNOS5 (Cortex-A15) SoC based systems
> This config is located at choice. It means it can't build the exynos4
> and exynos5 simultaneously. I'm not sure it's acceptable for mainline.

See Arnd's comments.

[...]

> > +obj-$(CONFIG_ARCH_EXYNOS5)	+= clock-exynos5.o
> Where's clock-exynos5.c file in this patch?. maybe it's another patch.

See 3rd patch.

[...]

> > +void exynos5_restart(char mode, const char *cmd)
> > +{
> > +	__raw_writel(0x1, EXYNOS_SWRESET);
> > +}
> Why new restart is required? it's same S5P_SWRESET and EXYNOS_SWRESET.
> see below.

It will be updated for exynos5.

[...]

> >
> >  #define S5P_SWRESET				S5P_PMUREG(0x0400)
> > +#define EXYNOS_SWRESET				S5P_PMUREG(0x0400)
> Please use just one.
> 
See above.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v2 06/11] ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5

[Kukjin Kim]

Kukjin Kim wrote:

[...]

> +struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
> +	[0] = {
> +		.resources	= exynos4_uart0_resource,
> +		.nr_resources	= ARRAY_SIZE(exynos4_uart0_resource),
> +	},
> +	[1] = {
> +		.resources	= exynos4_uart1_resource,
> +		.nr_resources	= ARRAY_SIZE(exynos4_uart0_resource),

Ooops, should be...

		.nr_resources	= ARRAY_SIZE(exynos4_uart1_resource),


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v2 04/11] ARM: EXYNOS: add interrupt definitions for EXYNOS5250

[Kukjin Kim]

Kukjin Kim wrote:
>
> This patch adds the interrupt definitions for EXYNOS5250 at
> <mach/irqs.h> file. Basically, now it is needed for EXYNOS5250
> interrupt and will be updated for single zImage next time.

[...]

> +#define JOP_IRQ_NUMBER		IRQ_SPI(118)

Typo :( Should be 'JOB_IRQ_...'

And I need to update every IRQ definitions...

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v2 03/11] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

[Turquette, Mike]

On Wed, Feb 15, 2012 at 9:22 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Thursday 16 February 2012, Kukjin Kim wrote:
>> Thanks for your sharing.
>>
>> OK, I and my team will follow up 'common struct clk' for exynos5250
>> and it will be done maybe next week. And since I need to
>> implement other features for exynos5250 now, firstly let me use this
>> and test this series in linux-next in a day.
>
> Ok, sounds good to me.
>
> If you like, you could also send the patches that you expect to stay
> stable for inclusion into arm-soc, or send the entire series as a
> preliminary branch that I will put into arm-soc now and then
> replace when you are done with the remaining changes.
>
> As we discussed last week at Linaro Connect, we will start taking
> both stable and unstable branches into arm-soc now, whereas we used
> to take only stable branches. Anything that is not considered stable
> yet will be marked as a staging branch, e.g. staging/samsung/soc instead
> of samsung/soc.
>
>> Ah, one more, would be better to us if arm-soc tree could provide
>> the topic branch for 'common struct clk' working as a base.
>
> Good point. Mike, can you send a pull request for whatever you have
> now as another staging branch for arm-soc?

Arnd, we discussed linux-next as the target for the common clk core
code at Linaro Connect.  Are you now asking for that code in arm-soc?
If so, I think it would be better to keep things simple only target
linux-next once V5 has hit the lists after ELC.

If you are instead referring to OMAP platform support for common clk,
that code is very infantile and not yet ready for arm-soc, especially
as it breaks OMAP2+ multi-boot.

Regards,
Mike

[PATCH v2 03/11] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

[Kukjin Kim]

Kukjin Kim wrote:
> 
> This patch adds clock-exynos5.c for EXYNOS5250 now
> and that can be used for other EXYNOS5 SoCs later.

[...]

> +static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
> +{
> +	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
> +}

This is not used yet. So I removed this function.

[...]

> +static struct clksrc_clk exynos5_clk_sclk_hdmi = {
> +	.clk	= {
> +		.name           = "sclk_hdmi",
                     ^^^^^^^^^^^
I fixed to use tab at above mark ^

[...]

> +static struct clk exynos5_clk_pdma0 = {
> +	.name		= "dma",
> +	.devname	= "dma-pl330.0",
> +	.enable		= exynos5_clk_ip_gen_ctrl,
> +	.ctrlbit	= (1 << 4),

I fixed like following.

	.enable		= exynos5_clk_ip_fsys_ctrl,
	.ctrlbit	= (1 << 1),

[...]

> +static struct clk exynos5_clk_pdma2 = {
> +	.name		= "dma",
> +	.devname	= "dma-pl330.2",
> +	.enable		= exynos5_clk_ip_fsys_ctrl,
> +	.ctrlbit	= (1 << 1),

static struct clk exynos5_clk_mdma1 = {
	.name		= "dma",
	.devname	= "dma-pl330.2",
	.enable		= exynos5_clk_ip_gen_ctrl,
	.ctrlbit	= (1 << 4),

[...]

> +static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
> +	.clk	= {
> +		.name		= "sclk_mmc",
> +		.devname	= "s3c-sdhci.1",
> +		.parent         = &exynos5_clk_dout_mmc1.clk,
                       ^^^^^^^^^
same as above

[...]

> +static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
> +	.clk	= {
> +		.name		= "sclk_mmc",
> +		.devname	= "s3c-sdhci.2",
> +		.parent         = &exynos5_clk_dout_mmc2.clk,
                       ^^^^^^^^^

[...]

> +static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
> +	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },

Ooops, this should be moved in above 'exynos5_clk_sclk_mmc2' :(

> +	.clk	= {
> +		.name		= "sclk_mmc",
> +		.devname	= "s3c-sdhci.3",
> +		.parent         = &exynos5_clk_dout_mmc3.clk,
                       ^^^^^^^^^

[...]

> +static struct clksrc_clk exynos5_clksrcs[] = {
> +	{
> +		.clk	= {
> +			.name		= "sclk_dwmci",
> +			.parent         = &exynos5_clk_dout_mmc4.clk,
                               ^^^^^^^^^

[...]

> +static struct clk *exynos5_clk_cdev[] = {
> +	&exynos5_clk_pdma0,
> +	&exynos5_clk_pdma1,
> +	&exynos5_clk_pdma2,

according to above changes,

	&exynos5_clk_mdma1,

[...]

> +	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
> +	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
> +	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_pdma2),

	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),

[...]

> +struct syscore_ops exynos5_clock_syscore_ops = {
> +	.suspend        = exynos5_clock_suspend,
                ^^^^^^^^
> +	.resume         = exynos5_clock_resume,
               ^^^^^^^^^
Tab

[...]

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v2 03/11] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

[Arnd Bergmann]

On Thursday 16 February 2012, Turquette, Mike wrote:
> >
> >> Ah, one more, would be better to us if arm-soc tree could provide
> >> the topic branch for 'common struct clk' working as a base.
> >
> > Good point. Mike, can you send a pull request for whatever you have
> > now as another staging branch for arm-soc?
> 
> Arnd, we discussed linux-next as the target for the common clk core
> code at Linaro Connect.  Are you now asking for that code in arm-soc?
> If so, I think it would be better to keep things simple only target
> linux-next once V5 has hit the lists after ELC.

I guess waiting for you to send out v5 is a good idea, but as Kgene
mentioned it would be nice to have the series in arm-soc in order
to base other branches on top of it, and we have now made it possible
to update branches like this one by declaring them "staging".

The main advantage that I see of putting your series into arm-soc
is that I can handle the dependencies: If you want to update the
series based to v6 after more review and send me a replacement pull
request, I can rebase the exynos5 patches (and other conversions)
on top of that. If you have a different tree in linux-next and plan
to rebase it, I cannot take any other patches into arm-soc that depend
on yours.

The alternative would be that I take the exynos5 patches in their
current shape into arm-soc and you put your patches into linux-next
based on the branch that I have, and with a patch to convert exynos5
to it on top.

> If you are instead referring to OMAP platform support for common clk,
> that code is very infantile and not yet ready for arm-soc, especially
> as it breaks OMAP2+ multi-boot.

I did not mean the omap specific parts.

	Arnd

[PATCH v2 03/11] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

[Turquette, Mike]

On Wed, Feb 15, 2012 at 9:50 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Thursday 16 February 2012, Turquette, Mike wrote:
>> >
>> >> Ah, one more, would be better to us if arm-soc tree could provide
>> >> the topic branch for 'common struct clk' working as a base.
>> >
>> > Good point. Mike, can you send a pull request for whatever you have
>> > now as another staging branch for arm-soc?
>>
>> Arnd, we discussed linux-next as the target for the common clk core
>> code at Linaro Connect. ?Are you now asking for that code in arm-soc?
>> If so, I think it would be better to keep things simple only target
>> linux-next once V5 has hit the lists after ELC.
>
> I guess waiting for you to send out v5 is a good idea, but as Kgene
> mentioned it would be nice to have the series in arm-soc in order
> to base other branches on top of it, and we have now made it possible
> to update branches like this one by declaring them "staging".
>
> The main advantage that I see of putting your series into arm-soc
> is that I can handle the dependencies: If you want to update the
> series based to v6 after more review and send me a replacement pull
> request, I can rebase the exynos5 patches (and other conversions)
> on top of that. If you have a different tree in linux-next and plan
> to rebase it, I cannot take any other patches into arm-soc that depend
> on yours.

Per our conversation at ELC, we can host in arm-soc to make it easier
for folks to port.  But the code should likely be merged through
Russell once we have the final version.

Regards,
Mike

> The alternative would be that I take the exynos5 patches in their
> current shape into arm-soc and you put your patches into linux-next
> based on the branch that I have, and with a patch to convert exynos5
> to it on top.
>
>> If you are instead referring to OMAP platform support for common clk,
>> that code is very infantile and not yet ready for arm-soc, especially
>> as it breaks OMAP2+ multi-boot.
>
> I did not mean the omap specific parts.
>
> ? ? ? ?Arnd

[PATCH v2 04/11] ARM: EXYNOS: add interrupt definitions for EXYNOS5250

[Olof Johansson]

Hi,

On Sat, Feb 11, 2012 at 9:34 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> This patch adds the interrupt definitions for EXYNOS5250 at
> <mach/irqs.h> file. Basically, now it is needed for EXYNOS5250
> interrupt and will be updated for single zImage next time.
>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> ---
> ?arch/arm/mach-exynos/include/mach/irqs.h | ?236 +++++++++++++++++++++++++++++-
> ?1 files changed, 232 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
> index f77bce0..0dab1b1 100644
> --- a/arch/arm/mach-exynos/include/mach/irqs.h
> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> @@ -1,9 +1,8 @@
> -/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
> - *
> - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> +/*
> + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
> ?* ? ? ? ? ? ? http://www.samsung.com
> ?*
> - * EXYNOS4 - IRQ definitions
> + * EXYNOS - IRQ definitions
> ?*
> ?* This program is free software; you can redistribute it and/or modify
> ?* it under the terms of the GNU General Public License version 2 as
> @@ -25,6 +24,8 @@
>
> ?#define IRQ_SPI(x) ? ? ? ? ? ? (x+32)
>
> +#ifdef CONFIG_ARCH_EXYNOS4
> +

irqs.h seems to be one of the major files that causes conflicts if a
combined EXYNOS4+5 kernel is built (after editing Kconfig to allow
both). Can you please try to come up with a way to allow both of them
to coexist instead of making them exclusive?


-Olof



-Olof

[PATCH v2 04/11] ARM: EXYNOS: add interrupt definitions for EXYNOS5250

[Kukjin Kim]

Olof Johansson wrote:
> 
> Hi,
> 
Hi Olof,

[snip]

> > +#ifdef CONFIG_ARCH_EXYNOS4
> > +
> 
> irqs.h seems to be one of the major files that causes conflicts if a
> combined EXYNOS4+5 kernel is built (after editing Kconfig to allow
> both). Can you please try to come up with a way to allow both of them
> to coexist instead of making them exclusive?
> 
Yes, as you said, it brakes single zImage for EXYNOS4 + EXYNOS5
(mach-exynos). So I'm working on regarding resource for EXYNOS SoCs and I
think, it can resolve the problem you said before v3.4 merge window.

If any updates, let you know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v2 04/11] ARM: EXYNOS: add interrupt definitions for EXYNOS5250

[Olof Johansson]

Hi,

On Tue, Feb 21, 2012 at 2:35 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:

> Yes, as you said, it brakes single zImage for EXYNOS4 + EXYNOS5
> (mach-exynos). So I'm working on regarding resource for EXYNOS SoCs and I
> think, it can resolve the problem you said before v3.4 merge window.
>
> If any updates, let you know.

Just a friendly reminder; the time is close to running out for staging
new code for 3.4.


-Olof

[PATCH v2 04/11] ARM: EXYNOS: add interrupt definitions for EXYNOS5250

[Kukjin Kim]

On 03/06/12 10:55, Olof Johansson wrote:
> Hi,
>
> On Tue, Feb 21, 2012 at 2:35 AM, Kukjin Kim<kgene.kim@samsung.com>  wrote:
>
>> Yes, as you said, it brakes single zImage for EXYNOS4 + EXYNOS5
>> (mach-exynos). So I'm working on regarding resource for EXYNOS SoCs and I
>> think, it can resolve the problem you said before v3.4 merge window.
>>
>> If any updates, let you know.
>
> Just a friendly reminder; the time is close to running out for staging
> new code for 3.4.
>
Hi Olof,

Thanks for your kindly reminder but I couldn't finish it yet because it 
is required to touch most of samsung stuff, and it's a big change. 
Frankly, I need more time...

So how about sending current exynos5 stuff for now and then sorting out 
single kernel for exynos4 and exynos5 next time? Actually, this exynos5 
arch part is _really_ needed for developing/contribution of drivers on 
exynos5.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v2 04/11] ARM: EXYNOS: add interrupt definitions for EXYNOS5250

[Kyungmin Park]

On Wed, Mar 7, 2012 at 10:12 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> On 03/06/12 10:55, Olof Johansson wrote:
>>
>> Hi,
>>
>> On Tue, Feb 21, 2012 at 2:35 AM, Kukjin Kim<kgene.kim@samsung.com> ?wrote:
>>
>>> Yes, as you said, it brakes single zImage for EXYNOS4 + EXYNOS5
>>> (mach-exynos). So I'm working on regarding resource for EXYNOS SoCs and I
>>> think, it can resolve the problem you said before v3.4 merge window.
>>>
>>> If any updates, let you know.
>>
>>
>> Just a friendly reminder; the time is close to running out for staging
>> new code for 3.4.
>>
> Hi Olof,
>
> Thanks for your kindly reminder but I couldn't finish it yet because it is
> required to touch most of samsung stuff, and it's a big change. Frankly, I
> need more time...
>
> So how about sending current exynos5 stuff for now and then sorting out
> single kernel for exynos4 and exynos5 next time? Actually, this exynos5 arch
> part is _really_ needed for developing/contribution of drivers on exynos5.
No,

I heard too many times. "we have plan to support ..." but I didn't see
any progress.
it's general rules. you should fix it correctly and merged correctly
instead of "not now"

Thank you,
Kyungmin Park
>
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html

[PATCH v2 04/11] ARM: EXYNOS: add interrupt definitions for EXYNOS5250

[Olof Johansson]

Hi,

On Wed, Mar 7, 2012 at 5:12 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:

> Thanks for your kindly reminder but I couldn't finish it yet because it is
> required to touch most of samsung stuff, and it's a big change. Frankly, I
> need more time...
>
> So how about sending current exynos5 stuff for now and then sorting out
> single kernel for exynos4 and exynos5 next time? Actually, this exynos5 arch
> part is _really_ needed for developing/contribution of drivers on exynos5.

I suggest that you work on the code until it's in shape to go in. If
we pick it up half-finished it just causes extra churn.

We have been pushing back on v6/v7 additions that are not multi-board
and multi-soc within the same machine type. Not being able to build a
combined binary with exynos 4 and 5 support in one would be a step
backwards on that effort.

I'm not sure I understand the argument about drivers -- they should
mostly be possible to submit and get included without the core SoC
patches such that when those land, you'll have a fully functional
system.


-Olof