[PATCH] ARM: perf: do not handle deleted counter in irq handler to avoid oops

[will.deacon@arm.com (Will Deacon)]

On Tue, Feb 21, 2012 at 03:49:22PM +0000, Ming Lei wrote:
> On Tue, Feb 21, 2012 at 11:40 PM, Will Deacon <will.deacon@arm.com> wrote:
> > Sure they do. When we read-modify-write the pmcr we &= ~mask, so we end up
> > writing the overflow flags back if they are set, which is sufficient to
> > clear them.
> 
> Sorry for missing it, but looks xscale uses standalone overflow
> register and does not
> clear its overflow flag.

Hmmm, I don't know very much about the xscale PMUs (the perf code is based
on the old OProfile code). The xscale2 overflow handler is certainly doing
something with some overflow flags though, but then it checks the pmnc again
for each counter...

I'd rather not touch that without knowing *exactly* what I'm doing. It may
be that the current code deals with the flag but, even if it doesn't, the
spurious interrupt isn't the end of the world. I have a board at home that
advertises its PMU as xscale2, so I could test that this patch doesn't cause
breakage.

Will