* [PATCH v4 1/2] ARM: Exynos: Add irq_domain support for interrupt combiner
2012-02-21 4:33 [PATCH v4 0/2] ARM: Exynos: Add irq_domain and device tree support for combiner Thomas Abraham
@ 2012-02-21 4:33 ` Thomas Abraham
2012-02-21 4:33 ` [PATCH v4 2/2] ARM: Exynos: Add device tree " Thomas Abraham
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Thomas Abraham @ 2012-02-21 4:33 UTC (permalink / raw)
To: linux-arm-kernel
Add irq_domain support for hardware interrupts of the interrupt combiner.
The hardware interrupts of all the instances of the combiner are grouped
in a single irq_domain.
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/common.c | 65 ++++++++++++++++++++++++++++------------
1 files changed, 45 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index f494db8..0c06fa6 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -19,6 +19,8 @@
#include <linux/serial_core.h>
#include <linux/of.h>
#include <linux/of_irq.h>
+#include <linux/export.h>
+#include <linux/irqdomain.h>
#include <asm/proc-fns.h>
#include <asm/exception.h>
@@ -284,6 +286,7 @@ struct combiner_chip_data {
void __iomem *base;
};
+static struct irq_domain *combiner_irq_domain;
static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
static inline void __iomem *combiner_base(struct irq_data *data)
@@ -296,14 +299,14 @@ static inline void __iomem *combiner_base(struct irq_data *data)
static void combiner_mask_irq(struct irq_data *data)
{
- u32 mask = 1 << (data->irq % 32);
+ u32 mask = 1 << (data->hwirq % 32);
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
}
static void combiner_unmask_irq(struct irq_data *data)
{
- u32 mask = 1 << (data->irq % 32);
+ u32 mask = 1 << (data->hwirq % 32);
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
}
@@ -352,30 +355,58 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
irq_set_chained_handler(irq, combiner_handle_cascade_irq);
}
-static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
- unsigned int irq_start)
+static void __init combiner_init_one(unsigned int combiner_nr,
+ void __iomem *base)
{
- unsigned int i;
-
if (combiner_nr >= MAX_COMBINER_NR)
BUG();
combiner_data[combiner_nr].base = base;
- combiner_data[combiner_nr].irq_offset = irq_start;
+ combiner_data[combiner_nr].irq_offset = irq_find_mapping(
+ combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
/* Disable all interrupts */
__raw_writel(combiner_data[combiner_nr].irq_mask,
base + COMBINER_ENABLE_CLEAR);
+}
+
+static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+{
+ irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
+ irq_set_chip_data(irq, &combiner_data[hw >> 3]);
+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+ return 0;
+}
- /* Setup the Linux IRQ subsystem */
+static struct irq_domain_ops combiner_irq_domain_ops = {
+ .map = combiner_irq_domain_map,
+};
- for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
- + MAX_IRQ_IN_COMBINER; i++) {
- irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
- irq_set_chip_data(i, &combiner_data[combiner_nr]);
- set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
+{
+ int i, irq_base;
+ int nr_irq = MAX_COMBINER_NR * MAX_IRQ_IN_COMBINER;
+
+ irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
+ if (IS_ERR_VALUE(irq_base)) {
+ irq_base = COMBINER_IRQ(0, 0);
+ pr_warning("combiner_init_irq_domain: irq desc alloc failed. "
+ "Continuing with %d as linux irq base\n", irq_base);
+ }
+
+ combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
+ &combiner_irq_domain_ops, &combiner_data);
+ if (WARN_ON(!combiner_irq_domain)) {
+ pr_warning("combiner_init_irq_domain: irq domain init failed\n");
+ return;
+ }
+
+ for (i = 0; i < MAX_COMBINER_NR; i++) {
+ combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
+ combiner_cascade_irq(i, IRQ_SPI(i));
}
}
@@ -388,7 +419,6 @@ static const struct of_device_id exynos4_dt_irq_match[] = {
void __init exynos4_init_irq(void)
{
- int irq;
unsigned int gic_bank_offset;
gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
@@ -400,12 +430,7 @@ void __init exynos4_init_irq(void)
of_irq_init(exynos4_dt_irq_match);
#endif
- for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
-
- combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
- COMBINER_IRQ(irq, 0));
- combiner_cascade_irq(irq, IRQ_SPI(irq));
- }
+ combiner_init(S5P_VA_COMBINER_BASE, NULL);
/*
* The parameters of s5p_init_irq() are for VIC init.
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v4 2/2] ARM: Exynos: Add device tree support for interrupt combiner
2012-02-21 4:33 [PATCH v4 0/2] ARM: Exynos: Add irq_domain and device tree support for combiner Thomas Abraham
2012-02-21 4:33 ` [PATCH v4 1/2] ARM: Exynos: Add irq_domain support for interrupt combiner Thomas Abraham
@ 2012-02-21 4:33 ` Thomas Abraham
2012-03-13 3:52 ` Grant Likely
2012-03-12 21:07 ` [PATCH v4 0/2] ARM: Exynos: Add irq_domain and device tree support for combiner Thomas Abraham
2012-03-13 1:34 ` Rob Herring
3 siblings, 1 reply; 7+ messages in thread
From: Thomas Abraham @ 2012-02-21 4:33 UTC (permalink / raw)
To: linux-arm-kernel
Add device tree based instantiation of the interrupt combiner controller.
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
.../bindings/arm/samsung/interrupt-combiner.txt | 48 ++++++++++++++++++
arch/arm/mach-exynos/common.c | 53 ++++++++++++++++++-
2 files changed, 98 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
diff --git a/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
new file mode 100644
index 0000000..2a57211
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
@@ -0,0 +1,48 @@
+* Samsung Exynos Interrupt Combiner Controller
+
+Samsung's Exynos4 architecture includes a interrupt combiner controller which
+can combine interrupt sources as a group and provide a single interrupt request
+for the group. The interrupt request from each group are connected to a parent
+interrupt controller, such as GIC in case of Exynos4210.
+
+The interrupt combiner controller consists of multiple combiners. Upto eight
+interrupt sources can be connected to a combiner. The combiner outputs one
+combined interrupt for its eight interrupt sources. The combined interrupt
+is usually connected to a parent interrupt controller.
+
+A single node in the device tree is used to describe the interrupt combiner
+controller module (which includes multiple combiners). A combiner in the
+interrupt controller module shares config/control registers with other
+combiners. For example, a 32-bit interrupt enable/disable config register
+can accommodate upto 4 interrupt combiners (with each combiner supporting
+upto 8 interrupt sources).
+
+Required properties:
+- compatible: should be "samsung,exynos4210-combiner".
+- interrupt-controller: Identifies the node as an interrupt controller.
+- #interrupt-cells: should be <2>. The meaning of the cells are
+ * First Cell: Combiner Group Number.
+ * Second Cell: Interrupt number within the group.
+- reg: Base address and size of interrupt combiner registers.
+- interrupts: The list of interrupts generated by the combiners which are then
+ connected to a parent interrupt controller. The format of the interrupt
+ specifier depends in the interrupt parent controller.
+
+Optional properties:
+- interrupt-parent: pHandle of the parent interrupt controller, if not
+ inherited from the parent node.
+
+Example:
+
+ The following is a an example from the Exynos4210 SoC dtsi file.
+
+ combiner:interrupt-controller at 10440000 {
+ compatible = "samsung,exynos4210-combiner";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x10440000 0x1000>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+ <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ };
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 0c06fa6..ac5ac0e 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -21,6 +21,7 @@
#include <linux/of_irq.h>
#include <linux/export.h>
#include <linux/irqdomain.h>
+#include <linux/of_address.h>
#include <asm/proc-fns.h>
#include <asm/exception.h>
@@ -372,6 +373,30 @@ static void __init combiner_init_one(unsigned int combiner_nr,
base + COMBINER_ENABLE_CLEAR);
}
+#ifdef CONFIG_OF
+static int combiner_irq_domain_xlate(struct irq_domain *d,
+ struct device_node *controller, const u32 *intspec,
+ unsigned int intsize, unsigned long *out_hwirq,
+ unsigned int *out_type)
+{
+ if (d->of_node != controller)
+ return -EINVAL;
+ if (intsize < 2)
+ return -EINVAL;
+ *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
+ *out_type = 0;
+ return 0;
+}
+#else
+static int combiner_irq_domain_xlate(struct irq_domain *d,
+ struct device_node *controller, const u32 *intspec,
+ unsigned int intsize, unsigned long *out_hwirq,
+ unsigned int *out_type)
+{
+ return -EINVAL;
+}
+#endif
+
static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
@@ -382,12 +407,13 @@ static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
}
static struct irq_domain_ops combiner_irq_domain_ops = {
+ .xlate = combiner_irq_domain_xlate,
.map = combiner_irq_domain_map,
};
void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
{
- int i, irq_base;
+ int i, irq, irq_base;
int nr_irq = MAX_COMBINER_NR * MAX_IRQ_IN_COMBINER;
irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
@@ -406,13 +432,33 @@ void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
for (i = 0; i < MAX_COMBINER_NR; i++) {
combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
- combiner_cascade_irq(i, IRQ_SPI(i));
+#ifdef CONFIG_OF
+ irq = np ? irq_of_parse_and_map(np, i) : IRQ_SPI(i);
+#else
+ irq = IRQ_SPI(i);
+#endif
+ combiner_cascade_irq(i, irq);
}
}
#ifdef CONFIG_OF
+void __init combiner_of_init(struct device_node *np, struct device_node *parent)
+{
+ void __iomem *combiner_base;
+
+ combiner_base = of_iomap(np, 0);
+ if (!combiner_base) {
+ pr_err("combiner_of_init: failed to map combiner registers\n");
+ return;
+ }
+
+ combiner_init(combiner_base, np);
+}
+
static const struct of_device_id exynos4_dt_irq_match[] = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+ { .compatible = "samsung,exynos4210-combiner",
+ .data = combiner_of_init, },
{},
};
#endif
@@ -430,7 +476,8 @@ void __init exynos4_init_irq(void)
of_irq_init(exynos4_dt_irq_match);
#endif
- combiner_init(S5P_VA_COMBINER_BASE, NULL);
+ if (!of_have_populated_dt())
+ combiner_init(S5P_VA_COMBINER_BASE, NULL);
/*
* The parameters of s5p_init_irq() are for VIC init.
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 7+ messages in thread