[PATCH] ARM: Enable I$/D$/BrPredict based on config

[PATCH] ARM: Enable I$/D$/BrPredict based on config

[Bryan Buckley]

Currently we only disable these bits based on config. Now we will
use this config option to explicitly enable these features at this
point regardless of what bootloader, other SW, or HW did before.

Signed-off-by: Bryan Buckley <bryan.buckley@ti.com>
---
 arch/arm/kernel/head.S |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 3bf0c7f..cec0de5 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -411,12 +411,18 @@ __enable_mmu:
 #endif
 #ifdef CONFIG_CPU_DCACHE_DISABLE
 	bic	r0, r0, #CR_C
+#else
+	orr	r0, r0, #CR_C
 #endif
 #ifdef CONFIG_CPU_BPREDICT_DISABLE
 	bic	r0, r0, #CR_Z
+#else
+	orr	r0, r0, #CR_Z
 #endif
 #ifdef CONFIG_CPU_ICACHE_DISABLE
 	bic	r0, r0, #CR_I
+#else
+	orr	r0, r0, #CR_I
 #endif
 #ifdef CONFIG_ARM_LPAE
 	mov	r5, #0
-- 
1.7.4.1

[PATCH] ARM: Enable I$/D$/BrPredict based on config

[Måns Rullgård]

Bryan Buckley <bryan.buckley@ti.com> writes:

> Currently we only disable these bits based on config. Now we will
> use this config option to explicitly enable these features at this
> point regardless of what bootloader, other SW, or HW did before.
>
> Signed-off-by: Bryan Buckley <bryan.buckley@ti.com>
> ---
>  arch/arm/kernel/head.S |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> index 3bf0c7f..cec0de5 100644
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -411,12 +411,18 @@ __enable_mmu:
>  #endif
>  #ifdef CONFIG_CPU_DCACHE_DISABLE
>  	bic	r0, r0, #CR_C
> +#else
> +	orr	r0, r0, #CR_C
>  #endif
>  #ifdef CONFIG_CPU_BPREDICT_DISABLE
>  	bic	r0, r0, #CR_Z
> +#else
> +	orr	r0, r0, #CR_Z
>  #endif
>  #ifdef CONFIG_CPU_ICACHE_DISABLE
>  	bic	r0, r0, #CR_I
> +#else
> +	orr	r0, r0, #CR_I
>  #endif
>  #ifdef CONFIG_ARM_LPAE
>  	mov	r5, #0
> -- 

Caches and branch predictors may require implementation defined
invalidation before being enabled.

-- 
M?ns Rullg?rd
mans at mansr.com

[PATCH] ARM: Enable I$/D$/BrPredict based on config

[Buckley, Bryan]

On Thu, May 3, 2012 at 5:23 PM, M?ns Rullg?rd <mans@mansr.com> wrote:
>
> Bryan Buckley <bryan.buckley@ti.com> writes:
>
> > Currently we only disable these bits based on config. Now we will
> > use this config option to explicitly enable these features at this
> > point regardless of what bootloader, other SW, or HW did before.
> >
> > Signed-off-by: Bryan Buckley <bryan.buckley@ti.com>
> > ---
> > ?arch/arm/kernel/head.S | ? ?6 ++++++
> > ?1 files changed, 6 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> > index 3bf0c7f..cec0de5 100644
> > --- a/arch/arm/kernel/head.S
> > +++ b/arch/arm/kernel/head.S
> > @@ -411,12 +411,18 @@ __enable_mmu:
> > ?#endif
> > ?#ifdef CONFIG_CPU_DCACHE_DISABLE
> > ? ? ? bic ? ? r0, r0, #CR_C
> > +#else
> > + ? ? orr ? ? r0, r0, #CR_C
> > ?#endif
> > ?#ifdef CONFIG_CPU_BPREDICT_DISABLE
> > ? ? ? bic ? ? r0, r0, #CR_Z
> > +#else
> > + ? ? orr ? ? r0, r0, #CR_Z
> > ?#endif
> > ?#ifdef CONFIG_CPU_ICACHE_DISABLE
> > ? ? ? bic ? ? r0, r0, #CR_I
> > +#else
> > + ? ? orr ? ? r0, r0, #CR_I
> > ?#endif
> > ?#ifdef CONFIG_ARM_LPAE
> > ? ? ? mov ? ? r5, #0
> > --
>
> Caches and branch predictors may require implementation defined
> invalidation before being enabled.
>

True.. I was relying on going through arch/arm/boot/compressed/head.S
to do that for me. Was that unreasonable?

> --
> M?ns Rullg?rd
> mans at mansr.com

[PATCH] ARM: Enable I$/D$/BrPredict based on config

[Russell King - ARM Linux]

On Thu, May 03, 2012 at 05:48:33PM -0500, Buckley, Bryan wrote:
> On Thu, May 3, 2012 at 5:23 PM, M?ns Rullg?rd <mans@mansr.com> wrote:
> >
> > Bryan Buckley <bryan.buckley@ti.com> writes:
> >
> > > Currently we only disable these bits based on config. Now we will
> > > use this config option to explicitly enable these features at this
> > > point regardless of what bootloader, other SW, or HW did before.
> > >
> > > Signed-off-by: Bryan Buckley <bryan.buckley@ti.com>
> > > ---
> > > ?arch/arm/kernel/head.S | ? ?6 ++++++
> > > ?1 files changed, 6 insertions(+), 0 deletions(-)
> > >
> > > diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> > > index 3bf0c7f..cec0de5 100644
> > > --- a/arch/arm/kernel/head.S
> > > +++ b/arch/arm/kernel/head.S
> > > @@ -411,12 +411,18 @@ __enable_mmu:
> > > ?#endif
> > > ?#ifdef CONFIG_CPU_DCACHE_DISABLE
> > > ? ? ? bic ? ? r0, r0, #CR_C
> > > +#else
> > > + ? ? orr ? ? r0, r0, #CR_C
> > > ?#endif
> > > ?#ifdef CONFIG_CPU_BPREDICT_DISABLE
> > > ? ? ? bic ? ? r0, r0, #CR_Z
> > > +#else
> > > + ? ? orr ? ? r0, r0, #CR_Z
> > > ?#endif
> > > ?#ifdef CONFIG_CPU_ICACHE_DISABLE
> > > ? ? ? bic ? ? r0, r0, #CR_I
> > > +#else
> > > + ? ? orr ? ? r0, r0, #CR_I
> > > ?#endif
> > > ?#ifdef CONFIG_ARM_LPAE
> > > ? ? ? mov ? ? r5, #0
> > > --
> >
> > Caches and branch predictors may require implementation defined
> > invalidation before being enabled.
> 
> True.. I was relying on going through arch/arm/boot/compressed/head.S
> to do that for me. Was that unreasonable?

Yes, because that may not always be used.

Where that _is_ dealt with is in the CPU specific setup assembly code,
just as providing the CPU specific default value for the CPU control
register in r0 is done.

[PATCH] ARM: Enable I$/D$/BrPredict based on config

[Måns Rullgård]

"Buckley, Bryan" <bryan.buckley@ti.com> writes:

> On Thu, May 3, 2012 at 5:23 PM, M?ns Rullg?rd <mans@mansr.com> wrote:
>>
>> Bryan Buckley <bryan.buckley@ti.com> writes:
>>
>> > Currently we only disable these bits based on config. Now we will
>> > use this config option to explicitly enable these features at this
>> > point regardless of what bootloader, other SW, or HW did before.
>> >
>> > Signed-off-by: Bryan Buckley <bryan.buckley@ti.com>
>> > ---
>> > ?arch/arm/kernel/head.S | ? ?6 ++++++
>> > ?1 files changed, 6 insertions(+), 0 deletions(-)
>> >
>> > diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
>> > index 3bf0c7f..cec0de5 100644
>> > --- a/arch/arm/kernel/head.S
>> > +++ b/arch/arm/kernel/head.S
>> > @@ -411,12 +411,18 @@ __enable_mmu:
>> > ?#endif
>> > ?#ifdef CONFIG_CPU_DCACHE_DISABLE
>> > ? ? ? bic ? ? r0, r0, #CR_C
>> > +#else
>> > + ? ? orr ? ? r0, r0, #CR_C
>> > ?#endif
>> > ?#ifdef CONFIG_CPU_BPREDICT_DISABLE
>> > ? ? ? bic ? ? r0, r0, #CR_Z
>> > +#else
>> > + ? ? orr ? ? r0, r0, #CR_Z
>> > ?#endif
>> > ?#ifdef CONFIG_CPU_ICACHE_DISABLE
>> > ? ? ? bic ? ? r0, r0, #CR_I
>> > +#else
>> > + ? ? orr ? ? r0, r0, #CR_I
>> > ?#endif
>> > ?#ifdef CONFIG_ARM_LPAE
>> > ? ? ? mov ? ? r5, #0
>> > --
>>
>> Caches and branch predictors may require implementation defined
>> invalidation before being enabled.
>
> True.. I was relying on going through arch/arm/boot/compressed/head.S
> to do that for me. Was that unreasonable?

I'd be inclined to qualify that as "other SW."  It is possible to start
the kernel without using that code, even if it is not typically done.

-- 
M?ns Rullg?rd
mans at mansr.com

[PATCH] ARM: Enable I$/D$/BrPredict based on config

[Buckley, Bryan]

On Thu, May 3, 2012 at 5:57 PM, M?ns Rullg?rd <mans@mansr.com> wrote:
> "Buckley, Bryan" <bryan.buckley@ti.com> writes:
>
>> On Thu, May 3, 2012 at 5:23 PM, M?ns Rullg?rd <mans@mansr.com> wrote:
>>>
>>> Bryan Buckley <bryan.buckley@ti.com> writes:
>>>
>>> > Currently we only disable these bits based on config. Now we will
>>> > use this config option to explicitly enable these features at this
>>> > point regardless of what bootloader, other SW, or HW did before.
>>> >
>>> > Signed-off-by: Bryan Buckley <bryan.buckley@ti.com>
>>> > ---
>>> > ?arch/arm/kernel/head.S | ? ?6 ++++++
>>> > ?1 files changed, 6 insertions(+), 0 deletions(-)
>>> >
>>> > diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
>>> > index 3bf0c7f..cec0de5 100644
>>> > --- a/arch/arm/kernel/head.S
>>> > +++ b/arch/arm/kernel/head.S
>>> > @@ -411,12 +411,18 @@ __enable_mmu:
>>> > ?#endif
>>> > ?#ifdef CONFIG_CPU_DCACHE_DISABLE
>>> > ? ? ? bic ? ? r0, r0, #CR_C
>>> > +#else
>>> > + ? ? orr ? ? r0, r0, #CR_C
>>> > ?#endif
>>> > ?#ifdef CONFIG_CPU_BPREDICT_DISABLE
>>> > ? ? ? bic ? ? r0, r0, #CR_Z
>>> > +#else
>>> > + ? ? orr ? ? r0, r0, #CR_Z
>>> > ?#endif
>>> > ?#ifdef CONFIG_CPU_ICACHE_DISABLE
>>> > ? ? ? bic ? ? r0, r0, #CR_I
>>> > +#else
>>> > + ? ? orr ? ? r0, r0, #CR_I
>>> > ?#endif
>>> > ?#ifdef CONFIG_ARM_LPAE
>>> > ? ? ? mov ? ? r5, #0
>>> > --
>>>
>>> Caches and branch predictors may require implementation defined
>>> invalidation before being enabled.
>>
>> True.. I was relying on going through arch/arm/boot/compressed/head.S
>> to do that for me. Was that unreasonable?
>
> I'd be inclined to qualify that as "other SW." ?It is possible to start
> the kernel without using that code, even if it is not typically done.
>

haha, yeah me too.

Thanks M?ns and Russel.

> --
> M?ns Rullg?rd
> mans at mansr.com

[PATCH] ARM: Enable I$/D$/BrPredict based on config

[Russell King - ARM Linux]

On Thu, May 03, 2012 at 04:00:25PM -0500, Bryan Buckley wrote:
> Currently we only disable these bits based on config. Now we will
> use this config option to explicitly enable these features at this
> point regardless of what bootloader, other SW, or HW did before.

NAK.  r0 comes from the CPU specific file.  It is up to the CPU
specific support file to decide what setting is appropriate.  For
example, a CPU not implementing the I bit will require this bit to
be preserved, rather than being explicitly written as one or zero.

The ifdefs here are just disable-overrides for that, primerily to allow
testing of new CPUs.