* [PATCH 1/2] ARM: i.MX5x clocks: Add EPIT support
@ 2012-06-27 7:08 Alexander Shiyan
2012-06-27 7:08 ` [PATCH 2/2] ARM: i.MX51 iomux: added missing pin definitions Alexander Shiyan
` (2 more replies)
0 siblings, 3 replies; 12+ messages in thread
From: Alexander Shiyan @ 2012-06-27 7:08 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support for Enhanced Periodic Interrupt Timer (EPIT)
to clock subsystem.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/mach-imx/clk-imx51-imx53.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index a2200c7..2944854 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -81,6 +81,7 @@ enum imx5_clks {
ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
+ epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
clk_max
};
@@ -226,6 +227,10 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
+ clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
+ clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "ipg", MXC_CCM_CCGR2, 4);
+ clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
+ clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "ipg", MXC_CCM_CCGR2, 8);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
@@ -279,6 +284,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
+ clk_register_clkdev(clk[epit1_ipg_gate], NULL, "imx-epit.0");
+ clk_register_clkdev(clk[epit2_ipg_gate], NULL, "imx-epit.1");
/* Set SDHC parents to be PLL2 */
clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
--
1.7.3.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 2/2] ARM: i.MX51 iomux: added missing pin definitions 2012-06-27 7:08 [PATCH 1/2] ARM: i.MX5x clocks: Add EPIT support Alexander Shiyan @ 2012-06-27 7:08 ` Alexander Shiyan 2012-07-02 9:26 ` [PATCH 1/2] ARM: i.MX5x clocks: Add EPIT support Sascha Hauer 2012-07-09 8:27 ` Sascha Hauer 2 siblings, 0 replies; 12+ messages in thread From: Alexander Shiyan @ 2012-06-27 7:08 UTC (permalink / raw) To: linux-arm-kernel This patch adds missing definitions for DISP, GPT and CCM pads. These pins are not used by kernel, but may be helpful for custom boards. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> --- arch/arm/plat-mxc/include/mach/iomux-mx51.h | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 36c8989..2623e7a 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -107,11 +107,13 @@ #define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL) #define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL) #define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D25__GPT_CMPOUT1 IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL) #define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL) #define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D26__GPT_CMPOUT2 IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) @@ -228,6 +230,7 @@ #define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DRAM_CS1__CCM_CLKO IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) @@ -256,12 +259,14 @@ #define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2 IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) #define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3 IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) @@ -637,7 +642,9 @@ #define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN15__DI1_PIN15 IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL) #define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL) @@ -780,6 +787,8 @@ #define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) +#define MX51_PAD_GPIO1_3__CCM_CLKO2 IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_3__GPT_CLKIN IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) #define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL) @@ -788,13 +797,16 @@ #define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) #define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_4__GPT_CAPIN1 IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_5__CCM_CLKO IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_6__GPT_CAPIN2 IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) @@ -803,11 +815,13 @@ #define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_8__CCM_CLKO2 IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__CCM_CLKO IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL) #endif /* __MACH_IOMUX_MX51_H__ */ -- 1.7.3.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/2] ARM: i.MX5x clocks: Add EPIT support 2012-06-27 7:08 [PATCH 1/2] ARM: i.MX5x clocks: Add EPIT support Alexander Shiyan 2012-06-27 7:08 ` [PATCH 2/2] ARM: i.MX51 iomux: added missing pin definitions Alexander Shiyan @ 2012-07-02 9:26 ` Sascha Hauer 2012-07-09 8:27 ` Sascha Hauer 2 siblings, 0 replies; 12+ messages in thread From: Sascha Hauer @ 2012-07-02 9:26 UTC (permalink / raw) To: linux-arm-kernel On Wed, Jun 27, 2012 at 11:08:04AM +0400, Alexander Shiyan wrote: > This patch adds support for Enhanced Periodic Interrupt Timer (EPIT) > to clock subsystem. > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Applied (both) Thanks Sascha > --- > arch/arm/mach-imx/clk-imx51-imx53.c | 7 +++++++ > 1 files changed, 7 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c > index a2200c7..2944854 100644 > --- a/arch/arm/mach-imx/clk-imx51-imx53.c > +++ b/arch/arm/mach-imx/clk-imx51-imx53.c > @@ -81,6 +81,7 @@ enum imx5_clks { > ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred, > ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate, > ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, > + epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate, > clk_max > }; > > @@ -226,6 +227,10 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, > clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26); > clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28); > clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30); > + clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2); > + clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "ipg", MXC_CCM_CCGR2, 4); > + clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); > + clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "ipg", MXC_CCM_CCGR2, 8); > > for (i = 0; i < ARRAY_SIZE(clk); i++) > if (IS_ERR(clk[i])) > @@ -279,6 +284,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, > clk_register_clkdev(clk[dummy], NULL, "imx-keypad"); > clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0"); > clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0"); > + clk_register_clkdev(clk[epit1_ipg_gate], NULL, "imx-epit.0"); > + clk_register_clkdev(clk[epit2_ipg_gate], NULL, "imx-epit.1"); > > /* Set SDHC parents to be PLL2 */ > clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]); > -- > 1.7.3.4 > > -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/2] ARM: i.MX5x clocks: Add EPIT support 2012-06-27 7:08 [PATCH 1/2] ARM: i.MX5x clocks: Add EPIT support Alexander Shiyan 2012-06-27 7:08 ` [PATCH 2/2] ARM: i.MX51 iomux: added missing pin definitions Alexander Shiyan 2012-07-02 9:26 ` [PATCH 1/2] ARM: i.MX5x clocks: Add EPIT support Sascha Hauer @ 2012-07-09 8:27 ` Sascha Hauer 2012-07-10 18:54 ` [PATCH 1/3] " Alexander Shiyan ` (2 more replies) 2 siblings, 3 replies; 12+ messages in thread From: Sascha Hauer @ 2012-07-09 8:27 UTC (permalink / raw) To: linux-arm-kernel Hi Alexander, On Wed, Jun 27, 2012 at 11:08:04AM +0400, Alexander Shiyan wrote: > This patch adds support for Enhanced Periodic Interrupt Timer (EPIT) > to clock subsystem. > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> > --- > arch/arm/mach-imx/clk-imx51-imx53.c | 7 +++++++ > 1 files changed, 7 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c > index a2200c7..2944854 100644 > --- a/arch/arm/mach-imx/clk-imx51-imx53.c > +++ b/arch/arm/mach-imx/clk-imx51-imx53.c > @@ -81,6 +81,7 @@ enum imx5_clks { > ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred, > ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate, > ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, > + epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate, > clk_max > }; > > @@ -226,6 +227,10 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, > clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26); > clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28); > clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30); > + clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2); > + clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "ipg", MXC_CCM_CCGR2, 4); > + clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); > + clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "ipg", MXC_CCM_CCGR2, 8); I just noticed this is wrong. The parent for the hf_gate is perclk_root, not the ipg clock. > > for (i = 0; i < ARRAY_SIZE(clk); i++) > if (IS_ERR(clk[i])) > @@ -279,6 +284,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, > clk_register_clkdev(clk[dummy], NULL, "imx-keypad"); > clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0"); > clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0"); > + clk_register_clkdev(clk[epit1_ipg_gate], NULL, "imx-epit.0"); > + clk_register_clkdev(clk[epit2_ipg_gate], NULL, "imx-epit.1"); Also, as the EPIT has two clocks you should register both: clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0"); clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0"); Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/3] ARM: i.MX5x clocks: Add EPIT support 2012-07-09 8:27 ` Sascha Hauer @ 2012-07-10 18:54 ` Alexander Shiyan 2012-07-10 18:54 ` [PATCH 2/3] ARM: i.MX5x clocks: Fix parent for PWM clocks Alexander Shiyan 2012-07-10 18:54 ` [PATCH 3/3] ARM: i.MX5x clocks: Fix GPT clocks Alexander Shiyan 2 siblings, 0 replies; 12+ messages in thread From: Alexander Shiyan @ 2012-07-10 18:54 UTC (permalink / raw) To: linux-arm-kernel This patch adds support for Enhanced Periodic Interrupt Timer (EPIT) to clock subsystem. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> --- arch/arm/mach-imx/clk-imx51-imx53.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index a2200c7..d9cb79f 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -81,6 +81,7 @@ enum imx5_clks { ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred, ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate, ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, + epit1_ipg_gate, epit1_per_gate, epit2_ipg_gate, epit2_per_gate, clk_max }; @@ -226,6 +227,10 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26); clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28); clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30); + clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2); + clk[epit1_per_gate] = imx_clk_gate2("epit1_per_gate", "per_root", MXC_CCM_CCGR2, 4); + clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); + clk[epit2_per_gate] = imx_clk_gate2("epit2_per_gate", "per_root", MXC_CCM_CCGR2, 8); for (i = 0; i < ARRAY_SIZE(clk); i++) if (IS_ERR(clk[i])) @@ -279,6 +284,10 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, clk_register_clkdev(clk[dummy], NULL, "imx-keypad"); clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0"); clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0"); + clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0"); + clk_register_clkdev(clk[epit1_per_gate], "per", "imx-epit.0"); + clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1"); + clk_register_clkdev(clk[epit2_per_gate], "per", "imx-epit.1"); /* Set SDHC parents to be PLL2 */ clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]); -- 1.7.3.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/3] ARM: i.MX5x clocks: Fix parent for PWM clocks 2012-07-09 8:27 ` Sascha Hauer 2012-07-10 18:54 ` [PATCH 1/3] " Alexander Shiyan @ 2012-07-10 18:54 ` Alexander Shiyan 2012-07-11 6:50 ` Sascha Hauer 2012-07-10 18:54 ` [PATCH 3/3] ARM: i.MX5x clocks: Fix GPT clocks Alexander Shiyan 2 siblings, 1 reply; 12+ messages in thread From: Alexander Shiyan @ 2012-07-10 18:54 UTC (permalink / raw) To: linux-arm-kernel This patch also changes the names of the clocks to reflect the changes. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> --- arch/arm/mach-imx/clk-imx51-imx53.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index d9cb79f..50e6043 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -57,7 +57,7 @@ enum imx5_clks { usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di, tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate, uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate, - gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate, + gpt_ipg_gate, pwm1_ipg_gate, pwm1_per_gate, pwm2_ipg_gate, pwm2_per_gate, gpt_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate, esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate, ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate, @@ -170,9 +170,9 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 20); clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); - clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12); + clk[pwm1_per_gate] = imx_clk_gate2("pwm1_per_gate", "per_root", MXC_CCM_CCGR2, 12); clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); - clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16); + clk[pwm2_per_gate] = imx_clk_gate2("pwm2_per_gate", "per_root", MXC_CCM_CCGR2, 16); clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per_root", MXC_CCM_CCGR2, 18); clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); -- 1.7.3.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/3] ARM: i.MX5x clocks: Fix parent for PWM clocks 2012-07-10 18:54 ` [PATCH 2/3] ARM: i.MX5x clocks: Fix parent for PWM clocks Alexander Shiyan @ 2012-07-11 6:50 ` Sascha Hauer 2012-07-11 19:11 ` Re[2]: " Alexander Shiyan 0 siblings, 1 reply; 12+ messages in thread From: Sascha Hauer @ 2012-07-11 6:50 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jul 10, 2012 at 10:54:28PM +0400, Alexander Shiyan wrote: > This patch also changes the names of the clocks to reflect the changes. > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> > --- > arch/arm/mach-imx/clk-imx51-imx53.c | 6 +++--- > 1 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c > index d9cb79f..50e6043 100644 > --- a/arch/arm/mach-imx/clk-imx51-imx53.c > +++ b/arch/arm/mach-imx/clk-imx51-imx53.c > @@ -57,7 +57,7 @@ enum imx5_clks { > usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di, > tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate, > uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate, > - gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate, > + gpt_ipg_gate, pwm1_ipg_gate, pwm1_per_gate, pwm2_ipg_gate, pwm2_per_gate, > gpt_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate, > esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate, > ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate, > @@ -170,9 +170,9 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, > clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); > clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 20); > clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); > - clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12); > + clk[pwm1_per_gate] = imx_clk_gate2("pwm1_per_gate", "per_root", MXC_CCM_CCGR2, 12); > clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); > - clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16); > + clk[pwm2_per_gate] = imx_clk_gate2("pwm2_per_gate", "per_root", MXC_CCM_CCGR2, 16); We should stick more closely to the clock names in the datasheet inside the clock tree. Inside the clock tree the clock really is named 'hf'. This makes matching the code with the datasheet easier. So please resend this one with only the functional change included, no renaming. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re[2]: [PATCH 2/3] ARM: i.MX5x clocks: Fix parent for PWM clocks 2012-07-11 6:50 ` Sascha Hauer @ 2012-07-11 19:11 ` Alexander Shiyan 0 siblings, 0 replies; 12+ messages in thread From: Alexander Shiyan @ 2012-07-11 19:11 UTC (permalink / raw) To: linux-arm-kernel Hello. Wed, 11 Jul 2012 08:50:27 +0200 ?? Sascha Hauer <s.hauer@pengutronix.de>: On Tue, Jul 10, 2012 at 10:54:28PM +0400, Alexander Shiyan wrote: > This patch also changes the names of the clocks to reflect the changes.... We should stick more closely to the clock names in the datasheet inside the clock tree. Inside the clock tree the clock really is named 'hf'. This makes matching the code with the datasheet easier. So please resend this one with only the functional change included, no renaming.OK. I'll post all three fixed patch in a new thread later. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20120711/f2bfa3d8/attachment.html> ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/3] ARM: i.MX5x clocks: Fix GPT clocks 2012-07-09 8:27 ` Sascha Hauer 2012-07-10 18:54 ` [PATCH 1/3] " Alexander Shiyan 2012-07-10 18:54 ` [PATCH 2/3] ARM: i.MX5x clocks: Fix parent for PWM clocks Alexander Shiyan @ 2012-07-10 18:54 ` Alexander Shiyan 2012-07-11 6:44 ` Sascha Hauer 2 siblings, 1 reply; 12+ messages in thread From: Alexander Shiyan @ 2012-07-10 18:54 UTC (permalink / raw) To: linux-arm-kernel This patch fix incorrect defined bits for GPT clocks according to datasheet. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> --- arch/arm/mach-imx/clk-imx51-imx53.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 50e6043..628e940 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -58,7 +58,7 @@ enum imx5_clks { tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate, uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate, gpt_ipg_gate, pwm1_ipg_gate, pwm1_per_gate, pwm2_ipg_gate, pwm2_per_gate, - gpt_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate, + gpt_per_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate, esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate, ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate, ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s, @@ -168,12 +168,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16); clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18); clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); - clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 20); clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); clk[pwm1_per_gate] = imx_clk_gate2("pwm1_per_gate", "per_root", MXC_CCM_CCGR2, 12); clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); clk[pwm2_per_gate] = imx_clk_gate2("pwm2_per_gate", "per_root", MXC_CCM_CCGR2, 16); - clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per_root", MXC_CCM_CCGR2, 18); + clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18); + clk[gpt_per_gate] = imx_clk_gate2("gpt_per_gate", "per_root", MXC_CCM_CCGR2, 20); clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); @@ -237,7 +237,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, pr_err("i.MX5 clk %d: register failed with %ld\n", i, PTR_ERR(clk[i])); - clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); + clk_register_clkdev(clk[gpt_per_gate], "per", "imx-gpt.0"); clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0"); clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0"); clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); -- 1.7.3.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/3] ARM: i.MX5x clocks: Fix GPT clocks 2012-07-10 18:54 ` [PATCH 3/3] ARM: i.MX5x clocks: Fix GPT clocks Alexander Shiyan @ 2012-07-11 6:44 ` Sascha Hauer 2012-07-11 7:11 ` Re[2]: " Alexander Shiyan 0 siblings, 1 reply; 12+ messages in thread From: Sascha Hauer @ 2012-07-11 6:44 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jul 10, 2012 at 10:54:29PM +0400, Alexander Shiyan wrote: > This patch fix incorrect defined bits for GPT clocks according to > datasheet. Fix is a strong word. As I can see it these are only cosmetic changes without any functional change, right? Sascha > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> > --- > arch/arm/mach-imx/clk-imx51-imx53.c | 8 ++++---- > 1 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c > index 50e6043..628e940 100644 > --- a/arch/arm/mach-imx/clk-imx51-imx53.c > +++ b/arch/arm/mach-imx/clk-imx51-imx53.c > @@ -58,7 +58,7 @@ enum imx5_clks { > tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate, > uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate, > gpt_ipg_gate, pwm1_ipg_gate, pwm1_per_gate, pwm2_ipg_gate, pwm2_per_gate, > - gpt_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate, > + gpt_per_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate, > esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate, > ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate, > ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s, > @@ -168,12 +168,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, > clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16); > clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18); > clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); > - clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 20); > clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); > clk[pwm1_per_gate] = imx_clk_gate2("pwm1_per_gate", "per_root", MXC_CCM_CCGR2, 12); > clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); > clk[pwm2_per_gate] = imx_clk_gate2("pwm2_per_gate", "per_root", MXC_CCM_CCGR2, 16); > - clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per_root", MXC_CCM_CCGR2, 18); > + clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18); > + clk[gpt_per_gate] = imx_clk_gate2("gpt_per_gate", "per_root", MXC_CCM_CCGR2, 20); > clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); > clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); > clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); > @@ -237,7 +237,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, > pr_err("i.MX5 clk %d: register failed with %ld\n", > i, PTR_ERR(clk[i])); > > - clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); > + clk_register_clkdev(clk[gpt_per_gate], "per", "imx-gpt.0"); > clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0"); > clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0"); > clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); > -- > 1.7.3.4 > > -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re[2]: [PATCH 3/3] ARM: i.MX5x clocks: Fix GPT clocks 2012-07-11 6:44 ` Sascha Hauer @ 2012-07-11 7:11 ` Alexander Shiyan 2012-07-11 18:46 ` Sascha Hauer 0 siblings, 1 reply; 12+ messages in thread From: Alexander Shiyan @ 2012-07-11 7:11 UTC (permalink / raw) To: linux-arm-kernel Hello. Wed, 11 Jul 2012 08:44:06 +0200 ?? Sascha Hauer <s.hauer@pengutronix.de>: On Tue, Jul 10, 2012 at 10:54:29PM +0400, Alexander Shiyan wrote: > This patch fix incorrect defined bits for GPT clocks according to > datasheet. Fix is a strong word. As I can see it these are only cosmetic changes without any functional change, right?No. GPT bits for "per_root" and "ipg" was be swapped. IMX51RM says: CCGR2 Register Mapping ... 9 gpt_ipg_clk 10 gpt_highfreq ... > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> > --- > arch/arm/mach-imx/clk-imx51-imx53.c | 8 ++++---- > 1 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c > index 50e6043..628e940 100644 > --- a/arch/arm/mach-imx/clk-imx51-imx53.c > +++ b/arch/arm/mach-imx/clk-imx51-imx53.c > @@ -58,7 +58,7 @@ enum imx5_clks { > tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate, > uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate, > gpt_ipg_gate, pwm1_ipg_gate, pwm1_per_gate, pwm2_ipg_gate, pwm2_per_gate, > - gpt_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate, > + gpt_per_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate, > esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate, > ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate, > ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s, > @@ -168,12 +168,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, > clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16); > clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18); > clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); > - clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 20); > clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); > clk[pwm1_per_gate] = imx_clk_gate2("pwm1_per_gate", "per_root", MXC_CCM_CCGR2, 12); > clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); > clk[pwm2_per_gate] = imx_clk_gate2("pwm2_per_gate", "per_root", MXC_CCM_CCGR2, 16); > - clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per_root", MXC_CCM_CCGR2, 18); > + clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18); > + clk[gpt_per_gate] = imx_clk_gate2("gpt_per_gate", "per_root", MXC_CCM_CCGR2, 20); > clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); > clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); > clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); > @@ -237,7 +237,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, > pr_err("i.MX5 clk %d: register failed with %ld\n", > i, PTR_ERR(clk[i])); > > - clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); > + clk_register_clkdev(clk[gpt_per_gate], "per", "imx-gpt.0"); > clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0"); > clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0"); > clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); > -- > 1.7.3.4 > > -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20120711/bdce0273/attachment-0001.html> ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/3] ARM: i.MX5x clocks: Fix GPT clocks 2012-07-11 7:11 ` Re[2]: " Alexander Shiyan @ 2012-07-11 18:46 ` Sascha Hauer 0 siblings, 0 replies; 12+ messages in thread From: Sascha Hauer @ 2012-07-11 18:46 UTC (permalink / raw) To: linux-arm-kernel On Wed, Jul 11, 2012 at 11:11:39AM +0400, Alexander Shiyan wrote: > Hello. > > > Wed, 11 Jul 2012 08:44:06 +0200 ?? Sascha Hauer <s.hauer@pengutronix.de>: > On Tue, Jul 10, 2012 at 10:54:29PM +0400, Alexander Shiyan wrote: > > This patch fix incorrect defined bits for GPT clocks according to > > datasheet. > > Fix is a strong word. As I can see it these are only cosmetic changes > without any functional change, right? > No. GPT bits for "per_root" and "ipg" was be swapped. IMX51RM says: > CCGR2 Register Mappingi > ... > 9 gpt_ipg_clk > 10 gpt_highfreq Ah, ok. So it seems clk_get_rate will return the correct clock, but the clk_enable() is mixed for both clocks. In this case I think this can wait for the merge window since the current code will enable both clocks anyway. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2012-07-11 19:11 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2012-06-27 7:08 [PATCH 1/2] ARM: i.MX5x clocks: Add EPIT support Alexander Shiyan 2012-06-27 7:08 ` [PATCH 2/2] ARM: i.MX51 iomux: added missing pin definitions Alexander Shiyan 2012-07-02 9:26 ` [PATCH 1/2] ARM: i.MX5x clocks: Add EPIT support Sascha Hauer 2012-07-09 8:27 ` Sascha Hauer 2012-07-10 18:54 ` [PATCH 1/3] " Alexander Shiyan 2012-07-10 18:54 ` [PATCH 2/3] ARM: i.MX5x clocks: Fix parent for PWM clocks Alexander Shiyan 2012-07-11 6:50 ` Sascha Hauer 2012-07-11 19:11 ` Re[2]: " Alexander Shiyan 2012-07-10 18:54 ` [PATCH 3/3] ARM: i.MX5x clocks: Fix GPT clocks Alexander Shiyan 2012-07-11 6:44 ` Sascha Hauer 2012-07-11 7:11 ` Re[2]: " Alexander Shiyan 2012-07-11 18:46 ` Sascha Hauer
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