[PATCH 1/6] ARM: DTS: SPEAr13xx: Fix Interrupt bindings

[PATCH 1/6] ARM: DTS: SPEAr13xx: Fix Interrupt bindings

[Shiraz Hashim]

From: Vipul Kumar Samar <vipulkumar.samar@st.com>

   - Fix interrupt bindings for uart, ethernet and pmu.
   - Add interrupt binding for keyboard.

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
---
 arch/arm/boot/dts/spear13xx.dtsi |   11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 10dcec7..f7b84ac 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -43,8 +43,8 @@
 
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
-		interrupts = <0 8 0x04
-			      0 9 0x04>;
+		interrupts = <0 6 0x04
+			      0 7 0x04>;
 	};
 
 	L2: l2-cache {
@@ -119,8 +119,8 @@
 		gmac0: eth at e2000000 {
 			compatible = "st,spear600-gmac";
 			reg = <0xe2000000 0x8000>;
-			interrupts = <0 23 0x4
-				      0 24 0x4>;
+			interrupts = <0 33 0x4
+				      0 34 0x4>;
 			interrupt-names = "macirq", "eth_wake_irq";
 			status = "disabled";
 		};
@@ -202,6 +202,7 @@
 			kbd at e0300000 {
 				compatible = "st,spear300-kbd";
 				reg = <0xe0300000 0x1000>;
+				interrupts = <0 52 0x4>;
 				status = "disabled";
 			};
 
@@ -224,7 +225,7 @@
 			serial at e0000000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0xe0000000 0x1000>;
-				interrupts = <0 36 0x4>;
+				interrupts = <0 35 0x4>;
 				status = "disabled";
 			};
 
-- 
1.7.10

[PATCH 2/6] clk: SPEAr1340: Fix clk enable register for uart1 and i2c1.

[Shiraz Hashim]

From: Vipul Kumar Samar <vipulkumar.samar@st.com>

This patch is to fix typing mistake of clk enable register of i2c1 and uart1.

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
---
 drivers/clk/spear/spear1340_clock.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index e3ea721..d77f54f 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -619,7 +619,7 @@ void __init spear1340_clk_init(void)
 	clk_register_clkdev(clk, "uart1_mux_clk", NULL);
 
 	clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0,
-			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
+			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
 			&_lock);
 	clk_register_clkdev(clk, NULL, "b4100000.serial");
 
@@ -744,7 +744,7 @@ void __init spear1340_clk_init(void)
 	clk_register_clkdev(clk, NULL, "e0280000.i2c");
 
 	clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
-			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
+			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
 			&_lock);
 	clk_register_clkdev(clk, NULL, "b4000000.i2c");
 
-- 
1.7.10

[PATCH 3/6] clk: SPEAr13xx: Add localtimer (twd) clock support

[Shiraz Hashim]

From: Vipul Kumar Samar <vipulkumar.samar@st.com>

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
---
 drivers/clk/spear/spear1310_clock.c |    4 ++++
 drivers/clk/spear/spear1340_clock.c |    4 ++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 8f05652..3a246b4 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -491,6 +491,10 @@ void __init spear1310_clk_init(void)
 			2);
 	clk_register_clkdev(clk, NULL, "ec800620.wdt");
 
+	clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
+			2);
+	clk_register_clkdev(clk, NULL, "smp_twd");
+
 	clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
 			6);
 	clk_register_clkdev(clk, "ahb_clk", NULL);
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index d77f54f..a7d5d32 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -537,6 +537,10 @@ void __init spear1340_clk_init(void)
 			2);
 	clk_register_clkdev(clk, NULL, "ec800620.wdt");
 
+	clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
+			2);
+	clk_register_clkdev(clk, NULL, "smp_twd");
+
 	clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
 			ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL,
 			SPEAR1340_HCLK_SRC_SEL_SHIFT,
-- 
1.7.10

[PATCH 4/6] Clk: SPEAr13xx: Initialize con_id for Ethernet phy clks

[Shiraz Hashim]

From: Vipul Kumar Samar <vipulkumar.samar@st.com>

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
---
 drivers/clk/spear/spear1310_clock.c |   10 +++++-----
 drivers/clk/spear/spear1340_clock.c |    2 +-
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 3a246b4..b6a6325 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -621,7 +621,7 @@ void __init spear1310_clk_init(void)
 			ARRAY_SIZE(gmac_phy_parents), 0,
 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
 			SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
-	clk_register_clkdev(clk, NULL, "stmmacphy.0");
+	clk_register_clkdev(clk, "stmmacphy.0", NULL);
 
 	/* clcd */
 	clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
@@ -922,15 +922,15 @@ void __init spear1310_clk_init(void)
 			SPEAR1310_RAS_CTRL_REG1,
 			SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
 			SPEAR1310_PHY_CLK_MASK, 0, &_lock);
-	clk_register_clkdev(clk, NULL, "stmmacphy.1");
-	clk_register_clkdev(clk, NULL, "stmmacphy.2");
-	clk_register_clkdev(clk, NULL, "stmmacphy.4");
+	clk_register_clkdev(clk, "stmmacphy.1", NULL);
+	clk_register_clkdev(clk, "stmmacphy.2", NULL);
+	clk_register_clkdev(clk, "stmmacphy.4", NULL);
 
 	clk = clk_register_mux(NULL, "rmii_phy_mux_clk", rmii_phy_parents,
 			ARRAY_SIZE(rmii_phy_parents), 0,
 			SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
 			SPEAR1310_PHY_CLK_MASK, 0, &_lock);
-	clk_register_clkdev(clk, NULL, "stmmacphy.3");
+	clk_register_clkdev(clk, "stmmacphy.3", NULL);
 
 	clk = clk_register_mux(NULL, "uart1_mux_clk", uart_parents,
 			ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index a7d5d32..e69c542 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -686,7 +686,7 @@ void __init spear1340_clk_init(void)
 			ARRAY_SIZE(gmac_phy_parents), 0,
 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
 			SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
-	clk_register_clkdev(clk, NULL, "stmmacphy.0");
+	clk_register_clkdev(clk, "stmmacphy.0", NULL);
 
 	/* clcd */
 	clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
-- 
1.7.10

[PATCH 5/6] Clk: SPEAr1340: fix sys clock parent source and corresponding mask value

[Shiraz Hashim]

From: Vipul Kumar Samar <vipulkumar.samar@st.com>

sys_clk have multiple parents and selection of parent is depends on
sys_clk_ctrl register (bit no. 23:25) with possible values,

   0XX: pll1_clk
   10X: sys_synth_clk
   110: pll2_clk
   111: pll3_clk

Update sys_clk parent array accordingly (ex. 0:3-pll1_clk) and
fix mask value to 7.

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
---
 drivers/clk/spear/spear1340_clock.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index e69c542..b3b56de 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -25,7 +25,7 @@
 	#define SPEAR1340_HCLK_SRC_SEL_SHIFT	27
 	#define SPEAR1340_HCLK_SRC_SEL_MASK	1
 	#define SPEAR1340_SCLK_SRC_SEL_SHIFT	23
-	#define SPEAR1340_SCLK_SRC_SEL_MASK	3
+	#define SPEAR1340_SCLK_SRC_SEL_MASK	7
 
 /* PLL related registers and bit values */
 #define SPEAR1340_PLL_CFG			(VA_MISC_BASE + 0x210)
@@ -369,8 +369,8 @@ static struct frac_rate_tbl gen_rtbl[] = {
 
 /* clock parents */
 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
-static const char *sys_parents[] = { "none", "pll1_clk", "none", "none",
-	"sys_synth_clk", "none", "pll2_clk", "pll3_clk", };
+static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
+	"pll1_clk", "sys_synth_clk", "sys_synth_clk", "pll2_clk", "pll3_clk", };
 static const char *ahb_parents[] = { "cpu_div3_clk", "amba_synth_clk", };
 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
 static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
-- 
1.7.10

[PATCH 1/6] ARM: DTS: SPEAr13xx: Fix Interrupt bindings

[viresh kumar]

On Mon, Jul 9, 2012 at 11:31 AM, Shiraz Hashim <shiraz.hashim@st.com> wrote:
> From: Vipul Kumar Samar <vipulkumar.samar@st.com>
>
>    - Fix interrupt bindings for uart, ethernet and pmu.
>    - Add interrupt binding for keyboard.
>
> Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>

Ahh.. Sorry for pushing wrong values in my initial patches.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

[PATCH 2/6] clk: SPEAr1340: Fix clk enable register for uart1 and i2c1.

[viresh kumar]

On Mon, Jul 9, 2012 at 11:31 AM, Shiraz Hashim <shiraz.hashim@st.com> wrote:
> From: Vipul Kumar Samar <vipulkumar.samar@st.com>
>
> This patch is to fix typing mistake of clk enable register of i2c1 and uart1.
>
> Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
> ---
>  drivers/clk/spear/spear1340_clock.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
> index e3ea721..d77f54f 100644
> --- a/drivers/clk/spear/spear1340_clock.c
> +++ b/drivers/clk/spear/spear1340_clock.c
> @@ -619,7 +619,7 @@ void __init spear1340_clk_init(void)
>         clk_register_clkdev(clk, "uart1_mux_clk", NULL);
>
>         clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0,
> -                       SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
> +                       SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
>                         &_lock);
>         clk_register_clkdev(clk, NULL, "b4100000.serial");
>
> @@ -744,7 +744,7 @@ void __init spear1340_clk_init(void)
>         clk_register_clkdev(clk, NULL, "e0280000.i2c");
>
>         clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
> -                       SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
> +                       SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
>                         &_lock);
>         clk_register_clkdev(clk, NULL, "b4000000.i2c");

:(

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

[PATCH 3/6] clk: SPEAr13xx: Add localtimer (twd) clock support

[viresh kumar]

On Mon, Jul 9, 2012 at 11:31 AM, Shiraz Hashim <shiraz.hashim@st.com> wrote:
> From: Vipul Kumar Samar <vipulkumar.samar@st.com>
>
> Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
> ---
>  drivers/clk/spear/spear1310_clock.c |    4 ++++
>  drivers/clk/spear/spear1340_clock.c |    4 ++++
>  2 files changed, 8 insertions(+)
>
> diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
> index 8f05652..3a246b4 100644
> --- a/drivers/clk/spear/spear1310_clock.c
> +++ b/drivers/clk/spear/spear1310_clock.c
> @@ -491,6 +491,10 @@ void __init spear1310_clk_init(void)
>                         2);
>         clk_register_clkdev(clk, NULL, "ec800620.wdt");
>
> +       clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
> +                       2);
> +       clk_register_clkdev(clk, NULL, "smp_twd");
> +
>         clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
>                         6);
>         clk_register_clkdev(clk, "ahb_clk", NULL);
> diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
> index d77f54f..a7d5d32 100644
> --- a/drivers/clk/spear/spear1340_clock.c
> +++ b/drivers/clk/spear/spear1340_clock.c
> @@ -537,6 +537,10 @@ void __init spear1340_clk_init(void)
>                         2);
>         clk_register_clkdev(clk, NULL, "ec800620.wdt");
>
> +       clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
> +                       2);
> +       clk_register_clkdev(clk, NULL, "smp_twd");
> +
>         clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
>                         ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL,
>                         SPEAR1340_HCLK_SRC_SEL_SHIFT,

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

[PATCH 4/6] Clk: SPEAr13xx: Initialize con_id for Ethernet phy clks

[viresh kumar]

On Mon, Jul 9, 2012 at 11:31 AM, Shiraz Hashim <shiraz.hashim@st.com> wrote:
> From: Vipul Kumar Samar <vipulkumar.samar@st.com>
>

Must have some lines here.

> Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
> ---
>  drivers/clk/spear/spear1310_clock.c |   10 +++++-----
>  drivers/clk/spear/spear1340_clock.c |    2 +-
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
> index 3a246b4..b6a6325 100644
> --- a/drivers/clk/spear/spear1310_clock.c
> +++ b/drivers/clk/spear/spear1310_clock.c
> @@ -621,7 +621,7 @@ void __init spear1310_clk_init(void)
>                         ARRAY_SIZE(gmac_phy_parents), 0,
>                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
>                         SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
> -       clk_register_clkdev(clk, NULL, "stmmacphy.0");
> +       clk_register_clkdev(clk, "stmmacphy.0", NULL);
>
>         /* clcd */
>         clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
> @@ -922,15 +922,15 @@ void __init spear1310_clk_init(void)
>                         SPEAR1310_RAS_CTRL_REG1,
>                         SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
>                         SPEAR1310_PHY_CLK_MASK, 0, &_lock);
> -       clk_register_clkdev(clk, NULL, "stmmacphy.1");
> -       clk_register_clkdev(clk, NULL, "stmmacphy.2");
> -       clk_register_clkdev(clk, NULL, "stmmacphy.4");
> +       clk_register_clkdev(clk, "stmmacphy.1", NULL);
> +       clk_register_clkdev(clk, "stmmacphy.2", NULL);
> +       clk_register_clkdev(clk, "stmmacphy.4", NULL);
>
>         clk = clk_register_mux(NULL, "rmii_phy_mux_clk", rmii_phy_parents,
>                         ARRAY_SIZE(rmii_phy_parents), 0,
>                         SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
>                         SPEAR1310_PHY_CLK_MASK, 0, &_lock);
> -       clk_register_clkdev(clk, NULL, "stmmacphy.3");
> +       clk_register_clkdev(clk, "stmmacphy.3", NULL);
>
>         clk = clk_register_mux(NULL, "uart1_mux_clk", uart_parents,
>                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
> diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
> index a7d5d32..e69c542 100644
> --- a/drivers/clk/spear/spear1340_clock.c
> +++ b/drivers/clk/spear/spear1340_clock.c
> @@ -686,7 +686,7 @@ void __init spear1340_clk_init(void)
>                         ARRAY_SIZE(gmac_phy_parents), 0,
>                         SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
>                         SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
> -       clk_register_clkdev(clk, NULL, "stmmacphy.0");
> +       clk_register_clkdev(clk, "stmmacphy.0", NULL);
>
>         /* clcd */
>         clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

[PATCH 5/6] Clk: SPEAr1340: fix sys clock parent source and corresponding mask value

[viresh kumar]

On Mon, Jul 9, 2012 at 11:31 AM, Shiraz Hashim <shiraz.hashim@st.com> wrote:
> From: Vipul Kumar Samar <vipulkumar.samar@st.com>
>
> sys_clk have multiple parents and selection of parent is depends on

s/ is//

> sys_clk_ctrl register (bit no. 23:25) with possible values,
>
>    0XX: pll1_clk
>    10X: sys_synth_clk
>    110: pll2_clk
>    111: pll3_clk
>
> Update sys_clk parent array accordingly (ex. 0:3-pll1_clk) and
> fix mask value to 7.
>
> Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
> ---
>  drivers/clk/spear/spear1340_clock.c |    6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
> index e69c542..b3b56de 100644
> --- a/drivers/clk/spear/spear1340_clock.c
> +++ b/drivers/clk/spear/spear1340_clock.c
> @@ -25,7 +25,7 @@
>         #define SPEAR1340_HCLK_SRC_SEL_SHIFT    27
>         #define SPEAR1340_HCLK_SRC_SEL_MASK     1
>         #define SPEAR1340_SCLK_SRC_SEL_SHIFT    23
> -       #define SPEAR1340_SCLK_SRC_SEL_MASK     3
> +       #define SPEAR1340_SCLK_SRC_SEL_MASK     7

AFAICR, Mask represents number of bits and not the actual mask.
Can you check that again?

>  /* PLL related registers and bit values */
>  #define SPEAR1340_PLL_CFG                      (VA_MISC_BASE + 0x210)
> @@ -369,8 +369,8 @@ static struct frac_rate_tbl gen_rtbl[] = {
>
>  /* clock parents */
>  static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
> -static const char *sys_parents[] = { "none", "pll1_clk", "none", "none",
> -       "sys_synth_clk", "none", "pll2_clk", "pll3_clk", };
> +static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
> +       "pll1_clk", "sys_synth_clk", "sys_synth_clk", "pll2_clk", "pll3_clk", };

Don't know what would be the implication of this?

@Mike: Can you please tell us what should we do in such cases?

--
viresh

[PATCH 6/6] ARM: SPEAr13xx: Add auxdata for Ethernet controller.

[Shiraz Hashim]

From: Vipul Kumar Samar <vipulkumar.samar@st.com>

Ethernet phy interface on SPEAr platform requires proper clock sources
and clock rate to be configured. We use AUXDATA presently to pass
callback to the driver to let platform configure the right clocks.

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
---
 arch/arm/mach-spear13xx/include/mach/generic.h |    2 +
 arch/arm/mach-spear13xx/include/mach/spear.h   |    3 +
 arch/arm/mach-spear13xx/spear1340.c            |   32 +++++++++
 arch/arm/mach-spear13xx/spear13xx.c            |   85 ++++++++++++++++++++++++
 4 files changed, 122 insertions(+)

diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index dac57fd..8c8fbaa 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -15,6 +15,7 @@
 #define __MACH_GENERIC_H
 
 #include <linux/dmaengine.h>
+#include <linux/platform_device.h>
 #include <asm/mach/time.h>
 
 /* Add spear13xx structure declarations here */
@@ -31,6 +32,7 @@ void __init spear13xx_map_io(void);
 void __init spear13xx_dt_init_irq(void);
 void __init spear13xx_l2x0_init(void);
 bool dw_dma_filter(struct dma_chan *chan, void *slave);
+int spear13xx_eth_phy_clk_cfg(struct platform_device *pdev);
 void spear_restart(char, const char *);
 void spear13xx_secondary_startup(void);
 
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index 65f27de..0ce064b 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -59,4 +59,7 @@
 #define SPEAR_DBG_UART_BASE			UART_BASE
 #define VA_SPEAR_DBG_UART_BASE			VA_UART_BASE
 
+/* Ethernet base address */
+#define SPEAR13XX_GETH_BASE			UL(0xE2000000)
+
 #endif /* __MACH_SPEAR13XX_H */
diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c
index 81e4ed7..ab282ed 100644
--- a/arch/arm/mach-spear13xx/spear1340.c
+++ b/arch/arm/mach-spear13xx/spear1340.c
@@ -18,6 +18,9 @@
 #include <linux/delay.h>
 #include <linux/dw_dmac.h>
 #include <linux/of_platform.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/stmmac.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <mach/dma.h>
@@ -100,6 +103,34 @@ static struct amba_pl011_data uart1_data = {
 	.dma_rx_param = &uart1_dma_param[1],
 };
 
+/* Ethernet platform data */
+static struct stmmac_mdio_bus_data mdio0_private_data = {
+	.bus_id = 0,
+	.phy_mask = 0,
+};
+
+static struct stmmac_dma_cfg dma0_private_data = {
+	.pbl = 16,
+	.fixed_burst = 1,
+	.burst_len = DMA_AXI_BLEN_ALL,
+};
+
+static struct plat_stmmacenet_data eth_data = {
+	.bus_id = 0,
+	.phy_addr = -1,
+	.interface = PHY_INTERFACE_MODE_RGMII,
+	.has_gmac = 1,
+	.enh_desc = 1,
+	.tx_coe = 1,
+	.dma_cfg = &dma0_private_data,
+	.rx_coe = STMMAC_RX_COE_TYPE2,
+	.bugged_jumbo = 1,
+	.pmt = 1,
+	.mdio_bus_data = &mdio0_private_data,
+	.init = spear13xx_eth_phy_clk_cfg,
+	.clk_csr = STMMAC_CSR_150_250M,
+};
+
 /* SATA device registration */
 static int sata_miphy_init(struct device *dev, void __iomem *addr)
 {
@@ -166,6 +197,7 @@ static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
 			&sata_pdata),
 	OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data),
+	OF_DEV_AUXDATA("st,spear600-gmac", SPEAR13XX_GETH_BASE, NULL, &eth_data),
 	{}
 };
 
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index cf936b1..285948a 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -18,6 +18,9 @@
 #include <linux/dw_dmac.h>
 #include <linux/err.h>
 #include <linux/of_irq.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/stmmac.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
@@ -80,6 +83,88 @@ struct dw_dma_platform_data dmac_plat_data = {
 	.chan_priority = CHAN_PRIORITY_DESCENDING,
 };
 
+/* Ethernet clock initialization */
+int spear13xx_eth_phy_clk_cfg(struct platform_device *pdev)
+{
+	int ret;
+	struct clk *input_clk, *input_pclk, *phy_pclk, *phy_clk;
+	struct plat_stmmacenet_data *pdata = dev_get_platdata(&pdev->dev);
+	const char *phy_clk_src_name[] = {
+		"phy_input_mclk",
+		"phy_synth_gclk",
+	};
+	const char *input_clk_src_name[] = {
+		"pll2_clk",
+		"gmii_pad_clk",
+		"osc_25m_clk",
+	};
+	const char *phy_clk_name[] = {
+		"stmmacphy.0"
+	};
+
+	if (pdata == NULL)
+		return -EINVAL;
+
+	/* Get the Pll-2 Clock as parent for PHY Input Clock Source */
+	input_pclk = clk_get(NULL, input_clk_src_name[0]);
+	if (IS_ERR(input_pclk)) {
+		ret = PTR_ERR(input_pclk);
+		goto fail_get_input_pclk;
+	}
+
+	/*
+	 * Get the Phy Input clock source as parent for Phy clock. Default
+	 * selection is gmac_phy_input_clk. This selection would be driving both
+	 * the synthesizer and phy clock.
+	 */
+	input_clk = clk_get(NULL, phy_clk_src_name[0]);
+	if (IS_ERR(input_clk)) {
+		ret = PTR_ERR(input_clk);
+		goto fail_get_input_clk;
+	}
+
+	/* Fetch the phy clock */
+	phy_clk = clk_get(NULL, phy_clk_name[pdata->bus_id]);
+	if (IS_ERR(phy_clk)) {
+		ret = PTR_ERR(phy_clk);
+		goto fail_get_phy_clk;
+	}
+
+	/* Set the pll-2 to 125 MHz */
+	clk_set_rate(input_pclk, 125000000);
+
+	/* Set the Pll-2 as parent for gmac_phy_input_clk */
+	clk_set_parent(input_clk, input_pclk);
+
+	if (pdata->interface == PHY_INTERFACE_MODE_RMII) {
+		/*
+		 * For the rmii interface select gmac_phy_synth_clk
+		 * as the parent and set the clock to 50 Mhz
+		 */
+		phy_pclk = clk_get(NULL, phy_clk_src_name[1]);
+		clk_set_rate(phy_pclk, 50000000);
+	} else {
+		/*
+		 * Set the gmac_phy_input_clk as the parent,
+		 * and pll-2 is already running as parent of
+		 * gmac_phy_input_clk at 125 Mhz
+		 */
+		phy_pclk = input_clk;
+	}
+
+	/* Select the parent for phy clock */
+	clk_set_parent(phy_clk, phy_pclk);
+	ret = clk_prepare_enable(phy_clk);
+
+	return ret;
+fail_get_phy_clk:
+	clk_put(input_clk);
+fail_get_input_clk:
+	clk_put(input_pclk);
+fail_get_input_pclk:
+	return ret;
+}
+
 void __init spear13xx_l2x0_init(void)
 {
 	/*
-- 
1.7.10

[PATCH 6/6] ARM: SPEAr13xx: Add auxdata for Ethernet controller.

[viresh kumar]

On Mon, Jul 9, 2012 at 12:18 PM, Shiraz Hashim <shiraz.hashim@st.com> wrote:
> From: Vipul Kumar Samar <vipulkumar.samar@st.com>
>
> Ethernet phy interface on SPEAr platform requires proper clock sources
> and clock rate to be configured. We use AUXDATA presently to pass
> callback to the driver to let platform configure the right clocks.
>
> Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
> ---
>  arch/arm/mach-spear13xx/include/mach/generic.h |    2 +
>  arch/arm/mach-spear13xx/include/mach/spear.h   |    3 +
>  arch/arm/mach-spear13xx/spear1340.c            |   32 +++++++++
>  arch/arm/mach-spear13xx/spear13xx.c            |   85 ++++++++++++++++++++++++
>  4 files changed, 122 insertions(+)
>
> diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
> index dac57fd..8c8fbaa 100644
> --- a/arch/arm/mach-spear13xx/include/mach/generic.h
> +++ b/arch/arm/mach-spear13xx/include/mach/generic.h
> @@ -15,6 +15,7 @@
>  #define __MACH_GENERIC_H
>
>  #include <linux/dmaengine.h>
> +#include <linux/platform_device.h>
>  #include <asm/mach/time.h>
>
>  /* Add spear13xx structure declarations here */
> @@ -31,6 +32,7 @@ void __init spear13xx_map_io(void);
>  void __init spear13xx_dt_init_irq(void);
>  void __init spear13xx_l2x0_init(void);
>  bool dw_dma_filter(struct dma_chan *chan, void *slave);
> +int spear13xx_eth_phy_clk_cfg(struct platform_device *pdev);

don't really need spear13xx_ prefix here. It is obviously for 13xx.

>  void spear_restart(char, const char *);
>  void spear13xx_secondary_startup(void);
>
> diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
> index 65f27de..0ce064b 100644
> --- a/arch/arm/mach-spear13xx/include/mach/spear.h
> +++ b/arch/arm/mach-spear13xx/include/mach/spear.h
> @@ -59,4 +59,7 @@
>  #define SPEAR_DBG_UART_BASE                    UART_BASE
>  #define VA_SPEAR_DBG_UART_BASE                 VA_UART_BASE
>
> +/* Ethernet base address */

Comment not required.

> +#define SPEAR13XX_GETH_BASE                    UL(0xE2000000)
> +
>  #endif /* __MACH_SPEAR13XX_H */
> diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c
> index 81e4ed7..ab282ed 100644
> --- a/arch/arm/mach-spear13xx/spear1340.c
> +++ b/arch/arm/mach-spear13xx/spear1340.c
> @@ -18,6 +18,9 @@
>  #include <linux/delay.h>
>  #include <linux/dw_dmac.h>
>  #include <linux/of_platform.h>
> +#include <linux/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/stmmac.h>
>  #include <asm/hardware/gic.h>
>  #include <asm/mach/arch.h>
>  #include <mach/dma.h>
> @@ -100,6 +103,34 @@ static struct amba_pl011_data uart1_data = {
>         .dma_rx_param = &uart1_dma_param[1],
>  };
>
> +/* Ethernet platform data */
> +static struct stmmac_mdio_bus_data mdio0_private_data = {
> +       .bus_id = 0,
> +       .phy_mask = 0,
> +};
> +
> +static struct stmmac_dma_cfg dma0_private_data = {
> +       .pbl = 16,
> +       .fixed_burst = 1,
> +       .burst_len = DMA_AXI_BLEN_ALL,
> +};
> +
> +static struct plat_stmmacenet_data eth_data = {
> +       .bus_id = 0,
> +       .phy_addr = -1,
> +       .interface = PHY_INTERFACE_MODE_RGMII,
> +       .has_gmac = 1,
> +       .enh_desc = 1,
> +       .tx_coe = 1,
> +       .dma_cfg = &dma0_private_data,
> +       .rx_coe = STMMAC_RX_COE_TYPE2,
> +       .bugged_jumbo = 1,
> +       .pmt = 1,
> +       .mdio_bus_data = &mdio0_private_data,
> +       .init = spear13xx_eth_phy_clk_cfg,
> +       .clk_csr = STMMAC_CSR_150_250M,
> +};
> +
>  /* SATA device registration */
>  static int sata_miphy_init(struct device *dev, void __iomem *addr)
>  {
> @@ -166,6 +197,7 @@ static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
>         OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
>                         &sata_pdata),
>         OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data),
> +       OF_DEV_AUXDATA("st,spear600-gmac", SPEAR13XX_GETH_BASE, NULL, &eth_data),
>         {}
>  };
>
> diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
> index cf936b1..285948a 100644
> --- a/arch/arm/mach-spear13xx/spear13xx.c
> +++ b/arch/arm/mach-spear13xx/spear13xx.c
> @@ -18,6 +18,9 @@
>  #include <linux/dw_dmac.h>
>  #include <linux/err.h>
>  #include <linux/of_irq.h>
> +#include <linux/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/stmmac.h>
>  #include <asm/hardware/cache-l2x0.h>
>  #include <asm/hardware/gic.h>
>  #include <asm/mach/map.h>
> @@ -80,6 +83,88 @@ struct dw_dma_platform_data dmac_plat_data = {
>         .chan_priority = CHAN_PRIORITY_DESCENDING,
>  };
>
> +/* Ethernet clock initialization */
> +int spear13xx_eth_phy_clk_cfg(struct platform_device *pdev)
> +{
> +       int ret;
> +       struct clk *input_clk, *input_pclk, *phy_pclk, *phy_clk;
> +       struct plat_stmmacenet_data *pdata = dev_get_platdata(&pdev->dev);
> +       const char *phy_clk_src_name[] = {
> +               "phy_input_mclk",
> +               "phy_synth_gclk",
> +       };
> +       const char *input_clk_src_name[] = {
> +               "pll2_clk",
> +               "gmii_pad_clk",
> +               "osc_25m_clk",
> +       };
> +       const char *phy_clk_name[] = {
> +               "stmmacphy.0"
> +       };
> +
> +       if (pdata == NULL)

if (!pdata)

> +               return -EINVAL;
> +
> +       /* Get the Pll-2 Clock as parent for PHY Input Clock Source */
> +       input_pclk = clk_get(NULL, input_clk_src_name[0]);
> +       if (IS_ERR(input_pclk)) {
> +               ret = PTR_ERR(input_pclk);
> +               goto fail_get_input_pclk;
> +       }
> +
> +       /*
> +        * Get the Phy Input clock source as parent for Phy clock. Default
> +        * selection is gmac_phy_input_clk. This selection would be driving both
> +        * the synthesizer and phy clock.
> +        */
> +       input_clk = clk_get(NULL, phy_clk_src_name[0]);
> +       if (IS_ERR(input_clk)) {
> +               ret = PTR_ERR(input_clk);
> +               goto fail_get_input_clk;
> +       }
> +
> +       /* Fetch the phy clock */
> +       phy_clk = clk_get(NULL, phy_clk_name[pdata->bus_id]);
> +       if (IS_ERR(phy_clk)) {
> +               ret = PTR_ERR(phy_clk);
> +               goto fail_get_phy_clk;
> +       }
> +
> +       /* Set the pll-2 to 125 MHz */
> +       clk_set_rate(input_pclk, 125000000);
> +
> +       /* Set the Pll-2 as parent for gmac_phy_input_clk */
> +       clk_set_parent(input_clk, input_pclk);

Above two calls can potentially fail.

> +
> +       if (pdata->interface == PHY_INTERFACE_MODE_RMII) {
> +               /*
> +                * For the rmii interface select gmac_phy_synth_clk
> +                * as the parent and set the clock to 50 Mhz
> +                */
> +               phy_pclk = clk_get(NULL, phy_clk_src_name[1]);
> +               clk_set_rate(phy_pclk, 50000000);
> +       } else {
> +               /*
> +                * Set the gmac_phy_input_clk as the parent,
> +                * and pll-2 is already running as parent of
> +                * gmac_phy_input_clk at 125 Mhz
> +                */
> +               phy_pclk = input_clk;
> +       }
> +
> +       /* Select the parent for phy clock */
> +       clk_set_parent(phy_clk, phy_pclk);

same here.

--
viresh

[PATCH 5/6] Clk: SPEAr1340: fix sys clock parent source and corresponding mask value

[vipul kumar samar]

On 7/9/2012 4:34 PM, viresh kumar wrote:
> On Mon, Jul 9, 2012 at 11:31 AM, Shiraz Hashim<shiraz.hashim@st.com>  wrote:
>> From: Vipul Kumar Samar<vipulkumar.samar@st.com>
>>
>> sys_clk have multiple parents and selection of parent is depends on
>
> s/ is//
>
>> sys_clk_ctrl register (bit no. 23:25) with possible values,
>>
>>     0XX: pll1_clk
>>     10X: sys_synth_clk
>>     110: pll2_clk
>>     111: pll3_clk
>>
>> Update sys_clk parent array accordingly (ex. 0:3-pll1_clk) and
>> fix mask value to 7.
>>
>> Signed-off-by: Vipul Kumar Samar<vipulkumar.samar@st.com>
>> ---
>>   drivers/clk/spear/spear1340_clock.c |    6 +++---
>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
>> index e69c542..b3b56de 100644
>> --- a/drivers/clk/spear/spear1340_clock.c
>> +++ b/drivers/clk/spear/spear1340_clock.c
>> @@ -25,7 +25,7 @@
>>          #define SPEAR1340_HCLK_SRC_SEL_SHIFT    27
>>          #define SPEAR1340_HCLK_SRC_SEL_MASK     1
>>          #define SPEAR1340_SCLK_SRC_SEL_SHIFT    23
>> -       #define SPEAR1340_SCLK_SRC_SEL_MASK     3
>> +       #define SPEAR1340_SCLK_SRC_SEL_MASK     7
>
> AFAICR, Mask represents number of bits and not the actual mask.
> Can you check that again?

Sorry, i'll correct it.

>
>>   /* PLL related registers and bit values */
>>   #define SPEAR1340_PLL_CFG                      (VA_MISC_BASE + 0x210)
>> @@ -369,8 +369,8 @@ static struct frac_rate_tbl gen_rtbl[] = {
>>
>>   /* clock parents */
>>   static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
>> -static const char *sys_parents[] = { "none", "pll1_clk", "none", "none",
>> -       "sys_synth_clk", "none", "pll2_clk", "pll3_clk", };
>> +static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
>> +       "pll1_clk", "sys_synth_clk", "sys_synth_clk", "pll2_clk", "pll3_clk", };
>
> Don't know what would be the implication of this?
>
> @Mike: Can you please tell us what should we do in such cases?
>

Is there any other solution for such cases ???

Regards
Vipul Samar

[PATCH 6/6] ARM: SPEAr13xx: Add auxdata for Ethernet controller.

[vipul kumar samar]

On 7/9/2012 5:00 PM, viresh kumar wrote:
> On Mon, Jul 9, 2012 at 12:18 PM, Shiraz Hashim<shiraz.hashim@st.com>  wrote:
>> From: Vipul Kumar Samar<vipulkumar.samar@st.com>
>>
>> Ethernet phy interface on SPEAr platform requires proper clock sources
>> and clock rate to be configured. We use AUXDATA presently to pass
>> callback to the driver to let platform configure the right clocks.
>>
>> Signed-off-by: Vipul Kumar Samar<vipulkumar.samar@st.com>
>> ---
>>   arch/arm/mach-spear13xx/include/mach/generic.h |    2 +
>>   arch/arm/mach-spear13xx/include/mach/spear.h   |    3 +
>>   arch/arm/mach-spear13xx/spear1340.c            |   32 +++++++++
>>   arch/arm/mach-spear13xx/spear13xx.c            |   85 ++++++++++++++++++++++++
>>   4 files changed, 122 insertions(+)
>>
>> diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
>> index dac57fd..8c8fbaa 100644
>> --- a/arch/arm/mach-spear13xx/include/mach/generic.h
>> +++ b/arch/arm/mach-spear13xx/include/mach/generic.h
>> @@ -15,6 +15,7 @@
>>   #define __MACH_GENERIC_H
>>
>>   #include<linux/dmaengine.h>
>> +#include<linux/platform_device.h>
>>   #include<asm/mach/time.h>
>>
>>   /* Add spear13xx structure declarations here */
>> @@ -31,6 +32,7 @@ void __init spear13xx_map_io(void);
>>   void __init spear13xx_dt_init_irq(void);
>>   void __init spear13xx_l2x0_init(void);
>>   bool dw_dma_filter(struct dma_chan *chan, void *slave);
>> +int spear13xx_eth_phy_clk_cfg(struct platform_device *pdev);
>
> don't really need spear13xx_ prefix here. It is obviously for 13xx.

ok,

>
>>   void spear_restart(char, const char *);
>>   void spear13xx_secondary_startup(void);
>>
>> diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
>> index 65f27de..0ce064b 100644
>> --- a/arch/arm/mach-spear13xx/include/mach/spear.h
>> +++ b/arch/arm/mach-spear13xx/include/mach/spear.h
>> @@ -59,4 +59,7 @@
>>   #define SPEAR_DBG_UART_BASE                    UART_BASE
>>   #define VA_SPEAR_DBG_UART_BASE                 VA_UART_BASE
>>
>> +/* Ethernet base address */
>
> Comment not required.

ok,

>
>> +#define SPEAR13XX_GETH_BASE                    UL(0xE2000000)
>> +
>>   #endif /* __MACH_SPEAR13XX_H */
>> diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c
>> index 81e4ed7..ab282ed 100644
>> --- a/arch/arm/mach-spear13xx/spear1340.c
>> +++ b/arch/arm/mach-spear13xx/spear1340.c
>> @@ -18,6 +18,9 @@
>>   #include<linux/delay.h>
>>   #include<linux/dw_dmac.h>
>>   #include<linux/of_platform.h>
>> +#include<linux/phy.h>
>> +#include<linux/platform_device.h>
>> +#include<linux/stmmac.h>
>>   #include<asm/hardware/gic.h>
>>   #include<asm/mach/arch.h>
>>   #include<mach/dma.h>
>> @@ -100,6 +103,34 @@ static struct amba_pl011_data uart1_data = {
>>          .dma_rx_param =&uart1_dma_param[1],
>>   };
>>
>> +/* Ethernet platform data */
>> +static struct stmmac_mdio_bus_data mdio0_private_data = {
>> +       .bus_id = 0,
>> +       .phy_mask = 0,
>> +};
>> +
>> +static struct stmmac_dma_cfg dma0_private_data = {
>> +       .pbl = 16,
>> +       .fixed_burst = 1,
>> +       .burst_len = DMA_AXI_BLEN_ALL,
>> +};
>> +
>> +static struct plat_stmmacenet_data eth_data = {
>> +       .bus_id = 0,
>> +       .phy_addr = -1,
>> +       .interface = PHY_INTERFACE_MODE_RGMII,
>> +       .has_gmac = 1,
>> +       .enh_desc = 1,
>> +       .tx_coe = 1,
>> +       .dma_cfg =&dma0_private_data,
>> +       .rx_coe = STMMAC_RX_COE_TYPE2,
>> +       .bugged_jumbo = 1,
>> +       .pmt = 1,
>> +       .mdio_bus_data =&mdio0_private_data,
>> +       .init = spear13xx_eth_phy_clk_cfg,
>> +       .clk_csr = STMMAC_CSR_150_250M,
>> +};
>> +
>>   /* SATA device registration */
>>   static int sata_miphy_init(struct device *dev, void __iomem *addr)
>>   {
>> @@ -166,6 +197,7 @@ static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
>>          OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
>>                          &sata_pdata),
>>          OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL,&uart1_data),
>> +       OF_DEV_AUXDATA("st,spear600-gmac", SPEAR13XX_GETH_BASE, NULL,&eth_data),
>>          {}
>>   };
>>
>> diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
>> index cf936b1..285948a 100644
>> --- a/arch/arm/mach-spear13xx/spear13xx.c
>> +++ b/arch/arm/mach-spear13xx/spear13xx.c
>> @@ -18,6 +18,9 @@
>>   #include<linux/dw_dmac.h>
>>   #include<linux/err.h>
>>   #include<linux/of_irq.h>
>> +#include<linux/phy.h>
>> +#include<linux/platform_device.h>
>> +#include<linux/stmmac.h>
>>   #include<asm/hardware/cache-l2x0.h>
>>   #include<asm/hardware/gic.h>
>>   #include<asm/mach/map.h>
>> @@ -80,6 +83,88 @@ struct dw_dma_platform_data dmac_plat_data = {
>>          .chan_priority = CHAN_PRIORITY_DESCENDING,
>>   };
>>
>> +/* Ethernet clock initialization */
>> +int spear13xx_eth_phy_clk_cfg(struct platform_device *pdev)
>> +{
>> +       int ret;
>> +       struct clk *input_clk, *input_pclk, *phy_pclk, *phy_clk;
>> +       struct plat_stmmacenet_data *pdata = dev_get_platdata(&pdev->dev);
>> +       const char *phy_clk_src_name[] = {
>> +               "phy_input_mclk",
>> +               "phy_synth_gclk",
>> +       };
>> +       const char *input_clk_src_name[] = {
>> +               "pll2_clk",
>> +               "gmii_pad_clk",
>> +               "osc_25m_clk",
>> +       };
>> +       const char *phy_clk_name[] = {
>> +               "stmmacphy.0"
>> +       };
>> +
>> +       if (pdata == NULL)
>
> if (!pdata)

ok,

>
>> +               return -EINVAL;
>> +
>> +       /* Get the Pll-2 Clock as parent for PHY Input Clock Source */
>> +       input_pclk = clk_get(NULL, input_clk_src_name[0]);
>> +       if (IS_ERR(input_pclk)) {
>> +               ret = PTR_ERR(input_pclk);
>> +               goto fail_get_input_pclk;
>> +       }
>> +
>> +       /*
>> +        * Get the Phy Input clock source as parent for Phy clock. Default
>> +        * selection is gmac_phy_input_clk. This selection would be driving both
>> +        * the synthesizer and phy clock.
>> +        */
>> +       input_clk = clk_get(NULL, phy_clk_src_name[0]);
>> +       if (IS_ERR(input_clk)) {
>> +               ret = PTR_ERR(input_clk);
>> +               goto fail_get_input_clk;
>> +       }
>> +
>> +       /* Fetch the phy clock */
>> +       phy_clk = clk_get(NULL, phy_clk_name[pdata->bus_id]);
>> +       if (IS_ERR(phy_clk)) {
>> +               ret = PTR_ERR(phy_clk);
>> +               goto fail_get_phy_clk;
>> +       }
>> +
>> +       /* Set the pll-2 to 125 MHz */
>> +       clk_set_rate(input_pclk, 125000000);
>> +
>> +       /* Set the Pll-2 as parent for gmac_phy_input_clk */
>> +       clk_set_parent(input_clk, input_pclk);
>
> Above two calls can potentially fail.

ok,
>
>> +
>> +       if (pdata->interface == PHY_INTERFACE_MODE_RMII) {
>> +               /*
>> +                * For the rmii interface select gmac_phy_synth_clk
>> +                * as the parent and set the clock to 50 Mhz
>> +                */
>> +               phy_pclk = clk_get(NULL, phy_clk_src_name[1]);
>> +               clk_set_rate(phy_pclk, 50000000);
>> +       } else {
>> +               /*
>> +                * Set the gmac_phy_input_clk as the parent,
>> +                * and pll-2 is already running as parent of
>> +                * gmac_phy_input_clk at 125 Mhz
>> +                */
>> +               phy_pclk = input_clk;
>> +       }
>> +
>> +       /* Select the parent for phy clock */
>> +       clk_set_parent(phy_clk, phy_pclk);
>
> same here.

ok, i'll correct all in v2.

Thanks and Regards
Vipul Samar

[PATCH 5/6] Clk: SPEAr1340: fix sys clock parent source and corresponding mask value

[viresh kumar]

On Mon, Jul 9, 2012 at 1:04 PM, vipul kumar samar
<vipulkumar.samar@st.com> wrote:
> On 7/9/2012 4:34 PM, viresh kumar wrote:
>>
>> On Mon, Jul 9, 2012 at 11:31 AM, Shiraz Hashim<shiraz.hashim@st.com>
>> wrote:
>>>
>>> From: Vipul Kumar Samar<vipulkumar.samar@st.com>
>>>
>>> sys_clk have multiple parents and selection of parent is depends on
>>
>>
>> s/ is//

I hope you haven't missed this comment :)

>>>   static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
>>> -static const char *sys_parents[] = { "none", "pll1_clk", "none", "none",
>>> -       "sys_synth_clk", "none", "pll2_clk", "pll3_clk", };
>>> +static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
>>> +       "pll1_clk", "sys_synth_clk", "sys_synth_clk", "pll2_clk",
>>> "pll3_clk", };
>>
>>
>> Don't know what would be the implication of this?
>>
>> @Mike: Can you please tell us what should we do in such cases?
>>
>
> Is there any other solution for such cases ???

That's what i have asked mike for :)
Probably you can go through the clock framework code and check how these
names are used. Shouldn't be too complex to understand.

--
viresh

[PATCH 5/6] Clk: SPEAr1340: fix sys clock parent source and corresponding mask value

[Mike Turquette]

On 20120709-13:34, viresh kumar wrote:
> On Mon, Jul 9, 2012 at 1:04 PM, vipul kumar samar
> <vipulkumar.samar@st.com> wrote:
> > On 7/9/2012 4:34 PM, viresh kumar wrote:
> >>
> >> On Mon, Jul 9, 2012 at 11:31 AM, Shiraz Hashim<shiraz.hashim@st.com>
> >> wrote:
> >>>
> >>> From: Vipul Kumar Samar<vipulkumar.samar@st.com>
> >>>
> >>> sys_clk have multiple parents and selection of parent is depends on
> >>
> >>
> >> s/ is//
> 
> I hope you haven't missed this comment :)
> 
> >>>   static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
> >>> -static const char *sys_parents[] = { "none", "pll1_clk", "none", "none",
> >>> -       "sys_synth_clk", "none", "pll2_clk", "pll3_clk", };
> >>> +static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
> >>> +       "pll1_clk", "sys_synth_clk", "sys_synth_clk", "pll2_clk",
> >>> "pll3_clk", };
> >>
> >>
> >> Don't know what would be the implication of this?
> >>
> >> @Mike: Can you please tell us what should we do in such cases?
> >>
> >
> > Is there any other solution for such cases ???
> 
> That's what i have asked mike for :)
> Probably you can go through the clock framework code and check how these
> names are used. Shouldn't be too complex to understand.
> 

I assume this change has been tested and wouldn't be posted if modifying
the parent names broke things.

That said, as long as the parent names are valid strings then the clk
framework should handle them.  When calling __clk_lookup for parent name
"none", __clk_lookup will return NULL (of course assuming no one else in
the system registered a clock named "none", which would be silly).  This
is handled gracefully by the clk framework by re-parenting your "sys"
clk from $old_parent to the "orphan" list.

At the top level, there are basically two clock trees.  The first tree
is "real" clock tree which starts as a list of clocks that set the
CLK_IS_ROOT flag.  The second tree is a tree of "orphans" for clocks
which are defined but "disconnected" from any real root clock (which
might be caused by missing data, etc).

In general it is OK to declare parent names which might result in your
clock being orphaned.  In practice it is more likely that your data
matches your code: e.g. if you don't support a parent clock in the data
then you likely never try use that missing parent clock in your code.

The OMAP port does in fact make use of the orphan tree for some clocks,
so it is tested.  However we haven't had any users of the clock tree
which made a lot of use of "dynamic" reparenting to and from the orphan
tree.  I did unit test this back during the 3.4 cycle, but I haven't
since.  Let me know if you have any problems with it.

Regards,
Mike

> --
> viresh
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 5/6] Clk: SPEAr1340: fix sys clock parent source and corresponding mask value

[Viresh Kumar]

On 9 July 2012 23:57, Mike Turquette <mturquette@ti.com> wrote:

> I assume this change has been tested and wouldn't be posted if modifying
> the parent names broke things.
>
> That said, as long as the parent names are valid strings then the clk
> framework should handle them.  When calling __clk_lookup for parent name
> "none", __clk_lookup will return NULL (of course assuming no one else in
> the system registered a clock named "none", which would be silly).  This
> is handled gracefully by the clk framework by re-parenting your "sys"
> clk from $old_parent to the "orphan" list.
>
> At the top level, there are basically two clock trees.  The first tree
> is "real" clock tree which starts as a list of clocks that set the
> CLK_IS_ROOT flag.  The second tree is a tree of "orphans" for clocks
> which are defined but "disconnected" from any real root clock (which
> might be caused by missing data, etc).
>
> In general it is OK to declare parent names which might result in your
> clock being orphaned.  In practice it is more likely that your data
> matches your code: e.g. if you don't support a parent clock in the data
> then you likely never try use that missing parent clock in your code.
>
> The OMAP port does in fact make use of the orphan tree for some clocks,
> so it is tested.  However we haven't had any users of the clock tree
> which made a lot of use of "dynamic" reparenting to and from the orphan
> tree.  I did unit test this back during the 3.4 cycle, but I haven't
> since.  Let me know if you have any problems with it.
>

Hi Mike,

For example, clk1 have parents pclk1 and pclk2. Register values
for pclk1 is 0X and for pclk2 is 1X. i.e. pclk1 is selected for both 00 and
01.
And pclk2 is selected for 10 and 11. so, its better to take care of all
these situations,
otherwise there can be corner cases like: In linux we decide to use 00 for
pclk1, 10 for
pclk2 and other two for "none". But bootloader, enabled the clock with 01
for pclk1.
This clock isn't a orphan but it will look like that in our clock tree.

So, is this OK in the current implementation of clk framework to have
parents like
"pclk1", "pclk1", "pclk2", "pclk2"?

--
viresh
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[PATCH 5/6] Clk: SPEAr1340: fix sys clock parent source and corresponding mask value

[Shiraz Hashim]

Hi Mike,

On Mon, Jul 09, 2012 at 03:57:00PM -0700, Mike Turquette wrote:
> On 20120709-13:34, viresh kumar wrote:
> > On Mon, Jul 9, 2012 at 1:04 PM, vipul kumar samar
> > <vipulkumar.samar@st.com> wrote:
> > > On 7/9/2012 4:34 PM, viresh kumar wrote:
> > >>
> > >> On Mon, Jul 9, 2012 at 11:31 AM, Shiraz Hashim<shiraz.hashim@st.com>
> > >> wrote:
> > >>>
> > >>> From: Vipul Kumar Samar<vipulkumar.samar@st.com>
> > >>>
> > >>> sys_clk have multiple parents and selection of parent is depends on
> > >>
> > >>
> > >> s/ is//
> > 
> > I hope you haven't missed this comment :)
> > 
> > >>>   static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
> > >>> -static const char *sys_parents[] = { "none", "pll1_clk", "none", "none",
> > >>> -       "sys_synth_clk", "none", "pll2_clk", "pll3_clk", };
> > >>> +static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
> > >>> +       "pll1_clk", "sys_synth_clk", "sys_synth_clk", "pll2_clk",
> > >>> "pll3_clk", };
> > >>
> > >>
> > >> Don't know what would be the implication of this?
> > >>
> > >> @Mike: Can you please tell us what should we do in such cases?
> > >>
> > >
> > > Is there any other solution for such cases ???
> > 
> > That's what i have asked mike for :)
> > Probably you can go through the clock framework code and check how these
> > names are used. Shouldn't be too complex to understand.
> > 
> 
> I assume this change has been tested and wouldn't be posted if modifying
> the parent names broke things.

Yes, it is working fine for us.

--
regards
Shiraz

[PATCH 5/6] Clk: SPEAr1340: fix sys clock parent source and corresponding mask value

[Mike Turquette]

On 20120710-09:21, Viresh Kumar wrote:
> On 9 July 2012 23:57, Mike Turquette <mturquette@ti.com> wrote:
> 
> > I assume this change has been tested and wouldn't be posted if modifying
> > the parent names broke things.
> >
> > That said, as long as the parent names are valid strings then the clk
> > framework should handle them.  When calling __clk_lookup for parent name
> > "none", __clk_lookup will return NULL (of course assuming no one else in
> > the system registered a clock named "none", which would be silly).  This
> > is handled gracefully by the clk framework by re-parenting your "sys"
> > clk from $old_parent to the "orphan" list.
> >
> > At the top level, there are basically two clock trees.  The first tree
> > is "real" clock tree which starts as a list of clocks that set the
> > CLK_IS_ROOT flag.  The second tree is a tree of "orphans" for clocks
> > which are defined but "disconnected" from any real root clock (which
> > might be caused by missing data, etc).
> >
> > In general it is OK to declare parent names which might result in your
> > clock being orphaned.  In practice it is more likely that your data
> > matches your code: e.g. if you don't support a parent clock in the data
> > then you likely never try use that missing parent clock in your code.
> >
> > The OMAP port does in fact make use of the orphan tree for some clocks,
> > so it is tested.  However we haven't had any users of the clock tree
> > which made a lot of use of "dynamic" reparenting to and from the orphan
> > tree.  I did unit test this back during the 3.4 cycle, but I haven't
> > since.  Let me know if you have any problems with it.
> >
> 
> Hi Mike,
> 
> For example, clk1 have parents pclk1 and pclk2. Register values
> for pclk1 is 0X and for pclk2 is 1X. i.e. pclk1 is selected for both 00 and
> 01.
> And pclk2 is selected for 10 and 11. so, its better to take care of all
> these situations,
> otherwise there can be corner cases like: In linux we decide to use 00 for
> pclk1, 10 for
> pclk2 and other two for "none". But bootloader, enabled the clock with 01
> for pclk1.
> This clock isn't a orphan but it will look like that in our clock tree.
> 
> So, is this OK in the current implementation of clk framework to have
> parents like
> "pclk1", "pclk1", "pclk2", "pclk2"?
> 

Hello Viresh,

I believe it will be OK, but that situation definitely needs testing.
There will not be duplicate clocks in the tree (which is good), but the
parent selection logic for clk1 will be a bit silly.  All in all
duplicating parent string names is a hack.

If this case is very common then a better way to handle it would be a
clk_mux-specific flag which handles this case gracefully.  Mark all of
your mux data with this flag for the affected clocks and then don't
worry about it anymore.

Regards,
Mike

> --
> viresh